[mirror_qemu.git] / include / exec / cpu-defs.h

/*
 * common defines for all CPUs
 *
 * Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef CPU_DEFS_H
#define CPU_DEFS_H

#ifndef NEED_CPU_H
#error cpu.h included from common code
#endif

#include "config.h"
#include <setjmp.h>
#include <inttypes.h>
#include "qemu/osdep.h"
#include "qemu/queue.h"
#include "exec/hwaddr.h"

#ifndef TARGET_LONG_BITS
#error TARGET_LONG_BITS must be defined before including this header
#endif

#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)

/* target_ulong is the type of a virtual address */
#if TARGET_LONG_SIZE == 4
typedef int32_t target_long;
typedef uint32_t target_ulong;
#define TARGET_FMT_lx "%08x"
#define TARGET_FMT_ld "%d"
#define TARGET_FMT_lu "%u"
#elif TARGET_LONG_SIZE == 8
typedef int64_t target_long;
typedef uint64_t target_ulong;
#define TARGET_FMT_lx "%016" PRIx64
#define TARGET_FMT_ld "%" PRId64
#define TARGET_FMT_lu "%" PRIu64
#else
#error TARGET_LONG_SIZE undefined
#endif

#define EXCP_INTERRUPT 	0x10000 /* async interruption */
#define EXCP_HLT        0x10001 /* hlt instruction reached */
#define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
#define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */

#define TB_JMP_CACHE_BITS 12
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)

/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
   addresses on the same page.  The top bits are the same.  This allows
   TLB invalidation to quickly clear a subset of the hash table.  */
#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)

#if !defined(CONFIG_USER_ONLY)
#define CPU_TLB_BITS 8
#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)

#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
#define CPU_TLB_ENTRY_BITS 4
#else
#define CPU_TLB_ENTRY_BITS 5
#endif

typedef struct CPUTLBEntry {
    /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
       bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
                                    go directly to ram.
       bit 3                      : indicates that the entry is invalid
       bit 2..0                   : zero
    */
    target_ulong addr_read;
    target_ulong addr_write;
    target_ulong addr_code;
    /* Addend to virtual address to get host address.  IO accesses
       use the corresponding iotlb value.  */
    uintptr_t addend;
    /* padding to get a power of two size */
    uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
                  (sizeof(target_ulong) * 3 +
                   ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
                   sizeof(uintptr_t))];
} CPUTLBEntry;

extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1];

#define CPU_COMMON_TLB \
    /* The meaning of the MMU modes is defined in the target code. */   \
    CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
    hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
    target_ulong tlb_flush_addr;                                        \
    target_ulong tlb_flush_mask;

#else

#define CPU_COMMON_TLB

#endif


#ifdef HOST_WORDS_BIGENDIAN
typedef struct icount_decr_u16 {
    uint16_t high;
    uint16_t low;
} icount_decr_u16;
#else
typedef struct icount_decr_u16 {
    uint16_t low;
    uint16_t high;
} icount_decr_u16;
#endif

typedef struct CPUBreakpoint {
    target_ulong pc;
    int flags; /* BP_* */
    QTAILQ_ENTRY(CPUBreakpoint) entry;
} CPUBreakpoint;

typedef struct CPUWatchpoint {
    target_ulong vaddr;
    target_ulong len_mask;
    int flags; /* BP_* */
    QTAILQ_ENTRY(CPUWatchpoint) entry;
} CPUWatchpoint;

#define CPU_TEMP_BUF_NLONGS 128
#define CPU_COMMON                                                      \
    /* soft mmu support */                                              \
    /* in order to avoid passing too many arguments to the MMIO         \
       helpers, we store some rarely used information in the CPU        \
       context) */                                                      \
    uintptr_t mem_io_pc; /* host pc at which the memory was             \
                            accessed */                                 \
    target_ulong mem_io_vaddr; /* target virtual addr at which the      \
                                     memory was accessed */             \
    CPU_COMMON_TLB                                                      \
    struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
    /* buffer for temporaries in the code generator */                  \
    long temp_buf[CPU_TEMP_BUF_NLONGS];                                 \
                                                                        \
    int64_t icount_extra; /* Instructions until next timer event.  */   \
    /* Number of cycles left, with interrupt flag in high bit.          \
       This allows a single read-compare-cbranch-write sequence to test \
       for both decrementer underflow and exceptions.  */               \
    union {                                                             \
        uint32_t u32;                                                   \
        icount_decr_u16 u16;                                            \
    } icount_decr;                                                      \
    uint32_t can_do_io; /* nonzero if memory mapped IO is safe.  */     \
                                                                        \
    /* from this point: preserved by CPU reset */                       \
    /* ice debug support */                                             \
    QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;            \
    int singlestep_enabled;                                             \
                                                                        \
    QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;            \
    CPUWatchpoint *watchpoint_hit;                                      \
                                                                        \
    struct GDBRegisterState *gdb_regs;                                  \
                                                                        \
    /* Core interrupt code */                                           \
    sigjmp_buf jmp_env;                                                 \
    int exception_index;                                                \
                                                                        \
    CPUArchState *next_cpu; /* next CPU sharing TB cache */                 \
    /* user data */                                                     \
    void *opaque;                                                       \
                                                                        \
    const char *cpu_model_str;

#endif
Commit	Line	Data
	1	/*
	2	* common defines for all CPUs
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef CPU_DEFS_H
	20	#define CPU_DEFS_H
	21
	22	#ifndef NEED_CPU_H
	23	#error cpu.h included from common code
	24	#endif
	25
	26	#include "config.h"
	27	#include <setjmp.h>
	28	#include <inttypes.h>
	29	#include "qemu/osdep.h"
	30	#include "qemu/queue.h"
	31	#include "exec/hwaddr.h"
	32
	33	#ifndef TARGET_LONG_BITS
	34	#error TARGET_LONG_BITS must be defined before including this header
	35	#endif
	36
	37	#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
	38
	39	/* target_ulong is the type of a virtual address */
	40	#if TARGET_LONG_SIZE == 4
	41	typedef int32_t target_long;
	42	typedef uint32_t target_ulong;
	43	#define TARGET_FMT_lx "%08x"
	44	#define TARGET_FMT_ld "%d"
	45	#define TARGET_FMT_lu "%u"
	46	#elif TARGET_LONG_SIZE == 8
	47	typedef int64_t target_long;
	48	typedef uint64_t target_ulong;
	49	#define TARGET_FMT_lx "%016" PRIx64
	50	#define TARGET_FMT_ld "%" PRId64
	51	#define TARGET_FMT_lu "%" PRIu64
	52	#else
	53	#error TARGET_LONG_SIZE undefined
	54	#endif
	55
	56	#define EXCP_INTERRUPT 0x10000 /* async interruption */
	57	#define EXCP_HLT 0x10001 /* hlt instruction reached */
	58	#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
	59	#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
	60
	61	#define TB_JMP_CACHE_BITS 12
	62	#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
	63
	64	/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
	65	addresses on the same page. The top bits are the same. This allows
	66	TLB invalidation to quickly clear a subset of the hash table. */
	67	#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
	68	#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
	69	#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
	70	#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
	71
	72	#if !defined(CONFIG_USER_ONLY)
	73	#define CPU_TLB_BITS 8
	74	#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
	75
	76	#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
	77	#define CPU_TLB_ENTRY_BITS 4
	78	#else
	79	#define CPU_TLB_ENTRY_BITS 5
	80	#endif
	81
	82	typedef struct CPUTLBEntry {
	83	/* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
	84	bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
	85	go directly to ram.
	86	bit 3 : indicates that the entry is invalid
	87	bit 2..0 : zero
	88	*/
	89	target_ulong addr_read;
	90	target_ulong addr_write;
	91	target_ulong addr_code;
	92	/* Addend to virtual address to get host address. IO accesses
	93	use the corresponding iotlb value. */
	94	uintptr_t addend;
	95	/* padding to get a power of two size */
	96	uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
	97	(sizeof(target_ulong) * 3 +
	98	((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
	99	sizeof(uintptr_t))];
	100	} CPUTLBEntry;
	101
	102	extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1];
	103
	104	#define CPU_COMMON_TLB \
	105	/* The meaning of the MMU modes is defined in the target code. */ \
	106	CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
	107	hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
	108	target_ulong tlb_flush_addr; \
	109	target_ulong tlb_flush_mask;
	110
	111	#else
	112
	113	#define CPU_COMMON_TLB
	114
	115	#endif
	116
	117
	118	#ifdef HOST_WORDS_BIGENDIAN
	119	typedef struct icount_decr_u16 {
	120	uint16_t high;
	121	uint16_t low;
	122	} icount_decr_u16;
	123	#else
	124	typedef struct icount_decr_u16 {
	125	uint16_t low;
	126	uint16_t high;
	127	} icount_decr_u16;
	128	#endif
	129
	130	typedef struct CPUBreakpoint {
	131	target_ulong pc;
	132	int flags; /* BP_* */
	133	QTAILQ_ENTRY(CPUBreakpoint) entry;
	134	} CPUBreakpoint;
	135
	136	typedef struct CPUWatchpoint {
	137	target_ulong vaddr;
	138	target_ulong len_mask;
	139	int flags; /* BP_* */
	140	QTAILQ_ENTRY(CPUWatchpoint) entry;
	141	} CPUWatchpoint;
	142
	143	#define CPU_TEMP_BUF_NLONGS 128
	144	#define CPU_COMMON \
	145	/* soft mmu support */ \
	146	/* in order to avoid passing too many arguments to the MMIO \
	147	helpers, we store some rarely used information in the CPU \
	148	context) */ \
	149	uintptr_t mem_io_pc; /* host pc at which the memory was \
	150	accessed */ \
	151	target_ulong mem_io_vaddr; /* target virtual addr at which the \
	152	memory was accessed */ \
	153	CPU_COMMON_TLB \
	154	struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
	155	/* buffer for temporaries in the code generator */ \
	156	long temp_buf[CPU_TEMP_BUF_NLONGS]; \
	157	\
	158	int64_t icount_extra; /* Instructions until next timer event. */ \
	159	/* Number of cycles left, with interrupt flag in high bit. \
	160	This allows a single read-compare-cbranch-write sequence to test \
	161	for both decrementer underflow and exceptions. */ \
	162	union { \
	163	uint32_t u32; \
	164	icount_decr_u16 u16; \
	165	} icount_decr; \
	166	uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
	167	\
	168	/* from this point: preserved by CPU reset */ \
	169	/* ice debug support */ \
	170	QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
	171	int singlestep_enabled; \
	172	\
	173	QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
	174	CPUWatchpoint *watchpoint_hit; \
	175	\
	176	struct GDBRegisterState *gdb_regs; \
	177	\
	178	/* Core interrupt code */ \
	179	sigjmp_buf jmp_env; \
	180	int exception_index; \
	181	\
	182	CPUArchState next_cpu; / next CPU sharing TB cache */ \
	183	/* user data */ \
	184	void *opaque; \
	185	\
	186	const char *cpu_model_str;
	187
	188	#endif