[mirror_qemu.git] / include / hw / i386 / pc.h

#ifndef HW_PC_H
#define HW_PC_H

#include "qemu-common.h"
#include "exec/memory.h"
#include "hw/isa/isa.h"
#include "hw/block/fdc.h"
#include "net/net.h"
#include "hw/i386/ioapic.h"

#include "qemu/range.h"
#include "qemu/bitmap.h"
#include "sysemu/sysemu.h"
#include "hw/pci/pci.h"

/* PC-style peripherals (also used by other machines).  */

typedef struct PcPciInfo {
    Range w32;
    Range w64;
} PcPciInfo;

#define ACPI_PM_PROP_S3_DISABLED "disable_s3"
#define ACPI_PM_PROP_S4_DISABLED "disable_s4"
#define ACPI_PM_PROP_S4_VAL "s4_val"
#define ACPI_PM_PROP_SCI_INT "sci_int"
#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"

struct PcGuestInfo {
    bool has_pci_info;
    bool isapc_ram_fw;
    hwaddr ram_size;
    unsigned apic_id_limit;
    bool apic_xrupt_override;
    uint64_t numa_nodes;
    uint64_t *node_mem;
    uint64_t *node_cpu;
    FWCfgState *fw_cfg;
};

/* parallel.c */
static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
{
    DeviceState *dev;
    ISADevice *isadev;

    isadev = isa_try_create(bus, "isa-parallel");
    if (!isadev) {
        return false;
    }
    dev = DEVICE(isadev);
    qdev_prop_set_uint32(dev, "index", index);
    qdev_prop_set_chr(dev, "chardev", chr);
    if (qdev_init(dev) < 0) {
        return false;
    }
    return true;
}

bool parallel_mm_init(MemoryRegion *address_space,
                      hwaddr base, int it_shift, qemu_irq irq,
                      CharDriverState *chr);

/* i8259.c */

extern DeviceState *isa_pic;
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
qemu_irq *kvm_i8259_init(ISABus *bus);
int pic_read_irq(DeviceState *d);
int pic_get_output(DeviceState *d);
void pic_info(Monitor *mon, const QDict *qdict);
void irq_info(Monitor *mon, const QDict *qdict);

/* Global System Interrupts */

#define GSI_NUM_PINS IOAPIC_NUM_PINS

typedef struct GSIState {
    qemu_irq i8259_irq[ISA_NUM_IRQS];
    qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
} GSIState;

void gsi_handler(void *opaque, int n, int level);

/* vmport.c */
typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);

static inline void vmport_init(ISABus *bus)
{
    isa_create_simple(bus, "vmport");
}

void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
void vmmouse_get_data(uint32_t *data);
void vmmouse_set_data(const uint32_t *data);

/* pckbd.c */

void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   MemoryRegion *region, ram_addr_t size,
                   hwaddr mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);

/* pc.c */
extern int fd_bootchk;

void pc_register_ferr_irq(qemu_irq irq);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);

void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
void pc_hot_add_cpu(const int64_t id, Error **errp);
void pc_acpi_init(const char *default_dsdt);

PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
                                ram_addr_t above_4g_mem_size);

#define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
#define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
#define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
#define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)

static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
{
    if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
        return 1ULL << 62;
    } else {
        return pci_hole64_size;
    }
}

void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
                        uint64_t pci_hole64_size);

FWCfgState *pc_memory_init(MemoryRegion *system_memory,
                           const char *kernel_filename,
                           const char *kernel_cmdline,
                           const char *initrd_filename,
                           ram_addr_t below_4g_mem_size,
                           ram_addr_t above_4g_mem_size,
                           MemoryRegion *rom_memory,
                           MemoryRegion **ram_memory,
                           PcGuestInfo *guest_info);
qemu_irq *pc_allocate_cpu_irq(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
                          ISADevice **rtc_state,
                          ISADevice **floppy,
                          bool no_vmport);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
                  const char *boot_device,
                  ISADevice *floppy, BusState *ide0, BusState *ide1,
                  ISADevice *s);
void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_pci_device_init(PCIBus *pci_bus);

typedef void (*cpu_set_smm_t)(int smm, void *arg);
void cpu_smm_register(cpu_set_smm_t callback, void *arg);

void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);

/* acpi_piix.c */

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int kvm_enabled, FWCfgState *fw_cfg);
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);

/* hpet.c */
extern int no_hpet;

/* piix_pci.c */
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
                    ISABus **isa_bus, qemu_irq *pic,
                    MemoryRegion *address_space_mem,
                    MemoryRegion *address_space_io,
                    ram_addr_t ram_size,
                    hwaddr pci_hole_start,
                    hwaddr pci_hole_size,
                    ram_addr_t above_4g_mem_size,
                    MemoryRegion *pci_memory,
                    MemoryRegion *ram_memory);

PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);

/* vga.c */
enum vga_retrace_method {
    VGA_RETRACE_DUMB,
    VGA_RETRACE_PRECISE
};

extern enum vga_retrace_method vga_retrace_method;

int isa_vga_mm_init(hwaddr vram_base,
                    hwaddr ctrl_base, int it_shift,
                    MemoryRegion *address_space);

/* ne2000.c */
static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
{
    DeviceState *dev;
    ISADevice *isadev;

    qemu_check_nic_model(nd, "ne2k_isa");

    isadev = isa_try_create(bus, "ne2k_isa");
    if (!isadev) {
        return false;
    }
    dev = DEVICE(isadev);
    qdev_prop_set_uint32(dev, "iobase", base);
    qdev_prop_set_uint32(dev, "irq",    irq);
    qdev_set_nic_properties(dev, nd);
    qdev_init_nofail(dev);
    return true;
}

/* pc_sysfw.c */
void pc_system_firmware_init(MemoryRegion *rom_memory,
                             bool isapc_ram_fw);

/* pvpanic.c */
void pvpanic_init(ISABus *bus);
uint16_t pvpanic_port(void);

/* e820 types */
#define E820_RAM        1
#define E820_RESERVED   2
#define E820_ACPI       3
#define E820_NVS        4
#define E820_UNUSABLE   5

int e820_add_entry(uint64_t, uint64_t, uint32_t);

#define PC_COMPAT_1_6 \
        {\
            .driver   = "e1000",\
            .property = "mitigation",\
            .value    = "off",\
        }

#define PC_COMPAT_1_5 \
        PC_COMPAT_1_6, \
        {\
            .driver   = "Conroe-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "Conroe-" TYPE_X86_CPU,\
            .property = "level",\
            .value    = stringify(2),\
        },{\
            .driver   = "Penryn-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "Penryn-" TYPE_X86_CPU,\
            .property = "level",\
            .value    = stringify(2),\
        },{\
            .driver   = "Nehalem-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "Nehalem-" TYPE_X86_CPU,\
            .property = "level",\
            .value    = stringify(2),\
        },{\
            .driver   = "virtio-net-pci",\
            .property = "any_layout",\
            .value    = "off",\
        },{\
            .driver = TYPE_X86_CPU,\
            .property = "pmu",\
            .value = "on",\
        }

#define PC_COMPAT_1_4 \
        PC_COMPAT_1_5, \
        {\
            .driver   = "scsi-hd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "scsi-cd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "scsi-disk",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "ide-hd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "ide-cd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "ide-drive",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
        },{\
            .driver   = "virtio-blk-pci",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "virtio-serial-pci",\
            .property = "vectors",\
            /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
            .value    = stringify(0xFFFFFFFF),\
        },{ \
            .driver   = "virtio-net-pci", \
            .property = "ctrl_guest_offloads", \
            .value    = "off", \
        },{\
            .driver   = "e1000",\
            .property = "romfile",\
            .value    = "pxe-e1000.rom",\
        },{\
            .driver   = "ne2k_pci",\
            .property = "romfile",\
            .value    = "pxe-ne2k_pci.rom",\
        },{\
            .driver   = "pcnet",\
            .property = "romfile",\
            .value    = "pxe-pcnet.rom",\
        },{\
            .driver   = "rtl8139",\
            .property = "romfile",\
            .value    = "pxe-rtl8139.rom",\
        },{\
            .driver   = "virtio-net-pci",\
            .property = "romfile",\
            .value    = "pxe-virtio.rom",\
        },{\
            .driver   = "486-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(0),\
        }

#define PC_COMMON_MACHINE_OPTIONS \
    .default_boot_order = "cad"

#define PC_DEFAULT_MACHINE_OPTIONS \
    PC_COMMON_MACHINE_OPTIONS, \
    .hot_add_cpu = pc_hot_add_cpu, \
    .max_cpus = 255

#endif
Commit	Line	Data
	1	#ifndef HW_PC_H
	2	#define HW_PC_H
	3
	4	#include "qemu-common.h"
	5	#include "exec/memory.h"
	6	#include "hw/isa/isa.h"
	7	#include "hw/block/fdc.h"
	8	#include "net/net.h"
	9	#include "hw/i386/ioapic.h"
	10
	11	#include "qemu/range.h"
	12	#include "qemu/bitmap.h"
	13	#include "sysemu/sysemu.h"
	14	#include "hw/pci/pci.h"
	15
	16	/* PC-style peripherals (also used by other machines). */
	17
	18	typedef struct PcPciInfo {
	19	Range w32;
	20	Range w64;
	21	} PcPciInfo;
	22
	23	#define ACPI_PM_PROP_S3_DISABLED "disable_s3"
	24	#define ACPI_PM_PROP_S4_DISABLED "disable_s4"
	25	#define ACPI_PM_PROP_S4_VAL "s4_val"
	26	#define ACPI_PM_PROP_SCI_INT "sci_int"
	27	#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
	28	#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
	29	#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
	30	#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
	31	#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
	32
	33	struct PcGuestInfo {
	34	bool has_pci_info;
	35	bool isapc_ram_fw;
	36	hwaddr ram_size;
	37	unsigned apic_id_limit;
	38	bool apic_xrupt_override;
	39	uint64_t numa_nodes;
	40	uint64_t *node_mem;
	41	uint64_t *node_cpu;
	42	FWCfgState *fw_cfg;
	43	};
	44
	45	/* parallel.c */
	46	static inline bool parallel_init(ISABus bus, int index, CharDriverState chr)
	47	{
	48	DeviceState *dev;
	49	ISADevice *isadev;
	50
	51	isadev = isa_try_create(bus, "isa-parallel");
	52	if (!isadev) {
	53	return false;
	54	}
	55	dev = DEVICE(isadev);
	56	qdev_prop_set_uint32(dev, "index", index);
	57	qdev_prop_set_chr(dev, "chardev", chr);
	58	if (qdev_init(dev) < 0) {
	59	return false;
	60	}
	61	return true;
	62	}
	63
	64	bool parallel_mm_init(MemoryRegion *address_space,
	65	hwaddr base, int it_shift, qemu_irq irq,
	66	CharDriverState *chr);
	67
	68	/* i8259.c */
	69
	70	extern DeviceState *isa_pic;
	71	qemu_irq i8259_init(ISABus bus, qemu_irq parent_irq);
	72	qemu_irq kvm_i8259_init(ISABus bus);
	73	int pic_read_irq(DeviceState *d);
	74	int pic_get_output(DeviceState *d);
	75	void pic_info(Monitor mon, const QDict qdict);
	76	void irq_info(Monitor mon, const QDict qdict);
	77
	78	/* Global System Interrupts */
	79
	80	#define GSI_NUM_PINS IOAPIC_NUM_PINS
	81
	82	typedef struct GSIState {
	83	qemu_irq i8259_irq[ISA_NUM_IRQS];
	84	qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
	85	} GSIState;
	86
	87	void gsi_handler(void *opaque, int n, int level);
	88
	89	/* vmport.c */
	90	typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
	91
	92	static inline void vmport_init(ISABus *bus)
	93	{
	94	isa_create_simple(bus, "vmport");
	95	}
	96
	97	void vmport_register(unsigned char command, VMPortReadFunc func, void opaque);
	98	void vmmouse_get_data(uint32_t *data);
	99	void vmmouse_set_data(const uint32_t *data);
	100
	101	/* pckbd.c */
	102
	103	void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
	104	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
	105	MemoryRegion *region, ram_addr_t size,
	106	hwaddr mask);
	107	void i8042_isa_mouse_fake_event(void *opaque);
	108	void i8042_setup_a20_line(ISADevice dev, qemu_irq a20_out);
	109
	110	/* pc.c */
	111	extern int fd_bootchk;
	112
	113	void pc_register_ferr_irq(qemu_irq irq);
	114	void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
	115
	116	void pc_cpus_init(const char cpu_model, DeviceState icc_bridge);
	117	void pc_hot_add_cpu(const int64_t id, Error **errp);
	118	void pc_acpi_init(const char *default_dsdt);
	119
	120	PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
	121	ram_addr_t above_4g_mem_size);
	122
	123	#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
	124	#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
	125	#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
	126	#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
	127	#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
	128	#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
	129
	130	static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
	131	{
	132	if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
	133	return 1ULL << 62;
	134	} else {
	135	return pci_hole64_size;
	136	}
	137	}
	138
	139	void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
	140	uint64_t pci_hole64_size);
	141
	142	FWCfgState pc_memory_init(MemoryRegion system_memory,
	143	const char *kernel_filename,
	144	const char *kernel_cmdline,
	145	const char *initrd_filename,
	146	ram_addr_t below_4g_mem_size,
	147	ram_addr_t above_4g_mem_size,
	148	MemoryRegion *rom_memory,
	149	MemoryRegion **ram_memory,
	150	PcGuestInfo *guest_info);
	151	qemu_irq *pc_allocate_cpu_irq(void);
	152	DeviceState pc_vga_init(ISABus isa_bus, PCIBus *pci_bus);
	153	void pc_basic_device_init(ISABus isa_bus, qemu_irq gsi,
	154	ISADevice **rtc_state,
	155	ISADevice **floppy,
	156	bool no_vmport);
	157	void pc_init_ne2k_isa(ISABus bus, NICInfo nd);
	158	void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
	159	const char *boot_device,
	160	ISADevice floppy, BusState ide0, BusState *ide1,
	161	ISADevice *s);
	162	void pc_nic_init(ISABus isa_bus, PCIBus pci_bus);
	163	void pc_pci_device_init(PCIBus *pci_bus);
	164
	165	typedef void (cpu_set_smm_t)(int smm, void arg);
	166	void cpu_smm_register(cpu_set_smm_t callback, void *arg);
	167
	168	void ioapic_init_gsi(GSIState gsi_state, const char parent_name);
	169
	170	/* acpi_piix.c */
	171
	172	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
	173	qemu_irq sci_irq, qemu_irq smi_irq,
	174	int kvm_enabled, FWCfgState *fw_cfg);
	175	void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
	176
	177	/* hpet.c */
	178	extern int no_hpet;
	179
	180	/* piix_pci.c */
	181	struct PCII440FXState;
	182	typedef struct PCII440FXState PCII440FXState;
	183
	184	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix_devfn,
	185	ISABus *isa_bus, qemu_irq pic,
	186	MemoryRegion *address_space_mem,
	187	MemoryRegion *address_space_io,
	188	ram_addr_t ram_size,
	189	hwaddr pci_hole_start,
	190	hwaddr pci_hole_size,
	191	ram_addr_t above_4g_mem_size,
	192	MemoryRegion *pci_memory,
	193	MemoryRegion *ram_memory);
	194
	195	PCIBus *find_i440fx(void);
	196	/* piix4.c */
	197	extern PCIDevice *piix4_dev;
	198	int piix4_init(PCIBus bus, ISABus *isa_bus, int devfn);
	199
	200	/* vga.c */
	201	enum vga_retrace_method {
	202	VGA_RETRACE_DUMB,
	203	VGA_RETRACE_PRECISE
	204	};
	205
	206	extern enum vga_retrace_method vga_retrace_method;
	207
	208	int isa_vga_mm_init(hwaddr vram_base,
	209	hwaddr ctrl_base, int it_shift,
	210	MemoryRegion *address_space);
	211
	212	/* ne2000.c */
	213	static inline bool isa_ne2000_init(ISABus bus, int base, int irq, NICInfo nd)
	214	{
	215	DeviceState *dev;
	216	ISADevice *isadev;
	217
	218	qemu_check_nic_model(nd, "ne2k_isa");
	219
	220	isadev = isa_try_create(bus, "ne2k_isa");
	221	if (!isadev) {
	222	return false;
	223	}
	224	dev = DEVICE(isadev);
	225	qdev_prop_set_uint32(dev, "iobase", base);
	226	qdev_prop_set_uint32(dev, "irq", irq);
	227	qdev_set_nic_properties(dev, nd);
	228	qdev_init_nofail(dev);
	229	return true;
	230	}
	231
	232	/* pc_sysfw.c */
	233	void pc_system_firmware_init(MemoryRegion *rom_memory,
	234	bool isapc_ram_fw);
	235
	236	/* pvpanic.c */
	237	void pvpanic_init(ISABus *bus);
	238	uint16_t pvpanic_port(void);
	239
	240	/* e820 types */
	241	#define E820_RAM 1
	242	#define E820_RESERVED 2
	243	#define E820_ACPI 3
	244	#define E820_NVS 4
	245	#define E820_UNUSABLE 5
	246
	247	int e820_add_entry(uint64_t, uint64_t, uint32_t);
	248
	249	#define PC_COMPAT_1_6 \
	250	{\
	251	.driver = "e1000",\
	252	.property = "mitigation",\
	253	.value = "off",\
	254	}
	255
	256	#define PC_COMPAT_1_5 \
	257	PC_COMPAT_1_6, \
	258	{\
	259	.driver = "Conroe-" TYPE_X86_CPU,\
	260	.property = "model",\
	261	.value = stringify(2),\
	262	},{\
	263	.driver = "Conroe-" TYPE_X86_CPU,\
	264	.property = "level",\
	265	.value = stringify(2),\
	266	},{\
	267	.driver = "Penryn-" TYPE_X86_CPU,\
	268	.property = "model",\
	269	.value = stringify(2),\
	270	},{\
	271	.driver = "Penryn-" TYPE_X86_CPU,\
	272	.property = "level",\
	273	.value = stringify(2),\
	274	},{\
	275	.driver = "Nehalem-" TYPE_X86_CPU,\
	276	.property = "model",\
	277	.value = stringify(2),\
	278	},{\
	279	.driver = "Nehalem-" TYPE_X86_CPU,\
	280	.property = "level",\
	281	.value = stringify(2),\
	282	},{\
	283	.driver = "virtio-net-pci",\
	284	.property = "any_layout",\
	285	.value = "off",\
	286	},{\
	287	.driver = TYPE_X86_CPU,\
	288	.property = "pmu",\
	289	.value = "on",\
	290	}
	291
	292	#define PC_COMPAT_1_4 \
	293	PC_COMPAT_1_5, \
	294	{\
	295	.driver = "scsi-hd",\
	296	.property = "discard_granularity",\
	297	.value = stringify(0),\
	298	},{\
	299	.driver = "scsi-cd",\
	300	.property = "discard_granularity",\
	301	.value = stringify(0),\
	302	},{\
	303	.driver = "scsi-disk",\
	304	.property = "discard_granularity",\
	305	.value = stringify(0),\
	306	},{\
	307	.driver = "ide-hd",\
	308	.property = "discard_granularity",\
	309	.value = stringify(0),\
	310	},{\
	311	.driver = "ide-cd",\
	312	.property = "discard_granularity",\
	313	.value = stringify(0),\
	314	},{\
	315	.driver = "ide-drive",\
	316	.property = "discard_granularity",\
	317	.value = stringify(0),\
	318	},{\
	319	.driver = "virtio-blk-pci",\
	320	.property = "discard_granularity",\
	321	.value = stringify(0),\
	322	},{\
	323	.driver = "virtio-serial-pci",\
	324	.property = "vectors",\
	325	/* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
	326	.value = stringify(0xFFFFFFFF),\
	327	},{ \
	328	.driver = "virtio-net-pci", \
	329	.property = "ctrl_guest_offloads", \
	330	.value = "off", \
	331	},{\
	332	.driver = "e1000",\
	333	.property = "romfile",\
	334	.value = "pxe-e1000.rom",\
	335	},{\
	336	.driver = "ne2k_pci",\
	337	.property = "romfile",\
	338	.value = "pxe-ne2k_pci.rom",\
	339	},{\
	340	.driver = "pcnet",\
	341	.property = "romfile",\
	342	.value = "pxe-pcnet.rom",\
	343	},{\
	344	.driver = "rtl8139",\
	345	.property = "romfile",\
	346	.value = "pxe-rtl8139.rom",\
	347	},{\
	348	.driver = "virtio-net-pci",\
	349	.property = "romfile",\
	350	.value = "pxe-virtio.rom",\
	351	},{\
	352	.driver = "486-" TYPE_X86_CPU,\
	353	.property = "model",\
	354	.value = stringify(0),\
	355	}
	356
	357	#define PC_COMMON_MACHINE_OPTIONS \
	358	.default_boot_order = "cad"
	359
	360	#define PC_DEFAULT_MACHINE_OPTIONS \
	361	PC_COMMON_MACHINE_OPTIONS, \
	362	.hot_add_cpu = pc_hot_add_cpu, \
	363	.max_cpus = 255
	364
	365	#endif