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1 | /* | |
2 | * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the Free | |
6 | * Software Foundation; either version 2 of the License, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * The full GNU General Public License is included in this distribution in the | |
15 | * file called COPYING. | |
16 | */ | |
17 | #ifndef LINUX_DMAENGINE_H | |
18 | #define LINUX_DMAENGINE_H | |
19 | ||
20 | #include <linux/device.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/uio.h> | |
23 | #include <linux/bug.h> | |
24 | #include <linux/scatterlist.h> | |
25 | #include <linux/bitmap.h> | |
26 | #include <linux/types.h> | |
27 | #include <asm/page.h> | |
28 | ||
29 | /** | |
30 | * typedef dma_cookie_t - an opaque DMA cookie | |
31 | * | |
32 | * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code | |
33 | */ | |
34 | typedef s32 dma_cookie_t; | |
35 | #define DMA_MIN_COOKIE 1 | |
36 | ||
37 | static inline int dma_submit_error(dma_cookie_t cookie) | |
38 | { | |
39 | return cookie < 0 ? cookie : 0; | |
40 | } | |
41 | ||
42 | /** | |
43 | * enum dma_status - DMA transaction status | |
44 | * @DMA_COMPLETE: transaction completed | |
45 | * @DMA_IN_PROGRESS: transaction not yet processed | |
46 | * @DMA_PAUSED: transaction is paused | |
47 | * @DMA_ERROR: transaction failed | |
48 | */ | |
49 | enum dma_status { | |
50 | DMA_COMPLETE, | |
51 | DMA_IN_PROGRESS, | |
52 | DMA_PAUSED, | |
53 | DMA_ERROR, | |
54 | }; | |
55 | ||
56 | /** | |
57 | * enum dma_transaction_type - DMA transaction types/indexes | |
58 | * | |
59 | * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is | |
60 | * automatically set as dma devices are registered. | |
61 | */ | |
62 | enum dma_transaction_type { | |
63 | DMA_MEMCPY, | |
64 | DMA_XOR, | |
65 | DMA_PQ, | |
66 | DMA_XOR_VAL, | |
67 | DMA_PQ_VAL, | |
68 | DMA_MEMSET, | |
69 | DMA_MEMSET_SG, | |
70 | DMA_INTERRUPT, | |
71 | DMA_SG, | |
72 | DMA_PRIVATE, | |
73 | DMA_ASYNC_TX, | |
74 | DMA_SLAVE, | |
75 | DMA_CYCLIC, | |
76 | DMA_INTERLEAVE, | |
77 | /* last transaction type for creation of the capabilities mask */ | |
78 | DMA_TX_TYPE_END, | |
79 | }; | |
80 | ||
81 | /** | |
82 | * enum dma_transfer_direction - dma transfer mode and direction indicator | |
83 | * @DMA_MEM_TO_MEM: Async/Memcpy mode | |
84 | * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device | |
85 | * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory | |
86 | * @DMA_DEV_TO_DEV: Slave mode & From Device to Device | |
87 | */ | |
88 | enum dma_transfer_direction { | |
89 | DMA_MEM_TO_MEM, | |
90 | DMA_MEM_TO_DEV, | |
91 | DMA_DEV_TO_MEM, | |
92 | DMA_DEV_TO_DEV, | |
93 | DMA_TRANS_NONE, | |
94 | }; | |
95 | ||
96 | /** | |
97 | * Interleaved Transfer Request | |
98 | * ---------------------------- | |
99 | * A chunk is collection of contiguous bytes to be transfered. | |
100 | * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG). | |
101 | * ICGs may or maynot change between chunks. | |
102 | * A FRAME is the smallest series of contiguous {chunk,icg} pairs, | |
103 | * that when repeated an integral number of times, specifies the transfer. | |
104 | * A transfer template is specification of a Frame, the number of times | |
105 | * it is to be repeated and other per-transfer attributes. | |
106 | * | |
107 | * Practically, a client driver would have ready a template for each | |
108 | * type of transfer it is going to need during its lifetime and | |
109 | * set only 'src_start' and 'dst_start' before submitting the requests. | |
110 | * | |
111 | * | |
112 | * | Frame-1 | Frame-2 | ~ | Frame-'numf' | | |
113 | * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...| | |
114 | * | |
115 | * == Chunk size | |
116 | * ... ICG | |
117 | */ | |
118 | ||
119 | /** | |
120 | * struct data_chunk - Element of scatter-gather list that makes a frame. | |
121 | * @size: Number of bytes to read from source. | |
122 | * size_dst := fn(op, size_src), so doesn't mean much for destination. | |
123 | * @icg: Number of bytes to jump after last src/dst address of this | |
124 | * chunk and before first src/dst address for next chunk. | |
125 | * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false. | |
126 | * Ignored for src(assumed 0), if src_inc is true and src_sgl is false. | |
127 | * @dst_icg: Number of bytes to jump after last dst address of this | |
128 | * chunk and before the first dst address for next chunk. | |
129 | * Ignored if dst_inc is true and dst_sgl is false. | |
130 | * @src_icg: Number of bytes to jump after last src address of this | |
131 | * chunk and before the first src address for next chunk. | |
132 | * Ignored if src_inc is true and src_sgl is false. | |
133 | */ | |
134 | struct data_chunk { | |
135 | size_t size; | |
136 | size_t icg; | |
137 | size_t dst_icg; | |
138 | size_t src_icg; | |
139 | }; | |
140 | ||
141 | /** | |
142 | * struct dma_interleaved_template - Template to convey DMAC the transfer pattern | |
143 | * and attributes. | |
144 | * @src_start: Bus address of source for the first chunk. | |
145 | * @dst_start: Bus address of destination for the first chunk. | |
146 | * @dir: Specifies the type of Source and Destination. | |
147 | * @src_inc: If the source address increments after reading from it. | |
148 | * @dst_inc: If the destination address increments after writing to it. | |
149 | * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read). | |
150 | * Otherwise, source is read contiguously (icg ignored). | |
151 | * Ignored if src_inc is false. | |
152 | * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write). | |
153 | * Otherwise, destination is filled contiguously (icg ignored). | |
154 | * Ignored if dst_inc is false. | |
155 | * @numf: Number of frames in this template. | |
156 | * @frame_size: Number of chunks in a frame i.e, size of sgl[]. | |
157 | * @sgl: Array of {chunk,icg} pairs that make up a frame. | |
158 | */ | |
159 | struct dma_interleaved_template { | |
160 | dma_addr_t src_start; | |
161 | dma_addr_t dst_start; | |
162 | enum dma_transfer_direction dir; | |
163 | bool src_inc; | |
164 | bool dst_inc; | |
165 | bool src_sgl; | |
166 | bool dst_sgl; | |
167 | size_t numf; | |
168 | size_t frame_size; | |
169 | struct data_chunk sgl[0]; | |
170 | }; | |
171 | ||
172 | /** | |
173 | * enum dma_ctrl_flags - DMA flags to augment operation preparation, | |
174 | * control completion, and communicate status. | |
175 | * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of | |
176 | * this transaction | |
177 | * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client | |
178 | * acknowledges receipt, i.e. has has a chance to establish any dependency | |
179 | * chains | |
180 | * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q | |
181 | * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P | |
182 | * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as | |
183 | * sources that were the result of a previous operation, in the case of a PQ | |
184 | * operation it continues the calculation with new sources | |
185 | * @DMA_PREP_FENCE - tell the driver that subsequent operations depend | |
186 | * on the result of this operation | |
187 | * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till | |
188 | * cleared or freed | |
189 | */ | |
190 | enum dma_ctrl_flags { | |
191 | DMA_PREP_INTERRUPT = (1 << 0), | |
192 | DMA_CTRL_ACK = (1 << 1), | |
193 | DMA_PREP_PQ_DISABLE_P = (1 << 2), | |
194 | DMA_PREP_PQ_DISABLE_Q = (1 << 3), | |
195 | DMA_PREP_CONTINUE = (1 << 4), | |
196 | DMA_PREP_FENCE = (1 << 5), | |
197 | DMA_CTRL_REUSE = (1 << 6), | |
198 | }; | |
199 | ||
200 | /** | |
201 | * enum sum_check_bits - bit position of pq_check_flags | |
202 | */ | |
203 | enum sum_check_bits { | |
204 | SUM_CHECK_P = 0, | |
205 | SUM_CHECK_Q = 1, | |
206 | }; | |
207 | ||
208 | /** | |
209 | * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations | |
210 | * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise | |
211 | * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise | |
212 | */ | |
213 | enum sum_check_flags { | |
214 | SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P), | |
215 | SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q), | |
216 | }; | |
217 | ||
218 | ||
219 | /** | |
220 | * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t. | |
221 | * See linux/cpumask.h | |
222 | */ | |
223 | typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |
224 | ||
225 | /** | |
226 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | |
227 | * @memcpy_count: transaction counter | |
228 | * @bytes_transferred: byte counter | |
229 | */ | |
230 | ||
231 | struct dma_chan_percpu { | |
232 | /* stats */ | |
233 | unsigned long memcpy_count; | |
234 | unsigned long bytes_transferred; | |
235 | }; | |
236 | ||
237 | /** | |
238 | * struct dma_router - DMA router structure | |
239 | * @dev: pointer to the DMA router device | |
240 | * @route_free: function to be called when the route can be disconnected | |
241 | */ | |
242 | struct dma_router { | |
243 | struct device *dev; | |
244 | void (*route_free)(struct device *dev, void *route_data); | |
245 | }; | |
246 | ||
247 | /** | |
248 | * struct dma_chan - devices supply DMA channels, clients use them | |
249 | * @device: ptr to the dma device who supplies this channel, always !%NULL | |
250 | * @cookie: last cookie value returned to client | |
251 | * @completed_cookie: last completed cookie for this channel | |
252 | * @chan_id: channel ID for sysfs | |
253 | * @dev: class device for sysfs | |
254 | * @device_node: used to add this to the device chan list | |
255 | * @local: per-cpu pointer to a struct dma_chan_percpu | |
256 | * @client_count: how many clients are using this channel | |
257 | * @table_count: number of appearances in the mem-to-mem allocation table | |
258 | * @router: pointer to the DMA router structure | |
259 | * @route_data: channel specific data for the router | |
260 | * @private: private data for certain client-channel associations | |
261 | */ | |
262 | struct dma_chan { | |
263 | struct dma_device *device; | |
264 | dma_cookie_t cookie; | |
265 | dma_cookie_t completed_cookie; | |
266 | ||
267 | /* sysfs */ | |
268 | int chan_id; | |
269 | struct dma_chan_dev *dev; | |
270 | ||
271 | struct list_head device_node; | |
272 | struct dma_chan_percpu __percpu *local; | |
273 | int client_count; | |
274 | int table_count; | |
275 | ||
276 | /* DMA router */ | |
277 | struct dma_router *router; | |
278 | void *route_data; | |
279 | ||
280 | void *private; | |
281 | }; | |
282 | ||
283 | /** | |
284 | * struct dma_chan_dev - relate sysfs device node to backing channel device | |
285 | * @chan: driver channel device | |
286 | * @device: sysfs device | |
287 | * @dev_id: parent dma_device dev_id | |
288 | * @idr_ref: reference count to gate release of dma_device dev_id | |
289 | */ | |
290 | struct dma_chan_dev { | |
291 | struct dma_chan *chan; | |
292 | struct device device; | |
293 | int dev_id; | |
294 | atomic_t *idr_ref; | |
295 | }; | |
296 | ||
297 | /** | |
298 | * enum dma_slave_buswidth - defines bus width of the DMA slave | |
299 | * device, source or target buses | |
300 | */ | |
301 | enum dma_slave_buswidth { | |
302 | DMA_SLAVE_BUSWIDTH_UNDEFINED = 0, | |
303 | DMA_SLAVE_BUSWIDTH_1_BYTE = 1, | |
304 | DMA_SLAVE_BUSWIDTH_2_BYTES = 2, | |
305 | DMA_SLAVE_BUSWIDTH_3_BYTES = 3, | |
306 | DMA_SLAVE_BUSWIDTH_4_BYTES = 4, | |
307 | DMA_SLAVE_BUSWIDTH_8_BYTES = 8, | |
308 | DMA_SLAVE_BUSWIDTH_16_BYTES = 16, | |
309 | DMA_SLAVE_BUSWIDTH_32_BYTES = 32, | |
310 | DMA_SLAVE_BUSWIDTH_64_BYTES = 64, | |
311 | }; | |
312 | ||
313 | /** | |
314 | * struct dma_slave_config - dma slave channel runtime config | |
315 | * @direction: whether the data shall go in or out on this slave | |
316 | * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are | |
317 | * legal values. DEPRECATED, drivers should use the direction argument | |
318 | * to the device_prep_slave_sg and device_prep_dma_cyclic functions or | |
319 | * the dir field in the dma_interleaved_template structure. | |
320 | * @src_addr: this is the physical address where DMA slave data | |
321 | * should be read (RX), if the source is memory this argument is | |
322 | * ignored. | |
323 | * @dst_addr: this is the physical address where DMA slave data | |
324 | * should be written (TX), if the source is memory this argument | |
325 | * is ignored. | |
326 | * @src_addr_width: this is the width in bytes of the source (RX) | |
327 | * register where DMA data shall be read. If the source | |
328 | * is memory this may be ignored depending on architecture. | |
329 | * Legal values: 1, 2, 4, 8. | |
330 | * @dst_addr_width: same as src_addr_width but for destination | |
331 | * target (TX) mutatis mutandis. | |
332 | * @src_maxburst: the maximum number of words (note: words, as in | |
333 | * units of the src_addr_width member, not bytes) that can be sent | |
334 | * in one burst to the device. Typically something like half the | |
335 | * FIFO depth on I/O peripherals so you don't overflow it. This | |
336 | * may or may not be applicable on memory sources. | |
337 | * @dst_maxburst: same as src_maxburst but for destination target | |
338 | * mutatis mutandis. | |
339 | * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill | |
340 | * with 'true' if peripheral should be flow controller. Direction will be | |
341 | * selected at Runtime. | |
342 | * @slave_id: Slave requester id. Only valid for slave channels. The dma | |
343 | * slave peripheral will have unique id as dma requester which need to be | |
344 | * pass as slave config. | |
345 | * | |
346 | * This struct is passed in as configuration data to a DMA engine | |
347 | * in order to set up a certain channel for DMA transport at runtime. | |
348 | * The DMA device/engine has to provide support for an additional | |
349 | * callback in the dma_device structure, device_config and this struct | |
350 | * will then be passed in as an argument to the function. | |
351 | * | |
352 | * The rationale for adding configuration information to this struct is as | |
353 | * follows: if it is likely that more than one DMA slave controllers in | |
354 | * the world will support the configuration option, then make it generic. | |
355 | * If not: if it is fixed so that it be sent in static from the platform | |
356 | * data, then prefer to do that. | |
357 | */ | |
358 | struct dma_slave_config { | |
359 | enum dma_transfer_direction direction; | |
360 | phys_addr_t src_addr; | |
361 | phys_addr_t dst_addr; | |
362 | enum dma_slave_buswidth src_addr_width; | |
363 | enum dma_slave_buswidth dst_addr_width; | |
364 | u32 src_maxburst; | |
365 | u32 dst_maxburst; | |
366 | bool device_fc; | |
367 | unsigned int slave_id; | |
368 | }; | |
369 | ||
370 | /** | |
371 | * enum dma_residue_granularity - Granularity of the reported transfer residue | |
372 | * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The | |
373 | * DMA channel is only able to tell whether a descriptor has been completed or | |
374 | * not, which means residue reporting is not supported by this channel. The | |
375 | * residue field of the dma_tx_state field will always be 0. | |
376 | * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully | |
377 | * completed segment of the transfer (For cyclic transfers this is after each | |
378 | * period). This is typically implemented by having the hardware generate an | |
379 | * interrupt after each transferred segment and then the drivers updates the | |
380 | * outstanding residue by the size of the segment. Another possibility is if | |
381 | * the hardware supports scatter-gather and the segment descriptor has a field | |
382 | * which gets set after the segment has been completed. The driver then counts | |
383 | * the number of segments without the flag set to compute the residue. | |
384 | * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred | |
385 | * burst. This is typically only supported if the hardware has a progress | |
386 | * register of some sort (E.g. a register with the current read/write address | |
387 | * or a register with the amount of bursts/beats/bytes that have been | |
388 | * transferred or still need to be transferred). | |
389 | */ | |
390 | enum dma_residue_granularity { | |
391 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0, | |
392 | DMA_RESIDUE_GRANULARITY_SEGMENT = 1, | |
393 | DMA_RESIDUE_GRANULARITY_BURST = 2, | |
394 | }; | |
395 | ||
396 | /* struct dma_slave_caps - expose capabilities of a slave channel only | |
397 | * | |
398 | * @src_addr_widths: bit mask of src addr widths the channel supports | |
399 | * @dst_addr_widths: bit mask of dstn addr widths the channel supports | |
400 | * @directions: bit mask of slave direction the channel supported | |
401 | * since the enum dma_transfer_direction is not defined as bits for each | |
402 | * type of direction, the dma controller should fill (1 << <TYPE>) and same | |
403 | * should be checked by controller as well | |
404 | * @max_burst: max burst capability per-transfer | |
405 | * @cmd_pause: true, if pause and thereby resume is supported | |
406 | * @cmd_terminate: true, if terminate cmd is supported | |
407 | * @residue_granularity: granularity of the reported transfer residue | |
408 | * @descriptor_reuse: if a descriptor can be reused by client and | |
409 | * resubmitted multiple times | |
410 | */ | |
411 | struct dma_slave_caps { | |
412 | u32 src_addr_widths; | |
413 | u32 dst_addr_widths; | |
414 | u32 directions; | |
415 | u32 max_burst; | |
416 | bool cmd_pause; | |
417 | bool cmd_terminate; | |
418 | enum dma_residue_granularity residue_granularity; | |
419 | bool descriptor_reuse; | |
420 | }; | |
421 | ||
422 | static inline const char *dma_chan_name(struct dma_chan *chan) | |
423 | { | |
424 | return dev_name(&chan->dev->device); | |
425 | } | |
426 | ||
427 | void dma_chan_cleanup(struct kref *kref); | |
428 | ||
429 | /** | |
430 | * typedef dma_filter_fn - callback filter for dma_request_channel | |
431 | * @chan: channel to be reviewed | |
432 | * @filter_param: opaque parameter passed through dma_request_channel | |
433 | * | |
434 | * When this optional parameter is specified in a call to dma_request_channel a | |
435 | * suitable channel is passed to this routine for further dispositioning before | |
436 | * being returned. Where 'suitable' indicates a non-busy channel that | |
437 | * satisfies the given capability mask. It returns 'true' to indicate that the | |
438 | * channel is suitable. | |
439 | */ | |
440 | typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param); | |
441 | ||
442 | typedef void (*dma_async_tx_callback)(void *dma_async_param); | |
443 | ||
444 | struct dmaengine_unmap_data { | |
445 | u8 map_cnt; | |
446 | u8 to_cnt; | |
447 | u8 from_cnt; | |
448 | u8 bidi_cnt; | |
449 | struct device *dev; | |
450 | struct kref kref; | |
451 | size_t len; | |
452 | dma_addr_t addr[0]; | |
453 | }; | |
454 | ||
455 | /** | |
456 | * struct dma_async_tx_descriptor - async transaction descriptor | |
457 | * ---dma generic offload fields--- | |
458 | * @cookie: tracking cookie for this transaction, set to -EBUSY if | |
459 | * this tx is sitting on a dependency list | |
460 | * @flags: flags to augment operation preparation, control completion, and | |
461 | * communicate status | |
462 | * @phys: physical address of the descriptor | |
463 | * @chan: target channel for this operation | |
464 | * @tx_submit: accept the descriptor, assign ordered cookie and mark the | |
465 | * descriptor pending. To be pushed on .issue_pending() call | |
466 | * @callback: routine to call after this operation is complete | |
467 | * @callback_param: general parameter to pass to the callback routine | |
468 | * ---async_tx api specific fields--- | |
469 | * @next: at completion submit this descriptor | |
470 | * @parent: pointer to the next level up in the dependency chain | |
471 | * @lock: protect the parent and next pointers | |
472 | */ | |
473 | struct dma_async_tx_descriptor { | |
474 | dma_cookie_t cookie; | |
475 | enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */ | |
476 | dma_addr_t phys; | |
477 | struct dma_chan *chan; | |
478 | dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx); | |
479 | int (*desc_free)(struct dma_async_tx_descriptor *tx); | |
480 | dma_async_tx_callback callback; | |
481 | void *callback_param; | |
482 | struct dmaengine_unmap_data *unmap; | |
483 | #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH | |
484 | struct dma_async_tx_descriptor *next; | |
485 | struct dma_async_tx_descriptor *parent; | |
486 | spinlock_t lock; | |
487 | #endif | |
488 | }; | |
489 | ||
490 | #ifdef CONFIG_DMA_ENGINE | |
491 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, | |
492 | struct dmaengine_unmap_data *unmap) | |
493 | { | |
494 | kref_get(&unmap->kref); | |
495 | tx->unmap = unmap; | |
496 | } | |
497 | ||
498 | struct dmaengine_unmap_data * | |
499 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags); | |
500 | void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap); | |
501 | #else | |
502 | static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx, | |
503 | struct dmaengine_unmap_data *unmap) | |
504 | { | |
505 | } | |
506 | static inline struct dmaengine_unmap_data * | |
507 | dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags) | |
508 | { | |
509 | return NULL; | |
510 | } | |
511 | static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap) | |
512 | { | |
513 | } | |
514 | #endif | |
515 | ||
516 | static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx) | |
517 | { | |
518 | if (tx->unmap) { | |
519 | dmaengine_unmap_put(tx->unmap); | |
520 | tx->unmap = NULL; | |
521 | } | |
522 | } | |
523 | ||
524 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH | |
525 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
526 | { | |
527 | } | |
528 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
529 | { | |
530 | } | |
531 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
532 | { | |
533 | BUG(); | |
534 | } | |
535 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
536 | { | |
537 | } | |
538 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
539 | { | |
540 | } | |
541 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
542 | { | |
543 | return NULL; | |
544 | } | |
545 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
546 | { | |
547 | return NULL; | |
548 | } | |
549 | ||
550 | #else | |
551 | static inline void txd_lock(struct dma_async_tx_descriptor *txd) | |
552 | { | |
553 | spin_lock_bh(&txd->lock); | |
554 | } | |
555 | static inline void txd_unlock(struct dma_async_tx_descriptor *txd) | |
556 | { | |
557 | spin_unlock_bh(&txd->lock); | |
558 | } | |
559 | static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next) | |
560 | { | |
561 | txd->next = next; | |
562 | next->parent = txd; | |
563 | } | |
564 | static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd) | |
565 | { | |
566 | txd->parent = NULL; | |
567 | } | |
568 | static inline void txd_clear_next(struct dma_async_tx_descriptor *txd) | |
569 | { | |
570 | txd->next = NULL; | |
571 | } | |
572 | static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd) | |
573 | { | |
574 | return txd->parent; | |
575 | } | |
576 | static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd) | |
577 | { | |
578 | return txd->next; | |
579 | } | |
580 | #endif | |
581 | ||
582 | /** | |
583 | * struct dma_tx_state - filled in to report the status of | |
584 | * a transfer. | |
585 | * @last: last completed DMA cookie | |
586 | * @used: last issued DMA cookie (i.e. the one in progress) | |
587 | * @residue: the remaining number of bytes left to transmit | |
588 | * on the selected transfer for states DMA_IN_PROGRESS and | |
589 | * DMA_PAUSED if this is implemented in the driver, else 0 | |
590 | */ | |
591 | struct dma_tx_state { | |
592 | dma_cookie_t last; | |
593 | dma_cookie_t used; | |
594 | u32 residue; | |
595 | }; | |
596 | ||
597 | /** | |
598 | * enum dmaengine_alignment - defines alignment of the DMA async tx | |
599 | * buffers | |
600 | */ | |
601 | enum dmaengine_alignment { | |
602 | DMAENGINE_ALIGN_1_BYTE = 0, | |
603 | DMAENGINE_ALIGN_2_BYTES = 1, | |
604 | DMAENGINE_ALIGN_4_BYTES = 2, | |
605 | DMAENGINE_ALIGN_8_BYTES = 3, | |
606 | DMAENGINE_ALIGN_16_BYTES = 4, | |
607 | DMAENGINE_ALIGN_32_BYTES = 5, | |
608 | DMAENGINE_ALIGN_64_BYTES = 6, | |
609 | }; | |
610 | ||
611 | /** | |
612 | * struct dma_slave_map - associates slave device and it's slave channel with | |
613 | * parameter to be used by a filter function | |
614 | * @devname: name of the device | |
615 | * @slave: slave channel name | |
616 | * @param: opaque parameter to pass to struct dma_filter.fn | |
617 | */ | |
618 | struct dma_slave_map { | |
619 | const char *devname; | |
620 | const char *slave; | |
621 | void *param; | |
622 | }; | |
623 | ||
624 | /** | |
625 | * struct dma_filter - information for slave device/channel to filter_fn/param | |
626 | * mapping | |
627 | * @fn: filter function callback | |
628 | * @mapcnt: number of slave device/channel in the map | |
629 | * @map: array of channel to filter mapping data | |
630 | */ | |
631 | struct dma_filter { | |
632 | dma_filter_fn fn; | |
633 | int mapcnt; | |
634 | const struct dma_slave_map *map; | |
635 | }; | |
636 | ||
637 | /** | |
638 | * struct dma_device - info on the entity supplying DMA services | |
639 | * @chancnt: how many DMA channels are supported | |
640 | * @privatecnt: how many DMA channels are requested by dma_request_channel | |
641 | * @channels: the list of struct dma_chan | |
642 | * @global_node: list_head for global dma_device_list | |
643 | * @filter: information for device/slave to filter function/param mapping | |
644 | * @cap_mask: one or more dma_capability flags | |
645 | * @max_xor: maximum number of xor sources, 0 if no capability | |
646 | * @max_pq: maximum number of PQ sources and PQ-continue capability | |
647 | * @copy_align: alignment shift for memcpy operations | |
648 | * @xor_align: alignment shift for xor operations | |
649 | * @pq_align: alignment shift for pq operations | |
650 | * @fill_align: alignment shift for memset operations | |
651 | * @dev_id: unique device ID | |
652 | * @dev: struct device reference for dma mapping api | |
653 | * @src_addr_widths: bit mask of src addr widths the device supports | |
654 | * @dst_addr_widths: bit mask of dst addr widths the device supports | |
655 | * @directions: bit mask of slave direction the device supports since | |
656 | * the enum dma_transfer_direction is not defined as bits for | |
657 | * each type of direction, the dma controller should fill (1 << | |
658 | * <TYPE>) and same should be checked by controller as well | |
659 | * @max_burst: max burst capability per-transfer | |
660 | * @residue_granularity: granularity of the transfer residue reported | |
661 | * by tx_status | |
662 | * @device_alloc_chan_resources: allocate resources and return the | |
663 | * number of allocated descriptors | |
664 | * @device_free_chan_resources: release DMA channel's resources | |
665 | * @device_prep_dma_memcpy: prepares a memcpy operation | |
666 | * @device_prep_dma_xor: prepares a xor operation | |
667 | * @device_prep_dma_xor_val: prepares a xor validation operation | |
668 | * @device_prep_dma_pq: prepares a pq operation | |
669 | * @device_prep_dma_pq_val: prepares a pqzero_sum operation | |
670 | * @device_prep_dma_memset: prepares a memset operation | |
671 | * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list | |
672 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | |
673 | * @device_prep_slave_sg: prepares a slave dma operation | |
674 | * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio. | |
675 | * The function takes a buffer of size buf_len. The callback function will | |
676 | * be called after period_len bytes have been transferred. | |
677 | * @device_prep_interleaved_dma: Transfer expression in a generic way. | |
678 | * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address | |
679 | * @device_config: Pushes a new configuration to a channel, return 0 or an error | |
680 | * code | |
681 | * @device_pause: Pauses any transfer happening on a channel. Returns | |
682 | * 0 or an error code | |
683 | * @device_resume: Resumes any transfer on a channel previously | |
684 | * paused. Returns 0 or an error code | |
685 | * @device_terminate_all: Aborts all transfers on a channel. Returns 0 | |
686 | * or an error code | |
687 | * @device_synchronize: Synchronizes the termination of a transfers to the | |
688 | * current context. | |
689 | * @device_tx_status: poll for transaction completion, the optional | |
690 | * txstate parameter can be supplied with a pointer to get a | |
691 | * struct with auxiliary transfer status information, otherwise the call | |
692 | * will just return a simple status code | |
693 | * @device_issue_pending: push pending transactions to hardware | |
694 | * @descriptor_reuse: a submitted transfer can be resubmitted after completion | |
695 | */ | |
696 | struct dma_device { | |
697 | ||
698 | unsigned int chancnt; | |
699 | unsigned int privatecnt; | |
700 | struct list_head channels; | |
701 | struct list_head global_node; | |
702 | struct dma_filter filter; | |
703 | dma_cap_mask_t cap_mask; | |
704 | unsigned short max_xor; | |
705 | unsigned short max_pq; | |
706 | enum dmaengine_alignment copy_align; | |
707 | enum dmaengine_alignment xor_align; | |
708 | enum dmaengine_alignment pq_align; | |
709 | enum dmaengine_alignment fill_align; | |
710 | #define DMA_HAS_PQ_CONTINUE (1 << 15) | |
711 | ||
712 | int dev_id; | |
713 | struct device *dev; | |
714 | ||
715 | u32 src_addr_widths; | |
716 | u32 dst_addr_widths; | |
717 | u32 directions; | |
718 | u32 max_burst; | |
719 | bool descriptor_reuse; | |
720 | enum dma_residue_granularity residue_granularity; | |
721 | ||
722 | int (*device_alloc_chan_resources)(struct dma_chan *chan); | |
723 | void (*device_free_chan_resources)(struct dma_chan *chan); | |
724 | ||
725 | struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)( | |
726 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, | |
727 | size_t len, unsigned long flags); | |
728 | struct dma_async_tx_descriptor *(*device_prep_dma_xor)( | |
729 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, | |
730 | unsigned int src_cnt, size_t len, unsigned long flags); | |
731 | struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)( | |
732 | struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt, | |
733 | size_t len, enum sum_check_flags *result, unsigned long flags); | |
734 | struct dma_async_tx_descriptor *(*device_prep_dma_pq)( | |
735 | struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
736 | unsigned int src_cnt, const unsigned char *scf, | |
737 | size_t len, unsigned long flags); | |
738 | struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)( | |
739 | struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
740 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
741 | enum sum_check_flags *pqres, unsigned long flags); | |
742 | struct dma_async_tx_descriptor *(*device_prep_dma_memset)( | |
743 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, | |
744 | unsigned long flags); | |
745 | struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)( | |
746 | struct dma_chan *chan, struct scatterlist *sg, | |
747 | unsigned int nents, int value, unsigned long flags); | |
748 | struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)( | |
749 | struct dma_chan *chan, unsigned long flags); | |
750 | struct dma_async_tx_descriptor *(*device_prep_dma_sg)( | |
751 | struct dma_chan *chan, | |
752 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
753 | struct scatterlist *src_sg, unsigned int src_nents, | |
754 | unsigned long flags); | |
755 | ||
756 | struct dma_async_tx_descriptor *(*device_prep_slave_sg)( | |
757 | struct dma_chan *chan, struct scatterlist *sgl, | |
758 | unsigned int sg_len, enum dma_transfer_direction direction, | |
759 | unsigned long flags, void *context); | |
760 | struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)( | |
761 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
762 | size_t period_len, enum dma_transfer_direction direction, | |
763 | unsigned long flags); | |
764 | struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)( | |
765 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
766 | unsigned long flags); | |
767 | struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)( | |
768 | struct dma_chan *chan, dma_addr_t dst, u64 data, | |
769 | unsigned long flags); | |
770 | ||
771 | int (*device_config)(struct dma_chan *chan, | |
772 | struct dma_slave_config *config); | |
773 | int (*device_pause)(struct dma_chan *chan); | |
774 | int (*device_resume)(struct dma_chan *chan); | |
775 | int (*device_terminate_all)(struct dma_chan *chan); | |
776 | void (*device_synchronize)(struct dma_chan *chan); | |
777 | ||
778 | enum dma_status (*device_tx_status)(struct dma_chan *chan, | |
779 | dma_cookie_t cookie, | |
780 | struct dma_tx_state *txstate); | |
781 | void (*device_issue_pending)(struct dma_chan *chan); | |
782 | }; | |
783 | ||
784 | static inline int dmaengine_slave_config(struct dma_chan *chan, | |
785 | struct dma_slave_config *config) | |
786 | { | |
787 | if (chan->device->device_config) | |
788 | return chan->device->device_config(chan, config); | |
789 | ||
790 | return -ENOSYS; | |
791 | } | |
792 | ||
793 | static inline bool is_slave_direction(enum dma_transfer_direction direction) | |
794 | { | |
795 | return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM); | |
796 | } | |
797 | ||
798 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single( | |
799 | struct dma_chan *chan, dma_addr_t buf, size_t len, | |
800 | enum dma_transfer_direction dir, unsigned long flags) | |
801 | { | |
802 | struct scatterlist sg; | |
803 | sg_init_table(&sg, 1); | |
804 | sg_dma_address(&sg) = buf; | |
805 | sg_dma_len(&sg) = len; | |
806 | ||
807 | if (!chan || !chan->device || !chan->device->device_prep_slave_sg) | |
808 | return NULL; | |
809 | ||
810 | return chan->device->device_prep_slave_sg(chan, &sg, 1, | |
811 | dir, flags, NULL); | |
812 | } | |
813 | ||
814 | static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg( | |
815 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
816 | enum dma_transfer_direction dir, unsigned long flags) | |
817 | { | |
818 | if (!chan || !chan->device || !chan->device->device_prep_slave_sg) | |
819 | return NULL; | |
820 | ||
821 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
822 | dir, flags, NULL); | |
823 | } | |
824 | ||
825 | #ifdef CONFIG_RAPIDIO_DMA_ENGINE | |
826 | struct rio_dma_ext; | |
827 | static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg( | |
828 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
829 | enum dma_transfer_direction dir, unsigned long flags, | |
830 | struct rio_dma_ext *rio_ext) | |
831 | { | |
832 | if (!chan || !chan->device || !chan->device->device_prep_slave_sg) | |
833 | return NULL; | |
834 | ||
835 | return chan->device->device_prep_slave_sg(chan, sgl, sg_len, | |
836 | dir, flags, rio_ext); | |
837 | } | |
838 | #endif | |
839 | ||
840 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic( | |
841 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
842 | size_t period_len, enum dma_transfer_direction dir, | |
843 | unsigned long flags) | |
844 | { | |
845 | if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic) | |
846 | return NULL; | |
847 | ||
848 | return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len, | |
849 | period_len, dir, flags); | |
850 | } | |
851 | ||
852 | static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( | |
853 | struct dma_chan *chan, struct dma_interleaved_template *xt, | |
854 | unsigned long flags) | |
855 | { | |
856 | if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma) | |
857 | return NULL; | |
858 | ||
859 | return chan->device->device_prep_interleaved_dma(chan, xt, flags); | |
860 | } | |
861 | ||
862 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset( | |
863 | struct dma_chan *chan, dma_addr_t dest, int value, size_t len, | |
864 | unsigned long flags) | |
865 | { | |
866 | if (!chan || !chan->device || !chan->device->device_prep_dma_memset) | |
867 | return NULL; | |
868 | ||
869 | return chan->device->device_prep_dma_memset(chan, dest, value, | |
870 | len, flags); | |
871 | } | |
872 | ||
873 | static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg( | |
874 | struct dma_chan *chan, | |
875 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
876 | struct scatterlist *src_sg, unsigned int src_nents, | |
877 | unsigned long flags) | |
878 | { | |
879 | if (!chan || !chan->device || !chan->device->device_prep_dma_sg) | |
880 | return NULL; | |
881 | ||
882 | return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents, | |
883 | src_sg, src_nents, flags); | |
884 | } | |
885 | ||
886 | /** | |
887 | * dmaengine_terminate_all() - Terminate all active DMA transfers | |
888 | * @chan: The channel for which to terminate the transfers | |
889 | * | |
890 | * This function is DEPRECATED use either dmaengine_terminate_sync() or | |
891 | * dmaengine_terminate_async() instead. | |
892 | */ | |
893 | static inline int dmaengine_terminate_all(struct dma_chan *chan) | |
894 | { | |
895 | if (chan->device->device_terminate_all) | |
896 | return chan->device->device_terminate_all(chan); | |
897 | ||
898 | return -ENOSYS; | |
899 | } | |
900 | ||
901 | /** | |
902 | * dmaengine_terminate_async() - Terminate all active DMA transfers | |
903 | * @chan: The channel for which to terminate the transfers | |
904 | * | |
905 | * Calling this function will terminate all active and pending descriptors | |
906 | * that have previously been submitted to the channel. It is not guaranteed | |
907 | * though that the transfer for the active descriptor has stopped when the | |
908 | * function returns. Furthermore it is possible the complete callback of a | |
909 | * submitted transfer is still running when this function returns. | |
910 | * | |
911 | * dmaengine_synchronize() needs to be called before it is safe to free | |
912 | * any memory that is accessed by previously submitted descriptors or before | |
913 | * freeing any resources accessed from within the completion callback of any | |
914 | * perviously submitted descriptors. | |
915 | * | |
916 | * This function can be called from atomic context as well as from within a | |
917 | * complete callback of a descriptor submitted on the same channel. | |
918 | * | |
919 | * If none of the two conditions above apply consider using | |
920 | * dmaengine_terminate_sync() instead. | |
921 | */ | |
922 | static inline int dmaengine_terminate_async(struct dma_chan *chan) | |
923 | { | |
924 | if (chan->device->device_terminate_all) | |
925 | return chan->device->device_terminate_all(chan); | |
926 | ||
927 | return -EINVAL; | |
928 | } | |
929 | ||
930 | /** | |
931 | * dmaengine_synchronize() - Synchronize DMA channel termination | |
932 | * @chan: The channel to synchronize | |
933 | * | |
934 | * Synchronizes to the DMA channel termination to the current context. When this | |
935 | * function returns it is guaranteed that all transfers for previously issued | |
936 | * descriptors have stopped and and it is safe to free the memory assoicated | |
937 | * with them. Furthermore it is guaranteed that all complete callback functions | |
938 | * for a previously submitted descriptor have finished running and it is safe to | |
939 | * free resources accessed from within the complete callbacks. | |
940 | * | |
941 | * The behavior of this function is undefined if dma_async_issue_pending() has | |
942 | * been called between dmaengine_terminate_async() and this function. | |
943 | * | |
944 | * This function must only be called from non-atomic context and must not be | |
945 | * called from within a complete callback of a descriptor submitted on the same | |
946 | * channel. | |
947 | */ | |
948 | static inline void dmaengine_synchronize(struct dma_chan *chan) | |
949 | { | |
950 | might_sleep(); | |
951 | ||
952 | if (chan->device->device_synchronize) | |
953 | chan->device->device_synchronize(chan); | |
954 | } | |
955 | ||
956 | /** | |
957 | * dmaengine_terminate_sync() - Terminate all active DMA transfers | |
958 | * @chan: The channel for which to terminate the transfers | |
959 | * | |
960 | * Calling this function will terminate all active and pending transfers | |
961 | * that have previously been submitted to the channel. It is similar to | |
962 | * dmaengine_terminate_async() but guarantees that the DMA transfer has actually | |
963 | * stopped and that all complete callbacks have finished running when the | |
964 | * function returns. | |
965 | * | |
966 | * This function must only be called from non-atomic context and must not be | |
967 | * called from within a complete callback of a descriptor submitted on the same | |
968 | * channel. | |
969 | */ | |
970 | static inline int dmaengine_terminate_sync(struct dma_chan *chan) | |
971 | { | |
972 | int ret; | |
973 | ||
974 | ret = dmaengine_terminate_async(chan); | |
975 | if (ret) | |
976 | return ret; | |
977 | ||
978 | dmaengine_synchronize(chan); | |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
983 | static inline int dmaengine_pause(struct dma_chan *chan) | |
984 | { | |
985 | if (chan->device->device_pause) | |
986 | return chan->device->device_pause(chan); | |
987 | ||
988 | return -ENOSYS; | |
989 | } | |
990 | ||
991 | static inline int dmaengine_resume(struct dma_chan *chan) | |
992 | { | |
993 | if (chan->device->device_resume) | |
994 | return chan->device->device_resume(chan); | |
995 | ||
996 | return -ENOSYS; | |
997 | } | |
998 | ||
999 | static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan, | |
1000 | dma_cookie_t cookie, struct dma_tx_state *state) | |
1001 | { | |
1002 | return chan->device->device_tx_status(chan, cookie, state); | |
1003 | } | |
1004 | ||
1005 | static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) | |
1006 | { | |
1007 | return desc->tx_submit(desc); | |
1008 | } | |
1009 | ||
1010 | static inline bool dmaengine_check_align(enum dmaengine_alignment align, | |
1011 | size_t off1, size_t off2, size_t len) | |
1012 | { | |
1013 | size_t mask; | |
1014 | ||
1015 | if (!align) | |
1016 | return true; | |
1017 | mask = (1 << align) - 1; | |
1018 | if (mask & (off1 | off2 | len)) | |
1019 | return false; | |
1020 | return true; | |
1021 | } | |
1022 | ||
1023 | static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1, | |
1024 | size_t off2, size_t len) | |
1025 | { | |
1026 | return dmaengine_check_align(dev->copy_align, off1, off2, len); | |
1027 | } | |
1028 | ||
1029 | static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1, | |
1030 | size_t off2, size_t len) | |
1031 | { | |
1032 | return dmaengine_check_align(dev->xor_align, off1, off2, len); | |
1033 | } | |
1034 | ||
1035 | static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1, | |
1036 | size_t off2, size_t len) | |
1037 | { | |
1038 | return dmaengine_check_align(dev->pq_align, off1, off2, len); | |
1039 | } | |
1040 | ||
1041 | static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1, | |
1042 | size_t off2, size_t len) | |
1043 | { | |
1044 | return dmaengine_check_align(dev->fill_align, off1, off2, len); | |
1045 | } | |
1046 | ||
1047 | static inline void | |
1048 | dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue) | |
1049 | { | |
1050 | dma->max_pq = maxpq; | |
1051 | if (has_pq_continue) | |
1052 | dma->max_pq |= DMA_HAS_PQ_CONTINUE; | |
1053 | } | |
1054 | ||
1055 | static inline bool dmaf_continue(enum dma_ctrl_flags flags) | |
1056 | { | |
1057 | return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE; | |
1058 | } | |
1059 | ||
1060 | static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags) | |
1061 | { | |
1062 | enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P; | |
1063 | ||
1064 | return (flags & mask) == mask; | |
1065 | } | |
1066 | ||
1067 | static inline bool dma_dev_has_pq_continue(struct dma_device *dma) | |
1068 | { | |
1069 | return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE; | |
1070 | } | |
1071 | ||
1072 | static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma) | |
1073 | { | |
1074 | return dma->max_pq & ~DMA_HAS_PQ_CONTINUE; | |
1075 | } | |
1076 | ||
1077 | /* dma_maxpq - reduce maxpq in the face of continued operations | |
1078 | * @dma - dma device with PQ capability | |
1079 | * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set | |
1080 | * | |
1081 | * When an engine does not support native continuation we need 3 extra | |
1082 | * source slots to reuse P and Q with the following coefficients: | |
1083 | * 1/ {00} * P : remove P from Q', but use it as a source for P' | |
1084 | * 2/ {01} * Q : use Q to continue Q' calculation | |
1085 | * 3/ {00} * Q : subtract Q from P' to cancel (2) | |
1086 | * | |
1087 | * In the case where P is disabled we only need 1 extra source: | |
1088 | * 1/ {01} * Q : use Q to continue Q' calculation | |
1089 | */ | |
1090 | static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags) | |
1091 | { | |
1092 | if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags)) | |
1093 | return dma_dev_to_maxpq(dma); | |
1094 | else if (dmaf_p_disabled_continue(flags)) | |
1095 | return dma_dev_to_maxpq(dma) - 1; | |
1096 | else if (dmaf_continue(flags)) | |
1097 | return dma_dev_to_maxpq(dma) - 3; | |
1098 | BUG(); | |
1099 | } | |
1100 | ||
1101 | static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg, | |
1102 | size_t dir_icg) | |
1103 | { | |
1104 | if (inc) { | |
1105 | if (dir_icg) | |
1106 | return dir_icg; | |
1107 | else if (sgl) | |
1108 | return icg; | |
1109 | } | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt, | |
1115 | struct data_chunk *chunk) | |
1116 | { | |
1117 | return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl, | |
1118 | chunk->icg, chunk->dst_icg); | |
1119 | } | |
1120 | ||
1121 | static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt, | |
1122 | struct data_chunk *chunk) | |
1123 | { | |
1124 | return dmaengine_get_icg(xt->src_inc, xt->src_sgl, | |
1125 | chunk->icg, chunk->src_icg); | |
1126 | } | |
1127 | ||
1128 | /* --- public DMA engine API --- */ | |
1129 | ||
1130 | #ifdef CONFIG_DMA_ENGINE | |
1131 | void dmaengine_get(void); | |
1132 | void dmaengine_put(void); | |
1133 | #else | |
1134 | static inline void dmaengine_get(void) | |
1135 | { | |
1136 | } | |
1137 | static inline void dmaengine_put(void) | |
1138 | { | |
1139 | } | |
1140 | #endif | |
1141 | ||
1142 | #ifdef CONFIG_ASYNC_TX_DMA | |
1143 | #define async_dmaengine_get() dmaengine_get() | |
1144 | #define async_dmaengine_put() dmaengine_put() | |
1145 | #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH | |
1146 | #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX) | |
1147 | #else | |
1148 | #define async_dma_find_channel(type) dma_find_channel(type) | |
1149 | #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */ | |
1150 | #else | |
1151 | static inline void async_dmaengine_get(void) | |
1152 | { | |
1153 | } | |
1154 | static inline void async_dmaengine_put(void) | |
1155 | { | |
1156 | } | |
1157 | static inline struct dma_chan * | |
1158 | async_dma_find_channel(enum dma_transaction_type type) | |
1159 | { | |
1160 | return NULL; | |
1161 | } | |
1162 | #endif /* CONFIG_ASYNC_TX_DMA */ | |
1163 | void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx, | |
1164 | struct dma_chan *chan); | |
1165 | ||
1166 | static inline void async_tx_ack(struct dma_async_tx_descriptor *tx) | |
1167 | { | |
1168 | tx->flags |= DMA_CTRL_ACK; | |
1169 | } | |
1170 | ||
1171 | static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx) | |
1172 | { | |
1173 | tx->flags &= ~DMA_CTRL_ACK; | |
1174 | } | |
1175 | ||
1176 | static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx) | |
1177 | { | |
1178 | return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK; | |
1179 | } | |
1180 | ||
1181 | #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask)) | |
1182 | static inline void | |
1183 | __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
1184 | { | |
1185 | set_bit(tx_type, dstp->bits); | |
1186 | } | |
1187 | ||
1188 | #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask)) | |
1189 | static inline void | |
1190 | __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp) | |
1191 | { | |
1192 | clear_bit(tx_type, dstp->bits); | |
1193 | } | |
1194 | ||
1195 | #define dma_cap_zero(mask) __dma_cap_zero(&(mask)) | |
1196 | static inline void __dma_cap_zero(dma_cap_mask_t *dstp) | |
1197 | { | |
1198 | bitmap_zero(dstp->bits, DMA_TX_TYPE_END); | |
1199 | } | |
1200 | ||
1201 | #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask)) | |
1202 | static inline int | |
1203 | __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp) | |
1204 | { | |
1205 | return test_bit(tx_type, srcp->bits); | |
1206 | } | |
1207 | ||
1208 | #define for_each_dma_cap_mask(cap, mask) \ | |
1209 | for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END) | |
1210 | ||
1211 | /** | |
1212 | * dma_async_issue_pending - flush pending transactions to HW | |
1213 | * @chan: target DMA channel | |
1214 | * | |
1215 | * This allows drivers to push copies to HW in batches, | |
1216 | * reducing MMIO writes where possible. | |
1217 | */ | |
1218 | static inline void dma_async_issue_pending(struct dma_chan *chan) | |
1219 | { | |
1220 | chan->device->device_issue_pending(chan); | |
1221 | } | |
1222 | ||
1223 | /** | |
1224 | * dma_async_is_tx_complete - poll for transaction completion | |
1225 | * @chan: DMA channel | |
1226 | * @cookie: transaction identifier to check status of | |
1227 | * @last: returns last completed cookie, can be NULL | |
1228 | * @used: returns last issued cookie, can be NULL | |
1229 | * | |
1230 | * If @last and @used are passed in, upon return they reflect the driver | |
1231 | * internal state and can be used with dma_async_is_complete() to check | |
1232 | * the status of multiple cookies without re-checking hardware state. | |
1233 | */ | |
1234 | static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan, | |
1235 | dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used) | |
1236 | { | |
1237 | struct dma_tx_state state; | |
1238 | enum dma_status status; | |
1239 | ||
1240 | status = chan->device->device_tx_status(chan, cookie, &state); | |
1241 | if (last) | |
1242 | *last = state.last; | |
1243 | if (used) | |
1244 | *used = state.used; | |
1245 | return status; | |
1246 | } | |
1247 | ||
1248 | /** | |
1249 | * dma_async_is_complete - test a cookie against chan state | |
1250 | * @cookie: transaction identifier to test status of | |
1251 | * @last_complete: last know completed transaction | |
1252 | * @last_used: last cookie value handed out | |
1253 | * | |
1254 | * dma_async_is_complete() is used in dma_async_is_tx_complete() | |
1255 | * the test logic is separated for lightweight testing of multiple cookies | |
1256 | */ | |
1257 | static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie, | |
1258 | dma_cookie_t last_complete, dma_cookie_t last_used) | |
1259 | { | |
1260 | if (last_complete <= last_used) { | |
1261 | if ((cookie <= last_complete) || (cookie > last_used)) | |
1262 | return DMA_COMPLETE; | |
1263 | } else { | |
1264 | if ((cookie <= last_complete) && (cookie > last_used)) | |
1265 | return DMA_COMPLETE; | |
1266 | } | |
1267 | return DMA_IN_PROGRESS; | |
1268 | } | |
1269 | ||
1270 | static inline void | |
1271 | dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue) | |
1272 | { | |
1273 | if (st) { | |
1274 | st->last = last; | |
1275 | st->used = used; | |
1276 | st->residue = residue; | |
1277 | } | |
1278 | } | |
1279 | ||
1280 | #ifdef CONFIG_DMA_ENGINE | |
1281 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); | |
1282 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); | |
1283 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | |
1284 | void dma_issue_pending_all(void); | |
1285 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, | |
1286 | dma_filter_fn fn, void *fn_param); | |
1287 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); | |
1288 | ||
1289 | struct dma_chan *dma_request_chan(struct device *dev, const char *name); | |
1290 | struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); | |
1291 | ||
1292 | void dma_release_channel(struct dma_chan *chan); | |
1293 | int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); | |
1294 | #else | |
1295 | static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) | |
1296 | { | |
1297 | return NULL; | |
1298 | } | |
1299 | static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) | |
1300 | { | |
1301 | return DMA_COMPLETE; | |
1302 | } | |
1303 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | |
1304 | { | |
1305 | return DMA_COMPLETE; | |
1306 | } | |
1307 | static inline void dma_issue_pending_all(void) | |
1308 | { | |
1309 | } | |
1310 | static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, | |
1311 | dma_filter_fn fn, void *fn_param) | |
1312 | { | |
1313 | return NULL; | |
1314 | } | |
1315 | static inline struct dma_chan *dma_request_slave_channel(struct device *dev, | |
1316 | const char *name) | |
1317 | { | |
1318 | return NULL; | |
1319 | } | |
1320 | static inline struct dma_chan *dma_request_chan(struct device *dev, | |
1321 | const char *name) | |
1322 | { | |
1323 | return ERR_PTR(-ENODEV); | |
1324 | } | |
1325 | static inline struct dma_chan *dma_request_chan_by_mask( | |
1326 | const dma_cap_mask_t *mask) | |
1327 | { | |
1328 | return ERR_PTR(-ENODEV); | |
1329 | } | |
1330 | static inline void dma_release_channel(struct dma_chan *chan) | |
1331 | { | |
1332 | } | |
1333 | static inline int dma_get_slave_caps(struct dma_chan *chan, | |
1334 | struct dma_slave_caps *caps) | |
1335 | { | |
1336 | return -ENXIO; | |
1337 | } | |
1338 | #endif | |
1339 | ||
1340 | #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name) | |
1341 | ||
1342 | static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx) | |
1343 | { | |
1344 | struct dma_slave_caps caps; | |
1345 | ||
1346 | dma_get_slave_caps(tx->chan, &caps); | |
1347 | ||
1348 | if (caps.descriptor_reuse) { | |
1349 | tx->flags |= DMA_CTRL_REUSE; | |
1350 | return 0; | |
1351 | } else { | |
1352 | return -EPERM; | |
1353 | } | |
1354 | } | |
1355 | ||
1356 | static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx) | |
1357 | { | |
1358 | tx->flags &= ~DMA_CTRL_REUSE; | |
1359 | } | |
1360 | ||
1361 | static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx) | |
1362 | { | |
1363 | return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE; | |
1364 | } | |
1365 | ||
1366 | static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc) | |
1367 | { | |
1368 | /* this is supported for reusable desc, so check that */ | |
1369 | if (dmaengine_desc_test_reuse(desc)) | |
1370 | return desc->desc_free(desc); | |
1371 | else | |
1372 | return -EPERM; | |
1373 | } | |
1374 | ||
1375 | /* --- DMA device --- */ | |
1376 | ||
1377 | int dma_async_device_register(struct dma_device *device); | |
1378 | void dma_async_device_unregister(struct dma_device *device); | |
1379 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); | |
1380 | struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); | |
1381 | struct dma_chan *dma_get_any_slave_channel(struct dma_device *device); | |
1382 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) | |
1383 | #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ | |
1384 | __dma_request_slave_channel_compat(&(mask), x, y, dev, name) | |
1385 | ||
1386 | static inline struct dma_chan | |
1387 | *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask, | |
1388 | dma_filter_fn fn, void *fn_param, | |
1389 | struct device *dev, const char *name) | |
1390 | { | |
1391 | struct dma_chan *chan; | |
1392 | ||
1393 | chan = dma_request_slave_channel(dev, name); | |
1394 | if (chan) | |
1395 | return chan; | |
1396 | ||
1397 | if (!fn || !fn_param) | |
1398 | return NULL; | |
1399 | ||
1400 | return __dma_request_channel(mask, fn, fn_param); | |
1401 | } | |
1402 | #endif /* DMAENGINE_H */ |