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net/mlx5_core: Make the vport helpers available for the IB driver too
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / device.h
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1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
64#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66
67/* insert a value to a struct */
68#define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
74} while (0)
75
76#define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
82} while (0)
83
84#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86__mlx5_mask(typ, fld))
87
88#define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
91 ___t; \
92})
93
94#define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98} while (0)
99
100#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
101
102enum {
103 MLX5_MAX_COMMANDS = 32,
104 MLX5_CMD_DATA_BLOCK_SIZE = 512,
105 MLX5_PCI_CMD_XPORT = 7,
106 MLX5_MKEY_BSF_OCTO_SIZE = 4,
107 MLX5_MAX_PSVS = 4,
108};
109
110enum {
111 MLX5_EXTENDED_UD_AV = 0x80000000,
112};
113
114enum {
115 MLX5_CQ_STATE_ARMED = 9,
116 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
117 MLX5_CQ_STATE_FIRED = 0xa,
118};
119
120enum {
121 MLX5_STAT_RATE_OFFSET = 5,
122};
123
124enum {
125 MLX5_INLINE_SEG = 0x80000000,
126};
127
128enum {
129 MLX5_MIN_PKEY_TABLE_SIZE = 128,
130 MLX5_MAX_LOG_PKEY_TABLE = 5,
131};
132
133enum {
134 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
135};
136
137enum {
138 MLX5_PFAULT_SUBTYPE_WQE = 0,
139 MLX5_PFAULT_SUBTYPE_RDMA = 1,
140};
141
142enum {
143 MLX5_PERM_LOCAL_READ = 1 << 2,
144 MLX5_PERM_LOCAL_WRITE = 1 << 3,
145 MLX5_PERM_REMOTE_READ = 1 << 4,
146 MLX5_PERM_REMOTE_WRITE = 1 << 5,
147 MLX5_PERM_ATOMIC = 1 << 6,
148 MLX5_PERM_UMR_EN = 1 << 7,
149};
150
151enum {
152 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
153 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
154 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
155 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
156 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
157};
158
159enum {
160 MLX5_ACCESS_MODE_PA = 0,
161 MLX5_ACCESS_MODE_MTT = 1,
162 MLX5_ACCESS_MODE_KLM = 2
163};
164
165enum {
166 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
167 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
168 MLX5_MKEY_BSF_EN = 1 << 30,
169 MLX5_MKEY_LEN64 = 1 << 31,
170};
171
172enum {
173 MLX5_EN_RD = (u64)1,
174 MLX5_EN_WR = (u64)2
175};
176
177enum {
178 MLX5_BF_REGS_PER_PAGE = 4,
179 MLX5_MAX_UAR_PAGES = 1 << 8,
180 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
181 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
182};
183
184enum {
185 MLX5_MKEY_MASK_LEN = 1ull << 0,
186 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
187 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
188 MLX5_MKEY_MASK_PD = 1ull << 7,
189 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
190 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
191 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
192 MLX5_MKEY_MASK_KEY = 1ull << 13,
193 MLX5_MKEY_MASK_QPN = 1ull << 14,
194 MLX5_MKEY_MASK_LR = 1ull << 17,
195 MLX5_MKEY_MASK_LW = 1ull << 18,
196 MLX5_MKEY_MASK_RR = 1ull << 19,
197 MLX5_MKEY_MASK_RW = 1ull << 20,
198 MLX5_MKEY_MASK_A = 1ull << 21,
199 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
200 MLX5_MKEY_MASK_FREE = 1ull << 29,
201};
202
203enum {
204 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
205
206 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
207 MLX5_UMR_CHECK_FREE = (2 << 5),
208
209 MLX5_UMR_INLINE = (1 << 7),
210};
211
212#define MLX5_UMR_MTT_ALIGNMENT 0x40
213#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
214#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
215
216enum mlx5_event {
217 MLX5_EVENT_TYPE_COMP = 0x0,
218
219 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
220 MLX5_EVENT_TYPE_COMM_EST = 0x02,
221 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
222 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
223 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
224
225 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
226 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
227 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
228 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
229 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
230 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
231
232 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
233 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
234 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
235 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
236
237 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
238 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
239
240 MLX5_EVENT_TYPE_CMD = 0x0a,
241 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
242
243 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
244};
245
246enum {
247 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
248 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
249 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
250 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
251 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
252 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
253 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
254};
255
256enum {
257 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
258 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
259 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
260 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
261 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
262 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
263 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
264 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
265 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
266 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
267 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
268 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
269};
270
271enum {
272 MLX5_OPCODE_NOP = 0x00,
273 MLX5_OPCODE_SEND_INVAL = 0x01,
274 MLX5_OPCODE_RDMA_WRITE = 0x08,
275 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
276 MLX5_OPCODE_SEND = 0x0a,
277 MLX5_OPCODE_SEND_IMM = 0x0b,
278 MLX5_OPCODE_LSO = 0x0e,
279 MLX5_OPCODE_RDMA_READ = 0x10,
280 MLX5_OPCODE_ATOMIC_CS = 0x11,
281 MLX5_OPCODE_ATOMIC_FA = 0x12,
282 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
283 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
284 MLX5_OPCODE_BIND_MW = 0x18,
285 MLX5_OPCODE_CONFIG_CMD = 0x1f,
286
287 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
288 MLX5_RECV_OPCODE_SEND = 0x01,
289 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
290 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
291
292 MLX5_CQE_OPCODE_ERROR = 0x1e,
293 MLX5_CQE_OPCODE_RESIZE = 0x16,
294
295 MLX5_OPCODE_SET_PSV = 0x20,
296 MLX5_OPCODE_GET_PSV = 0x21,
297 MLX5_OPCODE_CHECK_PSV = 0x22,
298 MLX5_OPCODE_RGET_PSV = 0x26,
299 MLX5_OPCODE_RCHECK_PSV = 0x27,
300
301 MLX5_OPCODE_UMR = 0x25,
302
303};
304
305enum {
306 MLX5_SET_PORT_RESET_QKEY = 0,
307 MLX5_SET_PORT_GUID0 = 16,
308 MLX5_SET_PORT_NODE_GUID = 17,
309 MLX5_SET_PORT_SYS_GUID = 18,
310 MLX5_SET_PORT_GID_TABLE = 19,
311 MLX5_SET_PORT_PKEY_TABLE = 20,
312};
313
314enum {
315 MLX5_MAX_PAGE_SHIFT = 31
316};
317
318enum {
319 MLX5_ADAPTER_PAGE_SHIFT = 12,
320 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
321};
322
323enum {
324 MLX5_CAP_OFF_CMDIF_CSUM = 46,
325};
326
327struct mlx5_inbox_hdr {
328 __be16 opcode;
329 u8 rsvd[4];
330 __be16 opmod;
331};
332
333struct mlx5_outbox_hdr {
334 u8 status;
335 u8 rsvd[3];
336 __be32 syndrome;
337};
338
339struct mlx5_cmd_query_adapter_mbox_in {
340 struct mlx5_inbox_hdr hdr;
341 u8 rsvd[8];
342};
343
344struct mlx5_cmd_query_adapter_mbox_out {
345 struct mlx5_outbox_hdr hdr;
346 u8 rsvd0[24];
347 u8 intapin;
348 u8 rsvd1[13];
349 __be16 vsd_vendor_id;
350 u8 vsd[208];
351 u8 vsd_psid[16];
352};
353
354enum mlx5_odp_transport_cap_bits {
355 MLX5_ODP_SUPPORT_SEND = 1 << 31,
356 MLX5_ODP_SUPPORT_RECV = 1 << 30,
357 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
358 MLX5_ODP_SUPPORT_READ = 1 << 28,
359};
360
361struct mlx5_odp_caps {
362 char reserved[0x10];
363 struct {
364 __be32 rc_odp_caps;
365 __be32 uc_odp_caps;
366 __be32 ud_odp_caps;
367 } per_transport_caps;
368 char reserved2[0xe4];
369};
370
371struct mlx5_cmd_init_hca_mbox_in {
372 struct mlx5_inbox_hdr hdr;
373 u8 rsvd0[2];
374 __be16 profile;
375 u8 rsvd1[4];
376};
377
378struct mlx5_cmd_init_hca_mbox_out {
379 struct mlx5_outbox_hdr hdr;
380 u8 rsvd[8];
381};
382
383struct mlx5_cmd_teardown_hca_mbox_in {
384 struct mlx5_inbox_hdr hdr;
385 u8 rsvd0[2];
386 __be16 profile;
387 u8 rsvd1[4];
388};
389
390struct mlx5_cmd_teardown_hca_mbox_out {
391 struct mlx5_outbox_hdr hdr;
392 u8 rsvd[8];
393};
394
395struct mlx5_cmd_layout {
396 u8 type;
397 u8 rsvd0[3];
398 __be32 inlen;
399 __be64 in_ptr;
400 __be32 in[4];
401 __be32 out[4];
402 __be64 out_ptr;
403 __be32 outlen;
404 u8 token;
405 u8 sig;
406 u8 rsvd1;
407 u8 status_own;
408};
409
410
411struct health_buffer {
412 __be32 assert_var[5];
413 __be32 rsvd0[3];
414 __be32 assert_exit_ptr;
415 __be32 assert_callra;
416 __be32 rsvd1[2];
417 __be32 fw_ver;
418 __be32 hw_id;
419 __be32 rsvd2;
420 u8 irisc_index;
421 u8 synd;
422 __be16 ext_sync;
423};
424
425struct mlx5_init_seg {
426 __be32 fw_rev;
427 __be32 cmdif_rev_fw_sub;
428 __be32 rsvd0[2];
429 __be32 cmdq_addr_h;
430 __be32 cmdq_addr_l_sz;
431 __be32 cmd_dbell;
432 __be32 rsvd1[121];
433 struct health_buffer health;
434 __be32 rsvd2[884];
435 __be32 health_counter;
436 __be32 rsvd3[1019];
437 __be64 ieee1588_clk;
438 __be32 ieee1588_clk_type;
439 __be32 clr_intx;
440};
441
442struct mlx5_eqe_comp {
443 __be32 reserved[6];
444 __be32 cqn;
445};
446
447struct mlx5_eqe_qp_srq {
448 __be32 reserved[6];
449 __be32 qp_srq_n;
450};
451
452struct mlx5_eqe_cq_err {
453 __be32 cqn;
454 u8 reserved1[7];
455 u8 syndrome;
456};
457
458struct mlx5_eqe_port_state {
459 u8 reserved0[8];
460 u8 port;
461};
462
463struct mlx5_eqe_gpio {
464 __be32 reserved0[2];
465 __be64 gpio_event;
466};
467
468struct mlx5_eqe_congestion {
469 u8 type;
470 u8 rsvd0;
471 u8 congestion_level;
472};
473
474struct mlx5_eqe_stall_vl {
475 u8 rsvd0[3];
476 u8 port_vl;
477};
478
479struct mlx5_eqe_cmd {
480 __be32 vector;
481 __be32 rsvd[6];
482};
483
484struct mlx5_eqe_page_req {
485 u8 rsvd0[2];
486 __be16 func_id;
487 __be32 num_pages;
488 __be32 rsvd1[5];
489};
490
491struct mlx5_eqe_page_fault {
492 __be32 bytes_committed;
493 union {
494 struct {
495 u16 reserved1;
496 __be16 wqe_index;
497 u16 reserved2;
498 __be16 packet_length;
499 u8 reserved3[12];
500 } __packed wqe;
501 struct {
502 __be32 r_key;
503 u16 reserved1;
504 __be16 packet_length;
505 __be32 rdma_op_len;
506 __be64 rdma_va;
507 } __packed rdma;
508 } __packed;
509 __be32 flags_qpn;
510} __packed;
511
512union ev_data {
513 __be32 raw[7];
514 struct mlx5_eqe_cmd cmd;
515 struct mlx5_eqe_comp comp;
516 struct mlx5_eqe_qp_srq qp_srq;
517 struct mlx5_eqe_cq_err cq_err;
518 struct mlx5_eqe_port_state port;
519 struct mlx5_eqe_gpio gpio;
520 struct mlx5_eqe_congestion cong;
521 struct mlx5_eqe_stall_vl stall_vl;
522 struct mlx5_eqe_page_req req_pages;
523 struct mlx5_eqe_page_fault page_fault;
524} __packed;
525
526struct mlx5_eqe {
527 u8 rsvd0;
528 u8 type;
529 u8 rsvd1;
530 u8 sub_type;
531 __be32 rsvd2[7];
532 union ev_data data;
533 __be16 rsvd3;
534 u8 signature;
535 u8 owner;
536} __packed;
537
538struct mlx5_cmd_prot_block {
539 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
540 u8 rsvd0[48];
541 __be64 next;
542 __be32 block_num;
543 u8 rsvd1;
544 u8 token;
545 u8 ctrl_sig;
546 u8 sig;
547};
548
549enum {
550 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
551};
552
553struct mlx5_err_cqe {
554 u8 rsvd0[32];
555 __be32 srqn;
556 u8 rsvd1[18];
557 u8 vendor_err_synd;
558 u8 syndrome;
559 __be32 s_wqe_opcode_qpn;
560 __be16 wqe_counter;
561 u8 signature;
562 u8 op_own;
563};
564
565struct mlx5_cqe64 {
566 u8 rsvd0[4];
567 u8 lro_tcppsh_abort_dupack;
568 u8 lro_min_ttl;
569 __be16 lro_tcp_win;
570 __be32 lro_ack_seq_num;
571 __be32 rss_hash_result;
572 u8 rss_hash_type;
573 u8 ml_path;
574 u8 rsvd20[2];
575 __be16 check_sum;
576 __be16 slid;
577 __be32 flags_rqpn;
578 u8 hds_ip_ext;
579 u8 l4_hdr_type_etc;
580 __be16 vlan_info;
581 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
582 __be32 imm_inval_pkey;
583 u8 rsvd40[4];
584 __be32 byte_cnt;
585 __be64 timestamp;
586 __be32 sop_drop_qpn;
587 __be16 wqe_counter;
588 u8 signature;
589 u8 op_own;
590};
591
592static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
593{
594 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
595}
596
597static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
598{
599 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
600}
601
602static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
603{
604 return !!(cqe->l4_hdr_type_etc & 0x1);
605}
606
607enum {
608 CQE_L4_HDR_TYPE_NONE = 0x0,
609 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
610 CQE_L4_HDR_TYPE_UDP = 0x2,
611 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
612 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
613};
614
615enum {
616 CQE_RSS_HTYPE_IP = 0x3 << 6,
617 CQE_RSS_HTYPE_L4 = 0x3 << 2,
618};
619
620enum {
621 CQE_L2_OK = 1 << 0,
622 CQE_L3_OK = 1 << 1,
623 CQE_L4_OK = 1 << 2,
624};
625
626struct mlx5_sig_err_cqe {
627 u8 rsvd0[16];
628 __be32 expected_trans_sig;
629 __be32 actual_trans_sig;
630 __be32 expected_reftag;
631 __be32 actual_reftag;
632 __be16 syndrome;
633 u8 rsvd22[2];
634 __be32 mkey;
635 __be64 err_offset;
636 u8 rsvd30[8];
637 __be32 qpn;
638 u8 rsvd38[2];
639 u8 signature;
640 u8 op_own;
641};
642
643struct mlx5_wqe_srq_next_seg {
644 u8 rsvd0[2];
645 __be16 next_wqe_index;
646 u8 signature;
647 u8 rsvd1[11];
648};
649
650union mlx5_ext_cqe {
651 struct ib_grh grh;
652 u8 inl[64];
653};
654
655struct mlx5_cqe128 {
656 union mlx5_ext_cqe inl_grh;
657 struct mlx5_cqe64 cqe64;
658};
659
660struct mlx5_srq_ctx {
661 u8 state_log_sz;
662 u8 rsvd0[3];
663 __be32 flags_xrcd;
664 __be32 pgoff_cqn;
665 u8 rsvd1[4];
666 u8 log_pg_sz;
667 u8 rsvd2[7];
668 __be32 pd;
669 __be16 lwm;
670 __be16 wqe_cnt;
671 u8 rsvd3[8];
672 __be64 db_record;
673};
674
675struct mlx5_create_srq_mbox_in {
676 struct mlx5_inbox_hdr hdr;
677 __be32 input_srqn;
678 u8 rsvd0[4];
679 struct mlx5_srq_ctx ctx;
680 u8 rsvd1[208];
681 __be64 pas[0];
682};
683
684struct mlx5_create_srq_mbox_out {
685 struct mlx5_outbox_hdr hdr;
686 __be32 srqn;
687 u8 rsvd[4];
688};
689
690struct mlx5_destroy_srq_mbox_in {
691 struct mlx5_inbox_hdr hdr;
692 __be32 srqn;
693 u8 rsvd[4];
694};
695
696struct mlx5_destroy_srq_mbox_out {
697 struct mlx5_outbox_hdr hdr;
698 u8 rsvd[8];
699};
700
701struct mlx5_query_srq_mbox_in {
702 struct mlx5_inbox_hdr hdr;
703 __be32 srqn;
704 u8 rsvd0[4];
705};
706
707struct mlx5_query_srq_mbox_out {
708 struct mlx5_outbox_hdr hdr;
709 u8 rsvd0[8];
710 struct mlx5_srq_ctx ctx;
711 u8 rsvd1[32];
712 __be64 pas[0];
713};
714
715struct mlx5_arm_srq_mbox_in {
716 struct mlx5_inbox_hdr hdr;
717 __be32 srqn;
718 __be16 rsvd;
719 __be16 lwm;
720};
721
722struct mlx5_arm_srq_mbox_out {
723 struct mlx5_outbox_hdr hdr;
724 u8 rsvd[8];
725};
726
727struct mlx5_cq_context {
728 u8 status;
729 u8 cqe_sz_flags;
730 u8 st;
731 u8 rsvd3;
732 u8 rsvd4[6];
733 __be16 page_offset;
734 __be32 log_sz_usr_page;
735 __be16 cq_period;
736 __be16 cq_max_count;
737 __be16 rsvd20;
738 __be16 c_eqn;
739 u8 log_pg_sz;
740 u8 rsvd25[7];
741 __be32 last_notified_index;
742 __be32 solicit_producer_index;
743 __be32 consumer_counter;
744 __be32 producer_counter;
745 u8 rsvd48[8];
746 __be64 db_record_addr;
747};
748
749struct mlx5_create_cq_mbox_in {
750 struct mlx5_inbox_hdr hdr;
751 __be32 input_cqn;
752 u8 rsvdx[4];
753 struct mlx5_cq_context ctx;
754 u8 rsvd6[192];
755 __be64 pas[0];
756};
757
758struct mlx5_create_cq_mbox_out {
759 struct mlx5_outbox_hdr hdr;
760 __be32 cqn;
761 u8 rsvd0[4];
762};
763
764struct mlx5_destroy_cq_mbox_in {
765 struct mlx5_inbox_hdr hdr;
766 __be32 cqn;
767 u8 rsvd0[4];
768};
769
770struct mlx5_destroy_cq_mbox_out {
771 struct mlx5_outbox_hdr hdr;
772 u8 rsvd0[8];
773};
774
775struct mlx5_query_cq_mbox_in {
776 struct mlx5_inbox_hdr hdr;
777 __be32 cqn;
778 u8 rsvd0[4];
779};
780
781struct mlx5_query_cq_mbox_out {
782 struct mlx5_outbox_hdr hdr;
783 u8 rsvd0[8];
784 struct mlx5_cq_context ctx;
785 u8 rsvd6[16];
786 __be64 pas[0];
787};
788
789struct mlx5_modify_cq_mbox_in {
790 struct mlx5_inbox_hdr hdr;
791 __be32 cqn;
792 __be32 field_select;
793 struct mlx5_cq_context ctx;
794 u8 rsvd[192];
795 __be64 pas[0];
796};
797
798struct mlx5_modify_cq_mbox_out {
799 struct mlx5_outbox_hdr hdr;
800 u8 rsvd[8];
801};
802
803struct mlx5_enable_hca_mbox_in {
804 struct mlx5_inbox_hdr hdr;
805 u8 rsvd[8];
806};
807
808struct mlx5_enable_hca_mbox_out {
809 struct mlx5_outbox_hdr hdr;
810 u8 rsvd[8];
811};
812
813struct mlx5_disable_hca_mbox_in {
814 struct mlx5_inbox_hdr hdr;
815 u8 rsvd[8];
816};
817
818struct mlx5_disable_hca_mbox_out {
819 struct mlx5_outbox_hdr hdr;
820 u8 rsvd[8];
821};
822
823struct mlx5_eq_context {
824 u8 status;
825 u8 ec_oi;
826 u8 st;
827 u8 rsvd2[7];
828 __be16 page_pffset;
829 __be32 log_sz_usr_page;
830 u8 rsvd3[7];
831 u8 intr;
832 u8 log_page_size;
833 u8 rsvd4[15];
834 __be32 consumer_counter;
835 __be32 produser_counter;
836 u8 rsvd5[16];
837};
838
839struct mlx5_create_eq_mbox_in {
840 struct mlx5_inbox_hdr hdr;
841 u8 rsvd0[3];
842 u8 input_eqn;
843 u8 rsvd1[4];
844 struct mlx5_eq_context ctx;
845 u8 rsvd2[8];
846 __be64 events_mask;
847 u8 rsvd3[176];
848 __be64 pas[0];
849};
850
851struct mlx5_create_eq_mbox_out {
852 struct mlx5_outbox_hdr hdr;
853 u8 rsvd0[3];
854 u8 eq_number;
855 u8 rsvd1[4];
856};
857
858struct mlx5_destroy_eq_mbox_in {
859 struct mlx5_inbox_hdr hdr;
860 u8 rsvd0[3];
861 u8 eqn;
862 u8 rsvd1[4];
863};
864
865struct mlx5_destroy_eq_mbox_out {
866 struct mlx5_outbox_hdr hdr;
867 u8 rsvd[8];
868};
869
870struct mlx5_map_eq_mbox_in {
871 struct mlx5_inbox_hdr hdr;
872 __be64 mask;
873 u8 mu;
874 u8 rsvd0[2];
875 u8 eqn;
876 u8 rsvd1[24];
877};
878
879struct mlx5_map_eq_mbox_out {
880 struct mlx5_outbox_hdr hdr;
881 u8 rsvd[8];
882};
883
884struct mlx5_query_eq_mbox_in {
885 struct mlx5_inbox_hdr hdr;
886 u8 rsvd0[3];
887 u8 eqn;
888 u8 rsvd1[4];
889};
890
891struct mlx5_query_eq_mbox_out {
892 struct mlx5_outbox_hdr hdr;
893 u8 rsvd[8];
894 struct mlx5_eq_context ctx;
895};
896
897enum {
898 MLX5_MKEY_STATUS_FREE = 1 << 6,
899};
900
901struct mlx5_mkey_seg {
902 /* This is a two bit field occupying bits 31-30.
903 * bit 31 is always 0,
904 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
905 */
906 u8 status;
907 u8 pcie_control;
908 u8 flags;
909 u8 version;
910 __be32 qpn_mkey7_0;
911 u8 rsvd1[4];
912 __be32 flags_pd;
913 __be64 start_addr;
914 __be64 len;
915 __be32 bsfs_octo_size;
916 u8 rsvd2[16];
917 __be32 xlt_oct_size;
918 u8 rsvd3[3];
919 u8 log2_page_size;
920 u8 rsvd4[4];
921};
922
923struct mlx5_query_special_ctxs_mbox_in {
924 struct mlx5_inbox_hdr hdr;
925 u8 rsvd[8];
926};
927
928struct mlx5_query_special_ctxs_mbox_out {
929 struct mlx5_outbox_hdr hdr;
930 __be32 dump_fill_mkey;
931 __be32 reserved_lkey;
932};
933
934struct mlx5_create_mkey_mbox_in {
935 struct mlx5_inbox_hdr hdr;
936 __be32 input_mkey_index;
937 __be32 flags;
938 struct mlx5_mkey_seg seg;
939 u8 rsvd1[16];
940 __be32 xlat_oct_act_size;
941 __be32 rsvd2;
942 u8 rsvd3[168];
943 __be64 pas[0];
944};
945
946struct mlx5_create_mkey_mbox_out {
947 struct mlx5_outbox_hdr hdr;
948 __be32 mkey;
949 u8 rsvd[4];
950};
951
952struct mlx5_destroy_mkey_mbox_in {
953 struct mlx5_inbox_hdr hdr;
954 __be32 mkey;
955 u8 rsvd[4];
956};
957
958struct mlx5_destroy_mkey_mbox_out {
959 struct mlx5_outbox_hdr hdr;
960 u8 rsvd[8];
961};
962
963struct mlx5_query_mkey_mbox_in {
964 struct mlx5_inbox_hdr hdr;
965 __be32 mkey;
966};
967
968struct mlx5_query_mkey_mbox_out {
969 struct mlx5_outbox_hdr hdr;
970 __be64 pas[0];
971};
972
973struct mlx5_modify_mkey_mbox_in {
974 struct mlx5_inbox_hdr hdr;
975 __be32 mkey;
976 __be64 pas[0];
977};
978
979struct mlx5_modify_mkey_mbox_out {
980 struct mlx5_outbox_hdr hdr;
981 u8 rsvd[8];
982};
983
984struct mlx5_dump_mkey_mbox_in {
985 struct mlx5_inbox_hdr hdr;
986};
987
988struct mlx5_dump_mkey_mbox_out {
989 struct mlx5_outbox_hdr hdr;
990 __be32 mkey;
991};
992
993struct mlx5_mad_ifc_mbox_in {
994 struct mlx5_inbox_hdr hdr;
995 __be16 remote_lid;
996 u8 rsvd0;
997 u8 port;
998 u8 rsvd1[4];
999 u8 data[256];
1000};
1001
1002struct mlx5_mad_ifc_mbox_out {
1003 struct mlx5_outbox_hdr hdr;
1004 u8 rsvd[8];
1005 u8 data[256];
1006};
1007
1008struct mlx5_access_reg_mbox_in {
1009 struct mlx5_inbox_hdr hdr;
1010 u8 rsvd0[2];
1011 __be16 register_id;
1012 __be32 arg;
1013 __be32 data[0];
1014};
1015
1016struct mlx5_access_reg_mbox_out {
1017 struct mlx5_outbox_hdr hdr;
1018 u8 rsvd[8];
1019 __be32 data[0];
1020};
1021
1022#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1023
1024enum {
1025 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1026};
1027
1028struct mlx5_allocate_psv_in {
1029 struct mlx5_inbox_hdr hdr;
1030 __be32 npsv_pd;
1031 __be32 rsvd_psv0;
1032};
1033
1034struct mlx5_allocate_psv_out {
1035 struct mlx5_outbox_hdr hdr;
1036 u8 rsvd[8];
1037 __be32 psv_idx[4];
1038};
1039
1040struct mlx5_destroy_psv_in {
1041 struct mlx5_inbox_hdr hdr;
1042 __be32 psv_number;
1043 u8 rsvd[4];
1044};
1045
1046struct mlx5_destroy_psv_out {
1047 struct mlx5_outbox_hdr hdr;
1048 u8 rsvd[8];
1049};
1050
1051#define MLX5_CMD_OP_MAX 0x920
1052
1053enum {
1054 VPORT_STATE_DOWN = 0x0,
1055 VPORT_STATE_UP = 0x1,
1056};
1057
1058enum {
1059 MLX5_L3_PROT_TYPE_IPV4 = 0,
1060 MLX5_L3_PROT_TYPE_IPV6 = 1,
1061};
1062
1063enum {
1064 MLX5_L4_PROT_TYPE_TCP = 0,
1065 MLX5_L4_PROT_TYPE_UDP = 1,
1066};
1067
1068enum {
1069 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1070 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1071 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1072 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1073 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1074};
1075
1076enum {
1077 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1078 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1079 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1080
1081};
1082
1083enum {
1084 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1085 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1086};
1087
1088enum {
1089 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1090 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1091 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1092};
1093
1094enum {
1095 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1096 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1097};
1098
1099/* MLX5 DEV CAPs */
1100
1101/* TODO: EAT.ME */
1102enum mlx5_cap_mode {
1103 HCA_CAP_OPMOD_GET_MAX = 0,
1104 HCA_CAP_OPMOD_GET_CUR = 1,
1105};
1106
1107enum mlx5_cap_type {
1108 MLX5_CAP_GENERAL = 0,
1109 MLX5_CAP_ETHERNET_OFFLOADS,
1110 MLX5_CAP_ODP,
1111 MLX5_CAP_ATOMIC,
1112 MLX5_CAP_ROCE,
1113 MLX5_CAP_IPOIB_OFFLOADS,
1114 MLX5_CAP_EOIB_OFFLOADS,
1115 MLX5_CAP_FLOW_TABLE,
1116 /* NUM OF CAP Types */
1117 MLX5_CAP_NUM
1118};
1119
1120/* GET Dev Caps macros */
1121#define MLX5_CAP_GEN(mdev, cap) \
1122 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1123
1124#define MLX5_CAP_GEN_MAX(mdev, cap) \
1125 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1126
1127#define MLX5_CAP_ETH(mdev, cap) \
1128 MLX5_GET(per_protocol_networking_offload_caps,\
1129 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1130
1131#define MLX5_CAP_ETH_MAX(mdev, cap) \
1132 MLX5_GET(per_protocol_networking_offload_caps,\
1133 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1134
1135#define MLX5_CAP_ROCE(mdev, cap) \
1136 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1137
1138#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1139 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1140
1141#define MLX5_CAP_ATOMIC(mdev, cap) \
1142 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1143
1144#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1145 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1146
1147#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1148 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1149
1150#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1151 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1152
1153#define MLX5_CAP_ODP(mdev, cap)\
1154 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1155
1156enum {
1157 MLX5_CMD_STAT_OK = 0x0,
1158 MLX5_CMD_STAT_INT_ERR = 0x1,
1159 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1160 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1161 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1162 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1163 MLX5_CMD_STAT_RES_BUSY = 0x6,
1164 MLX5_CMD_STAT_LIM_ERR = 0x8,
1165 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1166 MLX5_CMD_STAT_IX_ERR = 0xa,
1167 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1168 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1169 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1170 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1171 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1172 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1173};
1174
1175#endif /* MLX5_DEVICE_H */
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