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1 | /* SPDX-License-Identifier: GPL-2.0 */ | |
2 | /* | |
3 | * Definitions for the NVM Express interface | |
4 | * Copyright (c) 2011-2014, Intel Corporation. | |
5 | */ | |
6 | ||
7 | #ifndef _LINUX_NVME_H | |
8 | #define _LINUX_NVME_H | |
9 | ||
10 | #include <linux/types.h> | |
11 | #include <linux/uuid.h> | |
12 | ||
13 | /* NQN names in commands fields specified one size */ | |
14 | #define NVMF_NQN_FIELD_LEN 256 | |
15 | ||
16 | /* However the max length of a qualified name is another size */ | |
17 | #define NVMF_NQN_SIZE 223 | |
18 | ||
19 | #define NVMF_TRSVCID_SIZE 32 | |
20 | #define NVMF_TRADDR_SIZE 256 | |
21 | #define NVMF_TSAS_SIZE 256 | |
22 | ||
23 | #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery" | |
24 | ||
25 | #define NVME_RDMA_IP_PORT 4420 | |
26 | ||
27 | #define NVME_NSID_ALL 0xffffffff | |
28 | ||
29 | enum nvme_subsys_type { | |
30 | NVME_NQN_DISC = 1, /* Discovery type target subsystem */ | |
31 | NVME_NQN_NVME = 2, /* NVME type target subsystem */ | |
32 | }; | |
33 | ||
34 | /* Address Family codes for Discovery Log Page entry ADRFAM field */ | |
35 | enum { | |
36 | NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */ | |
37 | NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */ | |
38 | NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */ | |
39 | NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */ | |
40 | NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */ | |
41 | NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */ | |
42 | NVMF_ADDR_FAMILY_MAX, | |
43 | }; | |
44 | ||
45 | /* Transport Type codes for Discovery Log Page entry TRTYPE field */ | |
46 | enum { | |
47 | NVMF_TRTYPE_RDMA = 1, /* RDMA */ | |
48 | NVMF_TRTYPE_FC = 2, /* Fibre Channel */ | |
49 | NVMF_TRTYPE_TCP = 3, /* TCP/IP */ | |
50 | NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */ | |
51 | NVMF_TRTYPE_MAX, | |
52 | }; | |
53 | ||
54 | /* Transport Requirements codes for Discovery Log Page entry TREQ field */ | |
55 | enum { | |
56 | NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */ | |
57 | NVMF_TREQ_REQUIRED = 1, /* Required */ | |
58 | NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */ | |
59 | #define NVME_TREQ_SECURE_CHANNEL_MASK \ | |
60 | (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED) | |
61 | ||
62 | NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */ | |
63 | }; | |
64 | ||
65 | /* RDMA QP Service Type codes for Discovery Log Page entry TSAS | |
66 | * RDMA_QPTYPE field | |
67 | */ | |
68 | enum { | |
69 | NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */ | |
70 | NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */ | |
71 | }; | |
72 | ||
73 | /* RDMA QP Service Type codes for Discovery Log Page entry TSAS | |
74 | * RDMA_QPTYPE field | |
75 | */ | |
76 | enum { | |
77 | NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */ | |
78 | NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */ | |
79 | NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */ | |
80 | NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */ | |
81 | NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */ | |
82 | }; | |
83 | ||
84 | /* RDMA Connection Management Service Type codes for Discovery Log Page | |
85 | * entry TSAS RDMA_CMS field | |
86 | */ | |
87 | enum { | |
88 | NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */ | |
89 | }; | |
90 | ||
91 | #define NVME_AQ_DEPTH 32 | |
92 | #define NVME_NR_AEN_COMMANDS 1 | |
93 | #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS) | |
94 | ||
95 | /* | |
96 | * Subtract one to leave an empty queue entry for 'Full Queue' condition. See | |
97 | * NVM-Express 1.2 specification, section 4.1.2. | |
98 | */ | |
99 | #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1) | |
100 | ||
101 | enum { | |
102 | NVME_REG_CAP = 0x0000, /* Controller Capabilities */ | |
103 | NVME_REG_VS = 0x0008, /* Version */ | |
104 | NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */ | |
105 | NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */ | |
106 | NVME_REG_CC = 0x0014, /* Controller Configuration */ | |
107 | NVME_REG_CSTS = 0x001c, /* Controller Status */ | |
108 | NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */ | |
109 | NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */ | |
110 | NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */ | |
111 | NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */ | |
112 | NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */ | |
113 | NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */ | |
114 | NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */ | |
115 | NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */ | |
116 | NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer | |
117 | * Location | |
118 | */ | |
119 | NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory | |
120 | * Space Control | |
121 | */ | |
122 | NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */ | |
123 | NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */ | |
124 | NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */ | |
125 | NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity | |
126 | * Buffer Size | |
127 | */ | |
128 | NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained | |
129 | * Write Throughput | |
130 | */ | |
131 | NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */ | |
132 | }; | |
133 | ||
134 | #define NVME_CAP_MQES(cap) ((cap) & 0xffff) | |
135 | #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) | |
136 | #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) | |
137 | #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) | |
138 | #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff) | |
139 | #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) | |
140 | #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) | |
141 | #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1) | |
142 | ||
143 | #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) | |
144 | #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) | |
145 | ||
146 | enum { | |
147 | NVME_CMBSZ_SQS = 1 << 0, | |
148 | NVME_CMBSZ_CQS = 1 << 1, | |
149 | NVME_CMBSZ_LISTS = 1 << 2, | |
150 | NVME_CMBSZ_RDS = 1 << 3, | |
151 | NVME_CMBSZ_WDS = 1 << 4, | |
152 | ||
153 | NVME_CMBSZ_SZ_SHIFT = 12, | |
154 | NVME_CMBSZ_SZ_MASK = 0xfffff, | |
155 | ||
156 | NVME_CMBSZ_SZU_SHIFT = 8, | |
157 | NVME_CMBSZ_SZU_MASK = 0xf, | |
158 | }; | |
159 | ||
160 | /* | |
161 | * Submission and Completion Queue Entry Sizes for the NVM command set. | |
162 | * (In bytes and specified as a power of two (2^n)). | |
163 | */ | |
164 | #define NVME_ADM_SQES 6 | |
165 | #define NVME_NVM_IOSQES 6 | |
166 | #define NVME_NVM_IOCQES 4 | |
167 | ||
168 | enum { | |
169 | NVME_CC_ENABLE = 1 << 0, | |
170 | NVME_CC_EN_SHIFT = 0, | |
171 | NVME_CC_CSS_SHIFT = 4, | |
172 | NVME_CC_MPS_SHIFT = 7, | |
173 | NVME_CC_AMS_SHIFT = 11, | |
174 | NVME_CC_SHN_SHIFT = 14, | |
175 | NVME_CC_IOSQES_SHIFT = 16, | |
176 | NVME_CC_IOCQES_SHIFT = 20, | |
177 | NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT, | |
178 | NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT, | |
179 | NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT, | |
180 | NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT, | |
181 | NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT, | |
182 | NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT, | |
183 | NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT, | |
184 | NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT, | |
185 | NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT, | |
186 | NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT, | |
187 | NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT, | |
188 | NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT, | |
189 | NVME_CAP_CSS_NVM = 1 << 0, | |
190 | NVME_CAP_CSS_CSI = 1 << 6, | |
191 | NVME_CSTS_RDY = 1 << 0, | |
192 | NVME_CSTS_CFS = 1 << 1, | |
193 | NVME_CSTS_NSSRO = 1 << 4, | |
194 | NVME_CSTS_PP = 1 << 5, | |
195 | NVME_CSTS_SHST_NORMAL = 0 << 2, | |
196 | NVME_CSTS_SHST_OCCUR = 1 << 2, | |
197 | NVME_CSTS_SHST_CMPLT = 2 << 2, | |
198 | NVME_CSTS_SHST_MASK = 3 << 2, | |
199 | NVME_CMBMSC_CRE = 1 << 0, | |
200 | NVME_CMBMSC_CMSE = 1 << 1, | |
201 | }; | |
202 | ||
203 | struct nvme_id_power_state { | |
204 | __le16 max_power; /* centiwatts */ | |
205 | __u8 rsvd2; | |
206 | __u8 flags; | |
207 | __le32 entry_lat; /* microseconds */ | |
208 | __le32 exit_lat; /* microseconds */ | |
209 | __u8 read_tput; | |
210 | __u8 read_lat; | |
211 | __u8 write_tput; | |
212 | __u8 write_lat; | |
213 | __le16 idle_power; | |
214 | __u8 idle_scale; | |
215 | __u8 rsvd19; | |
216 | __le16 active_power; | |
217 | __u8 active_work_scale; | |
218 | __u8 rsvd23[9]; | |
219 | }; | |
220 | ||
221 | enum { | |
222 | NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0, | |
223 | NVME_PS_FLAGS_NON_OP_STATE = 1 << 1, | |
224 | }; | |
225 | ||
226 | enum nvme_ctrl_attr { | |
227 | NVME_CTRL_ATTR_HID_128_BIT = (1 << 0), | |
228 | NVME_CTRL_ATTR_TBKAS = (1 << 6), | |
229 | }; | |
230 | ||
231 | struct nvme_id_ctrl { | |
232 | __le16 vid; | |
233 | __le16 ssvid; | |
234 | char sn[20]; | |
235 | char mn[40]; | |
236 | char fr[8]; | |
237 | __u8 rab; | |
238 | __u8 ieee[3]; | |
239 | __u8 cmic; | |
240 | __u8 mdts; | |
241 | __le16 cntlid; | |
242 | __le32 ver; | |
243 | __le32 rtd3r; | |
244 | __le32 rtd3e; | |
245 | __le32 oaes; | |
246 | __le32 ctratt; | |
247 | __u8 rsvd100[28]; | |
248 | __le16 crdt1; | |
249 | __le16 crdt2; | |
250 | __le16 crdt3; | |
251 | __u8 rsvd134[122]; | |
252 | __le16 oacs; | |
253 | __u8 acl; | |
254 | __u8 aerl; | |
255 | __u8 frmw; | |
256 | __u8 lpa; | |
257 | __u8 elpe; | |
258 | __u8 npss; | |
259 | __u8 avscc; | |
260 | __u8 apsta; | |
261 | __le16 wctemp; | |
262 | __le16 cctemp; | |
263 | __le16 mtfa; | |
264 | __le32 hmpre; | |
265 | __le32 hmmin; | |
266 | __u8 tnvmcap[16]; | |
267 | __u8 unvmcap[16]; | |
268 | __le32 rpmbs; | |
269 | __le16 edstt; | |
270 | __u8 dsto; | |
271 | __u8 fwug; | |
272 | __le16 kas; | |
273 | __le16 hctma; | |
274 | __le16 mntmt; | |
275 | __le16 mxtmt; | |
276 | __le32 sanicap; | |
277 | __le32 hmminds; | |
278 | __le16 hmmaxd; | |
279 | __u8 rsvd338[4]; | |
280 | __u8 anatt; | |
281 | __u8 anacap; | |
282 | __le32 anagrpmax; | |
283 | __le32 nanagrpid; | |
284 | __u8 rsvd352[160]; | |
285 | __u8 sqes; | |
286 | __u8 cqes; | |
287 | __le16 maxcmd; | |
288 | __le32 nn; | |
289 | __le16 oncs; | |
290 | __le16 fuses; | |
291 | __u8 fna; | |
292 | __u8 vwc; | |
293 | __le16 awun; | |
294 | __le16 awupf; | |
295 | __u8 nvscc; | |
296 | __u8 nwpc; | |
297 | __le16 acwu; | |
298 | __u8 rsvd534[2]; | |
299 | __le32 sgls; | |
300 | __le32 mnan; | |
301 | __u8 rsvd544[224]; | |
302 | char subnqn[256]; | |
303 | __u8 rsvd1024[768]; | |
304 | __le32 ioccsz; | |
305 | __le32 iorcsz; | |
306 | __le16 icdoff; | |
307 | __u8 ctrattr; | |
308 | __u8 msdbd; | |
309 | __u8 rsvd1804[244]; | |
310 | struct nvme_id_power_state psd[32]; | |
311 | __u8 vs[1024]; | |
312 | }; | |
313 | ||
314 | enum { | |
315 | NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1, | |
316 | NVME_CTRL_CMIC_ANA = 1 << 3, | |
317 | NVME_CTRL_ONCS_COMPARE = 1 << 0, | |
318 | NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1, | |
319 | NVME_CTRL_ONCS_DSM = 1 << 2, | |
320 | NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3, | |
321 | NVME_CTRL_ONCS_RESERVATIONS = 1 << 5, | |
322 | NVME_CTRL_ONCS_TIMESTAMP = 1 << 6, | |
323 | NVME_CTRL_VWC_PRESENT = 1 << 0, | |
324 | NVME_CTRL_OACS_SEC_SUPP = 1 << 0, | |
325 | NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3, | |
326 | NVME_CTRL_OACS_DIRECTIVES = 1 << 5, | |
327 | NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8, | |
328 | NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1, | |
329 | NVME_CTRL_CTRATT_128_ID = 1 << 0, | |
330 | NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1, | |
331 | NVME_CTRL_CTRATT_NVM_SETS = 1 << 2, | |
332 | NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3, | |
333 | NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4, | |
334 | NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5, | |
335 | NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7, | |
336 | NVME_CTRL_CTRATT_UUID_LIST = 1 << 9, | |
337 | }; | |
338 | ||
339 | struct nvme_lbaf { | |
340 | __le16 ms; | |
341 | __u8 ds; | |
342 | __u8 rp; | |
343 | }; | |
344 | ||
345 | struct nvme_id_ns { | |
346 | __le64 nsze; | |
347 | __le64 ncap; | |
348 | __le64 nuse; | |
349 | __u8 nsfeat; | |
350 | __u8 nlbaf; | |
351 | __u8 flbas; | |
352 | __u8 mc; | |
353 | __u8 dpc; | |
354 | __u8 dps; | |
355 | __u8 nmic; | |
356 | __u8 rescap; | |
357 | __u8 fpi; | |
358 | __u8 dlfeat; | |
359 | __le16 nawun; | |
360 | __le16 nawupf; | |
361 | __le16 nacwu; | |
362 | __le16 nabsn; | |
363 | __le16 nabo; | |
364 | __le16 nabspf; | |
365 | __le16 noiob; | |
366 | __u8 nvmcap[16]; | |
367 | __le16 npwg; | |
368 | __le16 npwa; | |
369 | __le16 npdg; | |
370 | __le16 npda; | |
371 | __le16 nows; | |
372 | __u8 rsvd74[18]; | |
373 | __le32 anagrpid; | |
374 | __u8 rsvd96[3]; | |
375 | __u8 nsattr; | |
376 | __le16 nvmsetid; | |
377 | __le16 endgid; | |
378 | __u8 nguid[16]; | |
379 | __u8 eui64[8]; | |
380 | struct nvme_lbaf lbaf[16]; | |
381 | __u8 rsvd192[192]; | |
382 | __u8 vs[3712]; | |
383 | }; | |
384 | ||
385 | struct nvme_zns_lbafe { | |
386 | __le64 zsze; | |
387 | __u8 zdes; | |
388 | __u8 rsvd9[7]; | |
389 | }; | |
390 | ||
391 | struct nvme_id_ns_zns { | |
392 | __le16 zoc; | |
393 | __le16 ozcs; | |
394 | __le32 mar; | |
395 | __le32 mor; | |
396 | __le32 rrl; | |
397 | __le32 frl; | |
398 | __u8 rsvd20[2796]; | |
399 | struct nvme_zns_lbafe lbafe[16]; | |
400 | __u8 rsvd3072[768]; | |
401 | __u8 vs[256]; | |
402 | }; | |
403 | ||
404 | struct nvme_id_ctrl_zns { | |
405 | __u8 zasl; | |
406 | __u8 rsvd1[4095]; | |
407 | }; | |
408 | ||
409 | struct nvme_id_ctrl_nvm { | |
410 | __u8 vsl; | |
411 | __u8 wzsl; | |
412 | __u8 wusl; | |
413 | __u8 dmrl; | |
414 | __le32 dmrsl; | |
415 | __le64 dmsl; | |
416 | __u8 rsvd16[4080]; | |
417 | }; | |
418 | ||
419 | enum { | |
420 | NVME_ID_CNS_NS = 0x00, | |
421 | NVME_ID_CNS_CTRL = 0x01, | |
422 | NVME_ID_CNS_NS_ACTIVE_LIST = 0x02, | |
423 | NVME_ID_CNS_NS_DESC_LIST = 0x03, | |
424 | NVME_ID_CNS_CS_NS = 0x05, | |
425 | NVME_ID_CNS_CS_CTRL = 0x06, | |
426 | NVME_ID_CNS_NS_PRESENT_LIST = 0x10, | |
427 | NVME_ID_CNS_NS_PRESENT = 0x11, | |
428 | NVME_ID_CNS_CTRL_NS_LIST = 0x12, | |
429 | NVME_ID_CNS_CTRL_LIST = 0x13, | |
430 | NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15, | |
431 | NVME_ID_CNS_NS_GRANULARITY = 0x16, | |
432 | NVME_ID_CNS_UUID_LIST = 0x17, | |
433 | }; | |
434 | ||
435 | enum { | |
436 | NVME_CSI_NVM = 0, | |
437 | NVME_CSI_ZNS = 2, | |
438 | }; | |
439 | ||
440 | enum { | |
441 | NVME_DIR_IDENTIFY = 0x00, | |
442 | NVME_DIR_STREAMS = 0x01, | |
443 | NVME_DIR_SND_ID_OP_ENABLE = 0x01, | |
444 | NVME_DIR_SND_ST_OP_REL_ID = 0x01, | |
445 | NVME_DIR_SND_ST_OP_REL_RSC = 0x02, | |
446 | NVME_DIR_RCV_ID_OP_PARAM = 0x01, | |
447 | NVME_DIR_RCV_ST_OP_PARAM = 0x01, | |
448 | NVME_DIR_RCV_ST_OP_STATUS = 0x02, | |
449 | NVME_DIR_RCV_ST_OP_RESOURCE = 0x03, | |
450 | NVME_DIR_ENDIR = 0x01, | |
451 | }; | |
452 | ||
453 | enum { | |
454 | NVME_NS_FEAT_THIN = 1 << 0, | |
455 | NVME_NS_FEAT_ATOMICS = 1 << 1, | |
456 | NVME_NS_FEAT_IO_OPT = 1 << 4, | |
457 | NVME_NS_ATTR_RO = 1 << 0, | |
458 | NVME_NS_FLBAS_LBA_MASK = 0xf, | |
459 | NVME_NS_FLBAS_META_EXT = 0x10, | |
460 | NVME_NS_NMIC_SHARED = 1 << 0, | |
461 | NVME_LBAF_RP_BEST = 0, | |
462 | NVME_LBAF_RP_BETTER = 1, | |
463 | NVME_LBAF_RP_GOOD = 2, | |
464 | NVME_LBAF_RP_DEGRADED = 3, | |
465 | NVME_NS_DPC_PI_LAST = 1 << 4, | |
466 | NVME_NS_DPC_PI_FIRST = 1 << 3, | |
467 | NVME_NS_DPC_PI_TYPE3 = 1 << 2, | |
468 | NVME_NS_DPC_PI_TYPE2 = 1 << 1, | |
469 | NVME_NS_DPC_PI_TYPE1 = 1 << 0, | |
470 | NVME_NS_DPS_PI_FIRST = 1 << 3, | |
471 | NVME_NS_DPS_PI_MASK = 0x7, | |
472 | NVME_NS_DPS_PI_TYPE1 = 1, | |
473 | NVME_NS_DPS_PI_TYPE2 = 2, | |
474 | NVME_NS_DPS_PI_TYPE3 = 3, | |
475 | }; | |
476 | ||
477 | /* Identify Namespace Metadata Capabilities (MC): */ | |
478 | enum { | |
479 | NVME_MC_EXTENDED_LBA = (1 << 0), | |
480 | NVME_MC_METADATA_PTR = (1 << 1), | |
481 | }; | |
482 | ||
483 | struct nvme_ns_id_desc { | |
484 | __u8 nidt; | |
485 | __u8 nidl; | |
486 | __le16 reserved; | |
487 | }; | |
488 | ||
489 | #define NVME_NIDT_EUI64_LEN 8 | |
490 | #define NVME_NIDT_NGUID_LEN 16 | |
491 | #define NVME_NIDT_UUID_LEN 16 | |
492 | #define NVME_NIDT_CSI_LEN 1 | |
493 | ||
494 | enum { | |
495 | NVME_NIDT_EUI64 = 0x01, | |
496 | NVME_NIDT_NGUID = 0x02, | |
497 | NVME_NIDT_UUID = 0x03, | |
498 | NVME_NIDT_CSI = 0x04, | |
499 | }; | |
500 | ||
501 | struct nvme_smart_log { | |
502 | __u8 critical_warning; | |
503 | __u8 temperature[2]; | |
504 | __u8 avail_spare; | |
505 | __u8 spare_thresh; | |
506 | __u8 percent_used; | |
507 | __u8 endu_grp_crit_warn_sumry; | |
508 | __u8 rsvd7[25]; | |
509 | __u8 data_units_read[16]; | |
510 | __u8 data_units_written[16]; | |
511 | __u8 host_reads[16]; | |
512 | __u8 host_writes[16]; | |
513 | __u8 ctrl_busy_time[16]; | |
514 | __u8 power_cycles[16]; | |
515 | __u8 power_on_hours[16]; | |
516 | __u8 unsafe_shutdowns[16]; | |
517 | __u8 media_errors[16]; | |
518 | __u8 num_err_log_entries[16]; | |
519 | __le32 warning_temp_time; | |
520 | __le32 critical_comp_time; | |
521 | __le16 temp_sensor[8]; | |
522 | __le32 thm_temp1_trans_count; | |
523 | __le32 thm_temp2_trans_count; | |
524 | __le32 thm_temp1_total_time; | |
525 | __le32 thm_temp2_total_time; | |
526 | __u8 rsvd232[280]; | |
527 | }; | |
528 | ||
529 | struct nvme_fw_slot_info_log { | |
530 | __u8 afi; | |
531 | __u8 rsvd1[7]; | |
532 | __le64 frs[7]; | |
533 | __u8 rsvd64[448]; | |
534 | }; | |
535 | ||
536 | enum { | |
537 | NVME_CMD_EFFECTS_CSUPP = 1 << 0, | |
538 | NVME_CMD_EFFECTS_LBCC = 1 << 1, | |
539 | NVME_CMD_EFFECTS_NCC = 1 << 2, | |
540 | NVME_CMD_EFFECTS_NIC = 1 << 3, | |
541 | NVME_CMD_EFFECTS_CCC = 1 << 4, | |
542 | NVME_CMD_EFFECTS_CSE_MASK = 3 << 16, | |
543 | NVME_CMD_EFFECTS_UUID_SEL = 1 << 19, | |
544 | }; | |
545 | ||
546 | struct nvme_effects_log { | |
547 | __le32 acs[256]; | |
548 | __le32 iocs[256]; | |
549 | __u8 resv[2048]; | |
550 | }; | |
551 | ||
552 | enum nvme_ana_state { | |
553 | NVME_ANA_OPTIMIZED = 0x01, | |
554 | NVME_ANA_NONOPTIMIZED = 0x02, | |
555 | NVME_ANA_INACCESSIBLE = 0x03, | |
556 | NVME_ANA_PERSISTENT_LOSS = 0x04, | |
557 | NVME_ANA_CHANGE = 0x0f, | |
558 | }; | |
559 | ||
560 | struct nvme_ana_group_desc { | |
561 | __le32 grpid; | |
562 | __le32 nnsids; | |
563 | __le64 chgcnt; | |
564 | __u8 state; | |
565 | __u8 rsvd17[15]; | |
566 | __le32 nsids[]; | |
567 | }; | |
568 | ||
569 | /* flag for the log specific field of the ANA log */ | |
570 | #define NVME_ANA_LOG_RGO (1 << 0) | |
571 | ||
572 | struct nvme_ana_rsp_hdr { | |
573 | __le64 chgcnt; | |
574 | __le16 ngrps; | |
575 | __le16 rsvd10[3]; | |
576 | }; | |
577 | ||
578 | struct nvme_zone_descriptor { | |
579 | __u8 zt; | |
580 | __u8 zs; | |
581 | __u8 za; | |
582 | __u8 rsvd3[5]; | |
583 | __le64 zcap; | |
584 | __le64 zslba; | |
585 | __le64 wp; | |
586 | __u8 rsvd32[32]; | |
587 | }; | |
588 | ||
589 | enum { | |
590 | NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2, | |
591 | }; | |
592 | ||
593 | struct nvme_zone_report { | |
594 | __le64 nr_zones; | |
595 | __u8 resv8[56]; | |
596 | struct nvme_zone_descriptor entries[]; | |
597 | }; | |
598 | ||
599 | enum { | |
600 | NVME_SMART_CRIT_SPARE = 1 << 0, | |
601 | NVME_SMART_CRIT_TEMPERATURE = 1 << 1, | |
602 | NVME_SMART_CRIT_RELIABILITY = 1 << 2, | |
603 | NVME_SMART_CRIT_MEDIA = 1 << 3, | |
604 | NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4, | |
605 | }; | |
606 | ||
607 | enum { | |
608 | NVME_AER_ERROR = 0, | |
609 | NVME_AER_SMART = 1, | |
610 | NVME_AER_NOTICE = 2, | |
611 | NVME_AER_CSS = 6, | |
612 | NVME_AER_VS = 7, | |
613 | }; | |
614 | ||
615 | enum { | |
616 | NVME_AER_NOTICE_NS_CHANGED = 0x00, | |
617 | NVME_AER_NOTICE_FW_ACT_STARTING = 0x01, | |
618 | NVME_AER_NOTICE_ANA = 0x03, | |
619 | NVME_AER_NOTICE_DISC_CHANGED = 0xf0, | |
620 | }; | |
621 | ||
622 | enum { | |
623 | NVME_AEN_BIT_NS_ATTR = 8, | |
624 | NVME_AEN_BIT_FW_ACT = 9, | |
625 | NVME_AEN_BIT_ANA_CHANGE = 11, | |
626 | NVME_AEN_BIT_DISC_CHANGE = 31, | |
627 | }; | |
628 | ||
629 | enum { | |
630 | NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR, | |
631 | NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT, | |
632 | NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE, | |
633 | NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE, | |
634 | }; | |
635 | ||
636 | struct nvme_lba_range_type { | |
637 | __u8 type; | |
638 | __u8 attributes; | |
639 | __u8 rsvd2[14]; | |
640 | __le64 slba; | |
641 | __le64 nlb; | |
642 | __u8 guid[16]; | |
643 | __u8 rsvd48[16]; | |
644 | }; | |
645 | ||
646 | enum { | |
647 | NVME_LBART_TYPE_FS = 0x01, | |
648 | NVME_LBART_TYPE_RAID = 0x02, | |
649 | NVME_LBART_TYPE_CACHE = 0x03, | |
650 | NVME_LBART_TYPE_SWAP = 0x04, | |
651 | ||
652 | NVME_LBART_ATTRIB_TEMP = 1 << 0, | |
653 | NVME_LBART_ATTRIB_HIDE = 1 << 1, | |
654 | }; | |
655 | ||
656 | struct nvme_reservation_status { | |
657 | __le32 gen; | |
658 | __u8 rtype; | |
659 | __u8 regctl[2]; | |
660 | __u8 resv5[2]; | |
661 | __u8 ptpls; | |
662 | __u8 resv10[13]; | |
663 | struct { | |
664 | __le16 cntlid; | |
665 | __u8 rcsts; | |
666 | __u8 resv3[5]; | |
667 | __le64 hostid; | |
668 | __le64 rkey; | |
669 | } regctl_ds[]; | |
670 | }; | |
671 | ||
672 | enum nvme_async_event_type { | |
673 | NVME_AER_TYPE_ERROR = 0, | |
674 | NVME_AER_TYPE_SMART = 1, | |
675 | NVME_AER_TYPE_NOTICE = 2, | |
676 | }; | |
677 | ||
678 | /* I/O commands */ | |
679 | ||
680 | enum nvme_opcode { | |
681 | nvme_cmd_flush = 0x00, | |
682 | nvme_cmd_write = 0x01, | |
683 | nvme_cmd_read = 0x02, | |
684 | nvme_cmd_write_uncor = 0x04, | |
685 | nvme_cmd_compare = 0x05, | |
686 | nvme_cmd_write_zeroes = 0x08, | |
687 | nvme_cmd_dsm = 0x09, | |
688 | nvme_cmd_verify = 0x0c, | |
689 | nvme_cmd_resv_register = 0x0d, | |
690 | nvme_cmd_resv_report = 0x0e, | |
691 | nvme_cmd_resv_acquire = 0x11, | |
692 | nvme_cmd_resv_release = 0x15, | |
693 | nvme_cmd_zone_mgmt_send = 0x79, | |
694 | nvme_cmd_zone_mgmt_recv = 0x7a, | |
695 | nvme_cmd_zone_append = 0x7d, | |
696 | }; | |
697 | ||
698 | #define nvme_opcode_name(opcode) { opcode, #opcode } | |
699 | #define show_nvm_opcode_name(val) \ | |
700 | __print_symbolic(val, \ | |
701 | nvme_opcode_name(nvme_cmd_flush), \ | |
702 | nvme_opcode_name(nvme_cmd_write), \ | |
703 | nvme_opcode_name(nvme_cmd_read), \ | |
704 | nvme_opcode_name(nvme_cmd_write_uncor), \ | |
705 | nvme_opcode_name(nvme_cmd_compare), \ | |
706 | nvme_opcode_name(nvme_cmd_write_zeroes), \ | |
707 | nvme_opcode_name(nvme_cmd_dsm), \ | |
708 | nvme_opcode_name(nvme_cmd_resv_register), \ | |
709 | nvme_opcode_name(nvme_cmd_resv_report), \ | |
710 | nvme_opcode_name(nvme_cmd_resv_acquire), \ | |
711 | nvme_opcode_name(nvme_cmd_resv_release), \ | |
712 | nvme_opcode_name(nvme_cmd_zone_mgmt_send), \ | |
713 | nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \ | |
714 | nvme_opcode_name(nvme_cmd_zone_append)) | |
715 | ||
716 | ||
717 | ||
718 | /* | |
719 | * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier | |
720 | * | |
721 | * @NVME_SGL_FMT_ADDRESS: absolute address of the data block | |
722 | * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block | |
723 | * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA | |
724 | * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation | |
725 | * request subtype | |
726 | */ | |
727 | enum { | |
728 | NVME_SGL_FMT_ADDRESS = 0x00, | |
729 | NVME_SGL_FMT_OFFSET = 0x01, | |
730 | NVME_SGL_FMT_TRANSPORT_A = 0x0A, | |
731 | NVME_SGL_FMT_INVALIDATE = 0x0f, | |
732 | }; | |
733 | ||
734 | /* | |
735 | * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier | |
736 | * | |
737 | * For struct nvme_sgl_desc: | |
738 | * @NVME_SGL_FMT_DATA_DESC: data block descriptor | |
739 | * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor | |
740 | * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor | |
741 | * | |
742 | * For struct nvme_keyed_sgl_desc: | |
743 | * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor | |
744 | * | |
745 | * Transport-specific SGL types: | |
746 | * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor | |
747 | */ | |
748 | enum { | |
749 | NVME_SGL_FMT_DATA_DESC = 0x00, | |
750 | NVME_SGL_FMT_SEG_DESC = 0x02, | |
751 | NVME_SGL_FMT_LAST_SEG_DESC = 0x03, | |
752 | NVME_KEY_SGL_FMT_DATA_DESC = 0x04, | |
753 | NVME_TRANSPORT_SGL_DATA_DESC = 0x05, | |
754 | }; | |
755 | ||
756 | struct nvme_sgl_desc { | |
757 | __le64 addr; | |
758 | __le32 length; | |
759 | __u8 rsvd[3]; | |
760 | __u8 type; | |
761 | }; | |
762 | ||
763 | struct nvme_keyed_sgl_desc { | |
764 | __le64 addr; | |
765 | __u8 length[3]; | |
766 | __u8 key[4]; | |
767 | __u8 type; | |
768 | }; | |
769 | ||
770 | union nvme_data_ptr { | |
771 | struct { | |
772 | __le64 prp1; | |
773 | __le64 prp2; | |
774 | }; | |
775 | struct nvme_sgl_desc sgl; | |
776 | struct nvme_keyed_sgl_desc ksgl; | |
777 | }; | |
778 | ||
779 | /* | |
780 | * Lowest two bits of our flags field (FUSE field in the spec): | |
781 | * | |
782 | * @NVME_CMD_FUSE_FIRST: Fused Operation, first command | |
783 | * @NVME_CMD_FUSE_SECOND: Fused Operation, second command | |
784 | * | |
785 | * Highest two bits in our flags field (PSDT field in the spec): | |
786 | * | |
787 | * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer, | |
788 | * If used, MPTR contains addr of single physical buffer (byte aligned). | |
789 | * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer, | |
790 | * If used, MPTR contains an address of an SGL segment containing | |
791 | * exactly 1 SGL descriptor (qword aligned). | |
792 | */ | |
793 | enum { | |
794 | NVME_CMD_FUSE_FIRST = (1 << 0), | |
795 | NVME_CMD_FUSE_SECOND = (1 << 1), | |
796 | ||
797 | NVME_CMD_SGL_METABUF = (1 << 6), | |
798 | NVME_CMD_SGL_METASEG = (1 << 7), | |
799 | NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG, | |
800 | }; | |
801 | ||
802 | struct nvme_common_command { | |
803 | __u8 opcode; | |
804 | __u8 flags; | |
805 | __u16 command_id; | |
806 | __le32 nsid; | |
807 | __le32 cdw2[2]; | |
808 | __le64 metadata; | |
809 | union nvme_data_ptr dptr; | |
810 | __le32 cdw10; | |
811 | __le32 cdw11; | |
812 | __le32 cdw12; | |
813 | __le32 cdw13; | |
814 | __le32 cdw14; | |
815 | __le32 cdw15; | |
816 | }; | |
817 | ||
818 | struct nvme_rw_command { | |
819 | __u8 opcode; | |
820 | __u8 flags; | |
821 | __u16 command_id; | |
822 | __le32 nsid; | |
823 | __u64 rsvd2; | |
824 | __le64 metadata; | |
825 | union nvme_data_ptr dptr; | |
826 | __le64 slba; | |
827 | __le16 length; | |
828 | __le16 control; | |
829 | __le32 dsmgmt; | |
830 | __le32 reftag; | |
831 | __le16 apptag; | |
832 | __le16 appmask; | |
833 | }; | |
834 | ||
835 | enum { | |
836 | NVME_RW_LR = 1 << 15, | |
837 | NVME_RW_FUA = 1 << 14, | |
838 | NVME_RW_APPEND_PIREMAP = 1 << 9, | |
839 | NVME_RW_DSM_FREQ_UNSPEC = 0, | |
840 | NVME_RW_DSM_FREQ_TYPICAL = 1, | |
841 | NVME_RW_DSM_FREQ_RARE = 2, | |
842 | NVME_RW_DSM_FREQ_READS = 3, | |
843 | NVME_RW_DSM_FREQ_WRITES = 4, | |
844 | NVME_RW_DSM_FREQ_RW = 5, | |
845 | NVME_RW_DSM_FREQ_ONCE = 6, | |
846 | NVME_RW_DSM_FREQ_PREFETCH = 7, | |
847 | NVME_RW_DSM_FREQ_TEMP = 8, | |
848 | NVME_RW_DSM_LATENCY_NONE = 0 << 4, | |
849 | NVME_RW_DSM_LATENCY_IDLE = 1 << 4, | |
850 | NVME_RW_DSM_LATENCY_NORM = 2 << 4, | |
851 | NVME_RW_DSM_LATENCY_LOW = 3 << 4, | |
852 | NVME_RW_DSM_SEQ_REQ = 1 << 6, | |
853 | NVME_RW_DSM_COMPRESSED = 1 << 7, | |
854 | NVME_RW_PRINFO_PRCHK_REF = 1 << 10, | |
855 | NVME_RW_PRINFO_PRCHK_APP = 1 << 11, | |
856 | NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12, | |
857 | NVME_RW_PRINFO_PRACT = 1 << 13, | |
858 | NVME_RW_DTYPE_STREAMS = 1 << 4, | |
859 | }; | |
860 | ||
861 | struct nvme_dsm_cmd { | |
862 | __u8 opcode; | |
863 | __u8 flags; | |
864 | __u16 command_id; | |
865 | __le32 nsid; | |
866 | __u64 rsvd2[2]; | |
867 | union nvme_data_ptr dptr; | |
868 | __le32 nr; | |
869 | __le32 attributes; | |
870 | __u32 rsvd12[4]; | |
871 | }; | |
872 | ||
873 | enum { | |
874 | NVME_DSMGMT_IDR = 1 << 0, | |
875 | NVME_DSMGMT_IDW = 1 << 1, | |
876 | NVME_DSMGMT_AD = 1 << 2, | |
877 | }; | |
878 | ||
879 | #define NVME_DSM_MAX_RANGES 256 | |
880 | ||
881 | struct nvme_dsm_range { | |
882 | __le32 cattr; | |
883 | __le32 nlb; | |
884 | __le64 slba; | |
885 | }; | |
886 | ||
887 | struct nvme_write_zeroes_cmd { | |
888 | __u8 opcode; | |
889 | __u8 flags; | |
890 | __u16 command_id; | |
891 | __le32 nsid; | |
892 | __u64 rsvd2; | |
893 | __le64 metadata; | |
894 | union nvme_data_ptr dptr; | |
895 | __le64 slba; | |
896 | __le16 length; | |
897 | __le16 control; | |
898 | __le32 dsmgmt; | |
899 | __le32 reftag; | |
900 | __le16 apptag; | |
901 | __le16 appmask; | |
902 | }; | |
903 | ||
904 | enum nvme_zone_mgmt_action { | |
905 | NVME_ZONE_CLOSE = 0x1, | |
906 | NVME_ZONE_FINISH = 0x2, | |
907 | NVME_ZONE_OPEN = 0x3, | |
908 | NVME_ZONE_RESET = 0x4, | |
909 | NVME_ZONE_OFFLINE = 0x5, | |
910 | NVME_ZONE_SET_DESC_EXT = 0x10, | |
911 | }; | |
912 | ||
913 | struct nvme_zone_mgmt_send_cmd { | |
914 | __u8 opcode; | |
915 | __u8 flags; | |
916 | __u16 command_id; | |
917 | __le32 nsid; | |
918 | __le32 cdw2[2]; | |
919 | __le64 metadata; | |
920 | union nvme_data_ptr dptr; | |
921 | __le64 slba; | |
922 | __le32 cdw12; | |
923 | __u8 zsa; | |
924 | __u8 select_all; | |
925 | __u8 rsvd13[2]; | |
926 | __le32 cdw14[2]; | |
927 | }; | |
928 | ||
929 | struct nvme_zone_mgmt_recv_cmd { | |
930 | __u8 opcode; | |
931 | __u8 flags; | |
932 | __u16 command_id; | |
933 | __le32 nsid; | |
934 | __le64 rsvd2[2]; | |
935 | union nvme_data_ptr dptr; | |
936 | __le64 slba; | |
937 | __le32 numd; | |
938 | __u8 zra; | |
939 | __u8 zrasf; | |
940 | __u8 pr; | |
941 | __u8 rsvd13; | |
942 | __le32 cdw14[2]; | |
943 | }; | |
944 | ||
945 | enum { | |
946 | NVME_ZRA_ZONE_REPORT = 0, | |
947 | NVME_ZRASF_ZONE_REPORT_ALL = 0, | |
948 | NVME_ZRASF_ZONE_STATE_EMPTY = 0x01, | |
949 | NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02, | |
950 | NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03, | |
951 | NVME_ZRASF_ZONE_STATE_CLOSED = 0x04, | |
952 | NVME_ZRASF_ZONE_STATE_READONLY = 0x05, | |
953 | NVME_ZRASF_ZONE_STATE_FULL = 0x06, | |
954 | NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07, | |
955 | NVME_REPORT_ZONE_PARTIAL = 1, | |
956 | }; | |
957 | ||
958 | /* Features */ | |
959 | ||
960 | enum { | |
961 | NVME_TEMP_THRESH_MASK = 0xffff, | |
962 | NVME_TEMP_THRESH_SELECT_SHIFT = 16, | |
963 | NVME_TEMP_THRESH_TYPE_UNDER = 0x100000, | |
964 | }; | |
965 | ||
966 | struct nvme_feat_auto_pst { | |
967 | __le64 entries[32]; | |
968 | }; | |
969 | ||
970 | enum { | |
971 | NVME_HOST_MEM_ENABLE = (1 << 0), | |
972 | NVME_HOST_MEM_RETURN = (1 << 1), | |
973 | }; | |
974 | ||
975 | struct nvme_feat_host_behavior { | |
976 | __u8 acre; | |
977 | __u8 resv1[511]; | |
978 | }; | |
979 | ||
980 | enum { | |
981 | NVME_ENABLE_ACRE = 1, | |
982 | }; | |
983 | ||
984 | /* Admin commands */ | |
985 | ||
986 | enum nvme_admin_opcode { | |
987 | nvme_admin_delete_sq = 0x00, | |
988 | nvme_admin_create_sq = 0x01, | |
989 | nvme_admin_get_log_page = 0x02, | |
990 | nvme_admin_delete_cq = 0x04, | |
991 | nvme_admin_create_cq = 0x05, | |
992 | nvme_admin_identify = 0x06, | |
993 | nvme_admin_abort_cmd = 0x08, | |
994 | nvme_admin_set_features = 0x09, | |
995 | nvme_admin_get_features = 0x0a, | |
996 | nvme_admin_async_event = 0x0c, | |
997 | nvme_admin_ns_mgmt = 0x0d, | |
998 | nvme_admin_activate_fw = 0x10, | |
999 | nvme_admin_download_fw = 0x11, | |
1000 | nvme_admin_dev_self_test = 0x14, | |
1001 | nvme_admin_ns_attach = 0x15, | |
1002 | nvme_admin_keep_alive = 0x18, | |
1003 | nvme_admin_directive_send = 0x19, | |
1004 | nvme_admin_directive_recv = 0x1a, | |
1005 | nvme_admin_virtual_mgmt = 0x1c, | |
1006 | nvme_admin_nvme_mi_send = 0x1d, | |
1007 | nvme_admin_nvme_mi_recv = 0x1e, | |
1008 | nvme_admin_dbbuf = 0x7C, | |
1009 | nvme_admin_format_nvm = 0x80, | |
1010 | nvme_admin_security_send = 0x81, | |
1011 | nvme_admin_security_recv = 0x82, | |
1012 | nvme_admin_sanitize_nvm = 0x84, | |
1013 | nvme_admin_get_lba_status = 0x86, | |
1014 | nvme_admin_vendor_start = 0xC0, | |
1015 | }; | |
1016 | ||
1017 | #define nvme_admin_opcode_name(opcode) { opcode, #opcode } | |
1018 | #define show_admin_opcode_name(val) \ | |
1019 | __print_symbolic(val, \ | |
1020 | nvme_admin_opcode_name(nvme_admin_delete_sq), \ | |
1021 | nvme_admin_opcode_name(nvme_admin_create_sq), \ | |
1022 | nvme_admin_opcode_name(nvme_admin_get_log_page), \ | |
1023 | nvme_admin_opcode_name(nvme_admin_delete_cq), \ | |
1024 | nvme_admin_opcode_name(nvme_admin_create_cq), \ | |
1025 | nvme_admin_opcode_name(nvme_admin_identify), \ | |
1026 | nvme_admin_opcode_name(nvme_admin_abort_cmd), \ | |
1027 | nvme_admin_opcode_name(nvme_admin_set_features), \ | |
1028 | nvme_admin_opcode_name(nvme_admin_get_features), \ | |
1029 | nvme_admin_opcode_name(nvme_admin_async_event), \ | |
1030 | nvme_admin_opcode_name(nvme_admin_ns_mgmt), \ | |
1031 | nvme_admin_opcode_name(nvme_admin_activate_fw), \ | |
1032 | nvme_admin_opcode_name(nvme_admin_download_fw), \ | |
1033 | nvme_admin_opcode_name(nvme_admin_ns_attach), \ | |
1034 | nvme_admin_opcode_name(nvme_admin_keep_alive), \ | |
1035 | nvme_admin_opcode_name(nvme_admin_directive_send), \ | |
1036 | nvme_admin_opcode_name(nvme_admin_directive_recv), \ | |
1037 | nvme_admin_opcode_name(nvme_admin_dbbuf), \ | |
1038 | nvme_admin_opcode_name(nvme_admin_format_nvm), \ | |
1039 | nvme_admin_opcode_name(nvme_admin_security_send), \ | |
1040 | nvme_admin_opcode_name(nvme_admin_security_recv), \ | |
1041 | nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \ | |
1042 | nvme_admin_opcode_name(nvme_admin_get_lba_status)) | |
1043 | ||
1044 | enum { | |
1045 | NVME_QUEUE_PHYS_CONTIG = (1 << 0), | |
1046 | NVME_CQ_IRQ_ENABLED = (1 << 1), | |
1047 | NVME_SQ_PRIO_URGENT = (0 << 1), | |
1048 | NVME_SQ_PRIO_HIGH = (1 << 1), | |
1049 | NVME_SQ_PRIO_MEDIUM = (2 << 1), | |
1050 | NVME_SQ_PRIO_LOW = (3 << 1), | |
1051 | NVME_FEAT_ARBITRATION = 0x01, | |
1052 | NVME_FEAT_POWER_MGMT = 0x02, | |
1053 | NVME_FEAT_LBA_RANGE = 0x03, | |
1054 | NVME_FEAT_TEMP_THRESH = 0x04, | |
1055 | NVME_FEAT_ERR_RECOVERY = 0x05, | |
1056 | NVME_FEAT_VOLATILE_WC = 0x06, | |
1057 | NVME_FEAT_NUM_QUEUES = 0x07, | |
1058 | NVME_FEAT_IRQ_COALESCE = 0x08, | |
1059 | NVME_FEAT_IRQ_CONFIG = 0x09, | |
1060 | NVME_FEAT_WRITE_ATOMIC = 0x0a, | |
1061 | NVME_FEAT_ASYNC_EVENT = 0x0b, | |
1062 | NVME_FEAT_AUTO_PST = 0x0c, | |
1063 | NVME_FEAT_HOST_MEM_BUF = 0x0d, | |
1064 | NVME_FEAT_TIMESTAMP = 0x0e, | |
1065 | NVME_FEAT_KATO = 0x0f, | |
1066 | NVME_FEAT_HCTM = 0x10, | |
1067 | NVME_FEAT_NOPSC = 0x11, | |
1068 | NVME_FEAT_RRL = 0x12, | |
1069 | NVME_FEAT_PLM_CONFIG = 0x13, | |
1070 | NVME_FEAT_PLM_WINDOW = 0x14, | |
1071 | NVME_FEAT_HOST_BEHAVIOR = 0x16, | |
1072 | NVME_FEAT_SANITIZE = 0x17, | |
1073 | NVME_FEAT_SW_PROGRESS = 0x80, | |
1074 | NVME_FEAT_HOST_ID = 0x81, | |
1075 | NVME_FEAT_RESV_MASK = 0x82, | |
1076 | NVME_FEAT_RESV_PERSIST = 0x83, | |
1077 | NVME_FEAT_WRITE_PROTECT = 0x84, | |
1078 | NVME_FEAT_VENDOR_START = 0xC0, | |
1079 | NVME_FEAT_VENDOR_END = 0xFF, | |
1080 | NVME_LOG_ERROR = 0x01, | |
1081 | NVME_LOG_SMART = 0x02, | |
1082 | NVME_LOG_FW_SLOT = 0x03, | |
1083 | NVME_LOG_CHANGED_NS = 0x04, | |
1084 | NVME_LOG_CMD_EFFECTS = 0x05, | |
1085 | NVME_LOG_DEVICE_SELF_TEST = 0x06, | |
1086 | NVME_LOG_TELEMETRY_HOST = 0x07, | |
1087 | NVME_LOG_TELEMETRY_CTRL = 0x08, | |
1088 | NVME_LOG_ENDURANCE_GROUP = 0x09, | |
1089 | NVME_LOG_ANA = 0x0c, | |
1090 | NVME_LOG_DISC = 0x70, | |
1091 | NVME_LOG_RESERVATION = 0x80, | |
1092 | NVME_FWACT_REPL = (0 << 3), | |
1093 | NVME_FWACT_REPL_ACTV = (1 << 3), | |
1094 | NVME_FWACT_ACTV = (2 << 3), | |
1095 | }; | |
1096 | ||
1097 | /* NVMe Namespace Write Protect State */ | |
1098 | enum { | |
1099 | NVME_NS_NO_WRITE_PROTECT = 0, | |
1100 | NVME_NS_WRITE_PROTECT, | |
1101 | NVME_NS_WRITE_PROTECT_POWER_CYCLE, | |
1102 | NVME_NS_WRITE_PROTECT_PERMANENT, | |
1103 | }; | |
1104 | ||
1105 | #define NVME_MAX_CHANGED_NAMESPACES 1024 | |
1106 | ||
1107 | struct nvme_identify { | |
1108 | __u8 opcode; | |
1109 | __u8 flags; | |
1110 | __u16 command_id; | |
1111 | __le32 nsid; | |
1112 | __u64 rsvd2[2]; | |
1113 | union nvme_data_ptr dptr; | |
1114 | __u8 cns; | |
1115 | __u8 rsvd3; | |
1116 | __le16 ctrlid; | |
1117 | __u8 rsvd11[3]; | |
1118 | __u8 csi; | |
1119 | __u32 rsvd12[4]; | |
1120 | }; | |
1121 | ||
1122 | #define NVME_IDENTIFY_DATA_SIZE 4096 | |
1123 | ||
1124 | struct nvme_features { | |
1125 | __u8 opcode; | |
1126 | __u8 flags; | |
1127 | __u16 command_id; | |
1128 | __le32 nsid; | |
1129 | __u64 rsvd2[2]; | |
1130 | union nvme_data_ptr dptr; | |
1131 | __le32 fid; | |
1132 | __le32 dword11; | |
1133 | __le32 dword12; | |
1134 | __le32 dword13; | |
1135 | __le32 dword14; | |
1136 | __le32 dword15; | |
1137 | }; | |
1138 | ||
1139 | struct nvme_host_mem_buf_desc { | |
1140 | __le64 addr; | |
1141 | __le32 size; | |
1142 | __u32 rsvd; | |
1143 | }; | |
1144 | ||
1145 | struct nvme_create_cq { | |
1146 | __u8 opcode; | |
1147 | __u8 flags; | |
1148 | __u16 command_id; | |
1149 | __u32 rsvd1[5]; | |
1150 | __le64 prp1; | |
1151 | __u64 rsvd8; | |
1152 | __le16 cqid; | |
1153 | __le16 qsize; | |
1154 | __le16 cq_flags; | |
1155 | __le16 irq_vector; | |
1156 | __u32 rsvd12[4]; | |
1157 | }; | |
1158 | ||
1159 | struct nvme_create_sq { | |
1160 | __u8 opcode; | |
1161 | __u8 flags; | |
1162 | __u16 command_id; | |
1163 | __u32 rsvd1[5]; | |
1164 | __le64 prp1; | |
1165 | __u64 rsvd8; | |
1166 | __le16 sqid; | |
1167 | __le16 qsize; | |
1168 | __le16 sq_flags; | |
1169 | __le16 cqid; | |
1170 | __u32 rsvd12[4]; | |
1171 | }; | |
1172 | ||
1173 | struct nvme_delete_queue { | |
1174 | __u8 opcode; | |
1175 | __u8 flags; | |
1176 | __u16 command_id; | |
1177 | __u32 rsvd1[9]; | |
1178 | __le16 qid; | |
1179 | __u16 rsvd10; | |
1180 | __u32 rsvd11[5]; | |
1181 | }; | |
1182 | ||
1183 | struct nvme_abort_cmd { | |
1184 | __u8 opcode; | |
1185 | __u8 flags; | |
1186 | __u16 command_id; | |
1187 | __u32 rsvd1[9]; | |
1188 | __le16 sqid; | |
1189 | __u16 cid; | |
1190 | __u32 rsvd11[5]; | |
1191 | }; | |
1192 | ||
1193 | struct nvme_download_firmware { | |
1194 | __u8 opcode; | |
1195 | __u8 flags; | |
1196 | __u16 command_id; | |
1197 | __u32 rsvd1[5]; | |
1198 | union nvme_data_ptr dptr; | |
1199 | __le32 numd; | |
1200 | __le32 offset; | |
1201 | __u32 rsvd12[4]; | |
1202 | }; | |
1203 | ||
1204 | struct nvme_format_cmd { | |
1205 | __u8 opcode; | |
1206 | __u8 flags; | |
1207 | __u16 command_id; | |
1208 | __le32 nsid; | |
1209 | __u64 rsvd2[4]; | |
1210 | __le32 cdw10; | |
1211 | __u32 rsvd11[5]; | |
1212 | }; | |
1213 | ||
1214 | struct nvme_get_log_page_command { | |
1215 | __u8 opcode; | |
1216 | __u8 flags; | |
1217 | __u16 command_id; | |
1218 | __le32 nsid; | |
1219 | __u64 rsvd2[2]; | |
1220 | union nvme_data_ptr dptr; | |
1221 | __u8 lid; | |
1222 | __u8 lsp; /* upper 4 bits reserved */ | |
1223 | __le16 numdl; | |
1224 | __le16 numdu; | |
1225 | __u16 rsvd11; | |
1226 | union { | |
1227 | struct { | |
1228 | __le32 lpol; | |
1229 | __le32 lpou; | |
1230 | }; | |
1231 | __le64 lpo; | |
1232 | }; | |
1233 | __u8 rsvd14[3]; | |
1234 | __u8 csi; | |
1235 | __u32 rsvd15; | |
1236 | }; | |
1237 | ||
1238 | struct nvme_directive_cmd { | |
1239 | __u8 opcode; | |
1240 | __u8 flags; | |
1241 | __u16 command_id; | |
1242 | __le32 nsid; | |
1243 | __u64 rsvd2[2]; | |
1244 | union nvme_data_ptr dptr; | |
1245 | __le32 numd; | |
1246 | __u8 doper; | |
1247 | __u8 dtype; | |
1248 | __le16 dspec; | |
1249 | __u8 endir; | |
1250 | __u8 tdtype; | |
1251 | __u16 rsvd15; | |
1252 | ||
1253 | __u32 rsvd16[3]; | |
1254 | }; | |
1255 | ||
1256 | /* | |
1257 | * Fabrics subcommands. | |
1258 | */ | |
1259 | enum nvmf_fabrics_opcode { | |
1260 | nvme_fabrics_command = 0x7f, | |
1261 | }; | |
1262 | ||
1263 | enum nvmf_capsule_command { | |
1264 | nvme_fabrics_type_property_set = 0x00, | |
1265 | nvme_fabrics_type_connect = 0x01, | |
1266 | nvme_fabrics_type_property_get = 0x04, | |
1267 | }; | |
1268 | ||
1269 | #define nvme_fabrics_type_name(type) { type, #type } | |
1270 | #define show_fabrics_type_name(type) \ | |
1271 | __print_symbolic(type, \ | |
1272 | nvme_fabrics_type_name(nvme_fabrics_type_property_set), \ | |
1273 | nvme_fabrics_type_name(nvme_fabrics_type_connect), \ | |
1274 | nvme_fabrics_type_name(nvme_fabrics_type_property_get)) | |
1275 | ||
1276 | /* | |
1277 | * If not fabrics command, fctype will be ignored. | |
1278 | */ | |
1279 | #define show_opcode_name(qid, opcode, fctype) \ | |
1280 | ((opcode) == nvme_fabrics_command ? \ | |
1281 | show_fabrics_type_name(fctype) : \ | |
1282 | ((qid) ? \ | |
1283 | show_nvm_opcode_name(opcode) : \ | |
1284 | show_admin_opcode_name(opcode))) | |
1285 | ||
1286 | struct nvmf_common_command { | |
1287 | __u8 opcode; | |
1288 | __u8 resv1; | |
1289 | __u16 command_id; | |
1290 | __u8 fctype; | |
1291 | __u8 resv2[35]; | |
1292 | __u8 ts[24]; | |
1293 | }; | |
1294 | ||
1295 | /* | |
1296 | * The legal cntlid range a NVMe Target will provide. | |
1297 | * Note that cntlid of value 0 is considered illegal in the fabrics world. | |
1298 | * Devices based on earlier specs did not have the subsystem concept; | |
1299 | * therefore, those devices had their cntlid value set to 0 as a result. | |
1300 | */ | |
1301 | #define NVME_CNTLID_MIN 1 | |
1302 | #define NVME_CNTLID_MAX 0xffef | |
1303 | #define NVME_CNTLID_DYNAMIC 0xffff | |
1304 | ||
1305 | #define MAX_DISC_LOGS 255 | |
1306 | ||
1307 | /* Discovery log page entry */ | |
1308 | struct nvmf_disc_rsp_page_entry { | |
1309 | __u8 trtype; | |
1310 | __u8 adrfam; | |
1311 | __u8 subtype; | |
1312 | __u8 treq; | |
1313 | __le16 portid; | |
1314 | __le16 cntlid; | |
1315 | __le16 asqsz; | |
1316 | __u8 resv8[22]; | |
1317 | char trsvcid[NVMF_TRSVCID_SIZE]; | |
1318 | __u8 resv64[192]; | |
1319 | char subnqn[NVMF_NQN_FIELD_LEN]; | |
1320 | char traddr[NVMF_TRADDR_SIZE]; | |
1321 | union tsas { | |
1322 | char common[NVMF_TSAS_SIZE]; | |
1323 | struct rdma { | |
1324 | __u8 qptype; | |
1325 | __u8 prtype; | |
1326 | __u8 cms; | |
1327 | __u8 resv3[5]; | |
1328 | __u16 pkey; | |
1329 | __u8 resv10[246]; | |
1330 | } rdma; | |
1331 | } tsas; | |
1332 | }; | |
1333 | ||
1334 | /* Discovery log page header */ | |
1335 | struct nvmf_disc_rsp_page_hdr { | |
1336 | __le64 genctr; | |
1337 | __le64 numrec; | |
1338 | __le16 recfmt; | |
1339 | __u8 resv14[1006]; | |
1340 | struct nvmf_disc_rsp_page_entry entries[]; | |
1341 | }; | |
1342 | ||
1343 | enum { | |
1344 | NVME_CONNECT_DISABLE_SQFLOW = (1 << 2), | |
1345 | }; | |
1346 | ||
1347 | struct nvmf_connect_command { | |
1348 | __u8 opcode; | |
1349 | __u8 resv1; | |
1350 | __u16 command_id; | |
1351 | __u8 fctype; | |
1352 | __u8 resv2[19]; | |
1353 | union nvme_data_ptr dptr; | |
1354 | __le16 recfmt; | |
1355 | __le16 qid; | |
1356 | __le16 sqsize; | |
1357 | __u8 cattr; | |
1358 | __u8 resv3; | |
1359 | __le32 kato; | |
1360 | __u8 resv4[12]; | |
1361 | }; | |
1362 | ||
1363 | struct nvmf_connect_data { | |
1364 | uuid_t hostid; | |
1365 | __le16 cntlid; | |
1366 | char resv4[238]; | |
1367 | char subsysnqn[NVMF_NQN_FIELD_LEN]; | |
1368 | char hostnqn[NVMF_NQN_FIELD_LEN]; | |
1369 | char resv5[256]; | |
1370 | }; | |
1371 | ||
1372 | struct nvmf_property_set_command { | |
1373 | __u8 opcode; | |
1374 | __u8 resv1; | |
1375 | __u16 command_id; | |
1376 | __u8 fctype; | |
1377 | __u8 resv2[35]; | |
1378 | __u8 attrib; | |
1379 | __u8 resv3[3]; | |
1380 | __le32 offset; | |
1381 | __le64 value; | |
1382 | __u8 resv4[8]; | |
1383 | }; | |
1384 | ||
1385 | struct nvmf_property_get_command { | |
1386 | __u8 opcode; | |
1387 | __u8 resv1; | |
1388 | __u16 command_id; | |
1389 | __u8 fctype; | |
1390 | __u8 resv2[35]; | |
1391 | __u8 attrib; | |
1392 | __u8 resv3[3]; | |
1393 | __le32 offset; | |
1394 | __u8 resv4[16]; | |
1395 | }; | |
1396 | ||
1397 | struct nvme_dbbuf { | |
1398 | __u8 opcode; | |
1399 | __u8 flags; | |
1400 | __u16 command_id; | |
1401 | __u32 rsvd1[5]; | |
1402 | __le64 prp1; | |
1403 | __le64 prp2; | |
1404 | __u32 rsvd12[6]; | |
1405 | }; | |
1406 | ||
1407 | struct streams_directive_params { | |
1408 | __le16 msl; | |
1409 | __le16 nssa; | |
1410 | __le16 nsso; | |
1411 | __u8 rsvd[10]; | |
1412 | __le32 sws; | |
1413 | __le16 sgs; | |
1414 | __le16 nsa; | |
1415 | __le16 nso; | |
1416 | __u8 rsvd2[6]; | |
1417 | }; | |
1418 | ||
1419 | struct nvme_command { | |
1420 | union { | |
1421 | struct nvme_common_command common; | |
1422 | struct nvme_rw_command rw; | |
1423 | struct nvme_identify identify; | |
1424 | struct nvme_features features; | |
1425 | struct nvme_create_cq create_cq; | |
1426 | struct nvme_create_sq create_sq; | |
1427 | struct nvme_delete_queue delete_queue; | |
1428 | struct nvme_download_firmware dlfw; | |
1429 | struct nvme_format_cmd format; | |
1430 | struct nvme_dsm_cmd dsm; | |
1431 | struct nvme_write_zeroes_cmd write_zeroes; | |
1432 | struct nvme_zone_mgmt_send_cmd zms; | |
1433 | struct nvme_zone_mgmt_recv_cmd zmr; | |
1434 | struct nvme_abort_cmd abort; | |
1435 | struct nvme_get_log_page_command get_log_page; | |
1436 | struct nvmf_common_command fabrics; | |
1437 | struct nvmf_connect_command connect; | |
1438 | struct nvmf_property_set_command prop_set; | |
1439 | struct nvmf_property_get_command prop_get; | |
1440 | struct nvme_dbbuf dbbuf; | |
1441 | struct nvme_directive_cmd directive; | |
1442 | }; | |
1443 | }; | |
1444 | ||
1445 | static inline bool nvme_is_fabrics(struct nvme_command *cmd) | |
1446 | { | |
1447 | return cmd->common.opcode == nvme_fabrics_command; | |
1448 | } | |
1449 | ||
1450 | struct nvme_error_slot { | |
1451 | __le64 error_count; | |
1452 | __le16 sqid; | |
1453 | __le16 cmdid; | |
1454 | __le16 status_field; | |
1455 | __le16 param_error_location; | |
1456 | __le64 lba; | |
1457 | __le32 nsid; | |
1458 | __u8 vs; | |
1459 | __u8 resv[3]; | |
1460 | __le64 cs; | |
1461 | __u8 resv2[24]; | |
1462 | }; | |
1463 | ||
1464 | static inline bool nvme_is_write(struct nvme_command *cmd) | |
1465 | { | |
1466 | /* | |
1467 | * What a mess... | |
1468 | * | |
1469 | * Why can't we simply have a Fabrics In and Fabrics out command? | |
1470 | */ | |
1471 | if (unlikely(nvme_is_fabrics(cmd))) | |
1472 | return cmd->fabrics.fctype & 1; | |
1473 | return cmd->common.opcode & 1; | |
1474 | } | |
1475 | ||
1476 | enum { | |
1477 | /* | |
1478 | * Generic Command Status: | |
1479 | */ | |
1480 | NVME_SC_SUCCESS = 0x0, | |
1481 | NVME_SC_INVALID_OPCODE = 0x1, | |
1482 | NVME_SC_INVALID_FIELD = 0x2, | |
1483 | NVME_SC_CMDID_CONFLICT = 0x3, | |
1484 | NVME_SC_DATA_XFER_ERROR = 0x4, | |
1485 | NVME_SC_POWER_LOSS = 0x5, | |
1486 | NVME_SC_INTERNAL = 0x6, | |
1487 | NVME_SC_ABORT_REQ = 0x7, | |
1488 | NVME_SC_ABORT_QUEUE = 0x8, | |
1489 | NVME_SC_FUSED_FAIL = 0x9, | |
1490 | NVME_SC_FUSED_MISSING = 0xa, | |
1491 | NVME_SC_INVALID_NS = 0xb, | |
1492 | NVME_SC_CMD_SEQ_ERROR = 0xc, | |
1493 | NVME_SC_SGL_INVALID_LAST = 0xd, | |
1494 | NVME_SC_SGL_INVALID_COUNT = 0xe, | |
1495 | NVME_SC_SGL_INVALID_DATA = 0xf, | |
1496 | NVME_SC_SGL_INVALID_METADATA = 0x10, | |
1497 | NVME_SC_SGL_INVALID_TYPE = 0x11, | |
1498 | NVME_SC_CMB_INVALID_USE = 0x12, | |
1499 | NVME_SC_PRP_INVALID_OFFSET = 0x13, | |
1500 | NVME_SC_ATOMIC_WU_EXCEEDED = 0x14, | |
1501 | NVME_SC_OP_DENIED = 0x15, | |
1502 | NVME_SC_SGL_INVALID_OFFSET = 0x16, | |
1503 | NVME_SC_RESERVED = 0x17, | |
1504 | NVME_SC_HOST_ID_INCONSIST = 0x18, | |
1505 | NVME_SC_KA_TIMEOUT_EXPIRED = 0x19, | |
1506 | NVME_SC_KA_TIMEOUT_INVALID = 0x1A, | |
1507 | NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B, | |
1508 | NVME_SC_SANITIZE_FAILED = 0x1C, | |
1509 | NVME_SC_SANITIZE_IN_PROGRESS = 0x1D, | |
1510 | NVME_SC_SGL_INVALID_GRANULARITY = 0x1E, | |
1511 | NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F, | |
1512 | NVME_SC_NS_WRITE_PROTECTED = 0x20, | |
1513 | NVME_SC_CMD_INTERRUPTED = 0x21, | |
1514 | NVME_SC_TRANSIENT_TR_ERR = 0x22, | |
1515 | NVME_SC_INVALID_IO_CMD_SET = 0x2C, | |
1516 | ||
1517 | NVME_SC_LBA_RANGE = 0x80, | |
1518 | NVME_SC_CAP_EXCEEDED = 0x81, | |
1519 | NVME_SC_NS_NOT_READY = 0x82, | |
1520 | NVME_SC_RESERVATION_CONFLICT = 0x83, | |
1521 | NVME_SC_FORMAT_IN_PROGRESS = 0x84, | |
1522 | ||
1523 | /* | |
1524 | * Command Specific Status: | |
1525 | */ | |
1526 | NVME_SC_CQ_INVALID = 0x100, | |
1527 | NVME_SC_QID_INVALID = 0x101, | |
1528 | NVME_SC_QUEUE_SIZE = 0x102, | |
1529 | NVME_SC_ABORT_LIMIT = 0x103, | |
1530 | NVME_SC_ABORT_MISSING = 0x104, | |
1531 | NVME_SC_ASYNC_LIMIT = 0x105, | |
1532 | NVME_SC_FIRMWARE_SLOT = 0x106, | |
1533 | NVME_SC_FIRMWARE_IMAGE = 0x107, | |
1534 | NVME_SC_INVALID_VECTOR = 0x108, | |
1535 | NVME_SC_INVALID_LOG_PAGE = 0x109, | |
1536 | NVME_SC_INVALID_FORMAT = 0x10a, | |
1537 | NVME_SC_FW_NEEDS_CONV_RESET = 0x10b, | |
1538 | NVME_SC_INVALID_QUEUE = 0x10c, | |
1539 | NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d, | |
1540 | NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e, | |
1541 | NVME_SC_FEATURE_NOT_PER_NS = 0x10f, | |
1542 | NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110, | |
1543 | NVME_SC_FW_NEEDS_RESET = 0x111, | |
1544 | NVME_SC_FW_NEEDS_MAX_TIME = 0x112, | |
1545 | NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113, | |
1546 | NVME_SC_OVERLAPPING_RANGE = 0x114, | |
1547 | NVME_SC_NS_INSUFFICIENT_CAP = 0x115, | |
1548 | NVME_SC_NS_ID_UNAVAILABLE = 0x116, | |
1549 | NVME_SC_NS_ALREADY_ATTACHED = 0x118, | |
1550 | NVME_SC_NS_IS_PRIVATE = 0x119, | |
1551 | NVME_SC_NS_NOT_ATTACHED = 0x11a, | |
1552 | NVME_SC_THIN_PROV_NOT_SUPP = 0x11b, | |
1553 | NVME_SC_CTRL_LIST_INVALID = 0x11c, | |
1554 | NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d, | |
1555 | NVME_SC_BP_WRITE_PROHIBITED = 0x11e, | |
1556 | NVME_SC_CTRL_ID_INVALID = 0x11f, | |
1557 | NVME_SC_SEC_CTRL_STATE_INVALID = 0x120, | |
1558 | NVME_SC_CTRL_RES_NUM_INVALID = 0x121, | |
1559 | NVME_SC_RES_ID_INVALID = 0x122, | |
1560 | NVME_SC_PMR_SAN_PROHIBITED = 0x123, | |
1561 | NVME_SC_ANA_GROUP_ID_INVALID = 0x124, | |
1562 | NVME_SC_ANA_ATTACH_FAILED = 0x125, | |
1563 | ||
1564 | /* | |
1565 | * I/O Command Set Specific - NVM commands: | |
1566 | */ | |
1567 | NVME_SC_BAD_ATTRIBUTES = 0x180, | |
1568 | NVME_SC_INVALID_PI = 0x181, | |
1569 | NVME_SC_READ_ONLY = 0x182, | |
1570 | NVME_SC_ONCS_NOT_SUPPORTED = 0x183, | |
1571 | ||
1572 | /* | |
1573 | * I/O Command Set Specific - Fabrics commands: | |
1574 | */ | |
1575 | NVME_SC_CONNECT_FORMAT = 0x180, | |
1576 | NVME_SC_CONNECT_CTRL_BUSY = 0x181, | |
1577 | NVME_SC_CONNECT_INVALID_PARAM = 0x182, | |
1578 | NVME_SC_CONNECT_RESTART_DISC = 0x183, | |
1579 | NVME_SC_CONNECT_INVALID_HOST = 0x184, | |
1580 | ||
1581 | NVME_SC_DISCOVERY_RESTART = 0x190, | |
1582 | NVME_SC_AUTH_REQUIRED = 0x191, | |
1583 | ||
1584 | /* | |
1585 | * I/O Command Set Specific - Zoned commands: | |
1586 | */ | |
1587 | NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8, | |
1588 | NVME_SC_ZONE_FULL = 0x1b9, | |
1589 | NVME_SC_ZONE_READ_ONLY = 0x1ba, | |
1590 | NVME_SC_ZONE_OFFLINE = 0x1bb, | |
1591 | NVME_SC_ZONE_INVALID_WRITE = 0x1bc, | |
1592 | NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd, | |
1593 | NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be, | |
1594 | NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf, | |
1595 | ||
1596 | /* | |
1597 | * Media and Data Integrity Errors: | |
1598 | */ | |
1599 | NVME_SC_WRITE_FAULT = 0x280, | |
1600 | NVME_SC_READ_ERROR = 0x281, | |
1601 | NVME_SC_GUARD_CHECK = 0x282, | |
1602 | NVME_SC_APPTAG_CHECK = 0x283, | |
1603 | NVME_SC_REFTAG_CHECK = 0x284, | |
1604 | NVME_SC_COMPARE_FAILED = 0x285, | |
1605 | NVME_SC_ACCESS_DENIED = 0x286, | |
1606 | NVME_SC_UNWRITTEN_BLOCK = 0x287, | |
1607 | ||
1608 | /* | |
1609 | * Path-related Errors: | |
1610 | */ | |
1611 | NVME_SC_ANA_PERSISTENT_LOSS = 0x301, | |
1612 | NVME_SC_ANA_INACCESSIBLE = 0x302, | |
1613 | NVME_SC_ANA_TRANSITION = 0x303, | |
1614 | NVME_SC_HOST_PATH_ERROR = 0x370, | |
1615 | NVME_SC_HOST_ABORTED_CMD = 0x371, | |
1616 | ||
1617 | NVME_SC_CRD = 0x1800, | |
1618 | NVME_SC_DNR = 0x4000, | |
1619 | }; | |
1620 | ||
1621 | struct nvme_completion { | |
1622 | /* | |
1623 | * Used by Admin and Fabrics commands to return data: | |
1624 | */ | |
1625 | union nvme_result { | |
1626 | __le16 u16; | |
1627 | __le32 u32; | |
1628 | __le64 u64; | |
1629 | } result; | |
1630 | __le16 sq_head; /* how much of this queue may be reclaimed */ | |
1631 | __le16 sq_id; /* submission queue that generated this entry */ | |
1632 | __u16 command_id; /* of the command which completed */ | |
1633 | __le16 status; /* did the command fail, and if so, why? */ | |
1634 | }; | |
1635 | ||
1636 | #define NVME_VS(major, minor, tertiary) \ | |
1637 | (((major) << 16) | ((minor) << 8) | (tertiary)) | |
1638 | ||
1639 | #define NVME_MAJOR(ver) ((ver) >> 16) | |
1640 | #define NVME_MINOR(ver) (((ver) >> 8) & 0xff) | |
1641 | #define NVME_TERTIARY(ver) ((ver) & 0xff) | |
1642 | ||
1643 | #endif /* _LINUX_NVME_H */ |