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PCI: set PCI_PREF_RANGE_TYPE_64 in pci_bridge_check_ranges
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1/*
2 * pci.h
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20#include <linux/pci_regs.h> /* The pci register defines */
21
22/*
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
26 *
27 * 7:3 = slot
28 * 2:0 = function
29 */
30#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32#define PCI_FUNC(devfn) ((devfn) & 0x07)
33
34/* Ioctls for /proc/bus/pci/X/Y nodes. */
35#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
40
41#ifdef __KERNEL__
42
43#include <linux/mod_devicetable.h>
44
45#include <linux/types.h>
46#include <linux/init.h>
47#include <linux/ioport.h>
48#include <linux/list.h>
49#include <linux/compiler.h>
50#include <linux/errno.h>
51#include <linux/kobject.h>
52#include <asm/atomic.h>
53#include <linux/device.h>
54#include <linux/io.h>
55#include <linux/irqreturn.h>
56
57/* Include the ID list */
58#include <linux/pci_ids.h>
59
60/* pci_slot represents a physical slot */
61struct pci_slot {
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
66 struct kobject kobj;
67};
68
69static inline const char *pci_slot_name(const struct pci_slot *slot)
70{
71 return kobject_name(&slot->kobj);
72}
73
74/* File state for mmap()s on /proc/bus/pci/X/Y */
75enum pci_mmap_state {
76 pci_mmap_io,
77 pci_mmap_mem
78};
79
80/* This defines the direction arg to the DMA mapping routines. */
81#define PCI_DMA_BIDIRECTIONAL 0
82#define PCI_DMA_TODEVICE 1
83#define PCI_DMA_FROMDEVICE 2
84#define PCI_DMA_NONE 3
85
86/*
87 * For PCI devices, the region numbers are assigned this way:
88 */
89enum {
90 /* #0-5: standard PCI resources */
91 PCI_STD_RESOURCES,
92 PCI_STD_RESOURCE_END = 5,
93
94 /* #6: expansion ROM resource */
95 PCI_ROM_RESOURCE,
96
97 /* device specific resources */
98#ifdef CONFIG_PCI_IOV
99 PCI_IOV_RESOURCES,
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
101#endif
102
103 /* resources assigned to buses behind the bridge */
104#define PCI_BRIDGE_RESOURCE_NUM 4
105
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
109
110 /* total resources associated with a PCI device */
111 PCI_NUM_RESOURCES,
112
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
115};
116
117typedef int __bitwise pci_power_t;
118
119#define PCI_D0 ((pci_power_t __force) 0)
120#define PCI_D1 ((pci_power_t __force) 1)
121#define PCI_D2 ((pci_power_t __force) 2)
122#define PCI_D3hot ((pci_power_t __force) 3)
123#define PCI_D3cold ((pci_power_t __force) 4)
124#define PCI_UNKNOWN ((pci_power_t __force) 5)
125#define PCI_POWER_ERROR ((pci_power_t __force) -1)
126
127/* Remember to update this when the list above changes! */
128extern const char *pci_power_names[];
129
130static inline const char *pci_power_name(pci_power_t state)
131{
132 return pci_power_names[1 + (int) state];
133}
134
135#define PCI_PM_D2_DELAY 200
136#define PCI_PM_D3_WAIT 10
137#define PCI_PM_BUS_WAIT 50
138
139/** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
142 */
143typedef unsigned int __bitwise pci_channel_state_t;
144
145enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
148
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
151
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
154};
155
156typedef unsigned int __bitwise pcie_reset_state_t;
157
158enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
161
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
164
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
167};
168
169typedef unsigned short __bitwise pci_dev_flags_t;
170enum pci_dev_flags {
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
172 * generation too.
173 */
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177};
178
179enum pci_irq_reroute_variant {
180 INTEL_IRQ_REROUTE_VARIANT = 1,
181 MAX_IRQ_REROUTE_VARIANTS = 3
182};
183
184typedef unsigned short __bitwise pci_bus_flags_t;
185enum pci_bus_flags {
186 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
187 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
188};
189
190/* Based on the PCI Hotplug Spec, but some values are made up by us */
191enum pci_bus_speed {
192 PCI_SPEED_33MHz = 0x00,
193 PCI_SPEED_66MHz = 0x01,
194 PCI_SPEED_66MHz_PCIX = 0x02,
195 PCI_SPEED_100MHz_PCIX = 0x03,
196 PCI_SPEED_133MHz_PCIX = 0x04,
197 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
198 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
199 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
200 PCI_SPEED_66MHz_PCIX_266 = 0x09,
201 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
202 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
203 AGP_UNKNOWN = 0x0c,
204 AGP_1X = 0x0d,
205 AGP_2X = 0x0e,
206 AGP_4X = 0x0f,
207 AGP_8X = 0x10,
208 PCI_SPEED_66MHz_PCIX_533 = 0x11,
209 PCI_SPEED_100MHz_PCIX_533 = 0x12,
210 PCI_SPEED_133MHz_PCIX_533 = 0x13,
211 PCIE_SPEED_2_5GT = 0x14,
212 PCIE_SPEED_5_0GT = 0x15,
213 PCIE_SPEED_8_0GT = 0x16,
214 PCI_SPEED_UNKNOWN = 0xff,
215};
216
217struct pci_cap_saved_state {
218 struct hlist_node next;
219 char cap_nr;
220 u32 data[0];
221};
222
223struct pcie_link_state;
224struct pci_vpd;
225struct pci_sriov;
226struct pci_ats;
227
228/*
229 * The pci_dev structure is used to describe PCI devices.
230 */
231struct pci_dev {
232 struct list_head bus_list; /* node in per-bus list */
233 struct pci_bus *bus; /* bus this device is on */
234 struct pci_bus *subordinate; /* bus this device bridges to */
235
236 void *sysdata; /* hook for sys-specific extension */
237 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
238 struct pci_slot *slot; /* Physical slot this device is in */
239
240 unsigned int devfn; /* encoded device & function index */
241 unsigned short vendor;
242 unsigned short device;
243 unsigned short subsystem_vendor;
244 unsigned short subsystem_device;
245 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
246 u8 revision; /* PCI revision, low byte of class word */
247 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
248 u8 pcie_cap; /* PCI-E capability offset */
249 u8 pcie_type; /* PCI-E device/port type */
250 u8 rom_base_reg; /* which config register controls the ROM */
251 u8 pin; /* which interrupt pin this device uses */
252
253 struct pci_driver *driver; /* which driver has allocated this device */
254 u64 dma_mask; /* Mask of the bits of bus address this
255 device implements. Normally this is
256 0xffffffff. You only need to change
257 this if your device has broken DMA
258 or supports 64-bit transfers. */
259
260 struct device_dma_parameters dma_parms;
261
262 pci_power_t current_state; /* Current operating state. In ACPI-speak,
263 this is D0-D3, D0 being fully functional,
264 and D3 being off. */
265 int pm_cap; /* PM capability offset in the
266 configuration space */
267 unsigned int pme_support:5; /* Bitmask of states from which PME#
268 can be generated */
269 unsigned int d1_support:1; /* Low power state D1 is supported */
270 unsigned int d2_support:1; /* Low power state D2 is supported */
271 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
272 unsigned int wakeup_prepared:1;
273 unsigned int d3_delay; /* D3->D0 transition time in ms */
274
275#ifdef CONFIG_PCIEASPM
276 struct pcie_link_state *link_state; /* ASPM link state. */
277#endif
278
279 pci_channel_state_t error_state; /* current connectivity state */
280 struct device dev; /* Generic device interface */
281
282 int cfg_size; /* Size of configuration space */
283
284 /*
285 * Instead of touching interrupt line and base address registers
286 * directly, use the values stored here. They might be different!
287 */
288 unsigned int irq;
289 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
290
291 /* These fields are used by common fixups */
292 unsigned int transparent:1; /* Transparent PCI bridge */
293 unsigned int multifunction:1;/* Part of multi-function device */
294 /* keep track of device state */
295 unsigned int is_added:1;
296 unsigned int is_busmaster:1; /* device is busmaster */
297 unsigned int no_msi:1; /* device may not use msi */
298 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
299 unsigned int broken_parity_status:1; /* Device generates false positive parity */
300 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
301 unsigned int msi_enabled:1;
302 unsigned int msix_enabled:1;
303 unsigned int ari_enabled:1; /* ARI forwarding */
304 unsigned int is_managed:1;
305 unsigned int is_pcie:1;
306 unsigned int needs_freset:1; /* Dev requires fundamental reset */
307 unsigned int state_saved:1;
308 unsigned int is_physfn:1;
309 unsigned int is_virtfn:1;
310 unsigned int reset_fn:1;
311 unsigned int is_hotplug_bridge:1;
312 unsigned int aer_firmware_first:1;
313 pci_dev_flags_t dev_flags;
314 atomic_t enable_cnt; /* pci_enable_device has been called */
315
316 u32 saved_config_space[16]; /* config space saved at suspend time */
317 struct hlist_head saved_cap_space;
318 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
319 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
320 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
321 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
322#ifdef CONFIG_PCI_MSI
323 struct list_head msi_list;
324#endif
325 struct pci_vpd *vpd;
326#ifdef CONFIG_PCI_IOV
327 union {
328 struct pci_sriov *sriov; /* SR-IOV capability related */
329 struct pci_dev *physfn; /* the PF this VF is associated with */
330 };
331 struct pci_ats *ats; /* Address Translation Service */
332#endif
333};
334
335extern struct pci_dev *alloc_pci_dev(void);
336
337#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
338#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
339#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
340
341static inline int pci_channel_offline(struct pci_dev *pdev)
342{
343 return (pdev->error_state != pci_channel_io_normal);
344}
345
346static inline struct pci_cap_saved_state *pci_find_saved_cap(
347 struct pci_dev *pci_dev, char cap)
348{
349 struct pci_cap_saved_state *tmp;
350 struct hlist_node *pos;
351
352 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
353 if (tmp->cap_nr == cap)
354 return tmp;
355 }
356 return NULL;
357}
358
359static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
360 struct pci_cap_saved_state *new_cap)
361{
362 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
363}
364
365#ifndef PCI_BUS_NUM_RESOURCES
366#define PCI_BUS_NUM_RESOURCES 16
367#endif
368
369#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
370
371struct pci_bus {
372 struct list_head node; /* node in list of buses */
373 struct pci_bus *parent; /* parent bus this bridge is on */
374 struct list_head children; /* list of child buses */
375 struct list_head devices; /* list of devices on this bus */
376 struct pci_dev *self; /* bridge device as seen by parent */
377 struct list_head slots; /* list of slots on this bus */
378 struct resource *resource[PCI_BUS_NUM_RESOURCES];
379 /* address space routed to this bus */
380
381 struct pci_ops *ops; /* configuration access functions */
382 void *sysdata; /* hook for sys-specific extension */
383 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
384
385 unsigned char number; /* bus number */
386 unsigned char primary; /* number of primary bridge */
387 unsigned char secondary; /* number of secondary bridge */
388 unsigned char subordinate; /* max number of subordinate buses */
389 unsigned char max_bus_speed; /* enum pci_bus_speed */
390 unsigned char cur_bus_speed; /* enum pci_bus_speed */
391
392 char name[48];
393
394 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
395 pci_bus_flags_t bus_flags; /* Inherited by child busses */
396 struct device *bridge;
397 struct device dev;
398 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
399 struct bin_attribute *legacy_mem; /* legacy mem */
400 unsigned int is_added:1;
401};
402
403#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
404#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
405
406/*
407 * Returns true if the pci bus is root (behind host-pci bridge),
408 * false otherwise
409 */
410static inline bool pci_is_root_bus(struct pci_bus *pbus)
411{
412 return !(pbus->parent);
413}
414
415#ifdef CONFIG_PCI_MSI
416static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
417{
418 return pci_dev->msi_enabled || pci_dev->msix_enabled;
419}
420#else
421static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
422#endif
423
424/*
425 * Error values that may be returned by PCI functions.
426 */
427#define PCIBIOS_SUCCESSFUL 0x00
428#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
429#define PCIBIOS_BAD_VENDOR_ID 0x83
430#define PCIBIOS_DEVICE_NOT_FOUND 0x86
431#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
432#define PCIBIOS_SET_FAILED 0x88
433#define PCIBIOS_BUFFER_TOO_SMALL 0x89
434
435/* Low-level architecture-dependent routines */
436
437struct pci_ops {
438 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
439 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
440};
441
442/*
443 * ACPI needs to be able to access PCI config space before we've done a
444 * PCI bus scan and created pci_bus structures.
445 */
446extern int raw_pci_read(unsigned int domain, unsigned int bus,
447 unsigned int devfn, int reg, int len, u32 *val);
448extern int raw_pci_write(unsigned int domain, unsigned int bus,
449 unsigned int devfn, int reg, int len, u32 val);
450
451struct pci_bus_region {
452 resource_size_t start;
453 resource_size_t end;
454};
455
456struct pci_dynids {
457 spinlock_t lock; /* protects list, index */
458 struct list_head list; /* for IDs added at runtime */
459};
460
461/* ---------------------------------------------------------------- */
462/** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
463 * a set of callbacks in struct pci_error_handlers, then that device driver
464 * will be notified of PCI bus errors, and will be driven to recovery
465 * when an error occurs.
466 */
467
468typedef unsigned int __bitwise pci_ers_result_t;
469
470enum pci_ers_result {
471 /* no result/none/not supported in device driver */
472 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
473
474 /* Device driver can recover without slot reset */
475 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
476
477 /* Device driver wants slot to be reset. */
478 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
479
480 /* Device has completely failed, is unrecoverable */
481 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
482
483 /* Device driver is fully recovered and operational */
484 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
485};
486
487/* PCI bus error event callbacks */
488struct pci_error_handlers {
489 /* PCI bus error detected on this device */
490 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
491 enum pci_channel_state error);
492
493 /* MMIO has been re-enabled, but not DMA */
494 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
495
496 /* PCI Express link has been reset */
497 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
498
499 /* PCI slot has been reset */
500 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
501
502 /* Device driver may resume normal operations */
503 void (*resume)(struct pci_dev *dev);
504};
505
506/* ---------------------------------------------------------------- */
507
508struct module;
509struct pci_driver {
510 struct list_head node;
511 char *name;
512 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
513 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
514 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
515 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
516 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
517 int (*resume_early) (struct pci_dev *dev);
518 int (*resume) (struct pci_dev *dev); /* Device woken up */
519 void (*shutdown) (struct pci_dev *dev);
520 struct pci_error_handlers *err_handler;
521 struct device_driver driver;
522 struct pci_dynids dynids;
523};
524
525#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
526
527/**
528 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
529 * @_table: device table name
530 *
531 * This macro is used to create a struct pci_device_id array (a device table)
532 * in a generic manner.
533 */
534#define DEFINE_PCI_DEVICE_TABLE(_table) \
535 const struct pci_device_id _table[] __devinitconst
536
537/**
538 * PCI_DEVICE - macro used to describe a specific pci device
539 * @vend: the 16 bit PCI Vendor ID
540 * @dev: the 16 bit PCI Device ID
541 *
542 * This macro is used to create a struct pci_device_id that matches a
543 * specific device. The subvendor and subdevice fields will be set to
544 * PCI_ANY_ID.
545 */
546#define PCI_DEVICE(vend,dev) \
547 .vendor = (vend), .device = (dev), \
548 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
549
550/**
551 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
552 * @dev_class: the class, subclass, prog-if triple for this device
553 * @dev_class_mask: the class mask for this device
554 *
555 * This macro is used to create a struct pci_device_id that matches a
556 * specific PCI class. The vendor, device, subvendor, and subdevice
557 * fields will be set to PCI_ANY_ID.
558 */
559#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
560 .class = (dev_class), .class_mask = (dev_class_mask), \
561 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
562 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
563
564/**
565 * PCI_VDEVICE - macro used to describe a specific pci device in short form
566 * @vendor: the vendor name
567 * @device: the 16 bit PCI Device ID
568 *
569 * This macro is used to create a struct pci_device_id that matches a
570 * specific PCI device. The subvendor, and subdevice fields will be set
571 * to PCI_ANY_ID. The macro allows the next field to follow as the device
572 * private data.
573 */
574
575#define PCI_VDEVICE(vendor, device) \
576 PCI_VENDOR_ID_##vendor, (device), \
577 PCI_ANY_ID, PCI_ANY_ID, 0, 0
578
579/* these external functions are only available when PCI support is enabled */
580#ifdef CONFIG_PCI
581
582extern struct bus_type pci_bus_type;
583
584/* Do NOT directly access these two variables, unless you are arch specific pci
585 * code, or pci core code. */
586extern struct list_head pci_root_buses; /* list of all known PCI buses */
587/* Some device drivers need know if pci is initiated */
588extern int no_pci_devices(void);
589
590void pcibios_fixup_bus(struct pci_bus *);
591int __must_check pcibios_enable_device(struct pci_dev *, int mask);
592char *pcibios_setup(char *str);
593
594/* Used only when drivers/pci/setup.c is used */
595resource_size_t pcibios_align_resource(void *, const struct resource *,
596 resource_size_t,
597 resource_size_t);
598void pcibios_update_irq(struct pci_dev *, int irq);
599
600/* Weak but can be overriden by arch */
601void pci_fixup_cardbus(struct pci_bus *);
602
603/* Generic PCI functions used internally */
604
605extern struct pci_bus *pci_find_bus(int domain, int busnr);
606void pci_bus_add_devices(const struct pci_bus *bus);
607struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
608 struct pci_ops *ops, void *sysdata);
609static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
610 void *sysdata)
611{
612 struct pci_bus *root_bus;
613 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
614 if (root_bus)
615 pci_bus_add_devices(root_bus);
616 return root_bus;
617}
618struct pci_bus *pci_create_bus(struct device *parent, int bus,
619 struct pci_ops *ops, void *sysdata);
620struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
621 int busnr);
622void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
623struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
624 const char *name,
625 struct hotplug_slot *hotplug);
626void pci_destroy_slot(struct pci_slot *slot);
627void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
628int pci_scan_slot(struct pci_bus *bus, int devfn);
629struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
630void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
631unsigned int pci_scan_child_bus(struct pci_bus *bus);
632int __must_check pci_bus_add_device(struct pci_dev *dev);
633void pci_read_bridge_bases(struct pci_bus *child);
634struct resource *pci_find_parent_resource(const struct pci_dev *dev,
635 struct resource *res);
636u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
637int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
638u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
639extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
640extern void pci_dev_put(struct pci_dev *dev);
641extern void pci_remove_bus(struct pci_bus *b);
642extern void pci_remove_bus_device(struct pci_dev *dev);
643extern void pci_stop_bus_device(struct pci_dev *dev);
644void pci_setup_cardbus(struct pci_bus *bus);
645extern void pci_sort_breadthfirst(void);
646
647/* Generic PCI functions exported to card drivers */
648
649enum pci_lost_interrupt_reason {
650 PCI_LOST_IRQ_NO_INFORMATION = 0,
651 PCI_LOST_IRQ_DISABLE_MSI,
652 PCI_LOST_IRQ_DISABLE_MSIX,
653 PCI_LOST_IRQ_DISABLE_ACPI,
654};
655enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
656int pci_find_capability(struct pci_dev *dev, int cap);
657int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
658int pci_find_ext_capability(struct pci_dev *dev, int cap);
659int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
660int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
661struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
662
663struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
664 struct pci_dev *from);
665struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
666 unsigned int ss_vendor, unsigned int ss_device,
667 struct pci_dev *from);
668struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
669struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
670 unsigned int devfn);
671static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
672 unsigned int devfn)
673{
674 return pci_get_domain_bus_and_slot(0, bus, devfn);
675}
676struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
677int pci_dev_present(const struct pci_device_id *ids);
678
679int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
680 int where, u8 *val);
681int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
682 int where, u16 *val);
683int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
684 int where, u32 *val);
685int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
686 int where, u8 val);
687int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
688 int where, u16 val);
689int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
690 int where, u32 val);
691struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
692
693static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
694{
695 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
696}
697static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
698{
699 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
700}
701static inline int pci_read_config_dword(struct pci_dev *dev, int where,
702 u32 *val)
703{
704 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
705}
706static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
707{
708 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
709}
710static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
711{
712 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
713}
714static inline int pci_write_config_dword(struct pci_dev *dev, int where,
715 u32 val)
716{
717 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
718}
719
720int __must_check pci_enable_device(struct pci_dev *dev);
721int __must_check pci_enable_device_io(struct pci_dev *dev);
722int __must_check pci_enable_device_mem(struct pci_dev *dev);
723int __must_check pci_reenable_device(struct pci_dev *);
724int __must_check pcim_enable_device(struct pci_dev *pdev);
725void pcim_pin_device(struct pci_dev *pdev);
726
727static inline int pci_is_enabled(struct pci_dev *pdev)
728{
729 return (atomic_read(&pdev->enable_cnt) > 0);
730}
731
732static inline int pci_is_managed(struct pci_dev *pdev)
733{
734 return pdev->is_managed;
735}
736
737void pci_disable_device(struct pci_dev *dev);
738void pci_set_master(struct pci_dev *dev);
739void pci_clear_master(struct pci_dev *dev);
740int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
741int pci_set_cacheline_size(struct pci_dev *dev);
742#define HAVE_PCI_SET_MWI
743int __must_check pci_set_mwi(struct pci_dev *dev);
744int pci_try_set_mwi(struct pci_dev *dev);
745void pci_clear_mwi(struct pci_dev *dev);
746void pci_intx(struct pci_dev *dev, int enable);
747void pci_msi_off(struct pci_dev *dev);
748int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
749int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
750int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
751int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
752int pcix_get_max_mmrbc(struct pci_dev *dev);
753int pcix_get_mmrbc(struct pci_dev *dev);
754int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
755int pcie_get_readrq(struct pci_dev *dev);
756int pcie_set_readrq(struct pci_dev *dev, int rq);
757int __pci_reset_function(struct pci_dev *dev);
758int pci_reset_function(struct pci_dev *dev);
759void pci_update_resource(struct pci_dev *dev, int resno);
760int __must_check pci_assign_resource(struct pci_dev *dev, int i);
761int pci_select_bars(struct pci_dev *dev, unsigned long flags);
762
763/* ROM control related routines */
764int pci_enable_rom(struct pci_dev *pdev);
765void pci_disable_rom(struct pci_dev *pdev);
766void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
767void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
768size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
769
770/* Power management related routines */
771int pci_save_state(struct pci_dev *dev);
772int pci_restore_state(struct pci_dev *dev);
773int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
774int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
775pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
776bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
777void pci_pme_active(struct pci_dev *dev, bool enable);
778int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
779int pci_wake_from_d3(struct pci_dev *dev, bool enable);
780pci_power_t pci_target_state(struct pci_dev *dev);
781int pci_prepare_to_sleep(struct pci_dev *dev);
782int pci_back_from_sleep(struct pci_dev *dev);
783
784/* For use by arch with custom probe code */
785void set_pcie_port_type(struct pci_dev *pdev);
786void set_pcie_hotplug_bridge(struct pci_dev *pdev);
787
788/* Functions for PCI Hotplug drivers to use */
789int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
790#ifdef CONFIG_HOTPLUG
791unsigned int pci_rescan_bus(struct pci_bus *bus);
792#endif
793
794/* Vital product data routines */
795ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
796ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
797int pci_vpd_truncate(struct pci_dev *dev, size_t size);
798
799/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
800void pci_bus_assign_resources(const struct pci_bus *bus);
801void pci_bus_size_bridges(struct pci_bus *bus);
802int pci_claim_resource(struct pci_dev *, int);
803void pci_assign_unassigned_resources(void);
804void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
805void pdev_enable_device(struct pci_dev *);
806void pdev_sort_resources(struct pci_dev *, struct resource_list *);
807int pci_enable_resources(struct pci_dev *, int mask);
808void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
809 int (*)(struct pci_dev *, u8, u8));
810#define HAVE_PCI_REQ_REGIONS 2
811int __must_check pci_request_regions(struct pci_dev *, const char *);
812int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
813void pci_release_regions(struct pci_dev *);
814int __must_check pci_request_region(struct pci_dev *, int, const char *);
815int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
816void pci_release_region(struct pci_dev *, int);
817int pci_request_selected_regions(struct pci_dev *, int, const char *);
818int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
819void pci_release_selected_regions(struct pci_dev *, int);
820
821/* drivers/pci/bus.c */
822int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
823 struct resource *res, resource_size_t size,
824 resource_size_t align, resource_size_t min,
825 unsigned int type_mask,
826 resource_size_t (*alignf)(void *,
827 const struct resource *,
828 resource_size_t,
829 resource_size_t),
830 void *alignf_data);
831void pci_enable_bridges(struct pci_bus *bus);
832
833/* Proper probing supporting hot-pluggable devices */
834int __must_check __pci_register_driver(struct pci_driver *, struct module *,
835 const char *mod_name);
836
837/*
838 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
839 */
840#define pci_register_driver(driver) \
841 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
842
843void pci_unregister_driver(struct pci_driver *dev);
844void pci_remove_behind_bridge(struct pci_dev *dev);
845struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
846int pci_add_dynid(struct pci_driver *drv,
847 unsigned int vendor, unsigned int device,
848 unsigned int subvendor, unsigned int subdevice,
849 unsigned int class, unsigned int class_mask,
850 unsigned long driver_data);
851const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
852 struct pci_dev *dev);
853int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
854 int pass);
855
856void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
857 void *userdata);
858int pci_cfg_space_size_ext(struct pci_dev *dev);
859int pci_cfg_space_size(struct pci_dev *dev);
860unsigned char pci_bus_max_busnr(struct pci_bus *bus);
861
862int pci_set_vga_state(struct pci_dev *pdev, bool decode,
863 unsigned int command_bits, bool change_bridge);
864/* kmem_cache style wrapper around pci_alloc_consistent() */
865
866#include <linux/dmapool.h>
867
868#define pci_pool dma_pool
869#define pci_pool_create(name, pdev, size, align, allocation) \
870 dma_pool_create(name, &pdev->dev, size, align, allocation)
871#define pci_pool_destroy(pool) dma_pool_destroy(pool)
872#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
873#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
874
875enum pci_dma_burst_strategy {
876 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
877 strategy_parameter is N/A */
878 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
879 byte boundaries */
880 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
881 strategy_parameter byte boundaries */
882};
883
884struct msix_entry {
885 u32 vector; /* kernel uses to write allocated vector */
886 u16 entry; /* driver uses to specify entry, OS writes */
887};
888
889
890#ifndef CONFIG_PCI_MSI
891static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
892{
893 return -1;
894}
895
896static inline void pci_msi_shutdown(struct pci_dev *dev)
897{ }
898static inline void pci_disable_msi(struct pci_dev *dev)
899{ }
900
901static inline int pci_msix_table_size(struct pci_dev *dev)
902{
903 return 0;
904}
905static inline int pci_enable_msix(struct pci_dev *dev,
906 struct msix_entry *entries, int nvec)
907{
908 return -1;
909}
910
911static inline void pci_msix_shutdown(struct pci_dev *dev)
912{ }
913static inline void pci_disable_msix(struct pci_dev *dev)
914{ }
915
916static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
917{ }
918
919static inline void pci_restore_msi_state(struct pci_dev *dev)
920{ }
921static inline int pci_msi_enabled(void)
922{
923 return 0;
924}
925#else
926extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
927extern void pci_msi_shutdown(struct pci_dev *dev);
928extern void pci_disable_msi(struct pci_dev *dev);
929extern int pci_msix_table_size(struct pci_dev *dev);
930extern int pci_enable_msix(struct pci_dev *dev,
931 struct msix_entry *entries, int nvec);
932extern void pci_msix_shutdown(struct pci_dev *dev);
933extern void pci_disable_msix(struct pci_dev *dev);
934extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
935extern void pci_restore_msi_state(struct pci_dev *dev);
936extern int pci_msi_enabled(void);
937#endif
938
939#ifndef CONFIG_PCIEASPM
940static inline int pcie_aspm_enabled(void)
941{
942 return 0;
943}
944#else
945extern int pcie_aspm_enabled(void);
946#endif
947
948#ifndef CONFIG_PCIE_ECRC
949static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
950{
951 return;
952}
953static inline void pcie_ecrc_get_policy(char *str) {};
954#else
955extern void pcie_set_ecrc_checking(struct pci_dev *dev);
956extern void pcie_ecrc_get_policy(char *str);
957#endif
958
959#define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
960
961#ifdef CONFIG_HT_IRQ
962/* The functions a driver should call */
963int ht_create_irq(struct pci_dev *dev, int idx);
964void ht_destroy_irq(unsigned int irq);
965#endif /* CONFIG_HT_IRQ */
966
967extern void pci_block_user_cfg_access(struct pci_dev *dev);
968extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
969
970/*
971 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
972 * a PCI domain is defined to be a set of PCI busses which share
973 * configuration space.
974 */
975#ifdef CONFIG_PCI_DOMAINS
976extern int pci_domains_supported;
977#else
978enum { pci_domains_supported = 0 };
979static inline int pci_domain_nr(struct pci_bus *bus)
980{
981 return 0;
982}
983
984static inline int pci_proc_domain(struct pci_bus *bus)
985{
986 return 0;
987}
988#endif /* CONFIG_PCI_DOMAINS */
989
990#else /* CONFIG_PCI is not enabled */
991
992/*
993 * If the system does not have PCI, clearly these return errors. Define
994 * these as simple inline functions to avoid hair in drivers.
995 */
996
997#define _PCI_NOP(o, s, t) \
998 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
999 int where, t val) \
1000 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1001
1002#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1003 _PCI_NOP(o, word, u16 x) \
1004 _PCI_NOP(o, dword, u32 x)
1005_PCI_NOP_ALL(read, *)
1006_PCI_NOP_ALL(write,)
1007
1008static inline struct pci_dev *pci_get_device(unsigned int vendor,
1009 unsigned int device,
1010 struct pci_dev *from)
1011{
1012 return NULL;
1013}
1014
1015static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1016 unsigned int device,
1017 unsigned int ss_vendor,
1018 unsigned int ss_device,
1019 struct pci_dev *from)
1020{
1021 return NULL;
1022}
1023
1024static inline struct pci_dev *pci_get_class(unsigned int class,
1025 struct pci_dev *from)
1026{
1027 return NULL;
1028}
1029
1030#define pci_dev_present(ids) (0)
1031#define no_pci_devices() (1)
1032#define pci_dev_put(dev) do { } while (0)
1033
1034static inline void pci_set_master(struct pci_dev *dev)
1035{ }
1036
1037static inline int pci_enable_device(struct pci_dev *dev)
1038{
1039 return -EIO;
1040}
1041
1042static inline void pci_disable_device(struct pci_dev *dev)
1043{ }
1044
1045static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1046{
1047 return -EIO;
1048}
1049
1050static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1051{
1052 return -EIO;
1053}
1054
1055static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1056 unsigned int size)
1057{
1058 return -EIO;
1059}
1060
1061static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1062 unsigned long mask)
1063{
1064 return -EIO;
1065}
1066
1067static inline int pci_assign_resource(struct pci_dev *dev, int i)
1068{
1069 return -EBUSY;
1070}
1071
1072static inline int __pci_register_driver(struct pci_driver *drv,
1073 struct module *owner)
1074{
1075 return 0;
1076}
1077
1078static inline int pci_register_driver(struct pci_driver *drv)
1079{
1080 return 0;
1081}
1082
1083static inline void pci_unregister_driver(struct pci_driver *drv)
1084{ }
1085
1086static inline int pci_find_capability(struct pci_dev *dev, int cap)
1087{
1088 return 0;
1089}
1090
1091static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1092 int cap)
1093{
1094 return 0;
1095}
1096
1097static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1098{
1099 return 0;
1100}
1101
1102/* Power management related routines */
1103static inline int pci_save_state(struct pci_dev *dev)
1104{
1105 return 0;
1106}
1107
1108static inline int pci_restore_state(struct pci_dev *dev)
1109{
1110 return 0;
1111}
1112
1113static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1114{
1115 return 0;
1116}
1117
1118static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1119 pm_message_t state)
1120{
1121 return PCI_D0;
1122}
1123
1124static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1125 int enable)
1126{
1127 return 0;
1128}
1129
1130static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1131{
1132 return -EIO;
1133}
1134
1135static inline void pci_release_regions(struct pci_dev *dev)
1136{ }
1137
1138#define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1139
1140static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1141{ }
1142
1143static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1144{ }
1145
1146static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1147{ return NULL; }
1148
1149static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1150 unsigned int devfn)
1151{ return NULL; }
1152
1153static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1154 unsigned int devfn)
1155{ return NULL; }
1156
1157#endif /* CONFIG_PCI */
1158
1159/* Include architecture-dependent settings and functions */
1160
1161#include <asm/pci.h>
1162
1163#ifndef PCIBIOS_MAX_MEM_32
1164#define PCIBIOS_MAX_MEM_32 (-1)
1165#endif
1166
1167/* these helpers provide future and backwards compatibility
1168 * for accessing popular PCI BAR info */
1169#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1170#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1171#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1172#define pci_resource_len(dev,bar) \
1173 ((pci_resource_start((dev), (bar)) == 0 && \
1174 pci_resource_end((dev), (bar)) == \
1175 pci_resource_start((dev), (bar))) ? 0 : \
1176 \
1177 (pci_resource_end((dev), (bar)) - \
1178 pci_resource_start((dev), (bar)) + 1))
1179
1180/* Similar to the helpers above, these manipulate per-pci_dev
1181 * driver-specific data. They are really just a wrapper around
1182 * the generic device structure functions of these calls.
1183 */
1184static inline void *pci_get_drvdata(struct pci_dev *pdev)
1185{
1186 return dev_get_drvdata(&pdev->dev);
1187}
1188
1189static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1190{
1191 dev_set_drvdata(&pdev->dev, data);
1192}
1193
1194/* If you want to know what to call your pci_dev, ask this function.
1195 * Again, it's a wrapper around the generic device.
1196 */
1197static inline const char *pci_name(const struct pci_dev *pdev)
1198{
1199 return dev_name(&pdev->dev);
1200}
1201
1202
1203/* Some archs don't want to expose struct resource to userland as-is
1204 * in sysfs and /proc
1205 */
1206#ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1207static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1208 const struct resource *rsrc, resource_size_t *start,
1209 resource_size_t *end)
1210{
1211 *start = rsrc->start;
1212 *end = rsrc->end;
1213}
1214#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1215
1216
1217/*
1218 * The world is not perfect and supplies us with broken PCI devices.
1219 * For at least a part of these bugs we need a work-around, so both
1220 * generic (drivers/pci/quirks.c) and per-architecture code can define
1221 * fixup hooks to be called for particular buggy devices.
1222 */
1223
1224struct pci_fixup {
1225 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1226 void (*hook)(struct pci_dev *dev);
1227};
1228
1229enum pci_fixup_pass {
1230 pci_fixup_early, /* Before probing BARs */
1231 pci_fixup_header, /* After reading configuration header */
1232 pci_fixup_final, /* Final phase of device fixups */
1233 pci_fixup_enable, /* pci_enable_device() time */
1234 pci_fixup_resume, /* pci_device_resume() */
1235 pci_fixup_suspend, /* pci_device_suspend */
1236 pci_fixup_resume_early, /* pci_device_resume_early() */
1237};
1238
1239/* Anonymous variables would be nice... */
1240#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1241 static const struct pci_fixup __pci_fixup_##name __used \
1242 __attribute__((__section__(#section))) = { vendor, device, hook };
1243#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1244 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1245 vendor##device##hook, vendor, device, hook)
1246#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1247 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1248 vendor##device##hook, vendor, device, hook)
1249#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1250 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1251 vendor##device##hook, vendor, device, hook)
1252#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1253 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1254 vendor##device##hook, vendor, device, hook)
1255#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1256 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1257 resume##vendor##device##hook, vendor, device, hook)
1258#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1259 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1260 resume_early##vendor##device##hook, vendor, device, hook)
1261#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1262 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1263 suspend##vendor##device##hook, vendor, device, hook)
1264
1265#ifdef CONFIG_PCI_QUIRKS
1266void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1267#else
1268static inline void pci_fixup_device(enum pci_fixup_pass pass,
1269 struct pci_dev *dev) {}
1270#endif
1271
1272void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1273void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1274void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1275int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1276int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1277 const char *name);
1278void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1279
1280extern int pci_pci_problems;
1281#define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1282#define PCIPCI_TRITON 2
1283#define PCIPCI_NATOMA 4
1284#define PCIPCI_VIAETBF 8
1285#define PCIPCI_VSFX 16
1286#define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1287#define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1288
1289extern unsigned long pci_cardbus_io_size;
1290extern unsigned long pci_cardbus_mem_size;
1291extern u8 __devinitdata pci_dfl_cache_line_size;
1292extern u8 pci_cache_line_size;
1293
1294extern unsigned long pci_hotplug_io_size;
1295extern unsigned long pci_hotplug_mem_size;
1296
1297int pcibios_add_platform_entries(struct pci_dev *dev);
1298void pcibios_disable_device(struct pci_dev *dev);
1299int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1300 enum pcie_reset_state state);
1301
1302#ifdef CONFIG_PCI_MMCONFIG
1303extern void __init pci_mmcfg_early_init(void);
1304extern void __init pci_mmcfg_late_init(void);
1305#else
1306static inline void pci_mmcfg_early_init(void) { }
1307static inline void pci_mmcfg_late_init(void) { }
1308#endif
1309
1310int pci_ext_cfg_avail(struct pci_dev *dev);
1311
1312void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1313
1314#ifdef CONFIG_PCI_IOV
1315extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1316extern void pci_disable_sriov(struct pci_dev *dev);
1317extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1318#else
1319static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1320{
1321 return -ENODEV;
1322}
1323static inline void pci_disable_sriov(struct pci_dev *dev)
1324{
1325}
1326static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1327{
1328 return IRQ_NONE;
1329}
1330#endif
1331
1332#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1333extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1334extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1335#endif
1336
1337/**
1338 * pci_pcie_cap - get the saved PCIe capability offset
1339 * @dev: PCI device
1340 *
1341 * PCIe capability offset is calculated at PCI device initialization
1342 * time and saved in the data structure. This function returns saved
1343 * PCIe capability offset. Using this instead of pci_find_capability()
1344 * reduces unnecessary search in the PCI configuration space. If you
1345 * need to calculate PCIe capability offset from raw device for some
1346 * reasons, please use pci_find_capability() instead.
1347 */
1348static inline int pci_pcie_cap(struct pci_dev *dev)
1349{
1350 return dev->pcie_cap;
1351}
1352
1353/**
1354 * pci_is_pcie - check if the PCI device is PCI Express capable
1355 * @dev: PCI device
1356 *
1357 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1358 */
1359static inline bool pci_is_pcie(struct pci_dev *dev)
1360{
1361 return !!pci_pcie_cap(dev);
1362}
1363
1364void pci_request_acs(void);
1365
1366#endif /* __KERNEL__ */
1367#endif /* LINUX_PCI_H */
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