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1 | #ifndef __SH_CLOCK_H | |
2 | #define __SH_CLOCK_H | |
3 | ||
4 | #include <linux/list.h> | |
5 | #include <linux/seq_file.h> | |
6 | #include <linux/cpufreq.h> | |
7 | #include <linux/types.h> | |
8 | #include <linux/kref.h> | |
9 | #include <linux/clk.h> | |
10 | #include <linux/err.h> | |
11 | ||
12 | struct clk; | |
13 | ||
14 | struct clk_mapping { | |
15 | phys_addr_t phys; | |
16 | void __iomem *base; | |
17 | unsigned long len; | |
18 | struct kref ref; | |
19 | }; | |
20 | ||
21 | struct clk_ops { | |
22 | #ifdef CONFIG_SH_CLK_CPG_LEGACY | |
23 | void (*init)(struct clk *clk); | |
24 | #endif | |
25 | int (*enable)(struct clk *clk); | |
26 | void (*disable)(struct clk *clk); | |
27 | unsigned long (*recalc)(struct clk *clk); | |
28 | int (*set_rate)(struct clk *clk, unsigned long rate); | |
29 | int (*set_parent)(struct clk *clk, struct clk *parent); | |
30 | long (*round_rate)(struct clk *clk, unsigned long rate); | |
31 | }; | |
32 | ||
33 | struct clk { | |
34 | struct list_head node; | |
35 | struct clk *parent; | |
36 | struct clk **parent_table; /* list of parents to */ | |
37 | unsigned short parent_num; /* choose between */ | |
38 | unsigned char src_shift; /* source clock field in the */ | |
39 | unsigned char src_width; /* configuration register */ | |
40 | struct clk_ops *ops; | |
41 | ||
42 | struct list_head children; | |
43 | struct list_head sibling; /* node for children */ | |
44 | ||
45 | int usecount; | |
46 | ||
47 | unsigned long rate; | |
48 | unsigned long flags; | |
49 | ||
50 | void __iomem *enable_reg; | |
51 | unsigned int enable_bit; | |
52 | ||
53 | unsigned long arch_flags; | |
54 | void *priv; | |
55 | struct dentry *dentry; | |
56 | struct clk_mapping *mapping; | |
57 | struct cpufreq_frequency_table *freq_table; | |
58 | unsigned int nr_freqs; | |
59 | }; | |
60 | ||
61 | #define CLK_ENABLE_ON_INIT (1 << 0) | |
62 | ||
63 | /* drivers/sh/clk.c */ | |
64 | unsigned long followparent_recalc(struct clk *); | |
65 | void recalculate_root_clocks(void); | |
66 | void propagate_rate(struct clk *); | |
67 | int clk_reparent(struct clk *child, struct clk *parent); | |
68 | int clk_register(struct clk *); | |
69 | void clk_unregister(struct clk *); | |
70 | void clk_enable_init_clocks(void); | |
71 | ||
72 | struct clk_div_mult_table { | |
73 | unsigned int *divisors; | |
74 | unsigned int nr_divisors; | |
75 | unsigned int *multipliers; | |
76 | unsigned int nr_multipliers; | |
77 | }; | |
78 | ||
79 | struct cpufreq_frequency_table; | |
80 | void clk_rate_table_build(struct clk *clk, | |
81 | struct cpufreq_frequency_table *freq_table, | |
82 | int nr_freqs, | |
83 | struct clk_div_mult_table *src_table, | |
84 | unsigned long *bitmap); | |
85 | ||
86 | long clk_rate_table_round(struct clk *clk, | |
87 | struct cpufreq_frequency_table *freq_table, | |
88 | unsigned long rate); | |
89 | ||
90 | int clk_rate_table_find(struct clk *clk, | |
91 | struct cpufreq_frequency_table *freq_table, | |
92 | unsigned long rate); | |
93 | ||
94 | long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, | |
95 | unsigned int div_max, unsigned long rate); | |
96 | ||
97 | long clk_round_parent(struct clk *clk, unsigned long target, | |
98 | unsigned long *best_freq, unsigned long *parent_freq, | |
99 | unsigned int div_min, unsigned int div_max); | |
100 | ||
101 | #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \ | |
102 | { \ | |
103 | .parent = _parent, \ | |
104 | .enable_reg = (void __iomem *)_enable_reg, \ | |
105 | .enable_bit = _enable_bit, \ | |
106 | .flags = _flags, \ | |
107 | } | |
108 | ||
109 | int sh_clk_mstp32_register(struct clk *clks, int nr); | |
110 | ||
111 | #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ | |
112 | { \ | |
113 | .parent = _parent, \ | |
114 | .enable_reg = (void __iomem *)_reg, \ | |
115 | .enable_bit = _shift, \ | |
116 | .arch_flags = _div_bitmap, \ | |
117 | .flags = _flags, \ | |
118 | } | |
119 | ||
120 | struct clk_div4_table { | |
121 | struct clk_div_mult_table *div_mult_table; | |
122 | void (*kick)(struct clk *clk); | |
123 | }; | |
124 | ||
125 | int sh_clk_div4_register(struct clk *clks, int nr, | |
126 | struct clk_div4_table *table); | |
127 | int sh_clk_div4_enable_register(struct clk *clks, int nr, | |
128 | struct clk_div4_table *table); | |
129 | int sh_clk_div4_reparent_register(struct clk *clks, int nr, | |
130 | struct clk_div4_table *table); | |
131 | ||
132 | #define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \ | |
133 | _num_parents, _src_shift, _src_width) \ | |
134 | { \ | |
135 | .parent = _parent, \ | |
136 | .enable_reg = (void __iomem *)_reg, \ | |
137 | .flags = _flags, \ | |
138 | .parent_table = _parents, \ | |
139 | .parent_num = _num_parents, \ | |
140 | .src_shift = _src_shift, \ | |
141 | .src_width = _src_width, \ | |
142 | } | |
143 | ||
144 | #define SH_CLK_DIV6(_parent, _reg, _flags) \ | |
145 | SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0) | |
146 | ||
147 | int sh_clk_div6_register(struct clk *clks, int nr); | |
148 | int sh_clk_div6_reparent_register(struct clk *clks, int nr); | |
149 | ||
150 | #endif /* __SH_CLOCK_H */ |