]> git.proxmox.com Git - mirror_qemu.git/blame_incremental - memory.c
projects / mirror_qemu.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
iommu: Add IOMMU index concept to IOMMU API
[mirror_qemu.git] / memory.c
... / ...
CommitLineData
1/*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16#include "qemu/osdep.h"
17#include "qapi/error.h"
18#include "qemu-common.h"
19#include "cpu.h"
20#include "exec/memory.h"
21#include "exec/address-spaces.h"
22#include "qapi/visitor.h"
23#include "qemu/bitops.h"
24#include "qemu/error-report.h"
25#include "qom/object.h"
26#include "trace-root.h"
27
28#include "exec/memory-internal.h"
29#include "exec/ram_addr.h"
30#include "sysemu/kvm.h"
31#include "sysemu/sysemu.h"
32#include "hw/misc/mmio_interface.h"
33#include "hw/qdev-properties.h"
34#include "migration/vmstate.h"
35
36//#define DEBUG_UNASSIGNED
37
38static unsigned memory_region_transaction_depth;
39static bool memory_region_update_pending;
40static bool ioeventfd_update_pending;
41static bool global_dirty_log = false;
42
43static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
44 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
45
46static QTAILQ_HEAD(, AddressSpace) address_spaces
47 = QTAILQ_HEAD_INITIALIZER(address_spaces);
48
49static GHashTable *flat_views;
50
51typedef struct AddrRange AddrRange;
52
53/*
54 * Note that signed integers are needed for negative offsetting in aliases
55 * (large MemoryRegion::alias_offset).
56 */
57struct AddrRange {
58 Int128 start;
59 Int128 size;
60};
61
62static AddrRange addrrange_make(Int128 start, Int128 size)
63{
64 return (AddrRange) { start, size };
65}
66
67static bool addrrange_equal(AddrRange r1, AddrRange r2)
68{
69 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
70}
71
72static Int128 addrrange_end(AddrRange r)
73{
74 return int128_add(r.start, r.size);
75}
76
77static AddrRange addrrange_shift(AddrRange range, Int128 delta)
78{
79 int128_addto(&range.start, delta);
80 return range;
81}
82
83static bool addrrange_contains(AddrRange range, Int128 addr)
84{
85 return int128_ge(addr, range.start)
86 && int128_lt(addr, addrrange_end(range));
87}
88
89static bool addrrange_intersects(AddrRange r1, AddrRange r2)
90{
91 return addrrange_contains(r1, r2.start)
92 || addrrange_contains(r2, r1.start);
93}
94
95static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
96{
97 Int128 start = int128_max(r1.start, r2.start);
98 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
99 return addrrange_make(start, int128_sub(end, start));
100}
101
102enum ListenerDirection { Forward, Reverse };
103
104#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
105 do { \
106 MemoryListener *_listener; \
107 \
108 switch (_direction) { \
109 case Forward: \
110 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
111 if (_listener->_callback) { \
112 _listener->_callback(_listener, ##_args); \
113 } \
114 } \
115 break; \
116 case Reverse: \
117 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
118 memory_listeners, link) { \
119 if (_listener->_callback) { \
120 _listener->_callback(_listener, ##_args); \
121 } \
122 } \
123 break; \
124 default: \
125 abort(); \
126 } \
127 } while (0)
128
129#define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
130 do { \
131 MemoryListener *_listener; \
132 struct memory_listeners_as *list = &(_as)->listeners; \
133 \
134 switch (_direction) { \
135 case Forward: \
136 QTAILQ_FOREACH(_listener, list, link_as) { \
137 if (_listener->_callback) { \
138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
143 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
144 link_as) { \
145 if (_listener->_callback) { \
146 _listener->_callback(_listener, _section, ##_args); \
147 } \
148 } \
149 break; \
150 default: \
151 abort(); \
152 } \
153 } while (0)
154
155/* No need to ref/unref .mr, the FlatRange keeps it alive. */
156#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
157 do { \
158 MemoryRegionSection mrs = section_from_flat_range(fr, \
159 address_space_to_flatview(as)); \
160 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
161 } while(0)
162
163struct CoalescedMemoryRange {
164 AddrRange addr;
165 QTAILQ_ENTRY(CoalescedMemoryRange) link;
166};
167
168struct MemoryRegionIoeventfd {
169 AddrRange addr;
170 bool match_data;
171 uint64_t data;
172 EventNotifier *e;
173};
174
175static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
176 MemoryRegionIoeventfd *b)
177{
178 if (int128_lt(a->addr.start, b->addr.start)) {
179 return true;
180 } else if (int128_gt(a->addr.start, b->addr.start)) {
181 return false;
182 } else if (int128_lt(a->addr.size, b->addr.size)) {
183 return true;
184 } else if (int128_gt(a->addr.size, b->addr.size)) {
185 return false;
186 } else if (a->match_data < b->match_data) {
187 return true;
188 } else if (a->match_data > b->match_data) {
189 return false;
190 } else if (a->match_data) {
191 if (a->data < b->data) {
192 return true;
193 } else if (a->data > b->data) {
194 return false;
195 }
196 }
197 if (a->e < b->e) {
198 return true;
199 } else if (a->e > b->e) {
200 return false;
201 }
202 return false;
203}
204
205static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
206 MemoryRegionIoeventfd *b)
207{
208 return !memory_region_ioeventfd_before(a, b)
209 && !memory_region_ioeventfd_before(b, a);
210}
211
212/* Range of memory in the global map. Addresses are absolute. */
213struct FlatRange {
214 MemoryRegion *mr;
215 hwaddr offset_in_region;
216 AddrRange addr;
217 uint8_t dirty_log_mask;
218 bool romd_mode;
219 bool readonly;
220};
221
222#define FOR_EACH_FLAT_RANGE(var, view) \
223 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
224
225static inline MemoryRegionSection
226section_from_flat_range(FlatRange *fr, FlatView *fv)
227{
228 return (MemoryRegionSection) {
229 .mr = fr->mr,
230 .fv = fv,
231 .offset_within_region = fr->offset_in_region,
232 .size = fr->addr.size,
233 .offset_within_address_space = int128_get64(fr->addr.start),
234 .readonly = fr->readonly,
235 };
236}
237
238static bool flatrange_equal(FlatRange *a, FlatRange *b)
239{
240 return a->mr == b->mr
241 && addrrange_equal(a->addr, b->addr)
242 && a->offset_in_region == b->offset_in_region
243 && a->romd_mode == b->romd_mode
244 && a->readonly == b->readonly;
245}
246
247static FlatView *flatview_new(MemoryRegion *mr_root)
248{
249 FlatView *view;
250
251 view = g_new0(FlatView, 1);
252 view->ref = 1;
253 view->root = mr_root;
254 memory_region_ref(mr_root);
255 trace_flatview_new(view, mr_root);
256
257 return view;
258}
259
260/* Insert a range into a given position. Caller is responsible for maintaining
261 * sorting order.
262 */
263static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
264{
265 if (view->nr == view->nr_allocated) {
266 view->nr_allocated = MAX(2 * view->nr, 10);
267 view->ranges = g_realloc(view->ranges,
268 view->nr_allocated * sizeof(*view->ranges));
269 }
270 memmove(view->ranges + pos + 1, view->ranges + pos,
271 (view->nr - pos) * sizeof(FlatRange));
272 view->ranges[pos] = *range;
273 memory_region_ref(range->mr);
274 ++view->nr;
275}
276
277static void flatview_destroy(FlatView *view)
278{
279 int i;
280
281 trace_flatview_destroy(view, view->root);
282 if (view->dispatch) {
283 address_space_dispatch_free(view->dispatch);
284 }
285 for (i = 0; i < view->nr; i++) {
286 memory_region_unref(view->ranges[i].mr);
287 }
288 g_free(view->ranges);
289 memory_region_unref(view->root);
290 g_free(view);
291}
292
293static bool flatview_ref(FlatView *view)
294{
295 return atomic_fetch_inc_nonzero(&view->ref) > 0;
296}
297
298void flatview_unref(FlatView *view)
299{
300 if (atomic_fetch_dec(&view->ref) == 1) {
301 trace_flatview_destroy_rcu(view, view->root);
302 assert(view->root);
303 call_rcu(view, flatview_destroy, rcu);
304 }
305}
306
307static bool can_merge(FlatRange *r1, FlatRange *r2)
308{
309 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
310 && r1->mr == r2->mr
311 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
312 r1->addr.size),
313 int128_make64(r2->offset_in_region))
314 && r1->dirty_log_mask == r2->dirty_log_mask
315 && r1->romd_mode == r2->romd_mode
316 && r1->readonly == r2->readonly;
317}
318
319/* Attempt to simplify a view by merging adjacent ranges */
320static void flatview_simplify(FlatView *view)
321{
322 unsigned i, j;
323
324 i = 0;
325 while (i < view->nr) {
326 j = i + 1;
327 while (j < view->nr
328 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
329 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
330 ++j;
331 }
332 ++i;
333 memmove(&view->ranges[i], &view->ranges[j],
334 (view->nr - j) * sizeof(view->ranges[j]));
335 view->nr -= j - i;
336 }
337}
338
339static bool memory_region_big_endian(MemoryRegion *mr)
340{
341#ifdef TARGET_WORDS_BIGENDIAN
342 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
343#else
344 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
345#endif
346}
347
348static bool memory_region_wrong_endianness(MemoryRegion *mr)
349{
350#ifdef TARGET_WORDS_BIGENDIAN
351 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
352#else
353 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
354#endif
355}
356
357static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
358{
359 if (memory_region_wrong_endianness(mr)) {
360 switch (size) {
361 case 1:
362 break;
363 case 2:
364 *data = bswap16(*data);
365 break;
366 case 4:
367 *data = bswap32(*data);
368 break;
369 case 8:
370 *data = bswap64(*data);
371 break;
372 default:
373 abort();
374 }
375 }
376}
377
378static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
379{
380 MemoryRegion *root;
381 hwaddr abs_addr = offset;
382
383 abs_addr += mr->addr;
384 for (root = mr; root->container; ) {
385 root = root->container;
386 abs_addr += root->addr;
387 }
388
389 return abs_addr;
390}
391
392static int get_cpu_index(void)
393{
394 if (current_cpu) {
395 return current_cpu->cpu_index;
396 }
397 return -1;
398}
399
400static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
401 hwaddr addr,
402 uint64_t *value,
403 unsigned size,
404 unsigned shift,
405 uint64_t mask,
406 MemTxAttrs attrs)
407{
408 uint64_t tmp;
409
410 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
411 if (mr->subpage) {
412 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
413 } else if (mr == &io_mem_notdirty) {
414 /* Accesses to code which has previously been translated into a TB show
415 * up in the MMIO path, as accesses to the io_mem_notdirty
416 * MemoryRegion. */
417 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
418 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
419 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
420 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
421 }
422 *value |= (tmp & mask) << shift;
423 return MEMTX_OK;
424}
425
426static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
427 hwaddr addr,
428 uint64_t *value,
429 unsigned size,
430 unsigned shift,
431 uint64_t mask,
432 MemTxAttrs attrs)
433{
434 uint64_t tmp;
435
436 tmp = mr->ops->read(mr->opaque, addr, size);
437 if (mr->subpage) {
438 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
439 } else if (mr == &io_mem_notdirty) {
440 /* Accesses to code which has previously been translated into a TB show
441 * up in the MMIO path, as accesses to the io_mem_notdirty
442 * MemoryRegion. */
443 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
444 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
445 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
446 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
447 }
448 *value |= (tmp & mask) << shift;
449 return MEMTX_OK;
450}
451
452static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
453 hwaddr addr,
454 uint64_t *value,
455 unsigned size,
456 unsigned shift,
457 uint64_t mask,
458 MemTxAttrs attrs)
459{
460 uint64_t tmp = 0;
461 MemTxResult r;
462
463 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
464 if (mr->subpage) {
465 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
466 } else if (mr == &io_mem_notdirty) {
467 /* Accesses to code which has previously been translated into a TB show
468 * up in the MMIO path, as accesses to the io_mem_notdirty
469 * MemoryRegion. */
470 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
471 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
472 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
473 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
474 }
475 *value |= (tmp & mask) << shift;
476 return r;
477}
478
479static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
480 hwaddr addr,
481 uint64_t *value,
482 unsigned size,
483 unsigned shift,
484 uint64_t mask,
485 MemTxAttrs attrs)
486{
487 uint64_t tmp;
488
489 tmp = (*value >> shift) & mask;
490 if (mr->subpage) {
491 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
492 } else if (mr == &io_mem_notdirty) {
493 /* Accesses to code which has previously been translated into a TB show
494 * up in the MMIO path, as accesses to the io_mem_notdirty
495 * MemoryRegion. */
496 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
497 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
498 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
499 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
500 }
501 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
502 return MEMTX_OK;
503}
504
505static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
506 hwaddr addr,
507 uint64_t *value,
508 unsigned size,
509 unsigned shift,
510 uint64_t mask,
511 MemTxAttrs attrs)
512{
513 uint64_t tmp;
514
515 tmp = (*value >> shift) & mask;
516 if (mr->subpage) {
517 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
518 } else if (mr == &io_mem_notdirty) {
519 /* Accesses to code which has previously been translated into a TB show
520 * up in the MMIO path, as accesses to the io_mem_notdirty
521 * MemoryRegion. */
522 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
523 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
524 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
525 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
526 }
527 mr->ops->write(mr->opaque, addr, tmp, size);
528 return MEMTX_OK;
529}
530
531static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
532 hwaddr addr,
533 uint64_t *value,
534 unsigned size,
535 unsigned shift,
536 uint64_t mask,
537 MemTxAttrs attrs)
538{
539 uint64_t tmp;
540
541 tmp = (*value >> shift) & mask;
542 if (mr->subpage) {
543 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
544 } else if (mr == &io_mem_notdirty) {
545 /* Accesses to code which has previously been translated into a TB show
546 * up in the MMIO path, as accesses to the io_mem_notdirty
547 * MemoryRegion. */
548 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
549 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
550 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
551 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
552 }
553 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
554}
555
556static MemTxResult access_with_adjusted_size(hwaddr addr,
557 uint64_t *value,
558 unsigned size,
559 unsigned access_size_min,
560 unsigned access_size_max,
561 MemTxResult (*access_fn)
562 (MemoryRegion *mr,
563 hwaddr addr,
564 uint64_t *value,
565 unsigned size,
566 unsigned shift,
567 uint64_t mask,
568 MemTxAttrs attrs),
569 MemoryRegion *mr,
570 MemTxAttrs attrs)
571{
572 uint64_t access_mask;
573 unsigned access_size;
574 unsigned i;
575 MemTxResult r = MEMTX_OK;
576
577 if (!access_size_min) {
578 access_size_min = 1;
579 }
580 if (!access_size_max) {
581 access_size_max = 4;
582 }
583
584 /* FIXME: support unaligned access? */
585 access_size = MAX(MIN(size, access_size_max), access_size_min);
586 access_mask = -1ULL >> (64 - access_size * 8);
587 if (memory_region_big_endian(mr)) {
588 for (i = 0; i < size; i += access_size) {
589 r |= access_fn(mr, addr + i, value, access_size,
590 (size - access_size - i) * 8, access_mask, attrs);
591 }
592 } else {
593 for (i = 0; i < size; i += access_size) {
594 r |= access_fn(mr, addr + i, value, access_size, i * 8,
595 access_mask, attrs);
596 }
597 }
598 return r;
599}
600
601static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
602{
603 AddressSpace *as;
604
605 while (mr->container) {
606 mr = mr->container;
607 }
608 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
609 if (mr == as->root) {
610 return as;
611 }
612 }
613 return NULL;
614}
615
616/* Render a memory region into the global view. Ranges in @view obscure
617 * ranges in @mr.
618 */
619static void render_memory_region(FlatView *view,
620 MemoryRegion *mr,
621 Int128 base,
622 AddrRange clip,
623 bool readonly)
624{
625 MemoryRegion *subregion;
626 unsigned i;
627 hwaddr offset_in_region;
628 Int128 remain;
629 Int128 now;
630 FlatRange fr;
631 AddrRange tmp;
632
633 if (!mr->enabled) {
634 return;
635 }
636
637 int128_addto(&base, int128_make64(mr->addr));
638 readonly |= mr->readonly;
639
640 tmp = addrrange_make(base, mr->size);
641
642 if (!addrrange_intersects(tmp, clip)) {
643 return;
644 }
645
646 clip = addrrange_intersection(tmp, clip);
647
648 if (mr->alias) {
649 int128_subfrom(&base, int128_make64(mr->alias->addr));
650 int128_subfrom(&base, int128_make64(mr->alias_offset));
651 render_memory_region(view, mr->alias, base, clip, readonly);
652 return;
653 }
654
655 /* Render subregions in priority order. */
656 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
657 render_memory_region(view, subregion, base, clip, readonly);
658 }
659
660 if (!mr->terminates) {
661 return;
662 }
663
664 offset_in_region = int128_get64(int128_sub(clip.start, base));
665 base = clip.start;
666 remain = clip.size;
667
668 fr.mr = mr;
669 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
670 fr.romd_mode = mr->romd_mode;
671 fr.readonly = readonly;
672
673 /* Render the region itself into any gaps left by the current view. */
674 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
675 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
676 continue;
677 }
678 if (int128_lt(base, view->ranges[i].addr.start)) {
679 now = int128_min(remain,
680 int128_sub(view->ranges[i].addr.start, base));
681 fr.offset_in_region = offset_in_region;
682 fr.addr = addrrange_make(base, now);
683 flatview_insert(view, i, &fr);
684 ++i;
685 int128_addto(&base, now);
686 offset_in_region += int128_get64(now);
687 int128_subfrom(&remain, now);
688 }
689 now = int128_sub(int128_min(int128_add(base, remain),
690 addrrange_end(view->ranges[i].addr)),
691 base);
692 int128_addto(&base, now);
693 offset_in_region += int128_get64(now);
694 int128_subfrom(&remain, now);
695 }
696 if (int128_nz(remain)) {
697 fr.offset_in_region = offset_in_region;
698 fr.addr = addrrange_make(base, remain);
699 flatview_insert(view, i, &fr);
700 }
701}
702
703static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
704{
705 while (mr->enabled) {
706 if (mr->alias) {
707 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
708 /* The alias is included in its entirety. Use it as
709 * the "real" root, so that we can share more FlatViews.
710 */
711 mr = mr->alias;
712 continue;
713 }
714 } else if (!mr->terminates) {
715 unsigned int found = 0;
716 MemoryRegion *child, *next = NULL;
717 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
718 if (child->enabled) {
719 if (++found > 1) {
720 next = NULL;
721 break;
722 }
723 if (!child->addr && int128_ge(mr->size, child->size)) {
724 /* A child is included in its entirety. If it's the only
725 * enabled one, use it in the hope of finding an alias down the
726 * way. This will also let us share FlatViews.
727 */
728 next = child;
729 }
730 }
731 }
732 if (found == 0) {
733 return NULL;
734 }
735 if (next) {
736 mr = next;
737 continue;
738 }
739 }
740
741 return mr;
742 }
743
744 return NULL;
745}
746
747/* Render a memory topology into a list of disjoint absolute ranges. */
748static FlatView *generate_memory_topology(MemoryRegion *mr)
749{
750 int i;
751 FlatView *view;
752
753 view = flatview_new(mr);
754
755 if (mr) {
756 render_memory_region(view, mr, int128_zero(),
757 addrrange_make(int128_zero(), int128_2_64()), false);
758 }
759 flatview_simplify(view);
760
761 view->dispatch = address_space_dispatch_new(view);
762 for (i = 0; i < view->nr; i++) {
763 MemoryRegionSection mrs =
764 section_from_flat_range(&view->ranges[i], view);
765 flatview_add_to_dispatch(view, &mrs);
766 }
767 address_space_dispatch_compact(view->dispatch);
768 g_hash_table_replace(flat_views, mr, view);
769
770 return view;
771}
772
773static void address_space_add_del_ioeventfds(AddressSpace *as,
774 MemoryRegionIoeventfd *fds_new,
775 unsigned fds_new_nb,
776 MemoryRegionIoeventfd *fds_old,
777 unsigned fds_old_nb)
778{
779 unsigned iold, inew;
780 MemoryRegionIoeventfd *fd;
781 MemoryRegionSection section;
782
783 /* Generate a symmetric difference of the old and new fd sets, adding
784 * and deleting as necessary.
785 */
786
787 iold = inew = 0;
788 while (iold < fds_old_nb || inew < fds_new_nb) {
789 if (iold < fds_old_nb
790 && (inew == fds_new_nb
791 || memory_region_ioeventfd_before(&fds_old[iold],
792 &fds_new[inew]))) {
793 fd = &fds_old[iold];
794 section = (MemoryRegionSection) {
795 .fv = address_space_to_flatview(as),
796 .offset_within_address_space = int128_get64(fd->addr.start),
797 .size = fd->addr.size,
798 };
799 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
800 fd->match_data, fd->data, fd->e);
801 ++iold;
802 } else if (inew < fds_new_nb
803 && (iold == fds_old_nb
804 || memory_region_ioeventfd_before(&fds_new[inew],
805 &fds_old[iold]))) {
806 fd = &fds_new[inew];
807 section = (MemoryRegionSection) {
808 .fv = address_space_to_flatview(as),
809 .offset_within_address_space = int128_get64(fd->addr.start),
810 .size = fd->addr.size,
811 };
812 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
813 fd->match_data, fd->data, fd->e);
814 ++inew;
815 } else {
816 ++iold;
817 ++inew;
818 }
819 }
820}
821
822FlatView *address_space_get_flatview(AddressSpace *as)
823{
824 FlatView *view;
825
826 rcu_read_lock();
827 do {
828 view = address_space_to_flatview(as);
829 /* If somebody has replaced as->current_map concurrently,
830 * flatview_ref returns false.
831 */
832 } while (!flatview_ref(view));
833 rcu_read_unlock();
834 return view;
835}
836
837static void address_space_update_ioeventfds(AddressSpace *as)
838{
839 FlatView *view;
840 FlatRange *fr;
841 unsigned ioeventfd_nb = 0;
842 MemoryRegionIoeventfd *ioeventfds = NULL;
843 AddrRange tmp;
844 unsigned i;
845
846 view = address_space_get_flatview(as);
847 FOR_EACH_FLAT_RANGE(fr, view) {
848 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
849 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
850 int128_sub(fr->addr.start,
851 int128_make64(fr->offset_in_region)));
852 if (addrrange_intersects(fr->addr, tmp)) {
853 ++ioeventfd_nb;
854 ioeventfds = g_realloc(ioeventfds,
855 ioeventfd_nb * sizeof(*ioeventfds));
856 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
857 ioeventfds[ioeventfd_nb-1].addr = tmp;
858 }
859 }
860 }
861
862 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
863 as->ioeventfds, as->ioeventfd_nb);
864
865 g_free(as->ioeventfds);
866 as->ioeventfds = ioeventfds;
867 as->ioeventfd_nb = ioeventfd_nb;
868 flatview_unref(view);
869}
870
871static void address_space_update_topology_pass(AddressSpace *as,
872 const FlatView *old_view,
873 const FlatView *new_view,
874 bool adding)
875{
876 unsigned iold, inew;
877 FlatRange *frold, *frnew;
878
879 /* Generate a symmetric difference of the old and new memory maps.
880 * Kill ranges in the old map, and instantiate ranges in the new map.
881 */
882 iold = inew = 0;
883 while (iold < old_view->nr || inew < new_view->nr) {
884 if (iold < old_view->nr) {
885 frold = &old_view->ranges[iold];
886 } else {
887 frold = NULL;
888 }
889 if (inew < new_view->nr) {
890 frnew = &new_view->ranges[inew];
891 } else {
892 frnew = NULL;
893 }
894
895 if (frold
896 && (!frnew
897 || int128_lt(frold->addr.start, frnew->addr.start)
898 || (int128_eq(frold->addr.start, frnew->addr.start)
899 && !flatrange_equal(frold, frnew)))) {
900 /* In old but not in new, or in both but attributes changed. */
901
902 if (!adding) {
903 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
904 }
905
906 ++iold;
907 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
908 /* In both and unchanged (except logging may have changed) */
909
910 if (adding) {
911 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
912 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
913 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
914 frold->dirty_log_mask,
915 frnew->dirty_log_mask);
916 }
917 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
918 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
919 frold->dirty_log_mask,
920 frnew->dirty_log_mask);
921 }
922 }
923
924 ++iold;
925 ++inew;
926 } else {
927 /* In new */
928
929 if (adding) {
930 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
931 }
932
933 ++inew;
934 }
935 }
936}
937
938static void flatviews_init(void)
939{
940 static FlatView *empty_view;
941
942 if (flat_views) {
943 return;
944 }
945
946 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
947 (GDestroyNotify) flatview_unref);
948 if (!empty_view) {
949 empty_view = generate_memory_topology(NULL);
950 /* We keep it alive forever in the global variable. */
951 flatview_ref(empty_view);
952 } else {
953 g_hash_table_replace(flat_views, NULL, empty_view);
954 flatview_ref(empty_view);
955 }
956}
957
958static void flatviews_reset(void)
959{
960 AddressSpace *as;
961
962 if (flat_views) {
963 g_hash_table_unref(flat_views);
964 flat_views = NULL;
965 }
966 flatviews_init();
967
968 /* Render unique FVs */
969 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
970 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
971
972 if (g_hash_table_lookup(flat_views, physmr)) {
973 continue;
974 }
975
976 generate_memory_topology(physmr);
977 }
978}
979
980static void address_space_set_flatview(AddressSpace *as)
981{
982 FlatView *old_view = address_space_to_flatview(as);
983 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
984 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
985
986 assert(new_view);
987
988 if (old_view == new_view) {
989 return;
990 }
991
992 if (old_view) {
993 flatview_ref(old_view);
994 }
995
996 flatview_ref(new_view);
997
998 if (!QTAILQ_EMPTY(&as->listeners)) {
999 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1000
1001 if (!old_view2) {
1002 old_view2 = &tmpview;
1003 }
1004 address_space_update_topology_pass(as, old_view2, new_view, false);
1005 address_space_update_topology_pass(as, old_view2, new_view, true);
1006 }
1007
1008 /* Writes are protected by the BQL. */
1009 atomic_rcu_set(&as->current_map, new_view);
1010 if (old_view) {
1011 flatview_unref(old_view);
1012 }
1013
1014 /* Note that all the old MemoryRegions are still alive up to this
1015 * point. This relieves most MemoryListeners from the need to
1016 * ref/unref the MemoryRegions they get---unless they use them
1017 * outside the iothread mutex, in which case precise reference
1018 * counting is necessary.
1019 */
1020 if (old_view) {
1021 flatview_unref(old_view);
1022 }
1023}
1024
1025static void address_space_update_topology(AddressSpace *as)
1026{
1027 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1028
1029 flatviews_init();
1030 if (!g_hash_table_lookup(flat_views, physmr)) {
1031 generate_memory_topology(physmr);
1032 }
1033 address_space_set_flatview(as);
1034}
1035
1036void memory_region_transaction_begin(void)
1037{
1038 qemu_flush_coalesced_mmio_buffer();
1039 ++memory_region_transaction_depth;
1040}
1041
1042void memory_region_transaction_commit(void)
1043{
1044 AddressSpace *as;
1045
1046 assert(memory_region_transaction_depth);
1047 assert(qemu_mutex_iothread_locked());
1048
1049 --memory_region_transaction_depth;
1050 if (!memory_region_transaction_depth) {
1051 if (memory_region_update_pending) {
1052 flatviews_reset();
1053
1054 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1055
1056 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1057 address_space_set_flatview(as);
1058 address_space_update_ioeventfds(as);
1059 }
1060 memory_region_update_pending = false;
1061 ioeventfd_update_pending = false;
1062 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1063 } else if (ioeventfd_update_pending) {
1064 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1065 address_space_update_ioeventfds(as);
1066 }
1067 ioeventfd_update_pending = false;
1068 }
1069 }
1070}
1071
1072static void memory_region_destructor_none(MemoryRegion *mr)
1073{
1074}
1075
1076static void memory_region_destructor_ram(MemoryRegion *mr)
1077{
1078 qemu_ram_free(mr->ram_block);
1079}
1080
1081static bool memory_region_need_escape(char c)
1082{
1083 return c == '/' || c == '[' || c == '\\' || c == ']';
1084}
1085
1086static char *memory_region_escape_name(const char *name)
1087{
1088 const char *p;
1089 char *escaped, *q;
1090 uint8_t c;
1091 size_t bytes = 0;
1092
1093 for (p = name; *p; p++) {
1094 bytes += memory_region_need_escape(*p) ? 4 : 1;
1095 }
1096 if (bytes == p - name) {
1097 return g_memdup(name, bytes + 1);
1098 }
1099
1100 escaped = g_malloc(bytes + 1);
1101 for (p = name, q = escaped; *p; p++) {
1102 c = *p;
1103 if (unlikely(memory_region_need_escape(c))) {
1104 *q++ = '\\';
1105 *q++ = 'x';
1106 *q++ = "0123456789abcdef"[c >> 4];
1107 c = "0123456789abcdef"[c & 15];
1108 }
1109 *q++ = c;
1110 }
1111 *q = 0;
1112 return escaped;
1113}
1114
1115static void memory_region_do_init(MemoryRegion *mr,
1116 Object *owner,
1117 const char *name,
1118 uint64_t size)
1119{
1120 mr->size = int128_make64(size);
1121 if (size == UINT64_MAX) {
1122 mr->size = int128_2_64();
1123 }
1124 mr->name = g_strdup(name);
1125 mr->owner = owner;
1126 mr->ram_block = NULL;
1127
1128 if (name) {
1129 char *escaped_name = memory_region_escape_name(name);
1130 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1131
1132 if (!owner) {
1133 owner = container_get(qdev_get_machine(), "/unattached");
1134 }
1135
1136 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1137 object_unref(OBJECT(mr));
1138 g_free(name_array);
1139 g_free(escaped_name);
1140 }
1141}
1142
1143void memory_region_init(MemoryRegion *mr,
1144 Object *owner,
1145 const char *name,
1146 uint64_t size)
1147{
1148 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1149 memory_region_do_init(mr, owner, name, size);
1150}
1151
1152static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1153 void *opaque, Error **errp)
1154{
1155 MemoryRegion *mr = MEMORY_REGION(obj);
1156 uint64_t value = mr->addr;
1157
1158 visit_type_uint64(v, name, &value, errp);
1159}
1160
1161static void memory_region_get_container(Object *obj, Visitor *v,
1162 const char *name, void *opaque,
1163 Error **errp)
1164{
1165 MemoryRegion *mr = MEMORY_REGION(obj);
1166 gchar *path = (gchar *)"";
1167
1168 if (mr->container) {
1169 path = object_get_canonical_path(OBJECT(mr->container));
1170 }
1171 visit_type_str(v, name, &path, errp);
1172 if (mr->container) {
1173 g_free(path);
1174 }
1175}
1176
1177static Object *memory_region_resolve_container(Object *obj, void *opaque,
1178 const char *part)
1179{
1180 MemoryRegion *mr = MEMORY_REGION(obj);
1181
1182 return OBJECT(mr->container);
1183}
1184
1185static void memory_region_get_priority(Object *obj, Visitor *v,
1186 const char *name, void *opaque,
1187 Error **errp)
1188{
1189 MemoryRegion *mr = MEMORY_REGION(obj);
1190 int32_t value = mr->priority;
1191
1192 visit_type_int32(v, name, &value, errp);
1193}
1194
1195static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1196 void *opaque, Error **errp)
1197{
1198 MemoryRegion *mr = MEMORY_REGION(obj);
1199 uint64_t value = memory_region_size(mr);
1200
1201 visit_type_uint64(v, name, &value, errp);
1202}
1203
1204static void memory_region_initfn(Object *obj)
1205{
1206 MemoryRegion *mr = MEMORY_REGION(obj);
1207 ObjectProperty *op;
1208
1209 mr->ops = &unassigned_mem_ops;
1210 mr->enabled = true;
1211 mr->romd_mode = true;
1212 mr->global_locking = true;
1213 mr->destructor = memory_region_destructor_none;
1214 QTAILQ_INIT(&mr->subregions);
1215 QTAILQ_INIT(&mr->coalesced);
1216
1217 op = object_property_add(OBJECT(mr), "container",
1218 "link<" TYPE_MEMORY_REGION ">",
1219 memory_region_get_container,
1220 NULL, /* memory_region_set_container */
1221 NULL, NULL, &error_abort);
1222 op->resolve = memory_region_resolve_container;
1223
1224 object_property_add(OBJECT(mr), "addr", "uint64",
1225 memory_region_get_addr,
1226 NULL, /* memory_region_set_addr */
1227 NULL, NULL, &error_abort);
1228 object_property_add(OBJECT(mr), "priority", "uint32",
1229 memory_region_get_priority,
1230 NULL, /* memory_region_set_priority */
1231 NULL, NULL, &error_abort);
1232 object_property_add(OBJECT(mr), "size", "uint64",
1233 memory_region_get_size,
1234 NULL, /* memory_region_set_size, */
1235 NULL, NULL, &error_abort);
1236}
1237
1238static void iommu_memory_region_initfn(Object *obj)
1239{
1240 MemoryRegion *mr = MEMORY_REGION(obj);
1241
1242 mr->is_iommu = true;
1243}
1244
1245static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1246 unsigned size)
1247{
1248#ifdef DEBUG_UNASSIGNED
1249 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1250#endif
1251 if (current_cpu != NULL) {
1252 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
1253 }
1254 return 0;
1255}
1256
1257static void unassigned_mem_write(void *opaque, hwaddr addr,
1258 uint64_t val, unsigned size)
1259{
1260#ifdef DEBUG_UNASSIGNED
1261 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1262#endif
1263 if (current_cpu != NULL) {
1264 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1265 }
1266}
1267
1268static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1269 unsigned size, bool is_write,
1270 MemTxAttrs attrs)
1271{
1272 return false;
1273}
1274
1275const MemoryRegionOps unassigned_mem_ops = {
1276 .valid.accepts = unassigned_mem_accepts,
1277 .endianness = DEVICE_NATIVE_ENDIAN,
1278};
1279
1280static uint64_t memory_region_ram_device_read(void *opaque,
1281 hwaddr addr, unsigned size)
1282{
1283 MemoryRegion *mr = opaque;
1284 uint64_t data = (uint64_t)~0;
1285
1286 switch (size) {
1287 case 1:
1288 data = *(uint8_t *)(mr->ram_block->host + addr);
1289 break;
1290 case 2:
1291 data = *(uint16_t *)(mr->ram_block->host + addr);
1292 break;
1293 case 4:
1294 data = *(uint32_t *)(mr->ram_block->host + addr);
1295 break;
1296 case 8:
1297 data = *(uint64_t *)(mr->ram_block->host + addr);
1298 break;
1299 }
1300
1301 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1302
1303 return data;
1304}
1305
1306static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1307 uint64_t data, unsigned size)
1308{
1309 MemoryRegion *mr = opaque;
1310
1311 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1312
1313 switch (size) {
1314 case 1:
1315 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1316 break;
1317 case 2:
1318 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1319 break;
1320 case 4:
1321 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1322 break;
1323 case 8:
1324 *(uint64_t *)(mr->ram_block->host + addr) = data;
1325 break;
1326 }
1327}
1328
1329static const MemoryRegionOps ram_device_mem_ops = {
1330 .read = memory_region_ram_device_read,
1331 .write = memory_region_ram_device_write,
1332 .endianness = DEVICE_HOST_ENDIAN,
1333 .valid = {
1334 .min_access_size = 1,
1335 .max_access_size = 8,
1336 .unaligned = true,
1337 },
1338 .impl = {
1339 .min_access_size = 1,
1340 .max_access_size = 8,
1341 .unaligned = true,
1342 },
1343};
1344
1345bool memory_region_access_valid(MemoryRegion *mr,
1346 hwaddr addr,
1347 unsigned size,
1348 bool is_write,
1349 MemTxAttrs attrs)
1350{
1351 int access_size_min, access_size_max;
1352 int access_size, i;
1353
1354 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1355 return false;
1356 }
1357
1358 if (!mr->ops->valid.accepts) {
1359 return true;
1360 }
1361
1362 access_size_min = mr->ops->valid.min_access_size;
1363 if (!mr->ops->valid.min_access_size) {
1364 access_size_min = 1;
1365 }
1366
1367 access_size_max = mr->ops->valid.max_access_size;
1368 if (!mr->ops->valid.max_access_size) {
1369 access_size_max = 4;
1370 }
1371
1372 access_size = MAX(MIN(size, access_size_max), access_size_min);
1373 for (i = 0; i < size; i += access_size) {
1374 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1375 is_write, attrs)) {
1376 return false;
1377 }
1378 }
1379
1380 return true;
1381}
1382
1383static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1384 hwaddr addr,
1385 uint64_t *pval,
1386 unsigned size,
1387 MemTxAttrs attrs)
1388{
1389 *pval = 0;
1390
1391 if (mr->ops->read) {
1392 return access_with_adjusted_size(addr, pval, size,
1393 mr->ops->impl.min_access_size,
1394 mr->ops->impl.max_access_size,
1395 memory_region_read_accessor,
1396 mr, attrs);
1397 } else if (mr->ops->read_with_attrs) {
1398 return access_with_adjusted_size(addr, pval, size,
1399 mr->ops->impl.min_access_size,
1400 mr->ops->impl.max_access_size,
1401 memory_region_read_with_attrs_accessor,
1402 mr, attrs);
1403 } else {
1404 return access_with_adjusted_size(addr, pval, size, 1, 4,
1405 memory_region_oldmmio_read_accessor,
1406 mr, attrs);
1407 }
1408}
1409
1410MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1411 hwaddr addr,
1412 uint64_t *pval,
1413 unsigned size,
1414 MemTxAttrs attrs)
1415{
1416 MemTxResult r;
1417
1418 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1419 *pval = unassigned_mem_read(mr, addr, size);
1420 return MEMTX_DECODE_ERROR;
1421 }
1422
1423 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1424 adjust_endianness(mr, pval, size);
1425 return r;
1426}
1427
1428/* Return true if an eventfd was signalled */
1429static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1430 hwaddr addr,
1431 uint64_t data,
1432 unsigned size,
1433 MemTxAttrs attrs)
1434{
1435 MemoryRegionIoeventfd ioeventfd = {
1436 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1437 .data = data,
1438 };
1439 unsigned i;
1440
1441 for (i = 0; i < mr->ioeventfd_nb; i++) {
1442 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1443 ioeventfd.e = mr->ioeventfds[i].e;
1444
1445 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1446 event_notifier_set(ioeventfd.e);
1447 return true;
1448 }
1449 }
1450
1451 return false;
1452}
1453
1454MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1455 hwaddr addr,
1456 uint64_t data,
1457 unsigned size,
1458 MemTxAttrs attrs)
1459{
1460 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1461 unassigned_mem_write(mr, addr, data, size);
1462 return MEMTX_DECODE_ERROR;
1463 }
1464
1465 adjust_endianness(mr, &data, size);
1466
1467 if ((!kvm_eventfds_enabled()) &&
1468 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1469 return MEMTX_OK;
1470 }
1471
1472 if (mr->ops->write) {
1473 return access_with_adjusted_size(addr, &data, size,
1474 mr->ops->impl.min_access_size,
1475 mr->ops->impl.max_access_size,
1476 memory_region_write_accessor, mr,
1477 attrs);
1478 } else if (mr->ops->write_with_attrs) {
1479 return
1480 access_with_adjusted_size(addr, &data, size,
1481 mr->ops->impl.min_access_size,
1482 mr->ops->impl.max_access_size,
1483 memory_region_write_with_attrs_accessor,
1484 mr, attrs);
1485 } else {
1486 return access_with_adjusted_size(addr, &data, size, 1, 4,
1487 memory_region_oldmmio_write_accessor,
1488 mr, attrs);
1489 }
1490}
1491
1492void memory_region_init_io(MemoryRegion *mr,
1493 Object *owner,
1494 const MemoryRegionOps *ops,
1495 void *opaque,
1496 const char *name,
1497 uint64_t size)
1498{
1499 memory_region_init(mr, owner, name, size);
1500 mr->ops = ops ? ops : &unassigned_mem_ops;
1501 mr->opaque = opaque;
1502 mr->terminates = true;
1503}
1504
1505void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1506 Object *owner,
1507 const char *name,
1508 uint64_t size,
1509 Error **errp)
1510{
1511 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1512}
1513
1514void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1515 Object *owner,
1516 const char *name,
1517 uint64_t size,
1518 bool share,
1519 Error **errp)
1520{
1521 memory_region_init(mr, owner, name, size);
1522 mr->ram = true;
1523 mr->terminates = true;
1524 mr->destructor = memory_region_destructor_ram;
1525 mr->ram_block = qemu_ram_alloc(size, share, mr, errp);
1526 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1527}
1528
1529void memory_region_init_resizeable_ram(MemoryRegion *mr,
1530 Object *owner,
1531 const char *name,
1532 uint64_t size,
1533 uint64_t max_size,
1534 void (*resized)(const char*,
1535 uint64_t length,
1536 void *host),
1537 Error **errp)
1538{
1539 memory_region_init(mr, owner, name, size);
1540 mr->ram = true;
1541 mr->terminates = true;
1542 mr->destructor = memory_region_destructor_ram;
1543 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1544 mr, errp);
1545 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1546}
1547
1548#ifdef __linux__
1549void memory_region_init_ram_from_file(MemoryRegion *mr,
1550 struct Object *owner,
1551 const char *name,
1552 uint64_t size,
1553 uint64_t align,
1554 bool share,
1555 const char *path,
1556 Error **errp)
1557{
1558 memory_region_init(mr, owner, name, size);
1559 mr->ram = true;
1560 mr->terminates = true;
1561 mr->destructor = memory_region_destructor_ram;
1562 mr->align = align;
1563 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
1564 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1565}
1566
1567void memory_region_init_ram_from_fd(MemoryRegion *mr,
1568 struct Object *owner,
1569 const char *name,
1570 uint64_t size,
1571 bool share,
1572 int fd,
1573 Error **errp)
1574{
1575 memory_region_init(mr, owner, name, size);
1576 mr->ram = true;
1577 mr->terminates = true;
1578 mr->destructor = memory_region_destructor_ram;
1579 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1580 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1581}
1582#endif
1583
1584void memory_region_init_ram_ptr(MemoryRegion *mr,
1585 Object *owner,
1586 const char *name,
1587 uint64_t size,
1588 void *ptr)
1589{
1590 memory_region_init(mr, owner, name, size);
1591 mr->ram = true;
1592 mr->terminates = true;
1593 mr->destructor = memory_region_destructor_ram;
1594 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1595
1596 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1597 assert(ptr != NULL);
1598 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1599}
1600
1601void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1602 Object *owner,
1603 const char *name,
1604 uint64_t size,
1605 void *ptr)
1606{
1607 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1608 mr->ram_device = true;
1609 mr->ops = &ram_device_mem_ops;
1610 mr->opaque = mr;
1611}
1612
1613void memory_region_init_alias(MemoryRegion *mr,
1614 Object *owner,
1615 const char *name,
1616 MemoryRegion *orig,
1617 hwaddr offset,
1618 uint64_t size)
1619{
1620 memory_region_init(mr, owner, name, size);
1621 mr->alias = orig;
1622 mr->alias_offset = offset;
1623}
1624
1625void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1626 struct Object *owner,
1627 const char *name,
1628 uint64_t size,
1629 Error **errp)
1630{
1631 memory_region_init(mr, owner, name, size);
1632 mr->ram = true;
1633 mr->readonly = true;
1634 mr->terminates = true;
1635 mr->destructor = memory_region_destructor_ram;
1636 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
1637 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1638}
1639
1640void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1641 Object *owner,
1642 const MemoryRegionOps *ops,
1643 void *opaque,
1644 const char *name,
1645 uint64_t size,
1646 Error **errp)
1647{
1648 assert(ops);
1649 memory_region_init(mr, owner, name, size);
1650 mr->ops = ops;
1651 mr->opaque = opaque;
1652 mr->terminates = true;
1653 mr->rom_device = true;
1654 mr->destructor = memory_region_destructor_ram;
1655 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
1656}
1657
1658void memory_region_init_iommu(void *_iommu_mr,
1659 size_t instance_size,
1660 const char *mrtypename,
1661 Object *owner,
1662 const char *name,
1663 uint64_t size)
1664{
1665 struct IOMMUMemoryRegion *iommu_mr;
1666 struct MemoryRegion *mr;
1667
1668 object_initialize(_iommu_mr, instance_size, mrtypename);
1669 mr = MEMORY_REGION(_iommu_mr);
1670 memory_region_do_init(mr, owner, name, size);
1671 iommu_mr = IOMMU_MEMORY_REGION(mr);
1672 mr->terminates = true; /* then re-forwards */
1673 QLIST_INIT(&iommu_mr->iommu_notify);
1674 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1675}
1676
1677static void memory_region_finalize(Object *obj)
1678{
1679 MemoryRegion *mr = MEMORY_REGION(obj);
1680
1681 assert(!mr->container);
1682
1683 /* We know the region is not visible in any address space (it
1684 * does not have a container and cannot be a root either because
1685 * it has no references, so we can blindly clear mr->enabled.
1686 * memory_region_set_enabled instead could trigger a transaction
1687 * and cause an infinite loop.
1688 */
1689 mr->enabled = false;
1690 memory_region_transaction_begin();
1691 while (!QTAILQ_EMPTY(&mr->subregions)) {
1692 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1693 memory_region_del_subregion(mr, subregion);
1694 }
1695 memory_region_transaction_commit();
1696
1697 mr->destructor(mr);
1698 memory_region_clear_coalescing(mr);
1699 g_free((char *)mr->name);
1700 g_free(mr->ioeventfds);
1701}
1702
1703Object *memory_region_owner(MemoryRegion *mr)
1704{
1705 Object *obj = OBJECT(mr);
1706 return obj->parent;
1707}
1708
1709void memory_region_ref(MemoryRegion *mr)
1710{
1711 /* MMIO callbacks most likely will access data that belongs
1712 * to the owner, hence the need to ref/unref the owner whenever
1713 * the memory region is in use.
1714 *
1715 * The memory region is a child of its owner. As long as the
1716 * owner doesn't call unparent itself on the memory region,
1717 * ref-ing the owner will also keep the memory region alive.
1718 * Memory regions without an owner are supposed to never go away;
1719 * we do not ref/unref them because it slows down DMA sensibly.
1720 */
1721 if (mr && mr->owner) {
1722 object_ref(mr->owner);
1723 }
1724}
1725
1726void memory_region_unref(MemoryRegion *mr)
1727{
1728 if (mr && mr->owner) {
1729 object_unref(mr->owner);
1730 }
1731}
1732
1733uint64_t memory_region_size(MemoryRegion *mr)
1734{
1735 if (int128_eq(mr->size, int128_2_64())) {
1736 return UINT64_MAX;
1737 }
1738 return int128_get64(mr->size);
1739}
1740
1741const char *memory_region_name(const MemoryRegion *mr)
1742{
1743 if (!mr->name) {
1744 ((MemoryRegion *)mr)->name =
1745 object_get_canonical_path_component(OBJECT(mr));
1746 }
1747 return mr->name;
1748}
1749
1750bool memory_region_is_ram_device(MemoryRegion *mr)
1751{
1752 return mr->ram_device;
1753}
1754
1755uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1756{
1757 uint8_t mask = mr->dirty_log_mask;
1758 if (global_dirty_log && mr->ram_block) {
1759 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1760 }
1761 return mask;
1762}
1763
1764bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1765{
1766 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1767}
1768
1769static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1770{
1771 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1772 IOMMUNotifier *iommu_notifier;
1773 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1774
1775 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1776 flags |= iommu_notifier->notifier_flags;
1777 }
1778
1779 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1780 imrc->notify_flag_changed(iommu_mr,
1781 iommu_mr->iommu_notify_flags,
1782 flags);
1783 }
1784
1785 iommu_mr->iommu_notify_flags = flags;
1786}
1787
1788void memory_region_register_iommu_notifier(MemoryRegion *mr,
1789 IOMMUNotifier *n)
1790{
1791 IOMMUMemoryRegion *iommu_mr;
1792
1793 if (mr->alias) {
1794 memory_region_register_iommu_notifier(mr->alias, n);
1795 return;
1796 }
1797
1798 /* We need to register for at least one bitfield */
1799 iommu_mr = IOMMU_MEMORY_REGION(mr);
1800 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1801 assert(n->start <= n->end);
1802 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1803 memory_region_update_iommu_notify_flags(iommu_mr);
1804}
1805
1806uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1807{
1808 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1809
1810 if (imrc->get_min_page_size) {
1811 return imrc->get_min_page_size(iommu_mr);
1812 }
1813 return TARGET_PAGE_SIZE;
1814}
1815
1816void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1817{
1818 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1819 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1820 hwaddr addr, granularity;
1821 IOMMUTLBEntry iotlb;
1822
1823 /* If the IOMMU has its own replay callback, override */
1824 if (imrc->replay) {
1825 imrc->replay(iommu_mr, n);
1826 return;
1827 }
1828
1829 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1830
1831 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1832 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
1833 if (iotlb.perm != IOMMU_NONE) {
1834 n->notify(n, &iotlb);
1835 }
1836
1837 /* if (2^64 - MR size) < granularity, it's possible to get an
1838 * infinite loop here. This should catch such a wraparound */
1839 if ((addr + granularity) < addr) {
1840 break;
1841 }
1842 }
1843}
1844
1845void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1846{
1847 IOMMUNotifier *notifier;
1848
1849 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1850 memory_region_iommu_replay(iommu_mr, notifier);
1851 }
1852}
1853
1854void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1855 IOMMUNotifier *n)
1856{
1857 IOMMUMemoryRegion *iommu_mr;
1858
1859 if (mr->alias) {
1860 memory_region_unregister_iommu_notifier(mr->alias, n);
1861 return;
1862 }
1863 QLIST_REMOVE(n, node);
1864 iommu_mr = IOMMU_MEMORY_REGION(mr);
1865 memory_region_update_iommu_notify_flags(iommu_mr);
1866}
1867
1868void memory_region_notify_one(IOMMUNotifier *notifier,
1869 IOMMUTLBEntry *entry)
1870{
1871 IOMMUNotifierFlag request_flags;
1872
1873 /*
1874 * Skip the notification if the notification does not overlap
1875 * with registered range.
1876 */
1877 if (notifier->start > entry->iova + entry->addr_mask ||
1878 notifier->end < entry->iova) {
1879 return;
1880 }
1881
1882 if (entry->perm & IOMMU_RW) {
1883 request_flags = IOMMU_NOTIFIER_MAP;
1884 } else {
1885 request_flags = IOMMU_NOTIFIER_UNMAP;
1886 }
1887
1888 if (notifier->notifier_flags & request_flags) {
1889 notifier->notify(notifier, entry);
1890 }
1891}
1892
1893void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1894 IOMMUTLBEntry entry)
1895{
1896 IOMMUNotifier *iommu_notifier;
1897
1898 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1899
1900 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1901 memory_region_notify_one(iommu_notifier, &entry);
1902 }
1903}
1904
1905int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1906 enum IOMMUMemoryRegionAttr attr,
1907 void *data)
1908{
1909 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1910
1911 if (!imrc->get_attr) {
1912 return -EINVAL;
1913 }
1914
1915 return imrc->get_attr(iommu_mr, attr, data);
1916}
1917
1918int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1919 MemTxAttrs attrs)
1920{
1921 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1922
1923 if (!imrc->attrs_to_index) {
1924 return 0;
1925 }
1926
1927 return imrc->attrs_to_index(iommu_mr, attrs);
1928}
1929
1930int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1931{
1932 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1933
1934 if (!imrc->num_indexes) {
1935 return 1;
1936 }
1937
1938 return imrc->num_indexes(iommu_mr);
1939}
1940
1941void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1942{
1943 uint8_t mask = 1 << client;
1944 uint8_t old_logging;
1945
1946 assert(client == DIRTY_MEMORY_VGA);
1947 old_logging = mr->vga_logging_count;
1948 mr->vga_logging_count += log ? 1 : -1;
1949 if (!!old_logging == !!mr->vga_logging_count) {
1950 return;
1951 }
1952
1953 memory_region_transaction_begin();
1954 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
1955 memory_region_update_pending |= mr->enabled;
1956 memory_region_transaction_commit();
1957}
1958
1959bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1960 hwaddr size, unsigned client)
1961{
1962 assert(mr->ram_block);
1963 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1964 size, client);
1965}
1966
1967void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1968 hwaddr size)
1969{
1970 assert(mr->ram_block);
1971 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1972 size,
1973 memory_region_get_dirty_log_mask(mr));
1974}
1975
1976static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1977{
1978 MemoryListener *listener;
1979 AddressSpace *as;
1980 FlatView *view;
1981 FlatRange *fr;
1982
1983 /* If the same address space has multiple log_sync listeners, we
1984 * visit that address space's FlatView multiple times. But because
1985 * log_sync listeners are rare, it's still cheaper than walking each
1986 * address space once.
1987 */
1988 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1989 if (!listener->log_sync) {
1990 continue;
1991 }
1992 as = listener->address_space;
1993 view = address_space_get_flatview(as);
1994 FOR_EACH_FLAT_RANGE(fr, view) {
1995 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
1996 MemoryRegionSection mrs = section_from_flat_range(fr, view);
1997 listener->log_sync(listener, &mrs);
1998 }
1999 }
2000 flatview_unref(view);
2001 }
2002}
2003
2004DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2005 hwaddr addr,
2006 hwaddr size,
2007 unsigned client)
2008{
2009 assert(mr->ram_block);
2010 memory_region_sync_dirty_bitmap(mr);
2011 return cpu_physical_memory_snapshot_and_clear_dirty(
2012 memory_region_get_ram_addr(mr) + addr, size, client);
2013}
2014
2015bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2016 hwaddr addr, hwaddr size)
2017{
2018 assert(mr->ram_block);
2019 return cpu_physical_memory_snapshot_get_dirty(snap,
2020 memory_region_get_ram_addr(mr) + addr, size);
2021}
2022
2023void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2024{
2025 if (mr->readonly != readonly) {
2026 memory_region_transaction_begin();
2027 mr->readonly = readonly;
2028 memory_region_update_pending |= mr->enabled;
2029 memory_region_transaction_commit();
2030 }
2031}
2032
2033void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2034{
2035 if (mr->romd_mode != romd_mode) {
2036 memory_region_transaction_begin();
2037 mr->romd_mode = romd_mode;
2038 memory_region_update_pending |= mr->enabled;
2039 memory_region_transaction_commit();
2040 }
2041}
2042
2043void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2044 hwaddr size, unsigned client)
2045{
2046 assert(mr->ram_block);
2047 cpu_physical_memory_test_and_clear_dirty(
2048 memory_region_get_ram_addr(mr) + addr, size, client);
2049}
2050
2051int memory_region_get_fd(MemoryRegion *mr)
2052{
2053 int fd;
2054
2055 rcu_read_lock();
2056 while (mr->alias) {
2057 mr = mr->alias;
2058 }
2059 fd = mr->ram_block->fd;
2060 rcu_read_unlock();
2061
2062 return fd;
2063}
2064
2065void *memory_region_get_ram_ptr(MemoryRegion *mr)
2066{
2067 void *ptr;
2068 uint64_t offset = 0;
2069
2070 rcu_read_lock();
2071 while (mr->alias) {
2072 offset += mr->alias_offset;
2073 mr = mr->alias;
2074 }
2075 assert(mr->ram_block);
2076 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2077 rcu_read_unlock();
2078
2079 return ptr;
2080}
2081
2082MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2083{
2084 RAMBlock *block;
2085
2086 block = qemu_ram_block_from_host(ptr, false, offset);
2087 if (!block) {
2088 return NULL;
2089 }
2090
2091 return block->mr;
2092}
2093
2094ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2095{
2096 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2097}
2098
2099void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2100{
2101 assert(mr->ram_block);
2102
2103 qemu_ram_resize(mr->ram_block, newsize, errp);
2104}
2105
2106static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2107{
2108 FlatView *view;
2109 FlatRange *fr;
2110 CoalescedMemoryRange *cmr;
2111 AddrRange tmp;
2112 MemoryRegionSection section;
2113
2114 view = address_space_get_flatview(as);
2115 FOR_EACH_FLAT_RANGE(fr, view) {
2116 if (fr->mr == mr) {
2117 section = (MemoryRegionSection) {
2118 .fv = view,
2119 .offset_within_address_space = int128_get64(fr->addr.start),
2120 .size = fr->addr.size,
2121 };
2122
2123 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
2124 int128_get64(fr->addr.start),
2125 int128_get64(fr->addr.size));
2126 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2127 tmp = addrrange_shift(cmr->addr,
2128 int128_sub(fr->addr.start,
2129 int128_make64(fr->offset_in_region)));
2130 if (!addrrange_intersects(tmp, fr->addr)) {
2131 continue;
2132 }
2133 tmp = addrrange_intersection(tmp, fr->addr);
2134 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
2135 int128_get64(tmp.start),
2136 int128_get64(tmp.size));
2137 }
2138 }
2139 }
2140 flatview_unref(view);
2141}
2142
2143static void memory_region_update_coalesced_range(MemoryRegion *mr)
2144{
2145 AddressSpace *as;
2146
2147 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2148 memory_region_update_coalesced_range_as(mr, as);
2149 }
2150}
2151
2152void memory_region_set_coalescing(MemoryRegion *mr)
2153{
2154 memory_region_clear_coalescing(mr);
2155 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2156}
2157
2158void memory_region_add_coalescing(MemoryRegion *mr,
2159 hwaddr offset,
2160 uint64_t size)
2161{
2162 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2163
2164 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2165 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2166 memory_region_update_coalesced_range(mr);
2167 memory_region_set_flush_coalesced(mr);
2168}
2169
2170void memory_region_clear_coalescing(MemoryRegion *mr)
2171{
2172 CoalescedMemoryRange *cmr;
2173 bool updated = false;
2174
2175 qemu_flush_coalesced_mmio_buffer();
2176 mr->flush_coalesced_mmio = false;
2177
2178 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2179 cmr = QTAILQ_FIRST(&mr->coalesced);
2180 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2181 g_free(cmr);
2182 updated = true;
2183 }
2184
2185 if (updated) {
2186 memory_region_update_coalesced_range(mr);
2187 }
2188}
2189
2190void memory_region_set_flush_coalesced(MemoryRegion *mr)
2191{
2192 mr->flush_coalesced_mmio = true;
2193}
2194
2195void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2196{
2197 qemu_flush_coalesced_mmio_buffer();
2198 if (QTAILQ_EMPTY(&mr->coalesced)) {
2199 mr->flush_coalesced_mmio = false;
2200 }
2201}
2202
2203void memory_region_clear_global_locking(MemoryRegion *mr)
2204{
2205 mr->global_locking = false;
2206}
2207
2208static bool userspace_eventfd_warning;
2209
2210void memory_region_add_eventfd(MemoryRegion *mr,
2211 hwaddr addr,
2212 unsigned size,
2213 bool match_data,
2214 uint64_t data,
2215 EventNotifier *e)
2216{
2217 MemoryRegionIoeventfd mrfd = {
2218 .addr.start = int128_make64(addr),
2219 .addr.size = int128_make64(size),
2220 .match_data = match_data,
2221 .data = data,
2222 .e = e,
2223 };
2224 unsigned i;
2225
2226 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2227 userspace_eventfd_warning))) {
2228 userspace_eventfd_warning = true;
2229 error_report("Using eventfd without MMIO binding in KVM. "
2230 "Suboptimal performance expected");
2231 }
2232
2233 if (size) {
2234 adjust_endianness(mr, &mrfd.data, size);
2235 }
2236 memory_region_transaction_begin();
2237 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2238 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2239 break;
2240 }
2241 }
2242 ++mr->ioeventfd_nb;
2243 mr->ioeventfds = g_realloc(mr->ioeventfds,
2244 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2245 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2246 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2247 mr->ioeventfds[i] = mrfd;
2248 ioeventfd_update_pending |= mr->enabled;
2249 memory_region_transaction_commit();
2250}
2251
2252void memory_region_del_eventfd(MemoryRegion *mr,
2253 hwaddr addr,
2254 unsigned size,
2255 bool match_data,
2256 uint64_t data,
2257 EventNotifier *e)
2258{
2259 MemoryRegionIoeventfd mrfd = {
2260 .addr.start = int128_make64(addr),
2261 .addr.size = int128_make64(size),
2262 .match_data = match_data,
2263 .data = data,
2264 .e = e,
2265 };
2266 unsigned i;
2267
2268 if (size) {
2269 adjust_endianness(mr, &mrfd.data, size);
2270 }
2271 memory_region_transaction_begin();
2272 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2273 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2274 break;
2275 }
2276 }
2277 assert(i != mr->ioeventfd_nb);
2278 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2279 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2280 --mr->ioeventfd_nb;
2281 mr->ioeventfds = g_realloc(mr->ioeventfds,
2282 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2283 ioeventfd_update_pending |= mr->enabled;
2284 memory_region_transaction_commit();
2285}
2286
2287static void memory_region_update_container_subregions(MemoryRegion *subregion)
2288{
2289 MemoryRegion *mr = subregion->container;
2290 MemoryRegion *other;
2291
2292 memory_region_transaction_begin();
2293
2294 memory_region_ref(subregion);
2295 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2296 if (subregion->priority >= other->priority) {
2297 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2298 goto done;
2299 }
2300 }
2301 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2302done:
2303 memory_region_update_pending |= mr->enabled && subregion->enabled;
2304 memory_region_transaction_commit();
2305}
2306
2307static void memory_region_add_subregion_common(MemoryRegion *mr,
2308 hwaddr offset,
2309 MemoryRegion *subregion)
2310{
2311 assert(!subregion->container);
2312 subregion->container = mr;
2313 subregion->addr = offset;
2314 memory_region_update_container_subregions(subregion);
2315}
2316
2317void memory_region_add_subregion(MemoryRegion *mr,
2318 hwaddr offset,
2319 MemoryRegion *subregion)
2320{
2321 subregion->priority = 0;
2322 memory_region_add_subregion_common(mr, offset, subregion);
2323}
2324
2325void memory_region_add_subregion_overlap(MemoryRegion *mr,
2326 hwaddr offset,
2327 MemoryRegion *subregion,
2328 int priority)
2329{
2330 subregion->priority = priority;
2331 memory_region_add_subregion_common(mr, offset, subregion);
2332}
2333
2334void memory_region_del_subregion(MemoryRegion *mr,
2335 MemoryRegion *subregion)
2336{
2337 memory_region_transaction_begin();
2338 assert(subregion->container == mr);
2339 subregion->container = NULL;
2340 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2341 memory_region_unref(subregion);
2342 memory_region_update_pending |= mr->enabled && subregion->enabled;
2343 memory_region_transaction_commit();
2344}
2345
2346void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2347{
2348 if (enabled == mr->enabled) {
2349 return;
2350 }
2351 memory_region_transaction_begin();
2352 mr->enabled = enabled;
2353 memory_region_update_pending = true;
2354 memory_region_transaction_commit();
2355}
2356
2357void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2358{
2359 Int128 s = int128_make64(size);
2360
2361 if (size == UINT64_MAX) {
2362 s = int128_2_64();
2363 }
2364 if (int128_eq(s, mr->size)) {
2365 return;
2366 }
2367 memory_region_transaction_begin();
2368 mr->size = s;
2369 memory_region_update_pending = true;
2370 memory_region_transaction_commit();
2371}
2372
2373static void memory_region_readd_subregion(MemoryRegion *mr)
2374{
2375 MemoryRegion *container = mr->container;
2376
2377 if (container) {
2378 memory_region_transaction_begin();
2379 memory_region_ref(mr);
2380 memory_region_del_subregion(container, mr);
2381 mr->container = container;
2382 memory_region_update_container_subregions(mr);
2383 memory_region_unref(mr);
2384 memory_region_transaction_commit();
2385 }
2386}
2387
2388void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2389{
2390 if (addr != mr->addr) {
2391 mr->addr = addr;
2392 memory_region_readd_subregion(mr);
2393 }
2394}
2395
2396void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2397{
2398 assert(mr->alias);
2399
2400 if (offset == mr->alias_offset) {
2401 return;
2402 }
2403
2404 memory_region_transaction_begin();
2405 mr->alias_offset = offset;
2406 memory_region_update_pending |= mr->enabled;
2407 memory_region_transaction_commit();
2408}
2409
2410uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2411{
2412 return mr->align;
2413}
2414
2415static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2416{
2417 const AddrRange *addr = addr_;
2418 const FlatRange *fr = fr_;
2419
2420 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2421 return -1;
2422 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2423 return 1;
2424 }
2425 return 0;
2426}
2427
2428static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2429{
2430 return bsearch(&addr, view->ranges, view->nr,
2431 sizeof(FlatRange), cmp_flatrange_addr);
2432}
2433
2434bool memory_region_is_mapped(MemoryRegion *mr)
2435{
2436 return mr->container ? true : false;
2437}
2438
2439/* Same as memory_region_find, but it does not add a reference to the
2440 * returned region. It must be called from an RCU critical section.
2441 */
2442static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2443 hwaddr addr, uint64_t size)
2444{
2445 MemoryRegionSection ret = { .mr = NULL };
2446 MemoryRegion *root;
2447 AddressSpace *as;
2448 AddrRange range;
2449 FlatView *view;
2450 FlatRange *fr;
2451
2452 addr += mr->addr;
2453 for (root = mr; root->container; ) {
2454 root = root->container;
2455 addr += root->addr;
2456 }
2457
2458 as = memory_region_to_address_space(root);
2459 if (!as) {
2460 return ret;
2461 }
2462 range = addrrange_make(int128_make64(addr), int128_make64(size));
2463
2464 view = address_space_to_flatview(as);
2465 fr = flatview_lookup(view, range);
2466 if (!fr) {
2467 return ret;
2468 }
2469
2470 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2471 --fr;
2472 }
2473
2474 ret.mr = fr->mr;
2475 ret.fv = view;
2476 range = addrrange_intersection(range, fr->addr);
2477 ret.offset_within_region = fr->offset_in_region;
2478 ret.offset_within_region += int128_get64(int128_sub(range.start,
2479 fr->addr.start));
2480 ret.size = range.size;
2481 ret.offset_within_address_space = int128_get64(range.start);
2482 ret.readonly = fr->readonly;
2483 return ret;
2484}
2485
2486MemoryRegionSection memory_region_find(MemoryRegion *mr,
2487 hwaddr addr, uint64_t size)
2488{
2489 MemoryRegionSection ret;
2490 rcu_read_lock();
2491 ret = memory_region_find_rcu(mr, addr, size);
2492 if (ret.mr) {
2493 memory_region_ref(ret.mr);
2494 }
2495 rcu_read_unlock();
2496 return ret;
2497}
2498
2499bool memory_region_present(MemoryRegion *container, hwaddr addr)
2500{
2501 MemoryRegion *mr;
2502
2503 rcu_read_lock();
2504 mr = memory_region_find_rcu(container, addr, 1).mr;
2505 rcu_read_unlock();
2506 return mr && mr != container;
2507}
2508
2509void memory_global_dirty_log_sync(void)
2510{
2511 memory_region_sync_dirty_bitmap(NULL);
2512}
2513
2514static VMChangeStateEntry *vmstate_change;
2515
2516void memory_global_dirty_log_start(void)
2517{
2518 if (vmstate_change) {
2519 qemu_del_vm_change_state_handler(vmstate_change);
2520 vmstate_change = NULL;
2521 }
2522
2523 global_dirty_log = true;
2524
2525 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2526
2527 /* Refresh DIRTY_LOG_MIGRATION bit. */
2528 memory_region_transaction_begin();
2529 memory_region_update_pending = true;
2530 memory_region_transaction_commit();
2531}
2532
2533static void memory_global_dirty_log_do_stop(void)
2534{
2535 global_dirty_log = false;
2536
2537 /* Refresh DIRTY_LOG_MIGRATION bit. */
2538 memory_region_transaction_begin();
2539 memory_region_update_pending = true;
2540 memory_region_transaction_commit();
2541
2542 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2543}
2544
2545static void memory_vm_change_state_handler(void *opaque, int running,
2546 RunState state)
2547{
2548 if (running) {
2549 memory_global_dirty_log_do_stop();
2550
2551 if (vmstate_change) {
2552 qemu_del_vm_change_state_handler(vmstate_change);
2553 vmstate_change = NULL;
2554 }
2555 }
2556}
2557
2558void memory_global_dirty_log_stop(void)
2559{
2560 if (!runstate_is_running()) {
2561 if (vmstate_change) {
2562 return;
2563 }
2564 vmstate_change = qemu_add_vm_change_state_handler(
2565 memory_vm_change_state_handler, NULL);
2566 return;
2567 }
2568
2569 memory_global_dirty_log_do_stop();
2570}
2571
2572static void listener_add_address_space(MemoryListener *listener,
2573 AddressSpace *as)
2574{
2575 FlatView *view;
2576 FlatRange *fr;
2577
2578 if (listener->begin) {
2579 listener->begin(listener);
2580 }
2581 if (global_dirty_log) {
2582 if (listener->log_global_start) {
2583 listener->log_global_start(listener);
2584 }
2585 }
2586
2587 view = address_space_get_flatview(as);
2588 FOR_EACH_FLAT_RANGE(fr, view) {
2589 MemoryRegionSection section = section_from_flat_range(fr, view);
2590
2591 if (listener->region_add) {
2592 listener->region_add(listener, &section);
2593 }
2594 if (fr->dirty_log_mask && listener->log_start) {
2595 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2596 }
2597 }
2598 if (listener->commit) {
2599 listener->commit(listener);
2600 }
2601 flatview_unref(view);
2602}
2603
2604static void listener_del_address_space(MemoryListener *listener,
2605 AddressSpace *as)
2606{
2607 FlatView *view;
2608 FlatRange *fr;
2609
2610 if (listener->begin) {
2611 listener->begin(listener);
2612 }
2613 view = address_space_get_flatview(as);
2614 FOR_EACH_FLAT_RANGE(fr, view) {
2615 MemoryRegionSection section = section_from_flat_range(fr, view);
2616
2617 if (fr->dirty_log_mask && listener->log_stop) {
2618 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2619 }
2620 if (listener->region_del) {
2621 listener->region_del(listener, &section);
2622 }
2623 }
2624 if (listener->commit) {
2625 listener->commit(listener);
2626 }
2627 flatview_unref(view);
2628}
2629
2630void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2631{
2632 MemoryListener *other = NULL;
2633
2634 listener->address_space = as;
2635 if (QTAILQ_EMPTY(&memory_listeners)
2636 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2637 memory_listeners)->priority) {
2638 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2639 } else {
2640 QTAILQ_FOREACH(other, &memory_listeners, link) {
2641 if (listener->priority < other->priority) {
2642 break;
2643 }
2644 }
2645 QTAILQ_INSERT_BEFORE(other, listener, link);
2646 }
2647
2648 if (QTAILQ_EMPTY(&as->listeners)
2649 || listener->priority >= QTAILQ_LAST(&as->listeners,
2650 memory_listeners)->priority) {
2651 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2652 } else {
2653 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2654 if (listener->priority < other->priority) {
2655 break;
2656 }
2657 }
2658 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2659 }
2660
2661 listener_add_address_space(listener, as);
2662}
2663
2664void memory_listener_unregister(MemoryListener *listener)
2665{
2666 if (!listener->address_space) {
2667 return;
2668 }
2669
2670 listener_del_address_space(listener, listener->address_space);
2671 QTAILQ_REMOVE(&memory_listeners, listener, link);
2672 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2673 listener->address_space = NULL;
2674}
2675
2676bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2677{
2678 void *host;
2679 unsigned size = 0;
2680 unsigned offset = 0;
2681 Object *new_interface;
2682
2683 if (!mr || !mr->ops->request_ptr) {
2684 return false;
2685 }
2686
2687 /*
2688 * Avoid an update if the request_ptr call
2689 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2690 * a cache.
2691 */
2692 memory_region_transaction_begin();
2693
2694 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2695
2696 if (!host || !size) {
2697 memory_region_transaction_commit();
2698 return false;
2699 }
2700
2701 new_interface = object_new("mmio_interface");
2702 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2703 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2704 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2705 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2706 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2707 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2708
2709 memory_region_transaction_commit();
2710 return true;
2711}
2712
2713typedef struct MMIOPtrInvalidate {
2714 MemoryRegion *mr;
2715 hwaddr offset;
2716 unsigned size;
2717 int busy;
2718 int allocated;
2719} MMIOPtrInvalidate;
2720
2721#define MAX_MMIO_INVALIDATE 10
2722static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2723
2724static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2725 run_on_cpu_data data)
2726{
2727 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2728 MemoryRegion *mr = invalidate_data->mr;
2729 hwaddr offset = invalidate_data->offset;
2730 unsigned size = invalidate_data->size;
2731 MemoryRegionSection section = memory_region_find(mr, offset, size);
2732
2733 qemu_mutex_lock_iothread();
2734
2735 /* Reset dirty so this doesn't happen later. */
2736 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2737
2738 if (section.mr != mr) {
2739 /* memory_region_find add a ref on section.mr */
2740 memory_region_unref(section.mr);
2741 if (MMIO_INTERFACE(section.mr->owner)) {
2742 /* We found the interface just drop it. */
2743 object_property_set_bool(section.mr->owner, false, "realized",
2744 NULL);
2745 object_unref(section.mr->owner);
2746 object_unparent(section.mr->owner);
2747 }
2748 }
2749
2750 qemu_mutex_unlock_iothread();
2751
2752 if (invalidate_data->allocated) {
2753 g_free(invalidate_data);
2754 } else {
2755 invalidate_data->busy = 0;
2756 }
2757}
2758
2759void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2760 unsigned size)
2761{
2762 size_t i;
2763 MMIOPtrInvalidate *invalidate_data = NULL;
2764
2765 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2766 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2767 invalidate_data = &mmio_ptr_invalidate_list[i];
2768 break;
2769 }
2770 }
2771
2772 if (!invalidate_data) {
2773 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2774 invalidate_data->allocated = 1;
2775 }
2776
2777 invalidate_data->mr = mr;
2778 invalidate_data->offset = offset;
2779 invalidate_data->size = size;
2780
2781 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2782 RUN_ON_CPU_HOST_PTR(invalidate_data));
2783}
2784
2785void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2786{
2787 memory_region_ref(root);
2788 as->root = root;
2789 as->current_map = NULL;
2790 as->ioeventfd_nb = 0;
2791 as->ioeventfds = NULL;
2792 QTAILQ_INIT(&as->listeners);
2793 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2794 as->name = g_strdup(name ? name : "anonymous");
2795 address_space_update_topology(as);
2796 address_space_update_ioeventfds(as);
2797}
2798
2799static void do_address_space_destroy(AddressSpace *as)
2800{
2801 assert(QTAILQ_EMPTY(&as->listeners));
2802
2803 flatview_unref(as->current_map);
2804 g_free(as->name);
2805 g_free(as->ioeventfds);
2806 memory_region_unref(as->root);
2807}
2808
2809void address_space_destroy(AddressSpace *as)
2810{
2811 MemoryRegion *root = as->root;
2812
2813 /* Flush out anything from MemoryListeners listening in on this */
2814 memory_region_transaction_begin();
2815 as->root = NULL;
2816 memory_region_transaction_commit();
2817 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2818
2819 /* At this point, as->dispatch and as->current_map are dummy
2820 * entries that the guest should never use. Wait for the old
2821 * values to expire before freeing the data.
2822 */
2823 as->root = root;
2824 call_rcu(as, do_address_space_destroy, rcu);
2825}
2826
2827static const char *memory_region_type(MemoryRegion *mr)
2828{
2829 if (memory_region_is_ram_device(mr)) {
2830 return "ramd";
2831 } else if (memory_region_is_romd(mr)) {
2832 return "romd";
2833 } else if (memory_region_is_rom(mr)) {
2834 return "rom";
2835 } else if (memory_region_is_ram(mr)) {
2836 return "ram";
2837 } else {
2838 return "i/o";
2839 }
2840}
2841
2842typedef struct MemoryRegionList MemoryRegionList;
2843
2844struct MemoryRegionList {
2845 const MemoryRegion *mr;
2846 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2847};
2848
2849typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
2850
2851#define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2852 int128_sub((size), int128_one())) : 0)
2853#define MTREE_INDENT " "
2854
2855static void mtree_print_mr(fprintf_function mon_printf, void *f,
2856 const MemoryRegion *mr, unsigned int level,
2857 hwaddr base,
2858 MemoryRegionListHead *alias_print_queue)
2859{
2860 MemoryRegionList *new_ml, *ml, *next_ml;
2861 MemoryRegionListHead submr_print_queue;
2862 const MemoryRegion *submr;
2863 unsigned int i;
2864 hwaddr cur_start, cur_end;
2865
2866 if (!mr) {
2867 return;
2868 }
2869
2870 for (i = 0; i < level; i++) {
2871 mon_printf(f, MTREE_INDENT);
2872 }
2873
2874 cur_start = base + mr->addr;
2875 cur_end = cur_start + MR_SIZE(mr->size);
2876
2877 /*
2878 * Try to detect overflow of memory region. This should never
2879 * happen normally. When it happens, we dump something to warn the
2880 * user who is observing this.
2881 */
2882 if (cur_start < base || cur_end < cur_start) {
2883 mon_printf(f, "[DETECTED OVERFLOW!] ");
2884 }
2885
2886 if (mr->alias) {
2887 MemoryRegionList *ml;
2888 bool found = false;
2889
2890 /* check if the alias is already in the queue */
2891 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2892 if (ml->mr == mr->alias) {
2893 found = true;
2894 }
2895 }
2896
2897 if (!found) {
2898 ml = g_new(MemoryRegionList, 1);
2899 ml->mr = mr->alias;
2900 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2901 }
2902 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2903 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
2904 "-" TARGET_FMT_plx "%s\n",
2905 cur_start, cur_end,
2906 mr->priority,
2907 memory_region_type((MemoryRegion *)mr),
2908 memory_region_name(mr),
2909 memory_region_name(mr->alias),
2910 mr->alias_offset,
2911 mr->alias_offset + MR_SIZE(mr->size),
2912 mr->enabled ? "" : " [disabled]");
2913 } else {
2914 mon_printf(f,
2915 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
2916 cur_start, cur_end,
2917 mr->priority,
2918 memory_region_type((MemoryRegion *)mr),
2919 memory_region_name(mr),
2920 mr->enabled ? "" : " [disabled]");
2921 }
2922
2923 QTAILQ_INIT(&submr_print_queue);
2924
2925 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2926 new_ml = g_new(MemoryRegionList, 1);
2927 new_ml->mr = submr;
2928 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2929 if (new_ml->mr->addr < ml->mr->addr ||
2930 (new_ml->mr->addr == ml->mr->addr &&
2931 new_ml->mr->priority > ml->mr->priority)) {
2932 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2933 new_ml = NULL;
2934 break;
2935 }
2936 }
2937 if (new_ml) {
2938 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2939 }
2940 }
2941
2942 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2943 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
2944 alias_print_queue);
2945 }
2946
2947 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2948 g_free(ml);
2949 }
2950}
2951
2952struct FlatViewInfo {
2953 fprintf_function mon_printf;
2954 void *f;
2955 int counter;
2956 bool dispatch_tree;
2957};
2958
2959static void mtree_print_flatview(gpointer key, gpointer value,
2960 gpointer user_data)
2961{
2962 FlatView *view = key;
2963 GArray *fv_address_spaces = value;
2964 struct FlatViewInfo *fvi = user_data;
2965 fprintf_function p = fvi->mon_printf;
2966 void *f = fvi->f;
2967 FlatRange *range = &view->ranges[0];
2968 MemoryRegion *mr;
2969 int n = view->nr;
2970 int i;
2971 AddressSpace *as;
2972
2973 p(f, "FlatView #%d\n", fvi->counter);
2974 ++fvi->counter;
2975
2976 for (i = 0; i < fv_address_spaces->len; ++i) {
2977 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2978 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2979 if (as->root->alias) {
2980 p(f, ", alias %s", memory_region_name(as->root->alias));
2981 }
2982 p(f, "\n");
2983 }
2984
2985 p(f, " Root memory region: %s\n",
2986 view->root ? memory_region_name(view->root) : "(none)");
2987
2988 if (n <= 0) {
2989 p(f, MTREE_INDENT "No rendered FlatView\n\n");
2990 return;
2991 }
2992
2993 while (n--) {
2994 mr = range->mr;
2995 if (range->offset_in_region) {
2996 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2997 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2998 int128_get64(range->addr.start),
2999 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3000 mr->priority,
3001 range->readonly ? "rom" : memory_region_type(mr),
3002 memory_region_name(mr),
3003 range->offset_in_region);
3004 } else {
3005 p(f, MTREE_INDENT TARGET_FMT_plx "-"
3006 TARGET_FMT_plx " (prio %d, %s): %s\n",
3007 int128_get64(range->addr.start),
3008 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
3009 mr->priority,
3010 range->readonly ? "rom" : memory_region_type(mr),
3011 memory_region_name(mr));
3012 }
3013 range++;
3014 }
3015
3016#if !defined(CONFIG_USER_ONLY)
3017 if (fvi->dispatch_tree && view->root) {
3018 mtree_print_dispatch(p, f, view->dispatch, view->root);
3019 }
3020#endif
3021
3022 p(f, "\n");
3023}
3024
3025static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3026 gpointer user_data)
3027{
3028 FlatView *view = key;
3029 GArray *fv_address_spaces = value;
3030
3031 g_array_unref(fv_address_spaces);
3032 flatview_unref(view);
3033
3034 return true;
3035}
3036
3037void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3038 bool dispatch_tree)
3039{
3040 MemoryRegionListHead ml_head;
3041 MemoryRegionList *ml, *ml2;
3042 AddressSpace *as;
3043
3044 if (flatview) {
3045 FlatView *view;
3046 struct FlatViewInfo fvi = {
3047 .mon_printf = mon_printf,
3048 .f = f,
3049 .counter = 0,
3050 .dispatch_tree = dispatch_tree
3051 };
3052 GArray *fv_address_spaces;
3053 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3054
3055 /* Gather all FVs in one table */
3056 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3057 view = address_space_get_flatview(as);
3058
3059 fv_address_spaces = g_hash_table_lookup(views, view);
3060 if (!fv_address_spaces) {
3061 fv_address_spaces = g_array_new(false, false, sizeof(as));
3062 g_hash_table_insert(views, view, fv_address_spaces);
3063 }
3064
3065 g_array_append_val(fv_address_spaces, as);
3066 }
3067
3068 /* Print */
3069 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3070
3071 /* Free */
3072 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3073 g_hash_table_unref(views);
3074
3075 return;
3076 }
3077
3078 QTAILQ_INIT(&ml_head);
3079
3080 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3081 mon_printf(f, "address-space: %s\n", as->name);
3082 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
3083 mon_printf(f, "\n");
3084 }
3085
3086 /* print aliased regions */
3087 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3088 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3089 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
3090 mon_printf(f, "\n");
3091 }
3092
3093 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3094 g_free(ml);
3095 }
3096}
3097
3098void memory_region_init_ram(MemoryRegion *mr,
3099 struct Object *owner,
3100 const char *name,
3101 uint64_t size,
3102 Error **errp)
3103{
3104 DeviceState *owner_dev;
3105 Error *err = NULL;
3106
3107 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3108 if (err) {
3109 error_propagate(errp, err);
3110 return;
3111 }
3112 /* This will assert if owner is neither NULL nor a DeviceState.
3113 * We only want the owner here for the purposes of defining a
3114 * unique name for migration. TODO: Ideally we should implement
3115 * a naming scheme for Objects which are not DeviceStates, in
3116 * which case we can relax this restriction.
3117 */
3118 owner_dev = DEVICE(owner);
3119 vmstate_register_ram(mr, owner_dev);
3120}
3121
3122void memory_region_init_rom(MemoryRegion *mr,
3123 struct Object *owner,
3124 const char *name,
3125 uint64_t size,
3126 Error **errp)
3127{
3128 DeviceState *owner_dev;
3129 Error *err = NULL;
3130
3131 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3132 if (err) {
3133 error_propagate(errp, err);
3134 return;
3135 }
3136 /* This will assert if owner is neither NULL nor a DeviceState.
3137 * We only want the owner here for the purposes of defining a
3138 * unique name for migration. TODO: Ideally we should implement
3139 * a naming scheme for Objects which are not DeviceStates, in
3140 * which case we can relax this restriction.
3141 */
3142 owner_dev = DEVICE(owner);
3143 vmstate_register_ram(mr, owner_dev);
3144}
3145
3146void memory_region_init_rom_device(MemoryRegion *mr,
3147 struct Object *owner,
3148 const MemoryRegionOps *ops,
3149 void *opaque,
3150 const char *name,
3151 uint64_t size,
3152 Error **errp)
3153{
3154 DeviceState *owner_dev;
3155 Error *err = NULL;
3156
3157 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3158 name, size, &err);
3159 if (err) {
3160 error_propagate(errp, err);
3161 return;
3162 }
3163 /* This will assert if owner is neither NULL nor a DeviceState.
3164 * We only want the owner here for the purposes of defining a
3165 * unique name for migration. TODO: Ideally we should implement
3166 * a naming scheme for Objects which are not DeviceStates, in
3167 * which case we can relax this restriction.
3168 */
3169 owner_dev = DEVICE(owner);
3170 vmstate_register_ram(mr, owner_dev);
3171}
3172
3173static const TypeInfo memory_region_info = {
3174 .parent = TYPE_OBJECT,
3175 .name = TYPE_MEMORY_REGION,
3176 .instance_size = sizeof(MemoryRegion),
3177 .instance_init = memory_region_initfn,
3178 .instance_finalize = memory_region_finalize,
3179};
3180
3181static const TypeInfo iommu_memory_region_info = {
3182 .parent = TYPE_MEMORY_REGION,
3183 .name = TYPE_IOMMU_MEMORY_REGION,
3184 .class_size = sizeof(IOMMUMemoryRegionClass),
3185 .instance_size = sizeof(IOMMUMemoryRegion),
3186 .instance_init = iommu_memory_region_initfn,
3187 .abstract = true,
3188};
3189
3190static void memory_register_types(void)
3191{
3192 type_register_static(&memory_region_info);
3193 type_register_static(&iommu_memory_region_info);
3194}
3195
3196type_init(memory_register_types)
QEMU mirror