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1 | From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 | |
2 | From: Dave Hansen <dave.hansen@linux.intel.com> | |
3 | Date: Mon, 4 Dec 2017 15:07:54 +0100 | |
4 | Subject: [PATCH] x86/mm: Move the CR3 construction functions to tlbflush.h | |
5 | MIME-Version: 1.0 | |
6 | Content-Type: text/plain; charset=UTF-8 | |
7 | Content-Transfer-Encoding: 8bit | |
8 | ||
9 | CVE-2017-5754 | |
10 | ||
11 | For flushing the TLB, the ASID which has been programmed into the hardware | |
12 | must be known. That differs from what is in 'cpu_tlbstate'. | |
13 | ||
14 | Add functions to transform the 'cpu_tlbstate' values into to the one | |
15 | programmed into the hardware (CR3). | |
16 | ||
17 | It's not easy to include mmu_context.h into tlbflush.h, so just move the | |
18 | CR3 building over to tlbflush.h. | |
19 | ||
20 | Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> | |
21 | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> | |
22 | Cc: Andy Lutomirski <luto@kernel.org> | |
23 | Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> | |
24 | Cc: Borislav Petkov <bp@alien8.de> | |
25 | Cc: Brian Gerst <brgerst@gmail.com> | |
26 | Cc: David Laight <David.Laight@aculab.com> | |
27 | Cc: Denys Vlasenko <dvlasenk@redhat.com> | |
28 | Cc: Eduardo Valentin <eduval@amazon.com> | |
29 | Cc: Greg KH <gregkh@linuxfoundation.org> | |
30 | Cc: H. Peter Anvin <hpa@zytor.com> | |
31 | Cc: Josh Poimboeuf <jpoimboe@redhat.com> | |
32 | Cc: Juergen Gross <jgross@suse.com> | |
33 | Cc: Linus Torvalds <torvalds@linux-foundation.org> | |
34 | Cc: Peter Zijlstra <peterz@infradead.org> | |
35 | Cc: Will Deacon <will.deacon@arm.com> | |
36 | Cc: aliguori@amazon.com | |
37 | Cc: daniel.gruss@iaik.tugraz.at | |
38 | Cc: hughd@google.com | |
39 | Cc: keescook@google.com | |
40 | Cc: linux-mm@kvack.org | |
41 | Signed-off-by: Ingo Molnar <mingo@kernel.org> | |
42 | (cherry picked from commit 50fb83a62cf472dc53ba23bd3f7bd6c1b2b3b53e) | |
43 | Signed-off-by: Andy Whitcroft <apw@canonical.com> | |
44 | Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com> | |
45 | (cherry picked from commit f741923acf51c1061c11b45a168f8864d37dc5cd) | |
46 | Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com> | |
47 | --- | |
48 | arch/x86/include/asm/mmu_context.h | 29 +---------------------------- | |
49 | arch/x86/include/asm/tlbflush.h | 26 ++++++++++++++++++++++++++ | |
50 | arch/x86/mm/tlb.c | 8 ++++---- | |
51 | 3 files changed, 31 insertions(+), 32 deletions(-) | |
52 | ||
53 | diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h | |
54 | index 47ec51a821e8..89a01ad7e370 100644 | |
55 | --- a/arch/x86/include/asm/mmu_context.h | |
56 | +++ b/arch/x86/include/asm/mmu_context.h | |
57 | @@ -289,33 +289,6 @@ static inline bool arch_vma_access_permitted(struct vm_area_struct *vma, | |
58 | return __pkru_allows_pkey(vma_pkey(vma), write); | |
59 | } | |
60 | ||
61 | -/* | |
62 | - * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID | |
63 | - * bits. This serves two purposes. It prevents a nasty situation in | |
64 | - * which PCID-unaware code saves CR3, loads some other value (with PCID | |
65 | - * == 0), and then restores CR3, thus corrupting the TLB for ASID 0 if | |
66 | - * the saved ASID was nonzero. It also means that any bugs involving | |
67 | - * loading a PCID-enabled CR3 with CR4.PCIDE off will trigger | |
68 | - * deterministically. | |
69 | - */ | |
70 | - | |
71 | -static inline unsigned long build_cr3(struct mm_struct *mm, u16 asid) | |
72 | -{ | |
73 | - if (static_cpu_has(X86_FEATURE_PCID)) { | |
74 | - VM_WARN_ON_ONCE(asid > 4094); | |
75 | - return __sme_pa(mm->pgd) | (asid + 1); | |
76 | - } else { | |
77 | - VM_WARN_ON_ONCE(asid != 0); | |
78 | - return __sme_pa(mm->pgd); | |
79 | - } | |
80 | -} | |
81 | - | |
82 | -static inline unsigned long build_cr3_noflush(struct mm_struct *mm, u16 asid) | |
83 | -{ | |
84 | - VM_WARN_ON_ONCE(asid > 4094); | |
85 | - return __sme_pa(mm->pgd) | (asid + 1) | CR3_NOFLUSH; | |
86 | -} | |
87 | - | |
88 | /* | |
89 | * This can be used from process context to figure out what the value of | |
90 | * CR3 is without needing to do a (slow) __read_cr3(). | |
91 | @@ -325,7 +298,7 @@ static inline unsigned long build_cr3_noflush(struct mm_struct *mm, u16 asid) | |
92 | */ | |
93 | static inline unsigned long __get_current_cr3_fast(void) | |
94 | { | |
95 | - unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm), | |
96 | + unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd, | |
97 | this_cpu_read(cpu_tlbstate.loaded_mm_asid)); | |
98 | ||
99 | /* For now, be very restrictive about when this can be called. */ | |
100 | diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h | |
101 | index ed5d483c4a1b..3a421b164868 100644 | |
102 | --- a/arch/x86/include/asm/tlbflush.h | |
103 | +++ b/arch/x86/include/asm/tlbflush.h | |
104 | @@ -68,6 +68,32 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) | |
105 | return atomic64_inc_return(&mm->context.tlb_gen); | |
106 | } | |
107 | ||
108 | +/* | |
109 | + * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID bits. | |
110 | + * This serves two purposes. It prevents a nasty situation in which | |
111 | + * PCID-unaware code saves CR3, loads some other value (with PCID == 0), | |
112 | + * and then restores CR3, thus corrupting the TLB for ASID 0 if the saved | |
113 | + * ASID was nonzero. It also means that any bugs involving loading a | |
114 | + * PCID-enabled CR3 with CR4.PCIDE off will trigger deterministically. | |
115 | + */ | |
116 | +struct pgd_t; | |
117 | +static inline unsigned long build_cr3(pgd_t *pgd, u16 asid) | |
118 | +{ | |
119 | + if (static_cpu_has(X86_FEATURE_PCID)) { | |
120 | + VM_WARN_ON_ONCE(asid > 4094); | |
121 | + return __sme_pa(pgd) | (asid + 1); | |
122 | + } else { | |
123 | + VM_WARN_ON_ONCE(asid != 0); | |
124 | + return __sme_pa(pgd); | |
125 | + } | |
126 | +} | |
127 | + | |
128 | +static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid) | |
129 | +{ | |
130 | + VM_WARN_ON_ONCE(asid > 4094); | |
131 | + return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH; | |
132 | +} | |
133 | + | |
134 | #ifdef CONFIG_PARAVIRT | |
135 | #include <asm/paravirt.h> | |
136 | #else | |
137 | diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c | |
138 | index 5b4342c5039c..87d4f961bcb4 100644 | |
139 | --- a/arch/x86/mm/tlb.c | |
140 | +++ b/arch/x86/mm/tlb.c | |
141 | @@ -126,7 +126,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, | |
142 | * does something like write_cr3(read_cr3_pa()). | |
143 | */ | |
144 | #ifdef CONFIG_DEBUG_VM | |
145 | - if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev, prev_asid))) { | |
146 | + if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) { | |
147 | /* | |
148 | * If we were to BUG here, we'd be very likely to kill | |
149 | * the system so hard that we don't see the call trace. | |
150 | @@ -193,7 +193,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, | |
151 | if (need_flush) { | |
152 | this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); | |
153 | this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); | |
154 | - write_cr3(build_cr3(next, new_asid)); | |
155 | + write_cr3(build_cr3(next->pgd, new_asid)); | |
156 | ||
157 | /* | |
158 | * NB: This gets called via leave_mm() in the idle path | |
159 | @@ -206,7 +206,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next, | |
160 | trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL); | |
161 | } else { | |
162 | /* The new ASID is already up to date. */ | |
163 | - write_cr3(build_cr3_noflush(next, new_asid)); | |
164 | + write_cr3(build_cr3_noflush(next->pgd, new_asid)); | |
165 | ||
166 | /* See above wrt _rcuidle. */ | |
167 | trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0); | |
168 | @@ -283,7 +283,7 @@ void initialize_tlbstate_and_flush(void) | |
169 | !(cr4_read_shadow() & X86_CR4_PCIDE)); | |
170 | ||
171 | /* Force ASID 0 and force a TLB flush. */ | |
172 | - write_cr3(build_cr3(mm, 0)); | |
173 | + write_cr3(build_cr3(mm->pgd, 0)); | |
174 | ||
175 | /* Reinitialize tlbstate. */ | |
176 | this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0); | |
177 | -- | |
178 | 2.14.2 | |
179 |