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1 | /* | |
2 | * | |
3 | * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio. | |
4 | * | |
5 | * Copyright(c) 2004 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> | |
8 | * PeiSen Hou <pshou@realtek.com.tw> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the Free | |
12 | * Software Foundation; either version 2 of the License, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
18 | * more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along with | |
21 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
22 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
23 | * | |
24 | * CONTACTS: | |
25 | * | |
26 | * Matt Jared matt.jared@intel.com | |
27 | * Andy Kopp andy.kopp@intel.com | |
28 | * Dan Kogan dan.d.kogan@intel.com | |
29 | * | |
30 | * CHANGES: | |
31 | * | |
32 | * 2004.12.01 Major rewrite by tiwai, merged the work of pshou | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <sound/driver.h> | |
37 | #include <asm/io.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/kernel.h> | |
41 | #include <linux/module.h> | |
42 | #include <linux/moduleparam.h> | |
43 | #include <linux/init.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/pci.h> | |
46 | #include <linux/mutex.h> | |
47 | #include <sound/core.h> | |
48 | #include <sound/initval.h> | |
49 | #include "hda_codec.h" | |
50 | ||
51 | ||
52 | static int index = SNDRV_DEFAULT_IDX1; | |
53 | static char *id = SNDRV_DEFAULT_STR1; | |
54 | static char *model; | |
55 | static int position_fix; | |
56 | static int probe_mask = -1; | |
57 | static int single_cmd; | |
58 | static int enable_msi; | |
59 | ||
60 | module_param(index, int, 0444); | |
61 | MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); | |
62 | module_param(id, charp, 0444); | |
63 | MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); | |
64 | module_param(model, charp, 0444); | |
65 | MODULE_PARM_DESC(model, "Use the given board model."); | |
66 | module_param(position_fix, int, 0444); | |
67 | MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size)."); | |
68 | module_param(probe_mask, int, 0444); | |
69 | MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); | |
70 | module_param(single_cmd, bool, 0444); | |
71 | MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only)."); | |
72 | module_param(enable_msi, int, 0); | |
73 | MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); | |
74 | ||
75 | ||
76 | /* just for backward compatibility */ | |
77 | static int enable; | |
78 | module_param(enable, bool, 0444); | |
79 | ||
80 | MODULE_LICENSE("GPL"); | |
81 | MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," | |
82 | "{Intel, ICH6M}," | |
83 | "{Intel, ICH7}," | |
84 | "{Intel, ESB2}," | |
85 | "{Intel, ICH8}," | |
86 | "{Intel, ICH9}," | |
87 | "{ATI, SB450}," | |
88 | "{ATI, SB600}," | |
89 | "{ATI, RS600}," | |
90 | "{ATI, RS690}," | |
91 | "{VIA, VT8251}," | |
92 | "{VIA, VT8237A}," | |
93 | "{SiS, SIS966}," | |
94 | "{ULI, M5461}}"); | |
95 | MODULE_DESCRIPTION("Intel HDA driver"); | |
96 | ||
97 | #define SFX "hda-intel: " | |
98 | ||
99 | /* | |
100 | * registers | |
101 | */ | |
102 | #define ICH6_REG_GCAP 0x00 | |
103 | #define ICH6_REG_VMIN 0x02 | |
104 | #define ICH6_REG_VMAJ 0x03 | |
105 | #define ICH6_REG_OUTPAY 0x04 | |
106 | #define ICH6_REG_INPAY 0x06 | |
107 | #define ICH6_REG_GCTL 0x08 | |
108 | #define ICH6_REG_WAKEEN 0x0c | |
109 | #define ICH6_REG_STATESTS 0x0e | |
110 | #define ICH6_REG_GSTS 0x10 | |
111 | #define ICH6_REG_INTCTL 0x20 | |
112 | #define ICH6_REG_INTSTS 0x24 | |
113 | #define ICH6_REG_WALCLK 0x30 | |
114 | #define ICH6_REG_SYNC 0x34 | |
115 | #define ICH6_REG_CORBLBASE 0x40 | |
116 | #define ICH6_REG_CORBUBASE 0x44 | |
117 | #define ICH6_REG_CORBWP 0x48 | |
118 | #define ICH6_REG_CORBRP 0x4A | |
119 | #define ICH6_REG_CORBCTL 0x4c | |
120 | #define ICH6_REG_CORBSTS 0x4d | |
121 | #define ICH6_REG_CORBSIZE 0x4e | |
122 | ||
123 | #define ICH6_REG_RIRBLBASE 0x50 | |
124 | #define ICH6_REG_RIRBUBASE 0x54 | |
125 | #define ICH6_REG_RIRBWP 0x58 | |
126 | #define ICH6_REG_RINTCNT 0x5a | |
127 | #define ICH6_REG_RIRBCTL 0x5c | |
128 | #define ICH6_REG_RIRBSTS 0x5d | |
129 | #define ICH6_REG_RIRBSIZE 0x5e | |
130 | ||
131 | #define ICH6_REG_IC 0x60 | |
132 | #define ICH6_REG_IR 0x64 | |
133 | #define ICH6_REG_IRS 0x68 | |
134 | #define ICH6_IRS_VALID (1<<1) | |
135 | #define ICH6_IRS_BUSY (1<<0) | |
136 | ||
137 | #define ICH6_REG_DPLBASE 0x70 | |
138 | #define ICH6_REG_DPUBASE 0x74 | |
139 | #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
140 | ||
141 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
142 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
143 | ||
144 | /* stream register offsets from stream base */ | |
145 | #define ICH6_REG_SD_CTL 0x00 | |
146 | #define ICH6_REG_SD_STS 0x03 | |
147 | #define ICH6_REG_SD_LPIB 0x04 | |
148 | #define ICH6_REG_SD_CBL 0x08 | |
149 | #define ICH6_REG_SD_LVI 0x0c | |
150 | #define ICH6_REG_SD_FIFOW 0x0e | |
151 | #define ICH6_REG_SD_FIFOSIZE 0x10 | |
152 | #define ICH6_REG_SD_FORMAT 0x12 | |
153 | #define ICH6_REG_SD_BDLPL 0x18 | |
154 | #define ICH6_REG_SD_BDLPU 0x1c | |
155 | ||
156 | /* PCI space */ | |
157 | #define ICH6_PCIREG_TCSEL 0x44 | |
158 | ||
159 | /* | |
160 | * other constants | |
161 | */ | |
162 | ||
163 | /* max number of SDs */ | |
164 | /* ICH, ATI and VIA have 4 playback and 4 capture */ | |
165 | #define ICH6_CAPTURE_INDEX 0 | |
166 | #define ICH6_NUM_CAPTURE 4 | |
167 | #define ICH6_PLAYBACK_INDEX 4 | |
168 | #define ICH6_NUM_PLAYBACK 4 | |
169 | ||
170 | /* ULI has 6 playback and 5 capture */ | |
171 | #define ULI_CAPTURE_INDEX 0 | |
172 | #define ULI_NUM_CAPTURE 5 | |
173 | #define ULI_PLAYBACK_INDEX 5 | |
174 | #define ULI_NUM_PLAYBACK 6 | |
175 | ||
176 | /* ATI HDMI has 1 playback and 0 capture */ | |
177 | #define ATIHDMI_CAPTURE_INDEX 0 | |
178 | #define ATIHDMI_NUM_CAPTURE 0 | |
179 | #define ATIHDMI_PLAYBACK_INDEX 0 | |
180 | #define ATIHDMI_NUM_PLAYBACK 1 | |
181 | ||
182 | /* this number is statically defined for simplicity */ | |
183 | #define MAX_AZX_DEV 16 | |
184 | ||
185 | /* max number of fragments - we may use more if allocating more pages for BDL */ | |
186 | #define BDL_SIZE PAGE_ALIGN(8192) | |
187 | #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16)) | |
188 | /* max buffer size - no h/w limit, you can increase as you like */ | |
189 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
190 | /* max number of PCM devics per card */ | |
191 | #define AZX_MAX_AUDIO_PCMS 6 | |
192 | #define AZX_MAX_MODEM_PCMS 2 | |
193 | #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS) | |
194 | ||
195 | /* RIRB int mask: overrun[2], response[0] */ | |
196 | #define RIRB_INT_RESPONSE 0x01 | |
197 | #define RIRB_INT_OVERRUN 0x04 | |
198 | #define RIRB_INT_MASK 0x05 | |
199 | ||
200 | /* STATESTS int mask: SD2,SD1,SD0 */ | |
201 | #define STATESTS_INT_MASK 0x07 | |
202 | #define AZX_MAX_CODECS 4 | |
203 | ||
204 | /* SD_CTL bits */ | |
205 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
206 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
207 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) | |
208 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
209 | ||
210 | /* SD_CTL and SD_STS */ | |
211 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
212 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
213 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
214 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE) | |
215 | ||
216 | /* SD_STS */ | |
217 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
218 | ||
219 | /* INTCTL and INTSTS */ | |
220 | #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ | |
221 | #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
222 | #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
223 | ||
224 | /* GCTL unsolicited response enable bit */ | |
225 | #define ICH6_GCTL_UREN (1<<8) | |
226 | ||
227 | /* GCTL reset bit */ | |
228 | #define ICH6_GCTL_RESET (1<<0) | |
229 | ||
230 | /* CORB/RIRB control, read/write pointer */ | |
231 | #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */ | |
232 | #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */ | |
233 | #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */ | |
234 | /* below are so far hardcoded - should read registers in future */ | |
235 | #define ICH6_MAX_CORB_ENTRIES 256 | |
236 | #define ICH6_MAX_RIRB_ENTRIES 256 | |
237 | ||
238 | /* position fix mode */ | |
239 | enum { | |
240 | POS_FIX_AUTO, | |
241 | POS_FIX_NONE, | |
242 | POS_FIX_POSBUF, | |
243 | POS_FIX_FIFO, | |
244 | }; | |
245 | ||
246 | /* Defines for ATI HD Audio support in SB450 south bridge */ | |
247 | #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 | |
248 | #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 | |
249 | ||
250 | /* Defines for Nvidia HDA support */ | |
251 | #define NVIDIA_HDA_TRANSREG_ADDR 0x4e | |
252 | #define NVIDIA_HDA_ENABLE_COHBITS 0x0f | |
253 | ||
254 | /* | |
255 | */ | |
256 | ||
257 | struct azx_dev { | |
258 | u32 *bdl; /* virtual address of the BDL */ | |
259 | dma_addr_t bdl_addr; /* physical address of the BDL */ | |
260 | u32 *posbuf; /* position buffer pointer */ | |
261 | ||
262 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
263 | unsigned int fragsize; /* size of each period in bytes */ | |
264 | unsigned int frags; /* number for period in the play buffer */ | |
265 | unsigned int fifo_size; /* FIFO size */ | |
266 | ||
267 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
268 | ||
269 | u32 sd_int_sta_mask; /* stream int status mask */ | |
270 | ||
271 | /* pcm support */ | |
272 | struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */ | |
273 | unsigned int format_val; /* format value to be set in the controller and the codec */ | |
274 | unsigned char stream_tag; /* assigned stream */ | |
275 | unsigned char index; /* stream index */ | |
276 | /* for sanity check of position buffer */ | |
277 | unsigned int period_intr; | |
278 | ||
279 | unsigned int opened :1; | |
280 | unsigned int running :1; | |
281 | }; | |
282 | ||
283 | /* CORB/RIRB */ | |
284 | struct azx_rb { | |
285 | u32 *buf; /* CORB/RIRB buffer | |
286 | * Each CORB entry is 4byte, RIRB is 8byte | |
287 | */ | |
288 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
289 | /* for RIRB */ | |
290 | unsigned short rp, wp; /* read/write pointers */ | |
291 | int cmds; /* number of pending requests */ | |
292 | u32 res; /* last read value */ | |
293 | }; | |
294 | ||
295 | struct azx { | |
296 | struct snd_card *card; | |
297 | struct pci_dev *pci; | |
298 | ||
299 | /* chip type specific */ | |
300 | int driver_type; | |
301 | int playback_streams; | |
302 | int playback_index_offset; | |
303 | int capture_streams; | |
304 | int capture_index_offset; | |
305 | int num_streams; | |
306 | ||
307 | /* pci resources */ | |
308 | unsigned long addr; | |
309 | void __iomem *remap_addr; | |
310 | int irq; | |
311 | ||
312 | /* locks */ | |
313 | spinlock_t reg_lock; | |
314 | struct mutex open_mutex; | |
315 | ||
316 | /* streams (x num_streams) */ | |
317 | struct azx_dev *azx_dev; | |
318 | ||
319 | /* PCM */ | |
320 | unsigned int pcm_devs; | |
321 | struct snd_pcm *pcm[AZX_MAX_PCMS]; | |
322 | ||
323 | /* HD codec */ | |
324 | unsigned short codec_mask; | |
325 | struct hda_bus *bus; | |
326 | ||
327 | /* CORB/RIRB */ | |
328 | struct azx_rb corb; | |
329 | struct azx_rb rirb; | |
330 | ||
331 | /* BDL, CORB/RIRB and position buffers */ | |
332 | struct snd_dma_buffer bdl; | |
333 | struct snd_dma_buffer rb; | |
334 | struct snd_dma_buffer posbuf; | |
335 | ||
336 | /* flags */ | |
337 | int position_fix; | |
338 | unsigned int initialized :1; | |
339 | unsigned int single_cmd :1; | |
340 | unsigned int polling_mode :1; | |
341 | unsigned int msi :1; | |
342 | }; | |
343 | ||
344 | /* driver types */ | |
345 | enum { | |
346 | AZX_DRIVER_ICH, | |
347 | AZX_DRIVER_ATI, | |
348 | AZX_DRIVER_ATIHDMI, | |
349 | AZX_DRIVER_VIA, | |
350 | AZX_DRIVER_SIS, | |
351 | AZX_DRIVER_ULI, | |
352 | AZX_DRIVER_NVIDIA, | |
353 | }; | |
354 | ||
355 | static char *driver_short_names[] __devinitdata = { | |
356 | [AZX_DRIVER_ICH] = "HDA Intel", | |
357 | [AZX_DRIVER_ATI] = "HDA ATI SB", | |
358 | [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", | |
359 | [AZX_DRIVER_VIA] = "HDA VIA VT82xx", | |
360 | [AZX_DRIVER_SIS] = "HDA SIS966", | |
361 | [AZX_DRIVER_ULI] = "HDA ULI M5461", | |
362 | [AZX_DRIVER_NVIDIA] = "HDA NVidia", | |
363 | }; | |
364 | ||
365 | /* | |
366 | * macros for easy use | |
367 | */ | |
368 | #define azx_writel(chip,reg,value) \ | |
369 | writel(value, (chip)->remap_addr + ICH6_REG_##reg) | |
370 | #define azx_readl(chip,reg) \ | |
371 | readl((chip)->remap_addr + ICH6_REG_##reg) | |
372 | #define azx_writew(chip,reg,value) \ | |
373 | writew(value, (chip)->remap_addr + ICH6_REG_##reg) | |
374 | #define azx_readw(chip,reg) \ | |
375 | readw((chip)->remap_addr + ICH6_REG_##reg) | |
376 | #define azx_writeb(chip,reg,value) \ | |
377 | writeb(value, (chip)->remap_addr + ICH6_REG_##reg) | |
378 | #define azx_readb(chip,reg) \ | |
379 | readb((chip)->remap_addr + ICH6_REG_##reg) | |
380 | ||
381 | #define azx_sd_writel(dev,reg,value) \ | |
382 | writel(value, (dev)->sd_addr + ICH6_REG_##reg) | |
383 | #define azx_sd_readl(dev,reg) \ | |
384 | readl((dev)->sd_addr + ICH6_REG_##reg) | |
385 | #define azx_sd_writew(dev,reg,value) \ | |
386 | writew(value, (dev)->sd_addr + ICH6_REG_##reg) | |
387 | #define azx_sd_readw(dev,reg) \ | |
388 | readw((dev)->sd_addr + ICH6_REG_##reg) | |
389 | #define azx_sd_writeb(dev,reg,value) \ | |
390 | writeb(value, (dev)->sd_addr + ICH6_REG_##reg) | |
391 | #define azx_sd_readb(dev,reg) \ | |
392 | readb((dev)->sd_addr + ICH6_REG_##reg) | |
393 | ||
394 | /* for pcm support */ | |
395 | #define get_azx_dev(substream) (substream->runtime->private_data) | |
396 | ||
397 | /* Get the upper 32bit of the given dma_addr_t | |
398 | * Compiler should optimize and eliminate the code if dma_addr_t is 32bit | |
399 | */ | |
400 | #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0) | |
401 | ||
402 | static int azx_acquire_irq(struct azx *chip, int do_disconnect); | |
403 | ||
404 | /* | |
405 | * Interface for HD codec | |
406 | */ | |
407 | ||
408 | /* | |
409 | * CORB / RIRB interface | |
410 | */ | |
411 | static int azx_alloc_cmd_io(struct azx *chip) | |
412 | { | |
413 | int err; | |
414 | ||
415 | /* single page (at least 4096 bytes) must suffice for both ringbuffes */ | |
416 | err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
417 | PAGE_SIZE, &chip->rb); | |
418 | if (err < 0) { | |
419 | snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n"); | |
420 | return err; | |
421 | } | |
422 | return 0; | |
423 | } | |
424 | ||
425 | static void azx_init_cmd_io(struct azx *chip) | |
426 | { | |
427 | /* CORB set up */ | |
428 | chip->corb.addr = chip->rb.addr; | |
429 | chip->corb.buf = (u32 *)chip->rb.area; | |
430 | azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); | |
431 | azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr)); | |
432 | ||
433 | /* set the corb size to 256 entries (ULI requires explicitly) */ | |
434 | azx_writeb(chip, CORBSIZE, 0x02); | |
435 | /* set the corb write pointer to 0 */ | |
436 | azx_writew(chip, CORBWP, 0); | |
437 | /* reset the corb hw read pointer */ | |
438 | azx_writew(chip, CORBRP, ICH6_RBRWP_CLR); | |
439 | /* enable corb dma */ | |
440 | azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN); | |
441 | ||
442 | /* RIRB set up */ | |
443 | chip->rirb.addr = chip->rb.addr + 2048; | |
444 | chip->rirb.buf = (u32 *)(chip->rb.area + 2048); | |
445 | azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); | |
446 | azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr)); | |
447 | ||
448 | /* set the rirb size to 256 entries (ULI requires explicitly) */ | |
449 | azx_writeb(chip, RIRBSIZE, 0x02); | |
450 | /* reset the rirb hw write pointer */ | |
451 | azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR); | |
452 | /* set N=1, get RIRB response interrupt for new entry */ | |
453 | azx_writew(chip, RINTCNT, 1); | |
454 | /* enable rirb dma and response irq */ | |
455 | azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); | |
456 | chip->rirb.rp = chip->rirb.cmds = 0; | |
457 | } | |
458 | ||
459 | static void azx_free_cmd_io(struct azx *chip) | |
460 | { | |
461 | /* disable ringbuffer DMAs */ | |
462 | azx_writeb(chip, RIRBCTL, 0); | |
463 | azx_writeb(chip, CORBCTL, 0); | |
464 | } | |
465 | ||
466 | /* send a command */ | |
467 | static int azx_corb_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct, | |
468 | unsigned int verb, unsigned int para) | |
469 | { | |
470 | struct azx *chip = codec->bus->private_data; | |
471 | unsigned int wp; | |
472 | u32 val; | |
473 | ||
474 | val = (u32)(codec->addr & 0x0f) << 28; | |
475 | val |= (u32)direct << 27; | |
476 | val |= (u32)nid << 20; | |
477 | val |= verb << 8; | |
478 | val |= para; | |
479 | ||
480 | /* add command to corb */ | |
481 | wp = azx_readb(chip, CORBWP); | |
482 | wp++; | |
483 | wp %= ICH6_MAX_CORB_ENTRIES; | |
484 | ||
485 | spin_lock_irq(&chip->reg_lock); | |
486 | chip->rirb.cmds++; | |
487 | chip->corb.buf[wp] = cpu_to_le32(val); | |
488 | azx_writel(chip, CORBWP, wp); | |
489 | spin_unlock_irq(&chip->reg_lock); | |
490 | ||
491 | return 0; | |
492 | } | |
493 | ||
494 | #define ICH6_RIRB_EX_UNSOL_EV (1<<4) | |
495 | ||
496 | /* retrieve RIRB entry - called from interrupt handler */ | |
497 | static void azx_update_rirb(struct azx *chip) | |
498 | { | |
499 | unsigned int rp, wp; | |
500 | u32 res, res_ex; | |
501 | ||
502 | wp = azx_readb(chip, RIRBWP); | |
503 | if (wp == chip->rirb.wp) | |
504 | return; | |
505 | chip->rirb.wp = wp; | |
506 | ||
507 | while (chip->rirb.rp != wp) { | |
508 | chip->rirb.rp++; | |
509 | chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; | |
510 | ||
511 | rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ | |
512 | res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); | |
513 | res = le32_to_cpu(chip->rirb.buf[rp]); | |
514 | if (res_ex & ICH6_RIRB_EX_UNSOL_EV) | |
515 | snd_hda_queue_unsol_event(chip->bus, res, res_ex); | |
516 | else if (chip->rirb.cmds) { | |
517 | chip->rirb.cmds--; | |
518 | chip->rirb.res = res; | |
519 | } | |
520 | } | |
521 | } | |
522 | ||
523 | /* receive a response */ | |
524 | static unsigned int azx_rirb_get_response(struct hda_codec *codec) | |
525 | { | |
526 | struct azx *chip = codec->bus->private_data; | |
527 | unsigned long timeout; | |
528 | ||
529 | again: | |
530 | timeout = jiffies + msecs_to_jiffies(1000); | |
531 | do { | |
532 | if (chip->polling_mode) { | |
533 | spin_lock_irq(&chip->reg_lock); | |
534 | azx_update_rirb(chip); | |
535 | spin_unlock_irq(&chip->reg_lock); | |
536 | } | |
537 | if (! chip->rirb.cmds) | |
538 | return chip->rirb.res; /* the last value */ | |
539 | schedule_timeout_interruptible(1); | |
540 | } while (time_after_eq(timeout, jiffies)); | |
541 | ||
542 | if (chip->msi) { | |
543 | snd_printk(KERN_WARNING "hda_intel: No response from codec, " | |
544 | "disabling MSI...\n"); | |
545 | free_irq(chip->irq, chip); | |
546 | chip->irq = -1; | |
547 | pci_disable_msi(chip->pci); | |
548 | chip->msi = 0; | |
549 | if (azx_acquire_irq(chip, 1) < 0) | |
550 | return -1; | |
551 | goto again; | |
552 | } | |
553 | ||
554 | if (!chip->polling_mode) { | |
555 | snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, " | |
556 | "switching to polling mode...\n"); | |
557 | chip->polling_mode = 1; | |
558 | goto again; | |
559 | } | |
560 | ||
561 | snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " | |
562 | "switching to single_cmd mode...\n"); | |
563 | chip->rirb.rp = azx_readb(chip, RIRBWP); | |
564 | chip->rirb.cmds = 0; | |
565 | /* switch to single_cmd mode */ | |
566 | chip->single_cmd = 1; | |
567 | azx_free_cmd_io(chip); | |
568 | return -1; | |
569 | } | |
570 | ||
571 | /* | |
572 | * Use the single immediate command instead of CORB/RIRB for simplicity | |
573 | * | |
574 | * Note: according to Intel, this is not preferred use. The command was | |
575 | * intended for the BIOS only, and may get confused with unsolicited | |
576 | * responses. So, we shouldn't use it for normal operation from the | |
577 | * driver. | |
578 | * I left the codes, however, for debugging/testing purposes. | |
579 | */ | |
580 | ||
581 | /* send a command */ | |
582 | static int azx_single_send_cmd(struct hda_codec *codec, hda_nid_t nid, | |
583 | int direct, unsigned int verb, | |
584 | unsigned int para) | |
585 | { | |
586 | struct azx *chip = codec->bus->private_data; | |
587 | u32 val; | |
588 | int timeout = 50; | |
589 | ||
590 | val = (u32)(codec->addr & 0x0f) << 28; | |
591 | val |= (u32)direct << 27; | |
592 | val |= (u32)nid << 20; | |
593 | val |= verb << 8; | |
594 | val |= para; | |
595 | ||
596 | while (timeout--) { | |
597 | /* check ICB busy bit */ | |
598 | if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) { | |
599 | /* Clear IRV valid bit */ | |
600 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID); | |
601 | azx_writel(chip, IC, val); | |
602 | azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY); | |
603 | return 0; | |
604 | } | |
605 | udelay(1); | |
606 | } | |
607 | snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val); | |
608 | return -EIO; | |
609 | } | |
610 | ||
611 | /* receive a response */ | |
612 | static unsigned int azx_single_get_response(struct hda_codec *codec) | |
613 | { | |
614 | struct azx *chip = codec->bus->private_data; | |
615 | int timeout = 50; | |
616 | ||
617 | while (timeout--) { | |
618 | /* check IRV busy bit */ | |
619 | if (azx_readw(chip, IRS) & ICH6_IRS_VALID) | |
620 | return azx_readl(chip, IR); | |
621 | udelay(1); | |
622 | } | |
623 | snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS)); | |
624 | return (unsigned int)-1; | |
625 | } | |
626 | ||
627 | /* | |
628 | * The below are the main callbacks from hda_codec. | |
629 | * | |
630 | * They are just the skeleton to call sub-callbacks according to the | |
631 | * current setting of chip->single_cmd. | |
632 | */ | |
633 | ||
634 | /* send a command */ | |
635 | static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, | |
636 | int direct, unsigned int verb, | |
637 | unsigned int para) | |
638 | { | |
639 | struct azx *chip = codec->bus->private_data; | |
640 | if (chip->single_cmd) | |
641 | return azx_single_send_cmd(codec, nid, direct, verb, para); | |
642 | else | |
643 | return azx_corb_send_cmd(codec, nid, direct, verb, para); | |
644 | } | |
645 | ||
646 | /* get a response */ | |
647 | static unsigned int azx_get_response(struct hda_codec *codec) | |
648 | { | |
649 | struct azx *chip = codec->bus->private_data; | |
650 | if (chip->single_cmd) | |
651 | return azx_single_get_response(codec); | |
652 | else | |
653 | return azx_rirb_get_response(codec); | |
654 | } | |
655 | ||
656 | ||
657 | /* reset codec link */ | |
658 | static int azx_reset(struct azx *chip) | |
659 | { | |
660 | int count; | |
661 | ||
662 | /* reset controller */ | |
663 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); | |
664 | ||
665 | count = 50; | |
666 | while (azx_readb(chip, GCTL) && --count) | |
667 | msleep(1); | |
668 | ||
669 | /* delay for >= 100us for codec PLL to settle per spec | |
670 | * Rev 0.9 section 5.5.1 | |
671 | */ | |
672 | msleep(1); | |
673 | ||
674 | /* Bring controller out of reset */ | |
675 | azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); | |
676 | ||
677 | count = 50; | |
678 | while (!azx_readb(chip, GCTL) && --count) | |
679 | msleep(1); | |
680 | ||
681 | /* Brent Chartrand said to wait >= 540us for codecs to initialize */ | |
682 | msleep(1); | |
683 | ||
684 | /* check to see if controller is ready */ | |
685 | if (!azx_readb(chip, GCTL)) { | |
686 | snd_printd("azx_reset: controller not ready!\n"); | |
687 | return -EBUSY; | |
688 | } | |
689 | ||
690 | /* Accept unsolicited responses */ | |
691 | azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN); | |
692 | ||
693 | /* detect codecs */ | |
694 | if (!chip->codec_mask) { | |
695 | chip->codec_mask = azx_readw(chip, STATESTS); | |
696 | snd_printdd("codec_mask = 0x%x\n", chip->codec_mask); | |
697 | } | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
702 | ||
703 | /* | |
704 | * Lowlevel interface | |
705 | */ | |
706 | ||
707 | /* enable interrupts */ | |
708 | static void azx_int_enable(struct azx *chip) | |
709 | { | |
710 | /* enable controller CIE and GIE */ | |
711 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | | |
712 | ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); | |
713 | } | |
714 | ||
715 | /* disable interrupts */ | |
716 | static void azx_int_disable(struct azx *chip) | |
717 | { | |
718 | int i; | |
719 | ||
720 | /* disable interrupts in stream descriptor */ | |
721 | for (i = 0; i < chip->num_streams; i++) { | |
722 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | |
723 | azx_sd_writeb(azx_dev, SD_CTL, | |
724 | azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); | |
725 | } | |
726 | ||
727 | /* disable SIE for all streams */ | |
728 | azx_writeb(chip, INTCTL, 0); | |
729 | ||
730 | /* disable controller CIE and GIE */ | |
731 | azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & | |
732 | ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); | |
733 | } | |
734 | ||
735 | /* clear interrupts */ | |
736 | static void azx_int_clear(struct azx *chip) | |
737 | { | |
738 | int i; | |
739 | ||
740 | /* clear stream status */ | |
741 | for (i = 0; i < chip->num_streams; i++) { | |
742 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | |
743 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
744 | } | |
745 | ||
746 | /* clear STATESTS */ | |
747 | azx_writeb(chip, STATESTS, STATESTS_INT_MASK); | |
748 | ||
749 | /* clear rirb status */ | |
750 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
751 | ||
752 | /* clear int status */ | |
753 | azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); | |
754 | } | |
755 | ||
756 | /* start a stream */ | |
757 | static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) | |
758 | { | |
759 | /* enable SIE */ | |
760 | azx_writeb(chip, INTCTL, | |
761 | azx_readb(chip, INTCTL) | (1 << azx_dev->index)); | |
762 | /* set DMA start and interrupt mask */ | |
763 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | | |
764 | SD_CTL_DMA_START | SD_INT_MASK); | |
765 | } | |
766 | ||
767 | /* stop a stream */ | |
768 | static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) | |
769 | { | |
770 | /* stop DMA */ | |
771 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & | |
772 | ~(SD_CTL_DMA_START | SD_INT_MASK)); | |
773 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ | |
774 | /* disable SIE */ | |
775 | azx_writeb(chip, INTCTL, | |
776 | azx_readb(chip, INTCTL) & ~(1 << azx_dev->index)); | |
777 | } | |
778 | ||
779 | ||
780 | /* | |
781 | * initialize the chip | |
782 | */ | |
783 | static void azx_init_chip(struct azx *chip) | |
784 | { | |
785 | unsigned char reg; | |
786 | ||
787 | /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) | |
788 | * TCSEL == Traffic Class Select Register, which sets PCI express QOS | |
789 | * Ensuring these bits are 0 clears playback static on some HD Audio codecs | |
790 | */ | |
791 | pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, ®); | |
792 | pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8); | |
793 | ||
794 | /* reset controller */ | |
795 | azx_reset(chip); | |
796 | ||
797 | /* initialize interrupts */ | |
798 | azx_int_clear(chip); | |
799 | azx_int_enable(chip); | |
800 | ||
801 | /* initialize the codec command I/O */ | |
802 | if (!chip->single_cmd) | |
803 | azx_init_cmd_io(chip); | |
804 | ||
805 | /* program the position buffer */ | |
806 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); | |
807 | azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr)); | |
808 | ||
809 | switch (chip->driver_type) { | |
810 | case AZX_DRIVER_ATI: | |
811 | /* For ATI SB450 azalia HD audio, we need to enable snoop */ | |
812 | pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, | |
813 | ®); | |
814 | pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, | |
815 | (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP); | |
816 | break; | |
817 | case AZX_DRIVER_NVIDIA: | |
818 | /* For NVIDIA HDA, enable snoop */ | |
819 | pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, ®); | |
820 | pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, | |
821 | (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS); | |
822 | break; | |
823 | } | |
824 | } | |
825 | ||
826 | ||
827 | /* | |
828 | * interrupt handler | |
829 | */ | |
830 | static irqreturn_t azx_interrupt(int irq, void *dev_id) | |
831 | { | |
832 | struct azx *chip = dev_id; | |
833 | struct azx_dev *azx_dev; | |
834 | u32 status; | |
835 | int i; | |
836 | ||
837 | spin_lock(&chip->reg_lock); | |
838 | ||
839 | status = azx_readl(chip, INTSTS); | |
840 | if (status == 0) { | |
841 | spin_unlock(&chip->reg_lock); | |
842 | return IRQ_NONE; | |
843 | } | |
844 | ||
845 | for (i = 0; i < chip->num_streams; i++) { | |
846 | azx_dev = &chip->azx_dev[i]; | |
847 | if (status & azx_dev->sd_int_sta_mask) { | |
848 | azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); | |
849 | if (azx_dev->substream && azx_dev->running) { | |
850 | azx_dev->period_intr++; | |
851 | spin_unlock(&chip->reg_lock); | |
852 | snd_pcm_period_elapsed(azx_dev->substream); | |
853 | spin_lock(&chip->reg_lock); | |
854 | } | |
855 | } | |
856 | } | |
857 | ||
858 | /* clear rirb int */ | |
859 | status = azx_readb(chip, RIRBSTS); | |
860 | if (status & RIRB_INT_MASK) { | |
861 | if (! chip->single_cmd && (status & RIRB_INT_RESPONSE)) | |
862 | azx_update_rirb(chip); | |
863 | azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); | |
864 | } | |
865 | ||
866 | #if 0 | |
867 | /* clear state status int */ | |
868 | if (azx_readb(chip, STATESTS) & 0x04) | |
869 | azx_writeb(chip, STATESTS, 0x04); | |
870 | #endif | |
871 | spin_unlock(&chip->reg_lock); | |
872 | ||
873 | return IRQ_HANDLED; | |
874 | } | |
875 | ||
876 | ||
877 | /* | |
878 | * set up BDL entries | |
879 | */ | |
880 | static void azx_setup_periods(struct azx_dev *azx_dev) | |
881 | { | |
882 | u32 *bdl = azx_dev->bdl; | |
883 | dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr; | |
884 | int idx; | |
885 | ||
886 | /* reset BDL address */ | |
887 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
888 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
889 | ||
890 | /* program the initial BDL entries */ | |
891 | for (idx = 0; idx < azx_dev->frags; idx++) { | |
892 | unsigned int off = idx << 2; /* 4 dword step */ | |
893 | dma_addr_t addr = dma_addr + idx * azx_dev->fragsize; | |
894 | /* program the address field of the BDL entry */ | |
895 | bdl[off] = cpu_to_le32((u32)addr); | |
896 | bdl[off+1] = cpu_to_le32(upper_32bit(addr)); | |
897 | ||
898 | /* program the size field of the BDL entry */ | |
899 | bdl[off+2] = cpu_to_le32(azx_dev->fragsize); | |
900 | ||
901 | /* program the IOC to enable interrupt when buffer completes */ | |
902 | bdl[off+3] = cpu_to_le32(0x01); | |
903 | } | |
904 | } | |
905 | ||
906 | /* | |
907 | * set up the SD for streaming | |
908 | */ | |
909 | static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) | |
910 | { | |
911 | unsigned char val; | |
912 | int timeout; | |
913 | ||
914 | /* make sure the run bit is zero for SD */ | |
915 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START); | |
916 | /* reset stream */ | |
917 | azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET); | |
918 | udelay(3); | |
919 | timeout = 300; | |
920 | while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
921 | --timeout) | |
922 | ; | |
923 | val &= ~SD_CTL_STREAM_RESET; | |
924 | azx_sd_writeb(azx_dev, SD_CTL, val); | |
925 | udelay(3); | |
926 | ||
927 | timeout = 300; | |
928 | /* waiting for hardware to report that the stream is out of reset */ | |
929 | while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && | |
930 | --timeout) | |
931 | ; | |
932 | ||
933 | /* program the stream_tag */ | |
934 | azx_sd_writel(azx_dev, SD_CTL, | |
935 | (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) | | |
936 | (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT)); | |
937 | ||
938 | /* program the length of samples in cyclic buffer */ | |
939 | azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); | |
940 | ||
941 | /* program the stream format */ | |
942 | /* this value needs to be the same as the one programmed */ | |
943 | azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); | |
944 | ||
945 | /* program the stream LVI (last valid index) of the BDL */ | |
946 | azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); | |
947 | ||
948 | /* program the BDL address */ | |
949 | /* lower BDL address */ | |
950 | azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr); | |
951 | /* upper BDL address */ | |
952 | azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr)); | |
953 | ||
954 | /* enable the position buffer */ | |
955 | if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) | |
956 | azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); | |
957 | ||
958 | /* set the interrupt enable bits in the descriptor control register */ | |
959 | azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
964 | ||
965 | /* | |
966 | * Codec initialization | |
967 | */ | |
968 | ||
969 | static int __devinit azx_codec_create(struct azx *chip, const char *model) | |
970 | { | |
971 | struct hda_bus_template bus_temp; | |
972 | int c, codecs, err; | |
973 | ||
974 | memset(&bus_temp, 0, sizeof(bus_temp)); | |
975 | bus_temp.private_data = chip; | |
976 | bus_temp.modelname = model; | |
977 | bus_temp.pci = chip->pci; | |
978 | bus_temp.ops.command = azx_send_cmd; | |
979 | bus_temp.ops.get_response = azx_get_response; | |
980 | ||
981 | if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0) | |
982 | return err; | |
983 | ||
984 | codecs = 0; | |
985 | for (c = 0; c < AZX_MAX_CODECS; c++) { | |
986 | if ((chip->codec_mask & (1 << c)) & probe_mask) { | |
987 | err = snd_hda_codec_new(chip->bus, c, NULL); | |
988 | if (err < 0) | |
989 | continue; | |
990 | codecs++; | |
991 | } | |
992 | } | |
993 | if (! codecs) { | |
994 | snd_printk(KERN_ERR SFX "no codecs initialized\n"); | |
995 | return -ENXIO; | |
996 | } | |
997 | ||
998 | return 0; | |
999 | } | |
1000 | ||
1001 | ||
1002 | /* | |
1003 | * PCM support | |
1004 | */ | |
1005 | ||
1006 | /* assign a stream for the PCM */ | |
1007 | static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream) | |
1008 | { | |
1009 | int dev, i, nums; | |
1010 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
1011 | dev = chip->playback_index_offset; | |
1012 | nums = chip->playback_streams; | |
1013 | } else { | |
1014 | dev = chip->capture_index_offset; | |
1015 | nums = chip->capture_streams; | |
1016 | } | |
1017 | for (i = 0; i < nums; i++, dev++) | |
1018 | if (! chip->azx_dev[dev].opened) { | |
1019 | chip->azx_dev[dev].opened = 1; | |
1020 | return &chip->azx_dev[dev]; | |
1021 | } | |
1022 | return NULL; | |
1023 | } | |
1024 | ||
1025 | /* release the assigned stream */ | |
1026 | static inline void azx_release_device(struct azx_dev *azx_dev) | |
1027 | { | |
1028 | azx_dev->opened = 0; | |
1029 | } | |
1030 | ||
1031 | static struct snd_pcm_hardware azx_pcm_hw = { | |
1032 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
1033 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
1034 | SNDRV_PCM_INFO_MMAP_VALID | | |
1035 | /* No full-resume yet implemented */ | |
1036 | /* SNDRV_PCM_INFO_RESUME |*/ | |
1037 | SNDRV_PCM_INFO_PAUSE), | |
1038 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
1039 | .rates = SNDRV_PCM_RATE_48000, | |
1040 | .rate_min = 48000, | |
1041 | .rate_max = 48000, | |
1042 | .channels_min = 2, | |
1043 | .channels_max = 2, | |
1044 | .buffer_bytes_max = AZX_MAX_BUF_SIZE, | |
1045 | .period_bytes_min = 128, | |
1046 | .period_bytes_max = AZX_MAX_BUF_SIZE / 2, | |
1047 | .periods_min = 2, | |
1048 | .periods_max = AZX_MAX_FRAG, | |
1049 | .fifo_size = 0, | |
1050 | }; | |
1051 | ||
1052 | struct azx_pcm { | |
1053 | struct azx *chip; | |
1054 | struct hda_codec *codec; | |
1055 | struct hda_pcm_stream *hinfo[2]; | |
1056 | }; | |
1057 | ||
1058 | static int azx_pcm_open(struct snd_pcm_substream *substream) | |
1059 | { | |
1060 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1061 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
1062 | struct azx *chip = apcm->chip; | |
1063 | struct azx_dev *azx_dev; | |
1064 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1065 | unsigned long flags; | |
1066 | int err; | |
1067 | ||
1068 | mutex_lock(&chip->open_mutex); | |
1069 | azx_dev = azx_assign_device(chip, substream->stream); | |
1070 | if (azx_dev == NULL) { | |
1071 | mutex_unlock(&chip->open_mutex); | |
1072 | return -EBUSY; | |
1073 | } | |
1074 | runtime->hw = azx_pcm_hw; | |
1075 | runtime->hw.channels_min = hinfo->channels_min; | |
1076 | runtime->hw.channels_max = hinfo->channels_max; | |
1077 | runtime->hw.formats = hinfo->formats; | |
1078 | runtime->hw.rates = hinfo->rates; | |
1079 | snd_pcm_limit_hw_rates(runtime); | |
1080 | snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); | |
1081 | if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) { | |
1082 | azx_release_device(azx_dev); | |
1083 | mutex_unlock(&chip->open_mutex); | |
1084 | return err; | |
1085 | } | |
1086 | spin_lock_irqsave(&chip->reg_lock, flags); | |
1087 | azx_dev->substream = substream; | |
1088 | azx_dev->running = 0; | |
1089 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1090 | ||
1091 | runtime->private_data = azx_dev; | |
1092 | mutex_unlock(&chip->open_mutex); | |
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | static int azx_pcm_close(struct snd_pcm_substream *substream) | |
1097 | { | |
1098 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1099 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
1100 | struct azx *chip = apcm->chip; | |
1101 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1102 | unsigned long flags; | |
1103 | ||
1104 | mutex_lock(&chip->open_mutex); | |
1105 | spin_lock_irqsave(&chip->reg_lock, flags); | |
1106 | azx_dev->substream = NULL; | |
1107 | azx_dev->running = 0; | |
1108 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
1109 | azx_release_device(azx_dev); | |
1110 | hinfo->ops.close(hinfo, apcm->codec, substream); | |
1111 | mutex_unlock(&chip->open_mutex); | |
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params) | |
1116 | { | |
1117 | return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); | |
1118 | } | |
1119 | ||
1120 | static int azx_pcm_hw_free(struct snd_pcm_substream *substream) | |
1121 | { | |
1122 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1123 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1124 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
1125 | ||
1126 | /* reset BDL address */ | |
1127 | azx_sd_writel(azx_dev, SD_BDLPL, 0); | |
1128 | azx_sd_writel(azx_dev, SD_BDLPU, 0); | |
1129 | azx_sd_writel(azx_dev, SD_CTL, 0); | |
1130 | ||
1131 | hinfo->ops.cleanup(hinfo, apcm->codec, substream); | |
1132 | ||
1133 | return snd_pcm_lib_free_pages(substream); | |
1134 | } | |
1135 | ||
1136 | static int azx_pcm_prepare(struct snd_pcm_substream *substream) | |
1137 | { | |
1138 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1139 | struct azx *chip = apcm->chip; | |
1140 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1141 | struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; | |
1142 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1143 | ||
1144 | azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream); | |
1145 | azx_dev->fragsize = snd_pcm_lib_period_bytes(substream); | |
1146 | azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize; | |
1147 | azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate, | |
1148 | runtime->channels, | |
1149 | runtime->format, | |
1150 | hinfo->maxbps); | |
1151 | if (! azx_dev->format_val) { | |
1152 | snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n", | |
1153 | runtime->rate, runtime->channels, runtime->format); | |
1154 | return -EINVAL; | |
1155 | } | |
1156 | ||
1157 | snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n", | |
1158 | azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val); | |
1159 | azx_setup_periods(azx_dev); | |
1160 | azx_setup_controller(chip, azx_dev); | |
1161 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1162 | azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; | |
1163 | else | |
1164 | azx_dev->fifo_size = 0; | |
1165 | ||
1166 | return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag, | |
1167 | azx_dev->format_val, substream); | |
1168 | } | |
1169 | ||
1170 | static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) | |
1171 | { | |
1172 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1173 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1174 | struct azx *chip = apcm->chip; | |
1175 | int err = 0; | |
1176 | ||
1177 | spin_lock(&chip->reg_lock); | |
1178 | switch (cmd) { | |
1179 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
1180 | case SNDRV_PCM_TRIGGER_RESUME: | |
1181 | case SNDRV_PCM_TRIGGER_START: | |
1182 | azx_stream_start(chip, azx_dev); | |
1183 | azx_dev->running = 1; | |
1184 | break; | |
1185 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
1186 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
1187 | case SNDRV_PCM_TRIGGER_STOP: | |
1188 | azx_stream_stop(chip, azx_dev); | |
1189 | azx_dev->running = 0; | |
1190 | break; | |
1191 | default: | |
1192 | err = -EINVAL; | |
1193 | } | |
1194 | spin_unlock(&chip->reg_lock); | |
1195 | if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH || | |
1196 | cmd == SNDRV_PCM_TRIGGER_SUSPEND || | |
1197 | cmd == SNDRV_PCM_TRIGGER_STOP) { | |
1198 | int timeout = 5000; | |
1199 | while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout) | |
1200 | ; | |
1201 | } | |
1202 | return err; | |
1203 | } | |
1204 | ||
1205 | static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) | |
1206 | { | |
1207 | struct azx_pcm *apcm = snd_pcm_substream_chip(substream); | |
1208 | struct azx *chip = apcm->chip; | |
1209 | struct azx_dev *azx_dev = get_azx_dev(substream); | |
1210 | unsigned int pos; | |
1211 | ||
1212 | if (chip->position_fix == POS_FIX_POSBUF || | |
1213 | chip->position_fix == POS_FIX_AUTO) { | |
1214 | /* use the position buffer */ | |
1215 | pos = le32_to_cpu(*azx_dev->posbuf); | |
1216 | if (chip->position_fix == POS_FIX_AUTO && | |
1217 | azx_dev->period_intr == 1 && ! pos) { | |
1218 | printk(KERN_WARNING | |
1219 | "hda-intel: Invalid position buffer, " | |
1220 | "using LPIB read method instead.\n"); | |
1221 | chip->position_fix = POS_FIX_NONE; | |
1222 | goto read_lpib; | |
1223 | } | |
1224 | } else { | |
1225 | read_lpib: | |
1226 | /* read LPIB */ | |
1227 | pos = azx_sd_readl(azx_dev, SD_LPIB); | |
1228 | if (chip->position_fix == POS_FIX_FIFO) | |
1229 | pos += azx_dev->fifo_size; | |
1230 | } | |
1231 | if (pos >= azx_dev->bufsize) | |
1232 | pos = 0; | |
1233 | return bytes_to_frames(substream->runtime, pos); | |
1234 | } | |
1235 | ||
1236 | static struct snd_pcm_ops azx_pcm_ops = { | |
1237 | .open = azx_pcm_open, | |
1238 | .close = azx_pcm_close, | |
1239 | .ioctl = snd_pcm_lib_ioctl, | |
1240 | .hw_params = azx_pcm_hw_params, | |
1241 | .hw_free = azx_pcm_hw_free, | |
1242 | .prepare = azx_pcm_prepare, | |
1243 | .trigger = azx_pcm_trigger, | |
1244 | .pointer = azx_pcm_pointer, | |
1245 | }; | |
1246 | ||
1247 | static void azx_pcm_free(struct snd_pcm *pcm) | |
1248 | { | |
1249 | kfree(pcm->private_data); | |
1250 | } | |
1251 | ||
1252 | static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec, | |
1253 | struct hda_pcm *cpcm, int pcm_dev) | |
1254 | { | |
1255 | int err; | |
1256 | struct snd_pcm *pcm; | |
1257 | struct azx_pcm *apcm; | |
1258 | ||
1259 | /* if no substreams are defined for both playback and capture, | |
1260 | * it's just a placeholder. ignore it. | |
1261 | */ | |
1262 | if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams) | |
1263 | return 0; | |
1264 | ||
1265 | snd_assert(cpcm->name, return -EINVAL); | |
1266 | ||
1267 | err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, | |
1268 | cpcm->stream[0].substreams, cpcm->stream[1].substreams, | |
1269 | &pcm); | |
1270 | if (err < 0) | |
1271 | return err; | |
1272 | strcpy(pcm->name, cpcm->name); | |
1273 | apcm = kmalloc(sizeof(*apcm), GFP_KERNEL); | |
1274 | if (apcm == NULL) | |
1275 | return -ENOMEM; | |
1276 | apcm->chip = chip; | |
1277 | apcm->codec = codec; | |
1278 | apcm->hinfo[0] = &cpcm->stream[0]; | |
1279 | apcm->hinfo[1] = &cpcm->stream[1]; | |
1280 | pcm->private_data = apcm; | |
1281 | pcm->private_free = azx_pcm_free; | |
1282 | if (cpcm->stream[0].substreams) | |
1283 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops); | |
1284 | if (cpcm->stream[1].substreams) | |
1285 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops); | |
1286 | snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, | |
1287 | snd_dma_pci_data(chip->pci), | |
1288 | 1024 * 64, 1024 * 128); | |
1289 | chip->pcm[pcm_dev] = pcm; | |
1290 | if (chip->pcm_devs < pcm_dev + 1) | |
1291 | chip->pcm_devs = pcm_dev + 1; | |
1292 | ||
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | static int __devinit azx_pcm_create(struct azx *chip) | |
1297 | { | |
1298 | struct list_head *p; | |
1299 | struct hda_codec *codec; | |
1300 | int c, err; | |
1301 | int pcm_dev; | |
1302 | ||
1303 | if ((err = snd_hda_build_pcms(chip->bus)) < 0) | |
1304 | return err; | |
1305 | ||
1306 | /* create audio PCMs */ | |
1307 | pcm_dev = 0; | |
1308 | list_for_each(p, &chip->bus->codec_list) { | |
1309 | codec = list_entry(p, struct hda_codec, list); | |
1310 | for (c = 0; c < codec->num_pcms; c++) { | |
1311 | if (codec->pcm_info[c].is_modem) | |
1312 | continue; /* create later */ | |
1313 | if (pcm_dev >= AZX_MAX_AUDIO_PCMS) { | |
1314 | snd_printk(KERN_ERR SFX "Too many audio PCMs\n"); | |
1315 | return -EINVAL; | |
1316 | } | |
1317 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); | |
1318 | if (err < 0) | |
1319 | return err; | |
1320 | pcm_dev++; | |
1321 | } | |
1322 | } | |
1323 | ||
1324 | /* create modem PCMs */ | |
1325 | pcm_dev = AZX_MAX_AUDIO_PCMS; | |
1326 | list_for_each(p, &chip->bus->codec_list) { | |
1327 | codec = list_entry(p, struct hda_codec, list); | |
1328 | for (c = 0; c < codec->num_pcms; c++) { | |
1329 | if (! codec->pcm_info[c].is_modem) | |
1330 | continue; /* already created */ | |
1331 | if (pcm_dev >= AZX_MAX_PCMS) { | |
1332 | snd_printk(KERN_ERR SFX "Too many modem PCMs\n"); | |
1333 | return -EINVAL; | |
1334 | } | |
1335 | err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev); | |
1336 | if (err < 0) | |
1337 | return err; | |
1338 | chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM; | |
1339 | pcm_dev++; | |
1340 | } | |
1341 | } | |
1342 | return 0; | |
1343 | } | |
1344 | ||
1345 | /* | |
1346 | * mixer creation - all stuff is implemented in hda module | |
1347 | */ | |
1348 | static int __devinit azx_mixer_create(struct azx *chip) | |
1349 | { | |
1350 | return snd_hda_build_controls(chip->bus); | |
1351 | } | |
1352 | ||
1353 | ||
1354 | /* | |
1355 | * initialize SD streams | |
1356 | */ | |
1357 | static int __devinit azx_init_stream(struct azx *chip) | |
1358 | { | |
1359 | int i; | |
1360 | ||
1361 | /* initialize each stream (aka device) | |
1362 | * assign the starting bdl address to each stream (device) and initialize | |
1363 | */ | |
1364 | for (i = 0; i < chip->num_streams; i++) { | |
1365 | unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4); | |
1366 | struct azx_dev *azx_dev = &chip->azx_dev[i]; | |
1367 | azx_dev->bdl = (u32 *)(chip->bdl.area + off); | |
1368 | azx_dev->bdl_addr = chip->bdl.addr + off; | |
1369 | azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); | |
1370 | /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
1371 | azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); | |
1372 | /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ | |
1373 | azx_dev->sd_int_sta_mask = 1 << i; | |
1374 | /* stream tag: must be non-zero and unique */ | |
1375 | azx_dev->index = i; | |
1376 | azx_dev->stream_tag = i + 1; | |
1377 | } | |
1378 | ||
1379 | return 0; | |
1380 | } | |
1381 | ||
1382 | static int azx_acquire_irq(struct azx *chip, int do_disconnect) | |
1383 | { | |
1384 | if (request_irq(chip->pci->irq, azx_interrupt, | |
1385 | chip->msi ? 0 : IRQF_SHARED, | |
1386 | "HDA Intel", chip)) { | |
1387 | printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " | |
1388 | "disabling device\n", chip->pci->irq); | |
1389 | if (do_disconnect) | |
1390 | snd_card_disconnect(chip->card); | |
1391 | return -1; | |
1392 | } | |
1393 | chip->irq = chip->pci->irq; | |
1394 | return 0; | |
1395 | } | |
1396 | ||
1397 | ||
1398 | #ifdef CONFIG_PM | |
1399 | /* | |
1400 | * power management | |
1401 | */ | |
1402 | static int azx_suspend(struct pci_dev *pci, pm_message_t state) | |
1403 | { | |
1404 | struct snd_card *card = pci_get_drvdata(pci); | |
1405 | struct azx *chip = card->private_data; | |
1406 | int i; | |
1407 | ||
1408 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); | |
1409 | for (i = 0; i < chip->pcm_devs; i++) | |
1410 | snd_pcm_suspend_all(chip->pcm[i]); | |
1411 | snd_hda_suspend(chip->bus, state); | |
1412 | azx_free_cmd_io(chip); | |
1413 | if (chip->irq >= 0) { | |
1414 | synchronize_irq(chip->irq); | |
1415 | free_irq(chip->irq, chip); | |
1416 | chip->irq = -1; | |
1417 | } | |
1418 | if (chip->msi) | |
1419 | pci_disable_msi(chip->pci); | |
1420 | pci_disable_device(pci); | |
1421 | pci_save_state(pci); | |
1422 | pci_set_power_state(pci, pci_choose_state(pci, state)); | |
1423 | return 0; | |
1424 | } | |
1425 | ||
1426 | static int azx_resume(struct pci_dev *pci) | |
1427 | { | |
1428 | struct snd_card *card = pci_get_drvdata(pci); | |
1429 | struct azx *chip = card->private_data; | |
1430 | ||
1431 | pci_set_power_state(pci, PCI_D0); | |
1432 | pci_restore_state(pci); | |
1433 | if (pci_enable_device(pci) < 0) { | |
1434 | printk(KERN_ERR "hda-intel: pci_enable_device failed, " | |
1435 | "disabling device\n"); | |
1436 | snd_card_disconnect(card); | |
1437 | return -EIO; | |
1438 | } | |
1439 | pci_set_master(pci); | |
1440 | if (chip->msi) | |
1441 | if (pci_enable_msi(pci) < 0) | |
1442 | chip->msi = 0; | |
1443 | if (azx_acquire_irq(chip, 1) < 0) | |
1444 | return -EIO; | |
1445 | azx_init_chip(chip); | |
1446 | snd_hda_resume(chip->bus); | |
1447 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); | |
1448 | return 0; | |
1449 | } | |
1450 | #endif /* CONFIG_PM */ | |
1451 | ||
1452 | ||
1453 | /* | |
1454 | * destructor | |
1455 | */ | |
1456 | static int azx_free(struct azx *chip) | |
1457 | { | |
1458 | if (chip->initialized) { | |
1459 | int i; | |
1460 | ||
1461 | for (i = 0; i < chip->num_streams; i++) | |
1462 | azx_stream_stop(chip, &chip->azx_dev[i]); | |
1463 | ||
1464 | /* disable interrupts */ | |
1465 | azx_int_disable(chip); | |
1466 | azx_int_clear(chip); | |
1467 | ||
1468 | /* disable CORB/RIRB */ | |
1469 | azx_free_cmd_io(chip); | |
1470 | ||
1471 | /* disable position buffer */ | |
1472 | azx_writel(chip, DPLBASE, 0); | |
1473 | azx_writel(chip, DPUBASE, 0); | |
1474 | } | |
1475 | ||
1476 | if (chip->irq >= 0) { | |
1477 | synchronize_irq(chip->irq); | |
1478 | free_irq(chip->irq, (void*)chip); | |
1479 | } | |
1480 | if (chip->msi) | |
1481 | pci_disable_msi(chip->pci); | |
1482 | if (chip->remap_addr) | |
1483 | iounmap(chip->remap_addr); | |
1484 | ||
1485 | if (chip->bdl.area) | |
1486 | snd_dma_free_pages(&chip->bdl); | |
1487 | if (chip->rb.area) | |
1488 | snd_dma_free_pages(&chip->rb); | |
1489 | if (chip->posbuf.area) | |
1490 | snd_dma_free_pages(&chip->posbuf); | |
1491 | pci_release_regions(chip->pci); | |
1492 | pci_disable_device(chip->pci); | |
1493 | kfree(chip->azx_dev); | |
1494 | kfree(chip); | |
1495 | ||
1496 | return 0; | |
1497 | } | |
1498 | ||
1499 | static int azx_dev_free(struct snd_device *device) | |
1500 | { | |
1501 | return azx_free(device->device_data); | |
1502 | } | |
1503 | ||
1504 | /* | |
1505 | * constructor | |
1506 | */ | |
1507 | static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, | |
1508 | int driver_type, | |
1509 | struct azx **rchip) | |
1510 | { | |
1511 | struct azx *chip; | |
1512 | int err; | |
1513 | static struct snd_device_ops ops = { | |
1514 | .dev_free = azx_dev_free, | |
1515 | }; | |
1516 | ||
1517 | *rchip = NULL; | |
1518 | ||
1519 | err = pci_enable_device(pci); | |
1520 | if (err < 0) | |
1521 | return err; | |
1522 | ||
1523 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); | |
1524 | if (!chip) { | |
1525 | snd_printk(KERN_ERR SFX "cannot allocate chip\n"); | |
1526 | pci_disable_device(pci); | |
1527 | return -ENOMEM; | |
1528 | } | |
1529 | ||
1530 | spin_lock_init(&chip->reg_lock); | |
1531 | mutex_init(&chip->open_mutex); | |
1532 | chip->card = card; | |
1533 | chip->pci = pci; | |
1534 | chip->irq = -1; | |
1535 | chip->driver_type = driver_type; | |
1536 | chip->msi = enable_msi; | |
1537 | ||
1538 | chip->position_fix = position_fix; | |
1539 | chip->single_cmd = single_cmd; | |
1540 | ||
1541 | #if BITS_PER_LONG != 64 | |
1542 | /* Fix up base address on ULI M5461 */ | |
1543 | if (chip->driver_type == AZX_DRIVER_ULI) { | |
1544 | u16 tmp3; | |
1545 | pci_read_config_word(pci, 0x40, &tmp3); | |
1546 | pci_write_config_word(pci, 0x40, tmp3 | 0x10); | |
1547 | pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); | |
1548 | } | |
1549 | #endif | |
1550 | ||
1551 | err = pci_request_regions(pci, "ICH HD audio"); | |
1552 | if (err < 0) { | |
1553 | kfree(chip); | |
1554 | pci_disable_device(pci); | |
1555 | return err; | |
1556 | } | |
1557 | ||
1558 | chip->addr = pci_resource_start(pci, 0); | |
1559 | chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0)); | |
1560 | if (chip->remap_addr == NULL) { | |
1561 | snd_printk(KERN_ERR SFX "ioremap error\n"); | |
1562 | err = -ENXIO; | |
1563 | goto errout; | |
1564 | } | |
1565 | ||
1566 | if (chip->msi) | |
1567 | if (pci_enable_msi(pci) < 0) | |
1568 | chip->msi = 0; | |
1569 | ||
1570 | if (azx_acquire_irq(chip, 0) < 0) { | |
1571 | err = -EBUSY; | |
1572 | goto errout; | |
1573 | } | |
1574 | ||
1575 | pci_set_master(pci); | |
1576 | synchronize_irq(chip->irq); | |
1577 | ||
1578 | switch (chip->driver_type) { | |
1579 | case AZX_DRIVER_ULI: | |
1580 | chip->playback_streams = ULI_NUM_PLAYBACK; | |
1581 | chip->capture_streams = ULI_NUM_CAPTURE; | |
1582 | chip->playback_index_offset = ULI_PLAYBACK_INDEX; | |
1583 | chip->capture_index_offset = ULI_CAPTURE_INDEX; | |
1584 | break; | |
1585 | case AZX_DRIVER_ATIHDMI: | |
1586 | chip->playback_streams = ATIHDMI_NUM_PLAYBACK; | |
1587 | chip->capture_streams = ATIHDMI_NUM_CAPTURE; | |
1588 | chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX; | |
1589 | chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX; | |
1590 | break; | |
1591 | default: | |
1592 | chip->playback_streams = ICH6_NUM_PLAYBACK; | |
1593 | chip->capture_streams = ICH6_NUM_CAPTURE; | |
1594 | chip->playback_index_offset = ICH6_PLAYBACK_INDEX; | |
1595 | chip->capture_index_offset = ICH6_CAPTURE_INDEX; | |
1596 | break; | |
1597 | } | |
1598 | chip->num_streams = chip->playback_streams + chip->capture_streams; | |
1599 | chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL); | |
1600 | if (!chip->azx_dev) { | |
1601 | snd_printk(KERN_ERR "cannot malloc azx_dev\n"); | |
1602 | goto errout; | |
1603 | } | |
1604 | ||
1605 | /* allocate memory for the BDL for each stream */ | |
1606 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
1607 | BDL_SIZE, &chip->bdl)) < 0) { | |
1608 | snd_printk(KERN_ERR SFX "cannot allocate BDL\n"); | |
1609 | goto errout; | |
1610 | } | |
1611 | /* allocate memory for the position buffer */ | |
1612 | if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), | |
1613 | chip->num_streams * 8, &chip->posbuf)) < 0) { | |
1614 | snd_printk(KERN_ERR SFX "cannot allocate posbuf\n"); | |
1615 | goto errout; | |
1616 | } | |
1617 | /* allocate CORB/RIRB */ | |
1618 | if (! chip->single_cmd) | |
1619 | if ((err = azx_alloc_cmd_io(chip)) < 0) | |
1620 | goto errout; | |
1621 | ||
1622 | /* initialize streams */ | |
1623 | azx_init_stream(chip); | |
1624 | ||
1625 | /* initialize chip */ | |
1626 | azx_init_chip(chip); | |
1627 | ||
1628 | chip->initialized = 1; | |
1629 | ||
1630 | /* codec detection */ | |
1631 | if (!chip->codec_mask) { | |
1632 | snd_printk(KERN_ERR SFX "no codecs found!\n"); | |
1633 | err = -ENODEV; | |
1634 | goto errout; | |
1635 | } | |
1636 | ||
1637 | if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) { | |
1638 | snd_printk(KERN_ERR SFX "Error creating device [card]!\n"); | |
1639 | goto errout; | |
1640 | } | |
1641 | ||
1642 | strcpy(card->driver, "HDA-Intel"); | |
1643 | strcpy(card->shortname, driver_short_names[chip->driver_type]); | |
1644 | sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq); | |
1645 | ||
1646 | *rchip = chip; | |
1647 | return 0; | |
1648 | ||
1649 | errout: | |
1650 | azx_free(chip); | |
1651 | return err; | |
1652 | } | |
1653 | ||
1654 | static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) | |
1655 | { | |
1656 | struct snd_card *card; | |
1657 | struct azx *chip; | |
1658 | int err; | |
1659 | ||
1660 | card = snd_card_new(index, id, THIS_MODULE, 0); | |
1661 | if (!card) { | |
1662 | snd_printk(KERN_ERR SFX "Error creating card!\n"); | |
1663 | return -ENOMEM; | |
1664 | } | |
1665 | ||
1666 | err = azx_create(card, pci, pci_id->driver_data, &chip); | |
1667 | if (err < 0) { | |
1668 | snd_card_free(card); | |
1669 | return err; | |
1670 | } | |
1671 | card->private_data = chip; | |
1672 | ||
1673 | /* create codec instances */ | |
1674 | if ((err = azx_codec_create(chip, model)) < 0) { | |
1675 | snd_card_free(card); | |
1676 | return err; | |
1677 | } | |
1678 | ||
1679 | /* create PCM streams */ | |
1680 | if ((err = azx_pcm_create(chip)) < 0) { | |
1681 | snd_card_free(card); | |
1682 | return err; | |
1683 | } | |
1684 | ||
1685 | /* create mixer controls */ | |
1686 | if ((err = azx_mixer_create(chip)) < 0) { | |
1687 | snd_card_free(card); | |
1688 | return err; | |
1689 | } | |
1690 | ||
1691 | snd_card_set_dev(card, &pci->dev); | |
1692 | ||
1693 | if ((err = snd_card_register(card)) < 0) { | |
1694 | snd_card_free(card); | |
1695 | return err; | |
1696 | } | |
1697 | ||
1698 | pci_set_drvdata(pci, card); | |
1699 | ||
1700 | return err; | |
1701 | } | |
1702 | ||
1703 | static void __devexit azx_remove(struct pci_dev *pci) | |
1704 | { | |
1705 | snd_card_free(pci_get_drvdata(pci)); | |
1706 | pci_set_drvdata(pci, NULL); | |
1707 | } | |
1708 | ||
1709 | /* PCI IDs */ | |
1710 | static struct pci_device_id azx_ids[] = { | |
1711 | { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */ | |
1712 | { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */ | |
1713 | { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */ | |
1714 | { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */ | |
1715 | { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */ | |
1716 | { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */ | |
1717 | { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */ | |
1718 | { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */ | |
1719 | { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */ | |
1720 | { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */ | |
1721 | { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */ | |
1722 | { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */ | |
1723 | { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */ | |
1724 | { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */ | |
1725 | { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */ | |
1726 | { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */ | |
1727 | { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */ | |
1728 | { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */ | |
1729 | { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */ | |
1730 | { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */ | |
1731 | { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */ | |
1732 | { 0, } | |
1733 | }; | |
1734 | MODULE_DEVICE_TABLE(pci, azx_ids); | |
1735 | ||
1736 | /* pci_driver definition */ | |
1737 | static struct pci_driver driver = { | |
1738 | .name = "HDA Intel", | |
1739 | .id_table = azx_ids, | |
1740 | .probe = azx_probe, | |
1741 | .remove = __devexit_p(azx_remove), | |
1742 | #ifdef CONFIG_PM | |
1743 | .suspend = azx_suspend, | |
1744 | .resume = azx_resume, | |
1745 | #endif | |
1746 | }; | |
1747 | ||
1748 | static int __init alsa_card_azx_init(void) | |
1749 | { | |
1750 | return pci_register_driver(&driver); | |
1751 | } | |
1752 | ||
1753 | static void __exit alsa_card_azx_exit(void) | |
1754 | { | |
1755 | pci_unregister_driver(&driver); | |
1756 | } | |
1757 | ||
1758 | module_init(alsa_card_azx_init) | |
1759 | module_exit(alsa_card_azx_exit) |