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1 | /* | |
2 | * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port | |
3 | * | |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * | |
6 | * Contact: Jarkko Nikula <jarkko.nikula@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/device.h> | |
27 | #include <sound/core.h> | |
28 | #include <sound/pcm.h> | |
29 | #include <sound/pcm_params.h> | |
30 | #include <sound/initval.h> | |
31 | #include <sound/soc.h> | |
32 | ||
33 | #include <mach/control.h> | |
34 | #include <mach/dma.h> | |
35 | #include <mach/mcbsp.h> | |
36 | #include "omap-mcbsp.h" | |
37 | #include "omap-pcm.h" | |
38 | ||
39 | #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000) | |
40 | ||
41 | struct omap_mcbsp_data { | |
42 | unsigned int bus_id; | |
43 | struct omap_mcbsp_reg_cfg regs; | |
44 | unsigned int fmt; | |
45 | /* | |
46 | * Flags indicating is the bus already activated and configured by | |
47 | * another substream | |
48 | */ | |
49 | int active; | |
50 | int configured; | |
51 | }; | |
52 | ||
53 | #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id) | |
54 | ||
55 | static struct omap_mcbsp_data mcbsp_data[NUM_LINKS]; | |
56 | ||
57 | /* | |
58 | * Stream DMA parameters. DMA request line and port address are set runtime | |
59 | * since they are different between OMAP1 and later OMAPs | |
60 | */ | |
61 | static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2]; | |
62 | ||
63 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) | |
64 | static const int omap1_dma_reqs[][2] = { | |
65 | { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX }, | |
66 | { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX }, | |
67 | { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX }, | |
68 | }; | |
69 | static const unsigned long omap1_mcbsp_port[][2] = { | |
70 | { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, | |
71 | OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, | |
72 | { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, | |
73 | OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, | |
74 | { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1, | |
75 | OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 }, | |
76 | }; | |
77 | #else | |
78 | static const int omap1_dma_reqs[][2] = {}; | |
79 | static const unsigned long omap1_mcbsp_port[][2] = {}; | |
80 | #endif | |
81 | ||
82 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | |
83 | static const int omap24xx_dma_reqs[][2] = { | |
84 | { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, | |
85 | { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, | |
86 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX) | |
87 | { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX }, | |
88 | { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX }, | |
89 | { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX }, | |
90 | #endif | |
91 | }; | |
92 | #else | |
93 | static const int omap24xx_dma_reqs[][2] = {}; | |
94 | #endif | |
95 | ||
96 | #if defined(CONFIG_ARCH_OMAP2420) | |
97 | static const unsigned long omap2420_mcbsp_port[][2] = { | |
98 | { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, | |
99 | OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, | |
100 | { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, | |
101 | OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, | |
102 | }; | |
103 | #else | |
104 | static const unsigned long omap2420_mcbsp_port[][2] = {}; | |
105 | #endif | |
106 | ||
107 | #if defined(CONFIG_ARCH_OMAP2430) | |
108 | static const unsigned long omap2430_mcbsp_port[][2] = { | |
109 | { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, | |
110 | OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, | |
111 | { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, | |
112 | OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, | |
113 | { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, | |
114 | OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, | |
115 | { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, | |
116 | OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, | |
117 | { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, | |
118 | OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, | |
119 | }; | |
120 | #else | |
121 | static const unsigned long omap2430_mcbsp_port[][2] = {}; | |
122 | #endif | |
123 | ||
124 | #if defined(CONFIG_ARCH_OMAP34XX) | |
125 | static const unsigned long omap34xx_mcbsp_port[][2] = { | |
126 | { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, | |
127 | OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, | |
128 | { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, | |
129 | OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, | |
130 | { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, | |
131 | OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, | |
132 | { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, | |
133 | OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, | |
134 | { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, | |
135 | OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, | |
136 | }; | |
137 | #else | |
138 | static const unsigned long omap34xx_mcbsp_port[][2] = {}; | |
139 | #endif | |
140 | ||
141 | static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream, | |
142 | struct snd_soc_dai *dai) | |
143 | { | |
144 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
145 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
146 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
147 | int err = 0; | |
148 | ||
149 | if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) { | |
150 | /* | |
151 | * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer. | |
152 | * Set constraint for minimum buffer size to the same than FIFO | |
153 | * size in order to avoid underruns in playback startup because | |
154 | * HW is keeping the DMA request active until FIFO is filled. | |
155 | */ | |
156 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
157 | SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX); | |
158 | } | |
159 | ||
160 | if (!cpu_dai->active) | |
161 | err = omap_mcbsp_request(mcbsp_data->bus_id); | |
162 | ||
163 | return err; | |
164 | } | |
165 | ||
166 | static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream, | |
167 | struct snd_soc_dai *dai) | |
168 | { | |
169 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
170 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
171 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
172 | ||
173 | if (!cpu_dai->active) { | |
174 | omap_mcbsp_free(mcbsp_data->bus_id); | |
175 | mcbsp_data->configured = 0; | |
176 | } | |
177 | } | |
178 | ||
179 | static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd, | |
180 | struct snd_soc_dai *dai) | |
181 | { | |
182 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
183 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
184 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
185 | int err = 0; | |
186 | ||
187 | switch (cmd) { | |
188 | case SNDRV_PCM_TRIGGER_START: | |
189 | case SNDRV_PCM_TRIGGER_RESUME: | |
190 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
191 | if (!mcbsp_data->active++) | |
192 | omap_mcbsp_start(mcbsp_data->bus_id); | |
193 | break; | |
194 | ||
195 | case SNDRV_PCM_TRIGGER_STOP: | |
196 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
197 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
198 | if (!--mcbsp_data->active) | |
199 | omap_mcbsp_stop(mcbsp_data->bus_id); | |
200 | break; | |
201 | default: | |
202 | err = -EINVAL; | |
203 | } | |
204 | ||
205 | return err; | |
206 | } | |
207 | ||
208 | static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream, | |
209 | struct snd_pcm_hw_params *params, | |
210 | struct snd_soc_dai *dai) | |
211 | { | |
212 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
213 | struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; | |
214 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
215 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; | |
216 | int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id; | |
217 | int wlen, channels; | |
218 | unsigned long port; | |
219 | ||
220 | if (cpu_class_is_omap1()) { | |
221 | dma = omap1_dma_reqs[bus_id][substream->stream]; | |
222 | port = omap1_mcbsp_port[bus_id][substream->stream]; | |
223 | } else if (cpu_is_omap2420()) { | |
224 | dma = omap24xx_dma_reqs[bus_id][substream->stream]; | |
225 | port = omap2420_mcbsp_port[bus_id][substream->stream]; | |
226 | } else if (cpu_is_omap2430()) { | |
227 | dma = omap24xx_dma_reqs[bus_id][substream->stream]; | |
228 | port = omap2430_mcbsp_port[bus_id][substream->stream]; | |
229 | } else if (cpu_is_omap343x()) { | |
230 | dma = omap24xx_dma_reqs[bus_id][substream->stream]; | |
231 | port = omap34xx_mcbsp_port[bus_id][substream->stream]; | |
232 | } else { | |
233 | return -ENODEV; | |
234 | } | |
235 | omap_mcbsp_dai_dma_params[id][substream->stream].name = | |
236 | substream->stream ? "Audio Capture" : "Audio Playback"; | |
237 | omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma; | |
238 | omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port; | |
239 | cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream]; | |
240 | ||
241 | if (mcbsp_data->configured) { | |
242 | /* McBSP already configured by another stream */ | |
243 | return 0; | |
244 | } | |
245 | ||
246 | channels = params_channels(params); | |
247 | switch (channels) { | |
248 | case 2: | |
249 | /* Use dual-phase frames */ | |
250 | regs->rcr2 |= RPHASE; | |
251 | regs->xcr2 |= XPHASE; | |
252 | case 1: | |
253 | /* Set 1 word per (McBSP) frame */ | |
254 | regs->rcr2 |= RFRLEN2(1 - 1); | |
255 | regs->rcr1 |= RFRLEN1(1 - 1); | |
256 | regs->xcr2 |= XFRLEN2(1 - 1); | |
257 | regs->xcr1 |= XFRLEN1(1 - 1); | |
258 | break; | |
259 | default: | |
260 | /* Unsupported number of channels */ | |
261 | return -EINVAL; | |
262 | } | |
263 | ||
264 | switch (params_format(params)) { | |
265 | case SNDRV_PCM_FORMAT_S16_LE: | |
266 | /* Set word lengths */ | |
267 | wlen = 16; | |
268 | regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); | |
269 | regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16); | |
270 | regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16); | |
271 | regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16); | |
272 | break; | |
273 | default: | |
274 | /* Unsupported PCM format */ | |
275 | return -EINVAL; | |
276 | } | |
277 | ||
278 | /* Set FS period and length in terms of bit clock periods */ | |
279 | switch (mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
280 | case SND_SOC_DAIFMT_I2S: | |
281 | regs->srgr2 |= FPER(wlen * 2 - 1); | |
282 | regs->srgr1 |= FWID(wlen - 1); | |
283 | break; | |
284 | case SND_SOC_DAIFMT_DSP_B: | |
285 | regs->srgr2 |= FPER(wlen * channels - 1); | |
286 | regs->srgr1 |= FWID(wlen * channels - 2); | |
287 | break; | |
288 | } | |
289 | ||
290 | omap_mcbsp_config(bus_id, &mcbsp_data->regs); | |
291 | mcbsp_data->configured = 1; | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | /* | |
297 | * This must be called before _set_clkdiv and _set_sysclk since McBSP register | |
298 | * cache is initialized here | |
299 | */ | |
300 | static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |
301 | unsigned int fmt) | |
302 | { | |
303 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
304 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; | |
305 | ||
306 | if (mcbsp_data->configured) | |
307 | return 0; | |
308 | ||
309 | mcbsp_data->fmt = fmt; | |
310 | memset(regs, 0, sizeof(*regs)); | |
311 | /* Generic McBSP register settings */ | |
312 | regs->spcr2 |= XINTM(3) | FREE; | |
313 | regs->spcr1 |= RINTM(3); | |
314 | regs->rcr2 |= RFIG; | |
315 | regs->xcr2 |= XFIG; | |
316 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { | |
317 | regs->xccr = DXENDLY(1) | XDMAEN; | |
318 | regs->rccr = RFULL_CYCLE | RDMAEN; | |
319 | } | |
320 | ||
321 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
322 | case SND_SOC_DAIFMT_I2S: | |
323 | /* 1-bit data delay */ | |
324 | regs->rcr2 |= RDATDLY(1); | |
325 | regs->xcr2 |= XDATDLY(1); | |
326 | break; | |
327 | case SND_SOC_DAIFMT_DSP_B: | |
328 | /* 0-bit data delay */ | |
329 | regs->rcr2 |= RDATDLY(0); | |
330 | regs->xcr2 |= XDATDLY(0); | |
331 | break; | |
332 | default: | |
333 | /* Unsupported data format */ | |
334 | return -EINVAL; | |
335 | } | |
336 | ||
337 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
338 | case SND_SOC_DAIFMT_CBS_CFS: | |
339 | /* McBSP master. Set FS and bit clocks as outputs */ | |
340 | regs->pcr0 |= FSXM | FSRM | | |
341 | CLKXM | CLKRM; | |
342 | /* Sample rate generator drives the FS */ | |
343 | regs->srgr2 |= FSGM; | |
344 | break; | |
345 | case SND_SOC_DAIFMT_CBM_CFM: | |
346 | /* McBSP slave */ | |
347 | break; | |
348 | default: | |
349 | /* Unsupported master/slave configuration */ | |
350 | return -EINVAL; | |
351 | } | |
352 | ||
353 | /* Set bit clock (CLKX/CLKR) and FS polarities */ | |
354 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
355 | case SND_SOC_DAIFMT_NB_NF: | |
356 | /* | |
357 | * Normal BCLK + FS. | |
358 | * FS active low. TX data driven on falling edge of bit clock | |
359 | * and RX data sampled on rising edge of bit clock. | |
360 | */ | |
361 | regs->pcr0 |= FSXP | FSRP | | |
362 | CLKXP | CLKRP; | |
363 | break; | |
364 | case SND_SOC_DAIFMT_NB_IF: | |
365 | regs->pcr0 |= CLKXP | CLKRP; | |
366 | break; | |
367 | case SND_SOC_DAIFMT_IB_NF: | |
368 | regs->pcr0 |= FSXP | FSRP; | |
369 | break; | |
370 | case SND_SOC_DAIFMT_IB_IF: | |
371 | break; | |
372 | default: | |
373 | return -EINVAL; | |
374 | } | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, | |
380 | int div_id, int div) | |
381 | { | |
382 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
383 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; | |
384 | ||
385 | if (div_id != OMAP_MCBSP_CLKGDV) | |
386 | return -ENODEV; | |
387 | ||
388 | regs->srgr1 |= CLKGDV(div - 1); | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data, | |
394 | int clk_id) | |
395 | { | |
396 | int sel_bit; | |
397 | u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1; | |
398 | ||
399 | if (cpu_class_is_omap1()) { | |
400 | /* OMAP1's can use only external source clock */ | |
401 | if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)) | |
402 | return -EINVAL; | |
403 | else | |
404 | return 0; | |
405 | } | |
406 | ||
407 | if (cpu_is_omap2420() && mcbsp_data->bus_id > 1) | |
408 | return -EINVAL; | |
409 | ||
410 | if (cpu_is_omap343x()) | |
411 | reg_devconf1 = OMAP343X_CONTROL_DEVCONF1; | |
412 | ||
413 | switch (mcbsp_data->bus_id) { | |
414 | case 0: | |
415 | reg = OMAP2_CONTROL_DEVCONF0; | |
416 | sel_bit = 2; | |
417 | break; | |
418 | case 1: | |
419 | reg = OMAP2_CONTROL_DEVCONF0; | |
420 | sel_bit = 6; | |
421 | break; | |
422 | case 2: | |
423 | reg = reg_devconf1; | |
424 | sel_bit = 0; | |
425 | break; | |
426 | case 3: | |
427 | reg = reg_devconf1; | |
428 | sel_bit = 2; | |
429 | break; | |
430 | case 4: | |
431 | reg = reg_devconf1; | |
432 | sel_bit = 4; | |
433 | break; | |
434 | default: | |
435 | return -EINVAL; | |
436 | } | |
437 | ||
438 | if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK) | |
439 | omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg); | |
440 | else | |
441 | omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg); | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
446 | static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
447 | int clk_id, unsigned int freq, | |
448 | int dir) | |
449 | { | |
450 | struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data); | |
451 | struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs; | |
452 | int err = 0; | |
453 | ||
454 | switch (clk_id) { | |
455 | case OMAP_MCBSP_SYSCLK_CLK: | |
456 | regs->srgr2 |= CLKSM; | |
457 | break; | |
458 | case OMAP_MCBSP_SYSCLK_CLKS_FCLK: | |
459 | case OMAP_MCBSP_SYSCLK_CLKS_EXT: | |
460 | err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id); | |
461 | break; | |
462 | ||
463 | case OMAP_MCBSP_SYSCLK_CLKX_EXT: | |
464 | regs->srgr2 |= CLKSM; | |
465 | case OMAP_MCBSP_SYSCLK_CLKR_EXT: | |
466 | regs->pcr0 |= SCLKME; | |
467 | break; | |
468 | default: | |
469 | err = -ENODEV; | |
470 | } | |
471 | ||
472 | return err; | |
473 | } | |
474 | ||
475 | static struct snd_soc_dai_ops omap_mcbsp_dai_ops = { | |
476 | .startup = omap_mcbsp_dai_startup, | |
477 | .shutdown = omap_mcbsp_dai_shutdown, | |
478 | .trigger = omap_mcbsp_dai_trigger, | |
479 | .hw_params = omap_mcbsp_dai_hw_params, | |
480 | .set_fmt = omap_mcbsp_dai_set_dai_fmt, | |
481 | .set_clkdiv = omap_mcbsp_dai_set_clkdiv, | |
482 | .set_sysclk = omap_mcbsp_dai_set_dai_sysclk, | |
483 | }; | |
484 | ||
485 | #define OMAP_MCBSP_DAI_BUILDER(link_id) \ | |
486 | { \ | |
487 | .name = "omap-mcbsp-dai-"#link_id, \ | |
488 | .id = (link_id), \ | |
489 | .playback = { \ | |
490 | .channels_min = 1, \ | |
491 | .channels_max = 2, \ | |
492 | .rates = OMAP_MCBSP_RATES, \ | |
493 | .formats = SNDRV_PCM_FMTBIT_S16_LE, \ | |
494 | }, \ | |
495 | .capture = { \ | |
496 | .channels_min = 1, \ | |
497 | .channels_max = 2, \ | |
498 | .rates = OMAP_MCBSP_RATES, \ | |
499 | .formats = SNDRV_PCM_FMTBIT_S16_LE, \ | |
500 | }, \ | |
501 | .ops = &omap_mcbsp_dai_ops, \ | |
502 | .private_data = &mcbsp_data[(link_id)].bus_id, \ | |
503 | } | |
504 | ||
505 | struct snd_soc_dai omap_mcbsp_dai[] = { | |
506 | OMAP_MCBSP_DAI_BUILDER(0), | |
507 | OMAP_MCBSP_DAI_BUILDER(1), | |
508 | #if NUM_LINKS >= 3 | |
509 | OMAP_MCBSP_DAI_BUILDER(2), | |
510 | #endif | |
511 | #if NUM_LINKS == 5 | |
512 | OMAP_MCBSP_DAI_BUILDER(3), | |
513 | OMAP_MCBSP_DAI_BUILDER(4), | |
514 | #endif | |
515 | }; | |
516 | ||
517 | EXPORT_SYMBOL_GPL(omap_mcbsp_dai); | |
518 | ||
519 | static int __init snd_omap_mcbsp_init(void) | |
520 | { | |
521 | return snd_soc_register_dais(omap_mcbsp_dai, | |
522 | ARRAY_SIZE(omap_mcbsp_dai)); | |
523 | } | |
524 | module_init(snd_omap_mcbsp_init); | |
525 | ||
526 | static void __exit snd_omap_mcbsp_exit(void) | |
527 | { | |
528 | snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai)); | |
529 | } | |
530 | module_exit(snd_omap_mcbsp_exit); | |
531 | ||
532 | MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>"); | |
533 | MODULE_DESCRIPTION("OMAP I2S SoC Interface"); | |
534 | MODULE_LICENSE("GPL"); |