]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * tegra20_spdif.c - Tegra20 SPDIF driver | |
3 | * | |
4 | * Author: Stephen Warren <swarren@nvidia.com> | |
5 | * Copyright (C) 2011-2012 - NVIDIA, Inc. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * version 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
19 | * 02110-1301 USA | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/clk.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/pm_runtime.h> | |
29 | #include <linux/regmap.h> | |
30 | #include <linux/slab.h> | |
31 | #include <sound/core.h> | |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/soc.h> | |
35 | #include <sound/dmaengine_pcm.h> | |
36 | ||
37 | #include "tegra20_spdif.h" | |
38 | ||
39 | #define DRV_NAME "tegra20-spdif" | |
40 | ||
41 | static int tegra20_spdif_runtime_suspend(struct device *dev) | |
42 | { | |
43 | struct tegra20_spdif *spdif = dev_get_drvdata(dev); | |
44 | ||
45 | clk_disable_unprepare(spdif->clk_spdif_out); | |
46 | ||
47 | return 0; | |
48 | } | |
49 | ||
50 | static int tegra20_spdif_runtime_resume(struct device *dev) | |
51 | { | |
52 | struct tegra20_spdif *spdif = dev_get_drvdata(dev); | |
53 | int ret; | |
54 | ||
55 | ret = clk_prepare_enable(spdif->clk_spdif_out); | |
56 | if (ret) { | |
57 | dev_err(dev, "clk_enable failed: %d\n", ret); | |
58 | return ret; | |
59 | } | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
64 | static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream, | |
65 | struct snd_pcm_hw_params *params, | |
66 | struct snd_soc_dai *dai) | |
67 | { | |
68 | struct device *dev = dai->dev; | |
69 | struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai); | |
70 | unsigned int mask = 0, val = 0; | |
71 | int ret, spdifclock; | |
72 | ||
73 | mask |= TEGRA20_SPDIF_CTRL_PACK | | |
74 | TEGRA20_SPDIF_CTRL_BIT_MODE_MASK; | |
75 | switch (params_format(params)) { | |
76 | case SNDRV_PCM_FORMAT_S16_LE: | |
77 | val |= TEGRA20_SPDIF_CTRL_PACK | | |
78 | TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT; | |
79 | break; | |
80 | default: | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val); | |
85 | ||
86 | switch (params_rate(params)) { | |
87 | case 32000: | |
88 | spdifclock = 4096000; | |
89 | break; | |
90 | case 44100: | |
91 | spdifclock = 5644800; | |
92 | break; | |
93 | case 48000: | |
94 | spdifclock = 6144000; | |
95 | break; | |
96 | case 88200: | |
97 | spdifclock = 11289600; | |
98 | break; | |
99 | case 96000: | |
100 | spdifclock = 12288000; | |
101 | break; | |
102 | case 176400: | |
103 | spdifclock = 22579200; | |
104 | break; | |
105 | case 192000: | |
106 | spdifclock = 24576000; | |
107 | break; | |
108 | default: | |
109 | return -EINVAL; | |
110 | } | |
111 | ||
112 | ret = clk_set_rate(spdif->clk_spdif_out, spdifclock); | |
113 | if (ret) { | |
114 | dev_err(dev, "Can't set SPDIF clock rate: %d\n", ret); | |
115 | return ret; | |
116 | } | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
121 | static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif) | |
122 | { | |
123 | regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, | |
124 | TEGRA20_SPDIF_CTRL_TX_EN, | |
125 | TEGRA20_SPDIF_CTRL_TX_EN); | |
126 | } | |
127 | ||
128 | static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif) | |
129 | { | |
130 | regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, | |
131 | TEGRA20_SPDIF_CTRL_TX_EN, 0); | |
132 | } | |
133 | ||
134 | static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd, | |
135 | struct snd_soc_dai *dai) | |
136 | { | |
137 | struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai); | |
138 | ||
139 | switch (cmd) { | |
140 | case SNDRV_PCM_TRIGGER_START: | |
141 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
142 | case SNDRV_PCM_TRIGGER_RESUME: | |
143 | tegra20_spdif_start_playback(spdif); | |
144 | break; | |
145 | case SNDRV_PCM_TRIGGER_STOP: | |
146 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
147 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
148 | tegra20_spdif_stop_playback(spdif); | |
149 | break; | |
150 | default: | |
151 | return -EINVAL; | |
152 | } | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
157 | static int tegra20_spdif_probe(struct snd_soc_dai *dai) | |
158 | { | |
159 | struct tegra20_spdif *spdif = snd_soc_dai_get_drvdata(dai); | |
160 | ||
161 | dai->capture_dma_data = NULL; | |
162 | dai->playback_dma_data = &spdif->playback_dma_data; | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
167 | static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = { | |
168 | .hw_params = tegra20_spdif_hw_params, | |
169 | .trigger = tegra20_spdif_trigger, | |
170 | }; | |
171 | ||
172 | static struct snd_soc_dai_driver tegra20_spdif_dai = { | |
173 | .name = DRV_NAME, | |
174 | .probe = tegra20_spdif_probe, | |
175 | .playback = { | |
176 | .stream_name = "Playback", | |
177 | .channels_min = 2, | |
178 | .channels_max = 2, | |
179 | .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | | |
180 | SNDRV_PCM_RATE_48000, | |
181 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
182 | }, | |
183 | .ops = &tegra20_spdif_dai_ops, | |
184 | }; | |
185 | ||
186 | static const struct snd_soc_component_driver tegra20_spdif_component = { | |
187 | .name = DRV_NAME, | |
188 | }; | |
189 | ||
190 | static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg) | |
191 | { | |
192 | switch (reg) { | |
193 | case TEGRA20_SPDIF_CTRL: | |
194 | case TEGRA20_SPDIF_STATUS: | |
195 | case TEGRA20_SPDIF_STROBE_CTRL: | |
196 | case TEGRA20_SPDIF_DATA_FIFO_CSR: | |
197 | case TEGRA20_SPDIF_DATA_OUT: | |
198 | case TEGRA20_SPDIF_DATA_IN: | |
199 | case TEGRA20_SPDIF_CH_STA_RX_A: | |
200 | case TEGRA20_SPDIF_CH_STA_RX_B: | |
201 | case TEGRA20_SPDIF_CH_STA_RX_C: | |
202 | case TEGRA20_SPDIF_CH_STA_RX_D: | |
203 | case TEGRA20_SPDIF_CH_STA_RX_E: | |
204 | case TEGRA20_SPDIF_CH_STA_RX_F: | |
205 | case TEGRA20_SPDIF_CH_STA_TX_A: | |
206 | case TEGRA20_SPDIF_CH_STA_TX_B: | |
207 | case TEGRA20_SPDIF_CH_STA_TX_C: | |
208 | case TEGRA20_SPDIF_CH_STA_TX_D: | |
209 | case TEGRA20_SPDIF_CH_STA_TX_E: | |
210 | case TEGRA20_SPDIF_CH_STA_TX_F: | |
211 | case TEGRA20_SPDIF_USR_STA_RX_A: | |
212 | case TEGRA20_SPDIF_USR_DAT_TX_A: | |
213 | return true; | |
214 | default: | |
215 | return false; | |
216 | } | |
217 | } | |
218 | ||
219 | static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg) | |
220 | { | |
221 | switch (reg) { | |
222 | case TEGRA20_SPDIF_STATUS: | |
223 | case TEGRA20_SPDIF_DATA_FIFO_CSR: | |
224 | case TEGRA20_SPDIF_DATA_OUT: | |
225 | case TEGRA20_SPDIF_DATA_IN: | |
226 | case TEGRA20_SPDIF_CH_STA_RX_A: | |
227 | case TEGRA20_SPDIF_CH_STA_RX_B: | |
228 | case TEGRA20_SPDIF_CH_STA_RX_C: | |
229 | case TEGRA20_SPDIF_CH_STA_RX_D: | |
230 | case TEGRA20_SPDIF_CH_STA_RX_E: | |
231 | case TEGRA20_SPDIF_CH_STA_RX_F: | |
232 | case TEGRA20_SPDIF_USR_STA_RX_A: | |
233 | case TEGRA20_SPDIF_USR_DAT_TX_A: | |
234 | return true; | |
235 | default: | |
236 | return false; | |
237 | } | |
238 | } | |
239 | ||
240 | static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg) | |
241 | { | |
242 | switch (reg) { | |
243 | case TEGRA20_SPDIF_DATA_OUT: | |
244 | case TEGRA20_SPDIF_DATA_IN: | |
245 | case TEGRA20_SPDIF_USR_STA_RX_A: | |
246 | case TEGRA20_SPDIF_USR_DAT_TX_A: | |
247 | return true; | |
248 | default: | |
249 | return false; | |
250 | } | |
251 | } | |
252 | ||
253 | static const struct regmap_config tegra20_spdif_regmap_config = { | |
254 | .reg_bits = 32, | |
255 | .reg_stride = 4, | |
256 | .val_bits = 32, | |
257 | .max_register = TEGRA20_SPDIF_USR_DAT_TX_A, | |
258 | .writeable_reg = tegra20_spdif_wr_rd_reg, | |
259 | .readable_reg = tegra20_spdif_wr_rd_reg, | |
260 | .volatile_reg = tegra20_spdif_volatile_reg, | |
261 | .precious_reg = tegra20_spdif_precious_reg, | |
262 | .cache_type = REGCACHE_FLAT, | |
263 | }; | |
264 | ||
265 | static int tegra20_spdif_platform_probe(struct platform_device *pdev) | |
266 | { | |
267 | struct tegra20_spdif *spdif; | |
268 | struct resource *mem, *dmareq; | |
269 | void __iomem *regs; | |
270 | int ret; | |
271 | ||
272 | spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif), | |
273 | GFP_KERNEL); | |
274 | if (!spdif) | |
275 | return -ENOMEM; | |
276 | ||
277 | dev_set_drvdata(&pdev->dev, spdif); | |
278 | ||
279 | spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "spdif_out"); | |
280 | if (IS_ERR(spdif->clk_spdif_out)) { | |
281 | pr_err("Can't retrieve spdif clock\n"); | |
282 | ret = PTR_ERR(spdif->clk_spdif_out); | |
283 | return ret; | |
284 | } | |
285 | ||
286 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
287 | regs = devm_ioremap_resource(&pdev->dev, mem); | |
288 | if (IS_ERR(regs)) | |
289 | return PTR_ERR(regs); | |
290 | ||
291 | dmareq = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
292 | if (!dmareq) { | |
293 | dev_err(&pdev->dev, "No DMA resource\n"); | |
294 | return -ENODEV; | |
295 | } | |
296 | ||
297 | spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs, | |
298 | &tegra20_spdif_regmap_config); | |
299 | if (IS_ERR(spdif->regmap)) { | |
300 | dev_err(&pdev->dev, "regmap init failed\n"); | |
301 | ret = PTR_ERR(spdif->regmap); | |
302 | return ret; | |
303 | } | |
304 | ||
305 | spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT; | |
306 | spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
307 | spdif->playback_dma_data.maxburst = 4; | |
308 | spdif->playback_dma_data.slave_id = dmareq->start; | |
309 | ||
310 | pm_runtime_enable(&pdev->dev); | |
311 | if (!pm_runtime_enabled(&pdev->dev)) { | |
312 | ret = tegra20_spdif_runtime_resume(&pdev->dev); | |
313 | if (ret) | |
314 | goto err_pm_disable; | |
315 | } | |
316 | ||
317 | ret = snd_soc_register_component(&pdev->dev, &tegra20_spdif_component, | |
318 | &tegra20_spdif_dai, 1); | |
319 | if (ret) { | |
320 | dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); | |
321 | ret = -ENOMEM; | |
322 | goto err_suspend; | |
323 | } | |
324 | ||
325 | ret = tegra_pcm_platform_register(&pdev->dev); | |
326 | if (ret) { | |
327 | dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); | |
328 | goto err_unregister_component; | |
329 | } | |
330 | ||
331 | return 0; | |
332 | ||
333 | err_unregister_component: | |
334 | snd_soc_unregister_component(&pdev->dev); | |
335 | err_suspend: | |
336 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
337 | tegra20_spdif_runtime_suspend(&pdev->dev); | |
338 | err_pm_disable: | |
339 | pm_runtime_disable(&pdev->dev); | |
340 | ||
341 | return ret; | |
342 | } | |
343 | ||
344 | static int tegra20_spdif_platform_remove(struct platform_device *pdev) | |
345 | { | |
346 | pm_runtime_disable(&pdev->dev); | |
347 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
348 | tegra20_spdif_runtime_suspend(&pdev->dev); | |
349 | ||
350 | tegra_pcm_platform_unregister(&pdev->dev); | |
351 | snd_soc_unregister_component(&pdev->dev); | |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
356 | static const struct dev_pm_ops tegra20_spdif_pm_ops = { | |
357 | SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend, | |
358 | tegra20_spdif_runtime_resume, NULL) | |
359 | }; | |
360 | ||
361 | static struct platform_driver tegra20_spdif_driver = { | |
362 | .driver = { | |
363 | .name = DRV_NAME, | |
364 | .pm = &tegra20_spdif_pm_ops, | |
365 | }, | |
366 | .probe = tegra20_spdif_platform_probe, | |
367 | .remove = tegra20_spdif_platform_remove, | |
368 | }; | |
369 | ||
370 | module_platform_driver(tegra20_spdif_driver); | |
371 | ||
372 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); | |
373 | MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver"); | |
374 | MODULE_LICENSE("GPL"); | |
375 | MODULE_ALIAS("platform:" DRV_NAME); |