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1 | # AArch64 SVE instruction descriptions | |
2 | # | |
3 | # Copyright (c) 2017 Linaro, Ltd | |
4 | # | |
5 | # This library is free software; you can redistribute it and/or | |
6 | # modify it under the terms of the GNU Lesser General Public | |
7 | # License as published by the Free Software Foundation; either | |
8 | # version 2.1 of the License, or (at your option) any later version. | |
9 | # | |
10 | # This library is distributed in the hope that it will be useful, | |
11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | # Lesser General Public License for more details. | |
14 | # | |
15 | # You should have received a copy of the GNU Lesser General Public | |
16 | # License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
17 | ||
18 | # | |
19 | # This file is processed by scripts/decodetree.py | |
20 | # | |
21 | ||
22 | ########################################################################### | |
23 | # Named fields. These are primarily for disjoint fields. | |
24 | ||
25 | %imm4_16_p1 16:4 !function=plus1 | |
26 | %imm6_22_5 22:1 5:5 | |
27 | %imm7_22_16 22:2 16:5 | |
28 | %imm8_16_10 16:5 10:3 | |
29 | %imm9_16_10 16:s6 10:3 | |
30 | %size_23 23:2 | |
31 | %dtype_23_13 23:2 13:2 | |
32 | %index3_22_19 22:1 19:2 | |
33 | %index3_19_11 19:2 11:1 | |
34 | %index2_20_11 20:1 11:1 | |
35 | ||
36 | # A combination of tsz:imm3 -- extract esize. | |
37 | %tszimm_esz 22:2 5:5 !function=tszimm_esz | |
38 | # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) | |
39 | %tszimm_shr 22:2 5:5 !function=tszimm_shr | |
40 | # A combination of tsz:imm3 -- extract (tsz:imm3) - esize | |
41 | %tszimm_shl 22:2 5:5 !function=tszimm_shl | |
42 | ||
43 | # Similarly for the tszh/tszl pair at 22/16 for zzi | |
44 | %tszimm16_esz 22:2 16:5 !function=tszimm_esz | |
45 | %tszimm16_shr 22:2 16:5 !function=tszimm_shr | |
46 | %tszimm16_shl 22:2 16:5 !function=tszimm_shl | |
47 | ||
48 | # Signed 8-bit immediate, optionally shifted left by 8. | |
49 | %sh8_i8s 5:9 !function=expand_imm_sh8s | |
50 | # Unsigned 8-bit immediate, optionally shifted left by 8. | |
51 | %sh8_i8u 5:9 !function=expand_imm_sh8u | |
52 | ||
53 | # Unsigned load of msz into esz=2, represented as a dtype. | |
54 | %msz_dtype 23:2 !function=msz_dtype | |
55 | ||
56 | # Either a copy of rd (at bit 0), or a different source | |
57 | # as propagated via the MOVPRFX instruction. | |
58 | %reg_movprfx 0:5 | |
59 | ||
60 | ########################################################################### | |
61 | # Named attribute sets. These are used to make nice(er) names | |
62 | # when creating helpers common to those for the individual | |
63 | # instruction patterns. | |
64 | ||
65 | &rr_esz rd rn esz | |
66 | &rri rd rn imm | |
67 | &rr_dbm rd rn dbm | |
68 | &rrri rd rn rm imm | |
69 | &rri_esz rd rn imm esz | |
70 | &rrri_esz rd rn rm imm esz | |
71 | &rrr_esz rd rn rm esz | |
72 | &rrx_esz rd rn rm index esz | |
73 | &rpr_esz rd pg rn esz | |
74 | &rpr_s rd pg rn s | |
75 | &rprr_s rd pg rn rm s | |
76 | &rprr_esz rd pg rn rm esz | |
77 | &rrrr_esz rd ra rn rm esz | |
78 | &rrxr_esz rd rn rm ra index esz | |
79 | &rprrr_esz rd pg rn rm ra esz | |
80 | &rpri_esz rd pg rn imm esz | |
81 | &ptrue rd esz pat s | |
82 | &incdec_cnt rd pat esz imm d u | |
83 | &incdec2_cnt rd rn pat esz imm d u | |
84 | &incdec_pred rd pg esz d u | |
85 | &incdec2_pred rd rn pg esz d u | |
86 | &rprr_load rd pg rn rm dtype nreg | |
87 | &rpri_load rd pg rn imm dtype nreg | |
88 | &rprr_store rd pg rn rm msz esz nreg | |
89 | &rpri_store rd pg rn imm msz esz nreg | |
90 | &rprr_gather_load rd pg rn rm esz msz u ff xs scale | |
91 | &rpri_gather_load rd pg rn imm esz msz u ff | |
92 | &rprr_scatter_store rd pg rn rm esz msz xs scale | |
93 | &rpri_scatter_store rd pg rn imm esz msz | |
94 | ||
95 | ########################################################################### | |
96 | # Named instruction formats. These are generally used to | |
97 | # reduce the amount of duplication between instruction patterns. | |
98 | ||
99 | # Two operand with unused vector element size | |
100 | @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 | |
101 | ||
102 | # Two operand | |
103 | @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz | |
104 | @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz | |
105 | ||
106 | # Two operand with governing predicate, flags setting | |
107 | @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s | |
108 | @pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0 | |
109 | ||
110 | # Three operand with unused vector element size | |
111 | @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 | |
112 | ||
113 | # Three predicate operand, with governing predicate, flag setting | |
114 | @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s | |
115 | ||
116 | # Three operand, vector element size | |
117 | @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz | |
118 | @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz | |
119 | @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ | |
120 | &rrr_esz rn=%reg_movprfx | |
121 | @rdn_rm_e0 ........ .. ...... ...... rm:5 rd:5 \ | |
122 | &rrr_esz rn=%reg_movprfx esz=0 | |
123 | @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ | |
124 | &rri_esz rn=%reg_movprfx imm=%sh8_i8u | |
125 | @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ | |
126 | &rri_esz rn=%reg_movprfx | |
127 | @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ | |
128 | &rri_esz rn=%reg_movprfx | |
129 | ||
130 | # Four operand, vector element size | |
131 | @rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \ | |
132 | &rrrr_esz ra=%reg_movprfx | |
133 | ||
134 | # Four operand with unused vector element size | |
135 | @rda_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 \ | |
136 | &rrrr_esz esz=0 ra=%reg_movprfx | |
137 | @rdn_ra_rm_e0 ........ ... rm:5 ... ... ra:5 rd:5 \ | |
138 | &rrrr_esz esz=0 rn=%reg_movprfx | |
139 | ||
140 | # Three operand with "memory" size, aka immediate left shift | |
141 | @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri | |
142 | ||
143 | # Two register operand, with governing predicate, vector element size | |
144 | @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ | |
145 | &rprr_esz rn=%reg_movprfx | |
146 | @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ | |
147 | &rprr_esz rm=%reg_movprfx | |
148 | @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz | |
149 | @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz | |
150 | ||
151 | # Three register operand, with governing predicate, vector element size | |
152 | @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ | |
153 | &rprrr_esz ra=%reg_movprfx | |
154 | @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ | |
155 | &rprrr_esz rn=%reg_movprfx | |
156 | @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ | |
157 | &rprrr_esz rn=%reg_movprfx | |
158 | @rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz | |
159 | ||
160 | # One register operand, with governing predicate, vector element size | |
161 | @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz | |
162 | @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz | |
163 | @pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz | |
164 | ||
165 | # One register operand, with governing predicate, no vector element size | |
166 | @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 | |
167 | ||
168 | # Two register operands with a 6-bit signed immediate. | |
169 | @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri | |
170 | ||
171 | # Two register operand, one immediate operand, with predicate, | |
172 | # element size encoded as TSZHL. | |
173 | @rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \ | |
174 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl | |
175 | @rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \ | |
176 | &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr | |
177 | ||
178 | # Similarly without predicate. | |
179 | @rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \ | |
180 | &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl | |
181 | @rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \ | |
182 | &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr | |
183 | ||
184 | # Two register operand, one immediate operand, with 4-bit predicate. | |
185 | # User must fill in imm. | |
186 | @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ | |
187 | &rpri_esz rn=%reg_movprfx | |
188 | ||
189 | # Two register operand, one one-bit floating-point operand. | |
190 | @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \ | |
191 | &rpri_esz rn=%reg_movprfx | |
192 | ||
193 | # Two register operand, one encoded bitmask. | |
194 | @rdn_dbm ........ .. .... dbm:13 rd:5 \ | |
195 | &rr_dbm rn=%reg_movprfx | |
196 | ||
197 | # Predicate output, vector and immediate input, | |
198 | # controlling predicate, element size. | |
199 | @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz | |
200 | @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz | |
201 | ||
202 | # Basic Load/Store with 9-bit immediate offset | |
203 | @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ | |
204 | &rri imm=%imm9_16_10 | |
205 | @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ | |
206 | &rri imm=%imm9_16_10 | |
207 | ||
208 | # One register, pattern, and uint4+1. | |
209 | # User must fill in U and D. | |
210 | @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
211 | &incdec_cnt imm=%imm4_16_p1 | |
212 | @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ | |
213 | &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx | |
214 | ||
215 | # One register, predicate. | |
216 | # User must fill in U and D. | |
217 | @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred | |
218 | @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ | |
219 | &incdec2_pred rn=%reg_movprfx | |
220 | ||
221 | # Loads; user must fill in NREG. | |
222 | @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load | |
223 | @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load | |
224 | ||
225 | @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ | |
226 | &rprr_load dtype=%msz_dtype | |
227 | @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ | |
228 | &rpri_load dtype=%msz_dtype | |
229 | ||
230 | # Gather Loads. | |
231 | @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
232 | &rprr_gather_load xs=2 | |
233 | @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
234 | &rprr_gather_load | |
235 | @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
236 | &rprr_gather_load | |
237 | @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ | |
238 | &rprr_gather_load | |
239 | @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
240 | &rprr_gather_load xs=2 | |
241 | @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ | |
242 | &rprr_gather_load xs=2 | |
243 | @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ | |
244 | &rpri_gather_load | |
245 | ||
246 | # Stores; user must fill in ESZ, MSZ, NREG as needed. | |
247 | @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store | |
248 | @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store | |
249 | @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ | |
250 | &rprr_store nreg=0 | |
251 | @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \ | |
252 | &rprr_scatter_store | |
253 | @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \ | |
254 | &rpri_scatter_store | |
255 | ||
256 | # Two registers and a scalar by N-bit index | |
257 | @rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ | |
258 | &rrx_esz index=%index3_22_19 | |
259 | @rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz | |
260 | @rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz | |
261 | ||
262 | # Two registers and a scalar by N-bit index, alternate | |
263 | @rrx_3a ........ .. . .. rm:3 ...... rn:5 rd:5 \ | |
264 | &rrx_esz index=%index3_19_11 | |
265 | @rrx_2a ........ .. . . rm:4 ...... rn:5 rd:5 \ | |
266 | &rrx_esz index=%index2_20_11 | |
267 | ||
268 | # Three registers and a scalar by N-bit index | |
269 | @rrxr_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ | |
270 | &rrxr_esz ra=%reg_movprfx index=%index3_22_19 | |
271 | @rrxr_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 \ | |
272 | &rrxr_esz ra=%reg_movprfx | |
273 | @rrxr_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 \ | |
274 | &rrxr_esz ra=%reg_movprfx | |
275 | ||
276 | # Three registers and a scalar by N-bit index, alternate | |
277 | @rrxr_3a ........ .. ... rm:3 ...... rn:5 rd:5 \ | |
278 | &rrxr_esz ra=%reg_movprfx index=%index3_19_11 | |
279 | @rrxr_2a ........ .. .. rm:4 ...... rn:5 rd:5 \ | |
280 | &rrxr_esz ra=%reg_movprfx index=%index2_20_11 | |
281 | ||
282 | ########################################################################### | |
283 | # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. | |
284 | ||
285 | ### SVE Integer Arithmetic - Binary Predicated Group | |
286 | ||
287 | # SVE bitwise logical vector operations (predicated) | |
288 | ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm | |
289 | EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm | |
290 | AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm | |
291 | BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm | |
292 | ||
293 | # SVE integer add/subtract vectors (predicated) | |
294 | ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm | |
295 | SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm | |
296 | SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR | |
297 | ||
298 | # SVE integer min/max/difference (predicated) | |
299 | SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm | |
300 | UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm | |
301 | SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm | |
302 | UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm | |
303 | SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm | |
304 | UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm | |
305 | ||
306 | # SVE integer multiply/divide (predicated) | |
307 | MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm | |
308 | SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm | |
309 | UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm | |
310 | # Note that divide requires size >= 2; below 2 is unallocated. | |
311 | SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm | |
312 | UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm | |
313 | SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR | |
314 | UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR | |
315 | ||
316 | ### SVE Integer Reduction Group | |
317 | ||
318 | # SVE bitwise logical reduction (predicated) | |
319 | ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn | |
320 | EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn | |
321 | ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn | |
322 | ||
323 | # SVE constructive prefix (predicated) | |
324 | MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn | |
325 | MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn | |
326 | ||
327 | # SVE integer add reduction (predicated) | |
328 | # Note that saddv requires size != 3. | |
329 | UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn | |
330 | SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
331 | ||
332 | # SVE integer min/max reduction (predicated) | |
333 | SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn | |
334 | UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn | |
335 | SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn | |
336 | UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn | |
337 | ||
338 | ### SVE Shift by Immediate - Predicated Group | |
339 | ||
340 | # SVE bitwise shift by immediate (predicated) | |
341 | ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr | |
342 | LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr | |
343 | LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl | |
344 | ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr | |
345 | SQSHL_zpzi 00000100 .. 000 110 100 ... .. ... ..... @rdn_pg_tszimm_shl | |
346 | UQSHL_zpzi 00000100 .. 000 111 100 ... .. ... ..... @rdn_pg_tszimm_shl | |
347 | SRSHR 00000100 .. 001 100 100 ... .. ... ..... @rdn_pg_tszimm_shr | |
348 | URSHR 00000100 .. 001 101 100 ... .. ... ..... @rdn_pg_tszimm_shr | |
349 | SQSHLU 00000100 .. 001 111 100 ... .. ... ..... @rdn_pg_tszimm_shl | |
350 | ||
351 | # SVE bitwise shift by vector (predicated) | |
352 | ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
353 | LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
354 | LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
355 | ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR | |
356 | LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR | |
357 | LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR | |
358 | ||
359 | # SVE bitwise shift by wide elements (predicated) | |
360 | # Note these require size != 3. | |
361 | ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
362 | LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
363 | LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
364 | ||
365 | ### SVE Integer Arithmetic - Unary Predicated Group | |
366 | ||
367 | # SVE unary bit operations (predicated) | |
368 | # Note esz != 0 for FABS and FNEG. | |
369 | CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn | |
370 | CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn | |
371 | CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn | |
372 | CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn | |
373 | NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn | |
374 | FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn | |
375 | FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn | |
376 | ||
377 | # SVE integer unary operations (predicated) | |
378 | # Note esz > original size for extensions. | |
379 | ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn | |
380 | NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn | |
381 | SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn | |
382 | UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn | |
383 | SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn | |
384 | UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn | |
385 | SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn | |
386 | UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn | |
387 | ||
388 | ### SVE Floating Point Compare - Vectors Group | |
389 | ||
390 | # SVE floating-point compare vectors | |
391 | FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
392 | FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
393 | FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
394 | FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
395 | FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
396 | FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
397 | FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
398 | ||
399 | ### SVE Integer Multiply-Add Group | |
400 | ||
401 | # SVE integer multiply-add writing addend (predicated) | |
402 | MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
403 | MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
404 | ||
405 | # SVE integer multiply-add writing multiplicand (predicated) | |
406 | MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD | |
407 | MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB | |
408 | ||
409 | ### SVE Integer Arithmetic - Unpredicated Group | |
410 | ||
411 | # SVE integer add/subtract vectors (unpredicated) | |
412 | ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm | |
413 | SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm | |
414 | SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm | |
415 | UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm | |
416 | SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm | |
417 | UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm | |
418 | ||
419 | ### SVE Logical - Unpredicated Group | |
420 | ||
421 | # SVE bitwise logical operations (unpredicated) | |
422 | AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
423 | ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
424 | EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
425 | BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 | |
426 | ||
427 | XAR 00000100 .. 1 ..... 001 101 rm:5 rd:5 &rrri_esz \ | |
428 | rn=%reg_movprfx esz=%tszimm16_esz imm=%tszimm16_shr | |
429 | ||
430 | # SVE2 bitwise ternary operations | |
431 | EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 | |
432 | BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
433 | BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 | |
434 | BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
435 | BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
436 | NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 | |
437 | ||
438 | ### SVE Index Generation Group | |
439 | ||
440 | # SVE index generation (immediate start, immediate increment) | |
441 | INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 | |
442 | ||
443 | # SVE index generation (immediate start, register increment) | |
444 | INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 | |
445 | ||
446 | # SVE index generation (register start, immediate increment) | |
447 | INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 | |
448 | ||
449 | # SVE index generation (register start, register increment) | |
450 | INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm | |
451 | ||
452 | ### SVE Stack Allocation Group | |
453 | ||
454 | # SVE stack frame adjustment | |
455 | ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 | |
456 | ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 | |
457 | ||
458 | # SVE stack frame size | |
459 | RDVL 00000100 101 11111 01010 imm:s6 rd:5 | |
460 | ||
461 | ### SVE Bitwise Shift - Unpredicated Group | |
462 | ||
463 | # SVE bitwise shift by immediate (unpredicated) | |
464 | ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr | |
465 | LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr | |
466 | LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl | |
467 | ||
468 | # SVE bitwise shift by wide elements (unpredicated) | |
469 | # Note esz != 3 | |
470 | ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm | |
471 | LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm | |
472 | LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm | |
473 | ||
474 | ### SVE Compute Vector Address Group | |
475 | ||
476 | # SVE vector address generation | |
477 | ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
478 | ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
479 | ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
480 | ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm | |
481 | ||
482 | ### SVE Integer Misc - Unpredicated Group | |
483 | ||
484 | # SVE constructive prefix (unpredicated) | |
485 | MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 | |
486 | ||
487 | # SVE floating-point exponential accelerator | |
488 | # Note esz != 0 | |
489 | FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn | |
490 | ||
491 | # SVE floating-point trig select coefficient | |
492 | # Note esz != 0 | |
493 | FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm | |
494 | ||
495 | ### SVE Element Count Group | |
496 | ||
497 | # SVE element count | |
498 | CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 | |
499 | ||
500 | # SVE inc/dec register by element count | |
501 | INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 | |
502 | ||
503 | # SVE saturating inc/dec register by element count | |
504 | SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
505 | SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt | |
506 | ||
507 | # SVE inc/dec vector by element count | |
508 | # Note this requires esz != 0. | |
509 | INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 | |
510 | ||
511 | # SVE saturating inc/dec vector by element count | |
512 | # Note these require esz != 0. | |
513 | SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt | |
514 | ||
515 | ### SVE Bitwise Immediate Group | |
516 | ||
517 | # SVE bitwise logical with immediate (unpredicated) | |
518 | ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm | |
519 | EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm | |
520 | AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm | |
521 | ||
522 | # SVE broadcast bitmask immediate | |
523 | DUPM 00000101 11 0000 dbm:13 rd:5 | |
524 | ||
525 | ### SVE Integer Wide Immediate - Predicated Group | |
526 | ||
527 | # SVE copy floating-point immediate (predicated) | |
528 | FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 | |
529 | ||
530 | # SVE copy integer immediate (predicated) | |
531 | CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
532 | CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s | |
533 | ||
534 | ### SVE Permute - Extract Group | |
535 | ||
536 | # SVE extract vector (destructive) | |
537 | EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ | |
538 | &rrri rn=%reg_movprfx imm=%imm8_16_10 | |
539 | ||
540 | # SVE2 extract vector (constructive) | |
541 | EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \ | |
542 | &rri imm=%imm8_16_10 | |
543 | ||
544 | ### SVE Permute - Unpredicated Group | |
545 | ||
546 | # SVE broadcast general register | |
547 | DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn | |
548 | ||
549 | # SVE broadcast indexed element | |
550 | DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ | |
551 | &rri imm=%imm7_22_16 | |
552 | ||
553 | # SVE insert SIMD&FP scalar register | |
554 | INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm | |
555 | ||
556 | # SVE insert general register | |
557 | INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm | |
558 | ||
559 | # SVE reverse vector elements | |
560 | REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn | |
561 | ||
562 | # SVE vector table lookup | |
563 | TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm | |
564 | ||
565 | # SVE unpack vector elements | |
566 | UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 | |
567 | ||
568 | # SVE2 Table Lookup (three sources) | |
569 | ||
570 | TBL_sve2 00000101 .. 1 ..... 001010 ..... ..... @rd_rn_rm | |
571 | TBX 00000101 .. 1 ..... 001011 ..... ..... @rd_rn_rm | |
572 | ||
573 | ### SVE Permute - Predicates Group | |
574 | ||
575 | # SVE permute predicate elements | |
576 | ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm | |
577 | ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm | |
578 | UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm | |
579 | UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm | |
580 | TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm | |
581 | TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm | |
582 | ||
583 | # SVE reverse predicate elements | |
584 | REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn | |
585 | ||
586 | # SVE unpack predicate elements | |
587 | PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 | |
588 | PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 | |
589 | ||
590 | ### SVE Permute - Interleaving Group | |
591 | ||
592 | # SVE permute vector elements | |
593 | ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
594 | ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
595 | UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | |
596 | UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
597 | TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | |
598 | TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
599 | ||
600 | # SVE2 permute vector segments | |
601 | ZIP1_q 00000101 10 1 ..... 000 000 ..... ..... @rd_rn_rm_e0 | |
602 | ZIP2_q 00000101 10 1 ..... 000 001 ..... ..... @rd_rn_rm_e0 | |
603 | UZP1_q 00000101 10 1 ..... 000 010 ..... ..... @rd_rn_rm_e0 | |
604 | UZP2_q 00000101 10 1 ..... 000 011 ..... ..... @rd_rn_rm_e0 | |
605 | TRN1_q 00000101 10 1 ..... 000 110 ..... ..... @rd_rn_rm_e0 | |
606 | TRN2_q 00000101 10 1 ..... 000 111 ..... ..... @rd_rn_rm_e0 | |
607 | ||
608 | ### SVE Permute - Predicated Group | |
609 | ||
610 | # SVE compress active elements | |
611 | # Note esz >= 2 | |
612 | COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn | |
613 | ||
614 | # SVE conditionally broadcast element to vector | |
615 | CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm | |
616 | CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm | |
617 | ||
618 | # SVE conditionally copy element to SIMD&FP scalar | |
619 | CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn | |
620 | CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn | |
621 | ||
622 | # SVE conditionally copy element to general register | |
623 | CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn | |
624 | CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn | |
625 | ||
626 | # SVE copy element to SIMD&FP scalar register | |
627 | LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn | |
628 | LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn | |
629 | ||
630 | # SVE copy element to general register | |
631 | LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn | |
632 | LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn | |
633 | ||
634 | # SVE copy element from SIMD&FP scalar register | |
635 | CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn | |
636 | ||
637 | # SVE copy element from general register to vector (predicated) | |
638 | CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn | |
639 | ||
640 | # SVE reverse within elements | |
641 | # Note esz >= operation size | |
642 | REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn | |
643 | REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn | |
644 | REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn | |
645 | RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn | |
646 | ||
647 | # SVE vector splice (predicated, destructive) | |
648 | SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm | |
649 | ||
650 | # SVE2 vector splice (predicated, constructive) | |
651 | SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn | |
652 | ||
653 | ### SVE Select Vectors Group | |
654 | ||
655 | # SVE select vector elements (predicated) | |
656 | SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm | |
657 | ||
658 | ### SVE Integer Compare - Vectors Group | |
659 | ||
660 | # SVE integer compare_vectors | |
661 | CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm | |
662 | CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm | |
663 | CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
664 | CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
665 | CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm | |
666 | CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm | |
667 | ||
668 | # SVE integer compare with wide elements | |
669 | # Note these require esz != 3. | |
670 | CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm | |
671 | CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm | |
672 | CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm | |
673 | CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm | |
674 | CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm | |
675 | CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm | |
676 | CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm | |
677 | CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm | |
678 | CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm | |
679 | CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm | |
680 | ||
681 | ### SVE Integer Compare - Unsigned Immediate Group | |
682 | ||
683 | # SVE integer compare with unsigned immediate | |
684 | CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 | |
685 | CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 | |
686 | CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 | |
687 | CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 | |
688 | ||
689 | ### SVE Integer Compare - Signed Immediate Group | |
690 | ||
691 | # SVE integer compare with signed immediate | |
692 | CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 | |
693 | CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 | |
694 | CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 | |
695 | CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 | |
696 | CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 | |
697 | CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 | |
698 | ||
699 | ### SVE Predicate Logical Operations Group | |
700 | ||
701 | # SVE predicate logical operations | |
702 | AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
703 | BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
704 | EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
705 | SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
706 | ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
707 | ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
708 | NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s | |
709 | NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s | |
710 | ||
711 | ### SVE Predicate Misc Group | |
712 | ||
713 | # SVE predicate test | |
714 | PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 | |
715 | ||
716 | # SVE predicate initialize | |
717 | PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 | |
718 | ||
719 | # SVE initialize FFR | |
720 | SETFFR 00100101 0010 1100 1001 0000 0000 0000 | |
721 | ||
722 | # SVE zero predicate register | |
723 | PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 | |
724 | ||
725 | # SVE predicate read from FFR (predicated) | |
726 | RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 | |
727 | ||
728 | # SVE predicate read from FFR (unpredicated) | |
729 | RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 | |
730 | ||
731 | # SVE FFR write from predicate (WRFFR) | |
732 | WRFFR 00100101 0010 1000 1001 000 rn:4 00000 | |
733 | ||
734 | # SVE predicate first active | |
735 | PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 | |
736 | ||
737 | # SVE predicate next active | |
738 | PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn | |
739 | ||
740 | ### SVE Partition Break Group | |
741 | ||
742 | # SVE propagate break from previous partition | |
743 | BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s | |
744 | BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s | |
745 | ||
746 | # SVE partition break condition | |
747 | BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
748 | BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s | |
749 | BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 | |
750 | BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 | |
751 | ||
752 | # SVE propagate break to next partition | |
753 | BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s | |
754 | ||
755 | ### SVE Predicate Count Group | |
756 | ||
757 | # SVE predicate count | |
758 | CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn | |
759 | ||
760 | # SVE inc/dec register by predicate count | |
761 | INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 | |
762 | ||
763 | # SVE inc/dec vector by predicate count | |
764 | INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 | |
765 | ||
766 | # SVE saturating inc/dec register by predicate count | |
767 | SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred | |
768 | SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred | |
769 | ||
770 | # SVE saturating inc/dec vector by predicate count | |
771 | SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred | |
772 | ||
773 | ### SVE Integer Compare - Scalars Group | |
774 | ||
775 | # SVE conditionally terminate scalars | |
776 | CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 | |
777 | ||
778 | # SVE integer compare scalar count and limit | |
779 | WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 lt:1 rn:5 eq:1 rd:4 | |
780 | ||
781 | # SVE2 pointer conflict compare | |
782 | WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4 | |
783 | ||
784 | ### SVE Integer Wide Immediate - Unpredicated Group | |
785 | ||
786 | # SVE broadcast floating-point immediate (unpredicated) | |
787 | FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 | |
788 | ||
789 | # SVE broadcast integer immediate (unpredicated) | |
790 | DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s | |
791 | ||
792 | # SVE integer add/subtract immediate (unpredicated) | |
793 | ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u | |
794 | SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u | |
795 | SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u | |
796 | SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u | |
797 | UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u | |
798 | SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u | |
799 | UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u | |
800 | ||
801 | # SVE integer min/max immediate (unpredicated) | |
802 | SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s | |
803 | UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u | |
804 | SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s | |
805 | UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u | |
806 | ||
807 | # SVE integer multiply immediate (unpredicated) | |
808 | MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s | |
809 | ||
810 | # SVE integer dot product (unpredicated) | |
811 | DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \ | |
812 | ra=%reg_movprfx | |
813 | ||
814 | # SVE2 complex dot product (vectors) | |
815 | CDOT_zzzz 01000100 esz:2 0 rm:5 0001 rot:2 rn:5 rd:5 ra=%reg_movprfx | |
816 | ||
817 | #### SVE Multiply - Indexed | |
818 | ||
819 | # SVE integer dot product (indexed) | |
820 | SDOT_zzxw_s 01000100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 | |
821 | SDOT_zzxw_d 01000100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 | |
822 | UDOT_zzxw_s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 | |
823 | UDOT_zzxw_d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 | |
824 | ||
825 | # SVE2 integer multiply-add (indexed) | |
826 | MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1 | |
827 | MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2 | |
828 | MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3 | |
829 | MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1 | |
830 | MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2 | |
831 | MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3 | |
832 | ||
833 | # SVE2 saturating multiply-add high (indexed) | |
834 | SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1 | |
835 | SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2 | |
836 | SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3 | |
837 | SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1 | |
838 | SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2 | |
839 | SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3 | |
840 | ||
841 | # SVE mixed sign dot product (indexed) | |
842 | USDOT_zzxw_s 01000100 10 1 ..... 000110 ..... ..... @rrxr_2 esz=2 | |
843 | SUDOT_zzxw_s 01000100 10 1 ..... 000111 ..... ..... @rrxr_2 esz=2 | |
844 | ||
845 | # SVE2 saturating multiply-add (indexed) | |
846 | SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2 | |
847 | SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3 | |
848 | SQDMLALT_zzxw_s 01000100 10 1 ..... 0010.1 ..... ..... @rrxr_3a esz=2 | |
849 | SQDMLALT_zzxw_d 01000100 11 1 ..... 0010.1 ..... ..... @rrxr_2a esz=3 | |
850 | SQDMLSLB_zzxw_s 01000100 10 1 ..... 0011.0 ..... ..... @rrxr_3a esz=2 | |
851 | SQDMLSLB_zzxw_d 01000100 11 1 ..... 0011.0 ..... ..... @rrxr_2a esz=3 | |
852 | SQDMLSLT_zzxw_s 01000100 10 1 ..... 0011.1 ..... ..... @rrxr_3a esz=2 | |
853 | SQDMLSLT_zzxw_d 01000100 11 1 ..... 0011.1 ..... ..... @rrxr_2a esz=3 | |
854 | ||
855 | # SVE2 complex integer dot product (indexed) | |
856 | CDOT_zzxw_s 01000100 10 1 index:2 rm:3 0100 rot:2 rn:5 rd:5 \ | |
857 | ra=%reg_movprfx | |
858 | CDOT_zzxw_d 01000100 11 1 index:1 rm:4 0100 rot:2 rn:5 rd:5 \ | |
859 | ra=%reg_movprfx | |
860 | ||
861 | # SVE2 complex integer multiply-add (indexed) | |
862 | CMLA_zzxz_h 01000100 10 1 index:2 rm:3 0110 rot:2 rn:5 rd:5 \ | |
863 | ra=%reg_movprfx | |
864 | CMLA_zzxz_s 01000100 11 1 index:1 rm:4 0110 rot:2 rn:5 rd:5 \ | |
865 | ra=%reg_movprfx | |
866 | ||
867 | # SVE2 complex saturating integer multiply-add (indexed) | |
868 | SQRDCMLAH_zzxz_h 01000100 10 1 index:2 rm:3 0111 rot:2 rn:5 rd:5 \ | |
869 | ra=%reg_movprfx | |
870 | SQRDCMLAH_zzxz_s 01000100 11 1 index:1 rm:4 0111 rot:2 rn:5 rd:5 \ | |
871 | ra=%reg_movprfx | |
872 | ||
873 | # SVE2 multiply-add long (indexed) | |
874 | SMLALB_zzxw_s 01000100 10 1 ..... 1000.0 ..... ..... @rrxr_3a esz=2 | |
875 | SMLALB_zzxw_d 01000100 11 1 ..... 1000.0 ..... ..... @rrxr_2a esz=3 | |
876 | SMLALT_zzxw_s 01000100 10 1 ..... 1000.1 ..... ..... @rrxr_3a esz=2 | |
877 | SMLALT_zzxw_d 01000100 11 1 ..... 1000.1 ..... ..... @rrxr_2a esz=3 | |
878 | UMLALB_zzxw_s 01000100 10 1 ..... 1001.0 ..... ..... @rrxr_3a esz=2 | |
879 | UMLALB_zzxw_d 01000100 11 1 ..... 1001.0 ..... ..... @rrxr_2a esz=3 | |
880 | UMLALT_zzxw_s 01000100 10 1 ..... 1001.1 ..... ..... @rrxr_3a esz=2 | |
881 | UMLALT_zzxw_d 01000100 11 1 ..... 1001.1 ..... ..... @rrxr_2a esz=3 | |
882 | SMLSLB_zzxw_s 01000100 10 1 ..... 1010.0 ..... ..... @rrxr_3a esz=2 | |
883 | SMLSLB_zzxw_d 01000100 11 1 ..... 1010.0 ..... ..... @rrxr_2a esz=3 | |
884 | SMLSLT_zzxw_s 01000100 10 1 ..... 1010.1 ..... ..... @rrxr_3a esz=2 | |
885 | SMLSLT_zzxw_d 01000100 11 1 ..... 1010.1 ..... ..... @rrxr_2a esz=3 | |
886 | UMLSLB_zzxw_s 01000100 10 1 ..... 1011.0 ..... ..... @rrxr_3a esz=2 | |
887 | UMLSLB_zzxw_d 01000100 11 1 ..... 1011.0 ..... ..... @rrxr_2a esz=3 | |
888 | UMLSLT_zzxw_s 01000100 10 1 ..... 1011.1 ..... ..... @rrxr_3a esz=2 | |
889 | UMLSLT_zzxw_d 01000100 11 1 ..... 1011.1 ..... ..... @rrxr_2a esz=3 | |
890 | ||
891 | # SVE2 integer multiply long (indexed) | |
892 | SMULLB_zzx_s 01000100 10 1 ..... 1100.0 ..... ..... @rrx_3a esz=2 | |
893 | SMULLB_zzx_d 01000100 11 1 ..... 1100.0 ..... ..... @rrx_2a esz=3 | |
894 | SMULLT_zzx_s 01000100 10 1 ..... 1100.1 ..... ..... @rrx_3a esz=2 | |
895 | SMULLT_zzx_d 01000100 11 1 ..... 1100.1 ..... ..... @rrx_2a esz=3 | |
896 | UMULLB_zzx_s 01000100 10 1 ..... 1101.0 ..... ..... @rrx_3a esz=2 | |
897 | UMULLB_zzx_d 01000100 11 1 ..... 1101.0 ..... ..... @rrx_2a esz=3 | |
898 | UMULLT_zzx_s 01000100 10 1 ..... 1101.1 ..... ..... @rrx_3a esz=2 | |
899 | UMULLT_zzx_d 01000100 11 1 ..... 1101.1 ..... ..... @rrx_2a esz=3 | |
900 | ||
901 | # SVE2 saturating multiply (indexed) | |
902 | SQDMULLB_zzx_s 01000100 10 1 ..... 1110.0 ..... ..... @rrx_3a esz=2 | |
903 | SQDMULLB_zzx_d 01000100 11 1 ..... 1110.0 ..... ..... @rrx_2a esz=3 | |
904 | SQDMULLT_zzx_s 01000100 10 1 ..... 1110.1 ..... ..... @rrx_3a esz=2 | |
905 | SQDMULLT_zzx_d 01000100 11 1 ..... 1110.1 ..... ..... @rrx_2a esz=3 | |
906 | ||
907 | # SVE2 saturating multiply high (indexed) | |
908 | SQDMULH_zzx_h 01000100 0. 1 ..... 111100 ..... ..... @rrx_3 esz=1 | |
909 | SQDMULH_zzx_s 01000100 10 1 ..... 111100 ..... ..... @rrx_2 esz=2 | |
910 | SQDMULH_zzx_d 01000100 11 1 ..... 111100 ..... ..... @rrx_1 esz=3 | |
911 | SQRDMULH_zzx_h 01000100 0. 1 ..... 111101 ..... ..... @rrx_3 esz=1 | |
912 | SQRDMULH_zzx_s 01000100 10 1 ..... 111101 ..... ..... @rrx_2 esz=2 | |
913 | SQRDMULH_zzx_d 01000100 11 1 ..... 111101 ..... ..... @rrx_1 esz=3 | |
914 | ||
915 | # SVE2 integer multiply (indexed) | |
916 | MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1 | |
917 | MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2 | |
918 | MUL_zzx_d 01000100 11 1 ..... 111110 ..... ..... @rrx_1 esz=3 | |
919 | ||
920 | # SVE floating-point complex add (predicated) | |
921 | FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ | |
922 | rn=%reg_movprfx | |
923 | ||
924 | # SVE floating-point complex multiply-add (predicated) | |
925 | FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ | |
926 | ra=%reg_movprfx | |
927 | ||
928 | # SVE floating-point complex multiply-add (indexed) | |
929 | FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ | |
930 | ra=%reg_movprfx esz=1 | |
931 | FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ | |
932 | ra=%reg_movprfx esz=2 | |
933 | ||
934 | ### SVE FP Multiply-Add Indexed Group | |
935 | ||
936 | # SVE floating-point multiply-add (indexed) | |
937 | FMLA_zzxz 01100100 0. 1 ..... 000000 ..... ..... @rrxr_3 esz=1 | |
938 | FMLA_zzxz 01100100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 | |
939 | FMLA_zzxz 01100100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 | |
940 | FMLS_zzxz 01100100 0. 1 ..... 000001 ..... ..... @rrxr_3 esz=1 | |
941 | FMLS_zzxz 01100100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 | |
942 | FMLS_zzxz 01100100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 | |
943 | ||
944 | ### SVE FP Multiply Indexed Group | |
945 | ||
946 | # SVE floating-point multiply (indexed) | |
947 | FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1 | |
948 | FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2 | |
949 | FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3 | |
950 | ||
951 | ### SVE FP Fast Reduction Group | |
952 | ||
953 | FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn | |
954 | FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn | |
955 | FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn | |
956 | FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn | |
957 | FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn | |
958 | ||
959 | ## SVE Floating Point Unary Operations - Unpredicated Group | |
960 | ||
961 | FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn | |
962 | FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn | |
963 | ||
964 | ### SVE FP Compare with Zero Group | |
965 | ||
966 | FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn | |
967 | FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn | |
968 | FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn | |
969 | FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn | |
970 | FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn | |
971 | FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn | |
972 | ||
973 | ### SVE FP Accumulating Reduction Group | |
974 | ||
975 | # SVE floating-point serial reduction (predicated) | |
976 | FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm | |
977 | ||
978 | ### SVE Floating Point Arithmetic - Unpredicated Group | |
979 | ||
980 | # SVE floating-point arithmetic (unpredicated) | |
981 | FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm | |
982 | FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm | |
983 | FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm | |
984 | FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm | |
985 | FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm | |
986 | FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm | |
987 | ||
988 | ### SVE FP Arithmetic Predicated Group | |
989 | ||
990 | # SVE floating-point arithmetic (predicated) | |
991 | FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm | |
992 | FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm | |
993 | FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm | |
994 | FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR | |
995 | FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm | |
996 | FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm | |
997 | FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm | |
998 | FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm | |
999 | FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm | |
1000 | FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm | |
1001 | FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm | |
1002 | FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR | |
1003 | FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm | |
1004 | ||
1005 | # SVE floating-point arithmetic with immediate (predicated) | |
1006 | FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1 | |
1007 | FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1 | |
1008 | FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1 | |
1009 | FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1 | |
1010 | FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1 | |
1011 | FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1 | |
1012 | FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1 | |
1013 | FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1 | |
1014 | ||
1015 | # SVE floating-point trig multiply-add coefficient | |
1016 | FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx | |
1017 | ||
1018 | ### SVE FP Multiply-Add Group | |
1019 | ||
1020 | # SVE floating-point multiply-accumulate writing addend | |
1021 | FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm | |
1022 | FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm | |
1023 | FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm | |
1024 | FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm | |
1025 | ||
1026 | # SVE floating-point multiply-accumulate writing multiplicand | |
1027 | # Alter the operand extraction order and reuse the helpers from above. | |
1028 | # FMAD, FMSB, FNMAD, FNMS | |
1029 | FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra | |
1030 | FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra | |
1031 | FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra | |
1032 | FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra | |
1033 | ||
1034 | ### SVE FP Unary Operations Predicated Group | |
1035 | ||
1036 | # SVE floating-point convert precision | |
1037 | FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 | |
1038 | FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 | |
1039 | BFCVT 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 | |
1040 | FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0 | |
1041 | FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0 | |
1042 | FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 | |
1043 | FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 | |
1044 | ||
1045 | # SVE floating-point convert to integer | |
1046 | FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1047 | FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1048 | FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1049 | FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1050 | FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1051 | FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1052 | FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1053 | FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1054 | FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1055 | FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1056 | FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1057 | FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1058 | FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1059 | FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1060 | ||
1061 | # SVE floating-point round to integral value | |
1062 | FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn | |
1063 | FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn | |
1064 | FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn | |
1065 | FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn | |
1066 | FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn | |
1067 | FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn | |
1068 | FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn | |
1069 | ||
1070 | # SVE floating-point unary operations | |
1071 | FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn | |
1072 | FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn | |
1073 | ||
1074 | # SVE integer convert to floating-point | |
1075 | SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1076 | SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1077 | SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1078 | SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1079 | SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1080 | SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1081 | SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 | |
1082 | ||
1083 | UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1084 | UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1085 | UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1086 | UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1087 | UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1088 | UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1089 | UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 | |
1090 | ||
1091 | ### SVE Memory - 32-bit Gather and Unsized Contiguous Group | |
1092 | ||
1093 | # SVE load predicate register | |
1094 | LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 | |
1095 | ||
1096 | # SVE load vector register | |
1097 | LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 | |
1098 | ||
1099 | # SVE load and broadcast element | |
1100 | LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \ | |
1101 | &rpri_load dtype=%dtype_23_13 nreg=0 | |
1102 | ||
1103 | # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) | |
1104 | # SVE 32-bit gather load (scalar plus 32-bit scaled offsets) | |
1105 | LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \ | |
1106 | @rprr_g_load_xs_u esz=2 msz=0 scale=0 | |
1107 | LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \ | |
1108 | @rprr_g_load_xs_u_sc esz=2 msz=1 | |
1109 | LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \ | |
1110 | @rprr_g_load_xs_sc esz=2 msz=2 u=1 | |
1111 | ||
1112 | # SVE 32-bit gather load (vector plus immediate) | |
1113 | LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \ | |
1114 | @rpri_g_load esz=2 | |
1115 | ||
1116 | ### SVE Memory Contiguous Load Group | |
1117 | ||
1118 | # SVE contiguous load (scalar plus scalar) | |
1119 | LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 | |
1120 | ||
1121 | # SVE contiguous first-fault load (scalar plus scalar) | |
1122 | LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 | |
1123 | ||
1124 | # SVE contiguous load (scalar plus immediate) | |
1125 | LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
1126 | ||
1127 | # SVE contiguous non-fault load (scalar plus immediate) | |
1128 | LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 | |
1129 | ||
1130 | # SVE contiguous non-temporal load (scalar plus scalar) | |
1131 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
1132 | # SVE load multiple structures (scalar plus scalar) | |
1133 | # LD2B, LD2H, LD2W, LD2D; etc. | |
1134 | LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz | |
1135 | ||
1136 | # SVE contiguous non-temporal load (scalar plus immediate) | |
1137 | # LDNT1B, LDNT1H, LDNT1W, LDNT1D | |
1138 | # SVE load multiple structures (scalar plus immediate) | |
1139 | # LD2B, LD2H, LD2W, LD2D; etc. | |
1140 | LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz | |
1141 | ||
1142 | # SVE load and broadcast quadword (scalar plus scalar) | |
1143 | LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ | |
1144 | @rprr_load_msz nreg=0 | |
1145 | LD1RO_zprr 1010010 .. 01 ..... 000 ... ..... ..... \ | |
1146 | @rprr_load_msz nreg=0 | |
1147 | ||
1148 | # SVE load and broadcast quadword (scalar plus immediate) | |
1149 | # LD1RQB, LD1RQH, LD1RQS, LD1RQD | |
1150 | LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ | |
1151 | @rpri_load_msz nreg=0 | |
1152 | LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \ | |
1153 | @rpri_load_msz nreg=0 | |
1154 | ||
1155 | # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) | |
1156 | PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- | |
1157 | ||
1158 | # SVE 32-bit gather prefetch (vector plus immediate) | |
1159 | PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- | |
1160 | ||
1161 | # SVE contiguous prefetch (scalar plus immediate) | |
1162 | PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- | |
1163 | ||
1164 | # SVE contiguous prefetch (scalar plus scalar) | |
1165 | PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ---- | |
1166 | ||
1167 | ### SVE Memory 64-bit Gather Group | |
1168 | ||
1169 | # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets) | |
1170 | # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) | |
1171 | LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \ | |
1172 | @rprr_g_load_xs_u esz=3 msz=0 scale=0 | |
1173 | LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \ | |
1174 | @rprr_g_load_xs_u_sc esz=3 msz=1 | |
1175 | LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \ | |
1176 | @rprr_g_load_xs_u_sc esz=3 msz=2 | |
1177 | LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \ | |
1178 | @rprr_g_load_xs_sc esz=3 msz=3 u=1 | |
1179 | ||
1180 | # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets) | |
1181 | # SVE 64-bit gather load (scalar plus 64-bit scaled offsets) | |
1182 | LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \ | |
1183 | @rprr_g_load_u esz=3 msz=0 scale=0 | |
1184 | LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \ | |
1185 | @rprr_g_load_u_sc esz=3 msz=1 | |
1186 | LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \ | |
1187 | @rprr_g_load_u_sc esz=3 msz=2 | |
1188 | LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \ | |
1189 | @rprr_g_load_sc esz=3 msz=3 u=1 | |
1190 | ||
1191 | # SVE 64-bit gather load (vector plus immediate) | |
1192 | LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ | |
1193 | @rpri_g_load esz=3 | |
1194 | ||
1195 | # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) | |
1196 | PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- | |
1197 | ||
1198 | # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) | |
1199 | PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- | |
1200 | ||
1201 | # SVE 64-bit gather prefetch (vector plus immediate) | |
1202 | PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- | |
1203 | ||
1204 | ### SVE Memory Store Group | |
1205 | ||
1206 | # SVE store predicate register | |
1207 | STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9 | |
1208 | ||
1209 | # SVE store vector register | |
1210 | STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9 | |
1211 | ||
1212 | # SVE contiguous store (scalar plus immediate) | |
1213 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
1214 | ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \ | |
1215 | @rpri_store_msz nreg=0 | |
1216 | ||
1217 | # SVE contiguous store (scalar plus scalar) | |
1218 | # ST1B, ST1H, ST1W, ST1D; require msz <= esz | |
1219 | # Enumerate msz lest we conflict with STR_zri. | |
1220 | ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ | |
1221 | @rprr_store_esz_n0 msz=0 | |
1222 | ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ | |
1223 | @rprr_store_esz_n0 msz=1 | |
1224 | ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \ | |
1225 | @rprr_store_esz_n0 msz=2 | |
1226 | ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ | |
1227 | @rprr_store msz=3 esz=3 nreg=0 | |
1228 | ||
1229 | # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) | |
1230 | # SVE store multiple structures (scalar plus immediate) (nreg != 0) | |
1231 | ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ | |
1232 | @rpri_store_msz esz=%size_23 | |
1233 | ||
1234 | # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) | |
1235 | # SVE store multiple structures (scalar plus scalar) (nreg != 0) | |
1236 | ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \ | |
1237 | @rprr_store esz=%size_23 | |
1238 | ||
1239 | # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets) | |
1240 | # Require msz > 0 && msz <= esz. | |
1241 | ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \ | |
1242 | @rprr_scatter_store xs=0 esz=2 scale=1 | |
1243 | ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \ | |
1244 | @rprr_scatter_store xs=1 esz=2 scale=1 | |
1245 | ||
1246 | # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets) | |
1247 | # Require msz <= esz. | |
1248 | ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \ | |
1249 | @rprr_scatter_store xs=0 esz=2 scale=0 | |
1250 | ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \ | |
1251 | @rprr_scatter_store xs=1 esz=2 scale=0 | |
1252 | ||
1253 | # SVE 64-bit scatter store (scalar plus 64-bit scaled offset) | |
1254 | # Require msz > 0 | |
1255 | ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \ | |
1256 | @rprr_scatter_store xs=2 esz=3 scale=1 | |
1257 | ||
1258 | # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset) | |
1259 | ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \ | |
1260 | @rprr_scatter_store xs=2 esz=3 scale=0 | |
1261 | ||
1262 | # SVE 64-bit scatter store (vector plus immediate) | |
1263 | ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \ | |
1264 | @rpri_scatter_store esz=3 | |
1265 | ||
1266 | # SVE 32-bit scatter store (vector plus immediate) | |
1267 | ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \ | |
1268 | @rpri_scatter_store esz=2 | |
1269 | ||
1270 | # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset) | |
1271 | # Require msz > 0 | |
1272 | ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \ | |
1273 | @rprr_scatter_store xs=0 esz=3 scale=1 | |
1274 | ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \ | |
1275 | @rprr_scatter_store xs=1 esz=3 scale=1 | |
1276 | ||
1277 | # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset) | |
1278 | ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \ | |
1279 | @rprr_scatter_store xs=0 esz=3 scale=0 | |
1280 | ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \ | |
1281 | @rprr_scatter_store xs=1 esz=3 scale=0 | |
1282 | ||
1283 | #### SVE2 Support | |
1284 | ||
1285 | ### SVE2 Integer Multiply - Unpredicated | |
1286 | ||
1287 | # SVE2 integer multiply vectors (unpredicated) | |
1288 | MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm | |
1289 | SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm | |
1290 | UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm | |
1291 | PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0 | |
1292 | ||
1293 | # SVE2 signed saturating doubling multiply high (unpredicated) | |
1294 | SQDMULH_zzz 00000100 .. 1 ..... 0111 00 ..... ..... @rd_rn_rm | |
1295 | SQRDMULH_zzz 00000100 .. 1 ..... 0111 01 ..... ..... @rd_rn_rm | |
1296 | ||
1297 | ### SVE2 Integer - Predicated | |
1298 | ||
1299 | SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn | |
1300 | UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn | |
1301 | ||
1302 | ### SVE2 integer unary operations (predicated) | |
1303 | ||
1304 | URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn | |
1305 | URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn | |
1306 | SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn | |
1307 | SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn | |
1308 | ||
1309 | ### SVE2 saturating/rounding bitwise shift left (predicated) | |
1310 | ||
1311 | SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm | |
1312 | URSHL 01000100 .. 000 011 100 ... ..... ..... @rdn_pg_rm | |
1313 | SRSHL 01000100 .. 000 110 100 ... ..... ..... @rdm_pg_rn # SRSHLR | |
1314 | URSHL 01000100 .. 000 111 100 ... ..... ..... @rdm_pg_rn # URSHLR | |
1315 | ||
1316 | SQSHL 01000100 .. 001 000 100 ... ..... ..... @rdn_pg_rm | |
1317 | UQSHL 01000100 .. 001 001 100 ... ..... ..... @rdn_pg_rm | |
1318 | SQSHL 01000100 .. 001 100 100 ... ..... ..... @rdm_pg_rn # SQSHLR | |
1319 | UQSHL 01000100 .. 001 101 100 ... ..... ..... @rdm_pg_rn # UQSHLR | |
1320 | ||
1321 | SQRSHL 01000100 .. 001 010 100 ... ..... ..... @rdn_pg_rm | |
1322 | UQRSHL 01000100 .. 001 011 100 ... ..... ..... @rdn_pg_rm | |
1323 | SQRSHL 01000100 .. 001 110 100 ... ..... ..... @rdm_pg_rn # SQRSHLR | |
1324 | UQRSHL 01000100 .. 001 111 100 ... ..... ..... @rdm_pg_rn # UQRSHLR | |
1325 | ||
1326 | ### SVE2 integer halving add/subtract (predicated) | |
1327 | ||
1328 | SHADD 01000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm | |
1329 | UHADD 01000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm | |
1330 | SHSUB 01000100 .. 010 010 100 ... ..... ..... @rdn_pg_rm | |
1331 | UHSUB 01000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm | |
1332 | SRHADD 01000100 .. 010 100 100 ... ..... ..... @rdn_pg_rm | |
1333 | URHADD 01000100 .. 010 101 100 ... ..... ..... @rdn_pg_rm | |
1334 | SHSUB 01000100 .. 010 110 100 ... ..... ..... @rdm_pg_rn # SHSUBR | |
1335 | UHSUB 01000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # UHSUBR | |
1336 | ||
1337 | ### SVE2 integer pairwise arithmetic | |
1338 | ||
1339 | ADDP 01000100 .. 010 001 101 ... ..... ..... @rdn_pg_rm | |
1340 | SMAXP 01000100 .. 010 100 101 ... ..... ..... @rdn_pg_rm | |
1341 | UMAXP 01000100 .. 010 101 101 ... ..... ..... @rdn_pg_rm | |
1342 | SMINP 01000100 .. 010 110 101 ... ..... ..... @rdn_pg_rm | |
1343 | UMINP 01000100 .. 010 111 101 ... ..... ..... @rdn_pg_rm | |
1344 | ||
1345 | ### SVE2 saturating add/subtract (predicated) | |
1346 | ||
1347 | SQADD_zpzz 01000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm | |
1348 | UQADD_zpzz 01000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm | |
1349 | SQSUB_zpzz 01000100 .. 011 010 100 ... ..... ..... @rdn_pg_rm | |
1350 | UQSUB_zpzz 01000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm | |
1351 | SUQADD 01000100 .. 011 100 100 ... ..... ..... @rdn_pg_rm | |
1352 | USQADD 01000100 .. 011 101 100 ... ..... ..... @rdn_pg_rm | |
1353 | SQSUB_zpzz 01000100 .. 011 110 100 ... ..... ..... @rdm_pg_rn # SQSUBR | |
1354 | UQSUB_zpzz 01000100 .. 011 111 100 ... ..... ..... @rdm_pg_rn # UQSUBR | |
1355 | ||
1356 | #### SVE2 Widening Integer Arithmetic | |
1357 | ||
1358 | ## SVE2 integer add/subtract long | |
1359 | ||
1360 | SADDLB 01000101 .. 0 ..... 00 0000 ..... ..... @rd_rn_rm | |
1361 | SADDLT 01000101 .. 0 ..... 00 0001 ..... ..... @rd_rn_rm | |
1362 | UADDLB 01000101 .. 0 ..... 00 0010 ..... ..... @rd_rn_rm | |
1363 | UADDLT 01000101 .. 0 ..... 00 0011 ..... ..... @rd_rn_rm | |
1364 | ||
1365 | SSUBLB 01000101 .. 0 ..... 00 0100 ..... ..... @rd_rn_rm | |
1366 | SSUBLT 01000101 .. 0 ..... 00 0101 ..... ..... @rd_rn_rm | |
1367 | USUBLB 01000101 .. 0 ..... 00 0110 ..... ..... @rd_rn_rm | |
1368 | USUBLT 01000101 .. 0 ..... 00 0111 ..... ..... @rd_rn_rm | |
1369 | ||
1370 | SABDLB 01000101 .. 0 ..... 00 1100 ..... ..... @rd_rn_rm | |
1371 | SABDLT 01000101 .. 0 ..... 00 1101 ..... ..... @rd_rn_rm | |
1372 | UABDLB 01000101 .. 0 ..... 00 1110 ..... ..... @rd_rn_rm | |
1373 | UABDLT 01000101 .. 0 ..... 00 1111 ..... ..... @rd_rn_rm | |
1374 | ||
1375 | ## SVE2 integer add/subtract interleaved long | |
1376 | ||
1377 | SADDLBT 01000101 .. 0 ..... 1000 00 ..... ..... @rd_rn_rm | |
1378 | SSUBLBT 01000101 .. 0 ..... 1000 10 ..... ..... @rd_rn_rm | |
1379 | SSUBLTB 01000101 .. 0 ..... 1000 11 ..... ..... @rd_rn_rm | |
1380 | ||
1381 | ## SVE2 integer add/subtract wide | |
1382 | ||
1383 | SADDWB 01000101 .. 0 ..... 010 000 ..... ..... @rd_rn_rm | |
1384 | SADDWT 01000101 .. 0 ..... 010 001 ..... ..... @rd_rn_rm | |
1385 | UADDWB 01000101 .. 0 ..... 010 010 ..... ..... @rd_rn_rm | |
1386 | UADDWT 01000101 .. 0 ..... 010 011 ..... ..... @rd_rn_rm | |
1387 | ||
1388 | SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm | |
1389 | SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm | |
1390 | USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm | |
1391 | USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm | |
1392 | ||
1393 | ## SVE2 integer multiply long | |
1394 | ||
1395 | SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm | |
1396 | SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm | |
1397 | PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm | |
1398 | PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm | |
1399 | SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm | |
1400 | SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm | |
1401 | UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm | |
1402 | UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm | |
1403 | ||
1404 | ## SVE2 bitwise shift left long | |
1405 | ||
1406 | # Note bit23 == 0 is handled by esz > 0 in do_sve2_shll_tb. | |
1407 | SSHLLB 01000101 .. 0 ..... 1010 00 ..... ..... @rd_rn_tszimm_shl | |
1408 | SSHLLT 01000101 .. 0 ..... 1010 01 ..... ..... @rd_rn_tszimm_shl | |
1409 | USHLLB 01000101 .. 0 ..... 1010 10 ..... ..... @rd_rn_tszimm_shl | |
1410 | USHLLT 01000101 .. 0 ..... 1010 11 ..... ..... @rd_rn_tszimm_shl | |
1411 | ||
1412 | ## SVE2 bitwise exclusive-or interleaved | |
1413 | ||
1414 | EORBT 01000101 .. 0 ..... 10010 0 ..... ..... @rd_rn_rm | |
1415 | EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm | |
1416 | ||
1417 | ## SVE integer matrix multiply accumulate | |
1418 | ||
1419 | SMMLA 01000101 00 0 ..... 10011 0 ..... ..... @rda_rn_rm_e0 | |
1420 | USMMLA 01000101 10 0 ..... 10011 0 ..... ..... @rda_rn_rm_e0 | |
1421 | UMMLA 01000101 11 0 ..... 10011 0 ..... ..... @rda_rn_rm_e0 | |
1422 | ||
1423 | ## SVE2 bitwise permute | |
1424 | ||
1425 | BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm | |
1426 | BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm | |
1427 | BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm | |
1428 | ||
1429 | #### SVE2 Accumulate | |
1430 | ||
1431 | ## SVE2 complex integer add | |
1432 | ||
1433 | CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm | |
1434 | CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm | |
1435 | SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm | |
1436 | SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm | |
1437 | ||
1438 | ## SVE2 integer absolute difference and accumulate long | |
1439 | ||
1440 | SABALB 01000101 .. 0 ..... 1100 00 ..... ..... @rda_rn_rm | |
1441 | SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm | |
1442 | UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm | |
1443 | UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm | |
1444 | ||
1445 | ## SVE2 integer add/subtract long with carry | |
1446 | ||
1447 | # ADC and SBC decoded via size in helper dispatch. | |
1448 | ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm | |
1449 | ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm | |
1450 | ||
1451 | ## SVE2 bitwise shift right and accumulate | |
1452 | ||
1453 | # TODO: Use @rda and %reg_movprfx here. | |
1454 | SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr | |
1455 | USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr | |
1456 | SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr | |
1457 | URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr | |
1458 | ||
1459 | ## SVE2 bitwise shift and insert | |
1460 | ||
1461 | SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr | |
1462 | SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl | |
1463 | ||
1464 | ## SVE2 integer absolute difference and accumulate | |
1465 | ||
1466 | # TODO: Use @rda and %reg_movprfx here. | |
1467 | SABA 01000101 .. 0 ..... 11111 0 ..... ..... @rd_rn_rm | |
1468 | UABA 01000101 .. 0 ..... 11111 1 ..... ..... @rd_rn_rm | |
1469 | ||
1470 | #### SVE2 Narrowing | |
1471 | ||
1472 | ## SVE2 saturating extract narrow | |
1473 | ||
1474 | # Bits 23, 18-16 are zero, limited in the translator via esz < 3 & imm == 0. | |
1475 | SQXTNB 01000101 .. 1 ..... 010 000 ..... ..... @rd_rn_tszimm_shl | |
1476 | SQXTNT 01000101 .. 1 ..... 010 001 ..... ..... @rd_rn_tszimm_shl | |
1477 | UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl | |
1478 | UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl | |
1479 | SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl | |
1480 | SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl | |
1481 | ||
1482 | ## SVE2 bitwise shift right narrow | |
1483 | ||
1484 | # Bit 23 == 0 is handled by esz > 0 in the translator. | |
1485 | SQSHRUNB 01000101 .. 1 ..... 00 0000 ..... ..... @rd_rn_tszimm_shr | |
1486 | SQSHRUNT 01000101 .. 1 ..... 00 0001 ..... ..... @rd_rn_tszimm_shr | |
1487 | SQRSHRUNB 01000101 .. 1 ..... 00 0010 ..... ..... @rd_rn_tszimm_shr | |
1488 | SQRSHRUNT 01000101 .. 1 ..... 00 0011 ..... ..... @rd_rn_tszimm_shr | |
1489 | SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr | |
1490 | SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr | |
1491 | RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr | |
1492 | RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr | |
1493 | SQSHRNB 01000101 .. 1 ..... 00 1000 ..... ..... @rd_rn_tszimm_shr | |
1494 | SQSHRNT 01000101 .. 1 ..... 00 1001 ..... ..... @rd_rn_tszimm_shr | |
1495 | SQRSHRNB 01000101 .. 1 ..... 00 1010 ..... ..... @rd_rn_tszimm_shr | |
1496 | SQRSHRNT 01000101 .. 1 ..... 00 1011 ..... ..... @rd_rn_tszimm_shr | |
1497 | UQSHRNB 01000101 .. 1 ..... 00 1100 ..... ..... @rd_rn_tszimm_shr | |
1498 | UQSHRNT 01000101 .. 1 ..... 00 1101 ..... ..... @rd_rn_tszimm_shr | |
1499 | UQRSHRNB 01000101 .. 1 ..... 00 1110 ..... ..... @rd_rn_tszimm_shr | |
1500 | UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... ..... @rd_rn_tszimm_shr | |
1501 | ||
1502 | ## SVE2 integer add/subtract narrow high part | |
1503 | ||
1504 | ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm | |
1505 | ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm | |
1506 | RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm | |
1507 | RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm | |
1508 | SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm | |
1509 | SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm | |
1510 | RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm | |
1511 | RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm | |
1512 | ||
1513 | ### SVE2 Character Match | |
1514 | ||
1515 | MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm | |
1516 | NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm | |
1517 | ||
1518 | ### SVE2 Histogram Computation | |
1519 | ||
1520 | HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm | |
1521 | HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm | |
1522 | ||
1523 | ## SVE2 floating-point pairwise operations | |
1524 | ||
1525 | FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm | |
1526 | FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm | |
1527 | FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm | |
1528 | FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm | |
1529 | FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm | |
1530 | ||
1531 | #### SVE Integer Multiply-Add (unpredicated) | |
1532 | ||
1533 | ## SVE2 saturating multiply-add long | |
1534 | ||
1535 | SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm | |
1536 | SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm | |
1537 | SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm | |
1538 | SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm | |
1539 | ||
1540 | ## SVE2 saturating multiply-add interleaved long | |
1541 | ||
1542 | SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm | |
1543 | SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm | |
1544 | ||
1545 | ## SVE2 saturating multiply-add high | |
1546 | ||
1547 | SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm | |
1548 | SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm | |
1549 | ||
1550 | ## SVE2 integer multiply-add long | |
1551 | ||
1552 | SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm | |
1553 | SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm | |
1554 | UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm | |
1555 | UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm | |
1556 | SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm | |
1557 | SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm | |
1558 | UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm | |
1559 | UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm | |
1560 | ||
1561 | ## SVE2 complex integer multiply-add | |
1562 | ||
1563 | CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx | |
1564 | SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx | |
1565 | ||
1566 | ## SVE mixed sign dot product | |
1567 | ||
1568 | USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm | |
1569 | ||
1570 | ### SVE2 floating point matrix multiply accumulate | |
1571 | { | |
1572 | BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0 | |
1573 | FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm | |
1574 | } | |
1575 | ||
1576 | ### SVE2 Memory Gather Load Group | |
1577 | ||
1578 | # SVE2 64-bit gather non-temporal load | |
1579 | # (scalar plus unpacked 32-bit unscaled offsets) | |
1580 | LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ | |
1581 | &rprr_gather_load xs=0 esz=3 scale=0 ff=0 | |
1582 | ||
1583 | # SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) | |
1584 | LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ | |
1585 | &rprr_gather_load xs=0 esz=2 scale=0 ff=0 | |
1586 | ||
1587 | ### SVE2 Memory Store Group | |
1588 | ||
1589 | # SVE2 64-bit scatter non-temporal store (vector plus scalar) | |
1590 | STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \ | |
1591 | @rprr_scatter_store xs=2 esz=3 scale=0 | |
1592 | ||
1593 | # SVE2 32-bit scatter non-temporal store (vector plus scalar) | |
1594 | STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \ | |
1595 | @rprr_scatter_store xs=0 esz=2 scale=0 | |
1596 | ||
1597 | ### SVE2 Crypto Extensions | |
1598 | ||
1599 | # SVE2 crypto unary operations | |
1600 | # AESMC and AESIMC | |
1601 | AESMC 01000101 00 10000011100 decrypt:1 00000 rd:5 | |
1602 | ||
1603 | # SVE2 crypto destructive binary operations | |
1604 | AESE 01000101 00 10001 0 11100 0 ..... ..... @rdn_rm_e0 | |
1605 | AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0 | |
1606 | SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0 | |
1607 | ||
1608 | # SVE2 crypto constructive binary operations | |
1609 | SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 | |
1610 | RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 | |
1611 | ||
1612 | ### SVE2 floating-point convert precision odd elements | |
1613 | FCVTXNT_ds 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 | |
1614 | FCVTX_ds 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 | |
1615 | FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 | |
1616 | BFCVTNT 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 | |
1617 | FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 | |
1618 | FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 | |
1619 | FCVTLT_sd 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 | |
1620 | ||
1621 | ### SVE2 floating-point convert to integer | |
1622 | FLOGB 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz | |
1623 | ||
1624 | ### SVE2 floating-point multiply-add long (vectors) | |
1625 | FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_e0 | |
1626 | FMLALT_zzzw 01100100 10 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_e0 | |
1627 | FMLSLB_zzzw 01100100 10 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_e0 | |
1628 | FMLSLT_zzzw 01100100 10 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_e0 | |
1629 | ||
1630 | BFMLALB_zzzw 01100100 11 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_e0 | |
1631 | BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_e0 | |
1632 | ||
1633 | ### SVE2 floating-point bfloat16 dot-product | |
1634 | BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_e0 | |
1635 | ||
1636 | ### SVE2 floating-point multiply-add long (indexed) | |
1637 | FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2 | |
1638 | FMLALT_zzxw 01100100 10 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 | |
1639 | FMLSLB_zzxw 01100100 10 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2 | |
1640 | FMLSLT_zzxw 01100100 10 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2 | |
1641 | BFMLALB_zzxw 01100100 11 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2 | |
1642 | BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 | |
1643 | ||
1644 | ### SVE2 floating-point bfloat16 dot-product (indexed) | |
1645 | BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2 |