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1 | /* | |
2 | * i386 virtual CPU header | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef I386_CPU_H | |
21 | #define I386_CPU_H | |
22 | ||
23 | #include "sysemu/tcg.h" | |
24 | #include "cpu-qom.h" | |
25 | #include "kvm/hyperv-proto.h" | |
26 | #include "exec/cpu-defs.h" | |
27 | #include "qapi/qapi-types-common.h" | |
28 | #include "qemu/cpu-float.h" | |
29 | #include "qemu/timer.h" | |
30 | ||
31 | #define XEN_NR_VIRQS 24 | |
32 | ||
33 | #define KVM_HAVE_MCE_INJECTION 1 | |
34 | ||
35 | /* support for self modifying code even if the modified instruction is | |
36 | close to the modifying instruction */ | |
37 | #define TARGET_HAS_PRECISE_SMC | |
38 | ||
39 | #ifdef TARGET_X86_64 | |
40 | #define I386_ELF_MACHINE EM_X86_64 | |
41 | #define ELF_MACHINE_UNAME "x86_64" | |
42 | #else | |
43 | #define I386_ELF_MACHINE EM_386 | |
44 | #define ELF_MACHINE_UNAME "i686" | |
45 | #endif | |
46 | ||
47 | enum { | |
48 | R_EAX = 0, | |
49 | R_ECX = 1, | |
50 | R_EDX = 2, | |
51 | R_EBX = 3, | |
52 | R_ESP = 4, | |
53 | R_EBP = 5, | |
54 | R_ESI = 6, | |
55 | R_EDI = 7, | |
56 | R_R8 = 8, | |
57 | R_R9 = 9, | |
58 | R_R10 = 10, | |
59 | R_R11 = 11, | |
60 | R_R12 = 12, | |
61 | R_R13 = 13, | |
62 | R_R14 = 14, | |
63 | R_R15 = 15, | |
64 | ||
65 | R_AL = 0, | |
66 | R_CL = 1, | |
67 | R_DL = 2, | |
68 | R_BL = 3, | |
69 | R_AH = 4, | |
70 | R_CH = 5, | |
71 | R_DH = 6, | |
72 | R_BH = 7, | |
73 | }; | |
74 | ||
75 | typedef enum X86Seg { | |
76 | R_ES = 0, | |
77 | R_CS = 1, | |
78 | R_SS = 2, | |
79 | R_DS = 3, | |
80 | R_FS = 4, | |
81 | R_GS = 5, | |
82 | R_LDTR = 6, | |
83 | R_TR = 7, | |
84 | } X86Seg; | |
85 | ||
86 | /* segment descriptor fields */ | |
87 | #define DESC_G_SHIFT 23 | |
88 | #define DESC_G_MASK (1 << DESC_G_SHIFT) | |
89 | #define DESC_B_SHIFT 22 | |
90 | #define DESC_B_MASK (1 << DESC_B_SHIFT) | |
91 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ | |
92 | #define DESC_L_MASK (1 << DESC_L_SHIFT) | |
93 | #define DESC_AVL_SHIFT 20 | |
94 | #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT) | |
95 | #define DESC_P_SHIFT 15 | |
96 | #define DESC_P_MASK (1 << DESC_P_SHIFT) | |
97 | #define DESC_DPL_SHIFT 13 | |
98 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) | |
99 | #define DESC_S_SHIFT 12 | |
100 | #define DESC_S_MASK (1 << DESC_S_SHIFT) | |
101 | #define DESC_TYPE_SHIFT 8 | |
102 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) | |
103 | #define DESC_A_MASK (1 << 8) | |
104 | ||
105 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ | |
106 | #define DESC_C_MASK (1 << 10) /* code: conforming */ | |
107 | #define DESC_R_MASK (1 << 9) /* code: readable */ | |
108 | ||
109 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ | |
110 | #define DESC_W_MASK (1 << 9) /* data: writable */ | |
111 | ||
112 | #define DESC_TSS_BUSY_MASK (1 << 9) | |
113 | ||
114 | /* eflags masks */ | |
115 | #define CC_C 0x0001 | |
116 | #define CC_P 0x0004 | |
117 | #define CC_A 0x0010 | |
118 | #define CC_Z 0x0040 | |
119 | #define CC_S 0x0080 | |
120 | #define CC_O 0x0800 | |
121 | ||
122 | #define TF_SHIFT 8 | |
123 | #define IOPL_SHIFT 12 | |
124 | #define VM_SHIFT 17 | |
125 | ||
126 | #define TF_MASK 0x00000100 | |
127 | #define IF_MASK 0x00000200 | |
128 | #define DF_MASK 0x00000400 | |
129 | #define IOPL_MASK 0x00003000 | |
130 | #define NT_MASK 0x00004000 | |
131 | #define RF_MASK 0x00010000 | |
132 | #define VM_MASK 0x00020000 | |
133 | #define AC_MASK 0x00040000 | |
134 | #define VIF_MASK 0x00080000 | |
135 | #define VIP_MASK 0x00100000 | |
136 | #define ID_MASK 0x00200000 | |
137 | ||
138 | /* hidden flags - used internally by qemu to represent additional cpu | |
139 | states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We | |
140 | avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit | |
141 | positions to ease oring with eflags. */ | |
142 | /* current cpl */ | |
143 | #define HF_CPL_SHIFT 0 | |
144 | /* true if hardware interrupts must be disabled for next instruction */ | |
145 | #define HF_INHIBIT_IRQ_SHIFT 3 | |
146 | /* 16 or 32 segments */ | |
147 | #define HF_CS32_SHIFT 4 | |
148 | #define HF_SS32_SHIFT 5 | |
149 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ | |
150 | #define HF_ADDSEG_SHIFT 6 | |
151 | /* copy of CR0.PE (protected mode) */ | |
152 | #define HF_PE_SHIFT 7 | |
153 | #define HF_TF_SHIFT 8 /* must be same as eflags */ | |
154 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ | |
155 | #define HF_EM_SHIFT 10 | |
156 | #define HF_TS_SHIFT 11 | |
157 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ | |
158 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ | |
159 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ | |
160 | #define HF_RF_SHIFT 16 /* must be same as eflags */ | |
161 | #define HF_VM_SHIFT 17 /* must be same as eflags */ | |
162 | #define HF_AC_SHIFT 18 /* must be same as eflags */ | |
163 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ | |
164 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ | |
165 | #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */ | |
166 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ | |
167 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ | |
168 | #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ | |
169 | #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ | |
170 | #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ | |
171 | #define HF_UMIP_SHIFT 27 /* CR4.UMIP */ | |
172 | #define HF_AVX_EN_SHIFT 28 /* AVX Enabled (CR4+XCR0) */ | |
173 | ||
174 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) | |
175 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) | |
176 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) | |
177 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) | |
178 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) | |
179 | #define HF_PE_MASK (1 << HF_PE_SHIFT) | |
180 | #define HF_TF_MASK (1 << HF_TF_SHIFT) | |
181 | #define HF_MP_MASK (1 << HF_MP_SHIFT) | |
182 | #define HF_EM_MASK (1 << HF_EM_SHIFT) | |
183 | #define HF_TS_MASK (1 << HF_TS_SHIFT) | |
184 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) | |
185 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) | |
186 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) | |
187 | #define HF_RF_MASK (1 << HF_RF_SHIFT) | |
188 | #define HF_VM_MASK (1 << HF_VM_SHIFT) | |
189 | #define HF_AC_MASK (1 << HF_AC_SHIFT) | |
190 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) | |
191 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) | |
192 | #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT) | |
193 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) | |
194 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) | |
195 | #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) | |
196 | #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) | |
197 | #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) | |
198 | #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT) | |
199 | #define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT) | |
200 | ||
201 | /* hflags2 */ | |
202 | ||
203 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ | |
204 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ | |
205 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ | |
206 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ | |
207 | #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ | |
208 | #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ | |
209 | #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */ | |
210 | #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */ | |
211 | #define HF2_VGIF_SHIFT 8 /* Can take VIRQ*/ | |
212 | ||
213 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) | |
214 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) | |
215 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) | |
216 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) | |
217 | #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) | |
218 | #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) | |
219 | #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT) | |
220 | #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT) | |
221 | #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT) | |
222 | ||
223 | #define CR0_PE_SHIFT 0 | |
224 | #define CR0_MP_SHIFT 1 | |
225 | ||
226 | #define CR0_PE_MASK (1U << 0) | |
227 | #define CR0_MP_MASK (1U << 1) | |
228 | #define CR0_EM_MASK (1U << 2) | |
229 | #define CR0_TS_MASK (1U << 3) | |
230 | #define CR0_ET_MASK (1U << 4) | |
231 | #define CR0_NE_MASK (1U << 5) | |
232 | #define CR0_WP_MASK (1U << 16) | |
233 | #define CR0_AM_MASK (1U << 18) | |
234 | #define CR0_NW_MASK (1U << 29) | |
235 | #define CR0_CD_MASK (1U << 30) | |
236 | #define CR0_PG_MASK (1U << 31) | |
237 | ||
238 | #define CR4_VME_MASK (1U << 0) | |
239 | #define CR4_PVI_MASK (1U << 1) | |
240 | #define CR4_TSD_MASK (1U << 2) | |
241 | #define CR4_DE_MASK (1U << 3) | |
242 | #define CR4_PSE_MASK (1U << 4) | |
243 | #define CR4_PAE_MASK (1U << 5) | |
244 | #define CR4_MCE_MASK (1U << 6) | |
245 | #define CR4_PGE_MASK (1U << 7) | |
246 | #define CR4_PCE_MASK (1U << 8) | |
247 | #define CR4_OSFXSR_SHIFT 9 | |
248 | #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) | |
249 | #define CR4_OSXMMEXCPT_MASK (1U << 10) | |
250 | #define CR4_UMIP_MASK (1U << 11) | |
251 | #define CR4_LA57_MASK (1U << 12) | |
252 | #define CR4_VMXE_MASK (1U << 13) | |
253 | #define CR4_SMXE_MASK (1U << 14) | |
254 | #define CR4_FSGSBASE_MASK (1U << 16) | |
255 | #define CR4_PCIDE_MASK (1U << 17) | |
256 | #define CR4_OSXSAVE_MASK (1U << 18) | |
257 | #define CR4_SMEP_MASK (1U << 20) | |
258 | #define CR4_SMAP_MASK (1U << 21) | |
259 | #define CR4_PKE_MASK (1U << 22) | |
260 | #define CR4_PKS_MASK (1U << 24) | |
261 | ||
262 | #define CR4_RESERVED_MASK \ | |
263 | (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \ | |
264 | | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ | |
265 | | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ | |
266 | | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \ | |
267 | | CR4_LA57_MASK \ | |
268 | | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ | |
269 | | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) | |
270 | ||
271 | #define DR6_BD (1 << 13) | |
272 | #define DR6_BS (1 << 14) | |
273 | #define DR6_BT (1 << 15) | |
274 | #define DR6_FIXED_1 0xffff0ff0 | |
275 | ||
276 | #define DR7_GD (1 << 13) | |
277 | #define DR7_TYPE_SHIFT 16 | |
278 | #define DR7_LEN_SHIFT 18 | |
279 | #define DR7_FIXED_1 0x00000400 | |
280 | #define DR7_GLOBAL_BP_MASK 0xaa | |
281 | #define DR7_LOCAL_BP_MASK 0x55 | |
282 | #define DR7_MAX_BP 4 | |
283 | #define DR7_TYPE_BP_INST 0x0 | |
284 | #define DR7_TYPE_DATA_WR 0x1 | |
285 | #define DR7_TYPE_IO_RW 0x2 | |
286 | #define DR7_TYPE_DATA_RW 0x3 | |
287 | ||
288 | #define DR_RESERVED_MASK 0xffffffff00000000ULL | |
289 | ||
290 | #define PG_PRESENT_BIT 0 | |
291 | #define PG_RW_BIT 1 | |
292 | #define PG_USER_BIT 2 | |
293 | #define PG_PWT_BIT 3 | |
294 | #define PG_PCD_BIT 4 | |
295 | #define PG_ACCESSED_BIT 5 | |
296 | #define PG_DIRTY_BIT 6 | |
297 | #define PG_PSE_BIT 7 | |
298 | #define PG_GLOBAL_BIT 8 | |
299 | #define PG_PSE_PAT_BIT 12 | |
300 | #define PG_PKRU_BIT 59 | |
301 | #define PG_NX_BIT 63 | |
302 | ||
303 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) | |
304 | #define PG_RW_MASK (1 << PG_RW_BIT) | |
305 | #define PG_USER_MASK (1 << PG_USER_BIT) | |
306 | #define PG_PWT_MASK (1 << PG_PWT_BIT) | |
307 | #define PG_PCD_MASK (1 << PG_PCD_BIT) | |
308 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
309 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) | |
310 | #define PG_PSE_MASK (1 << PG_PSE_BIT) | |
311 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) | |
312 | #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) | |
313 | #define PG_ADDRESS_MASK 0x000ffffffffff000LL | |
314 | #define PG_HI_USER_MASK 0x7ff0000000000000LL | |
315 | #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) | |
316 | #define PG_NX_MASK (1ULL << PG_NX_BIT) | |
317 | ||
318 | #define PG_ERROR_W_BIT 1 | |
319 | ||
320 | #define PG_ERROR_P_MASK 0x01 | |
321 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) | |
322 | #define PG_ERROR_U_MASK 0x04 | |
323 | #define PG_ERROR_RSVD_MASK 0x08 | |
324 | #define PG_ERROR_I_D_MASK 0x10 | |
325 | #define PG_ERROR_PK_MASK 0x20 | |
326 | ||
327 | #define PG_MODE_PAE (1 << 0) | |
328 | #define PG_MODE_LMA (1 << 1) | |
329 | #define PG_MODE_NXE (1 << 2) | |
330 | #define PG_MODE_PSE (1 << 3) | |
331 | #define PG_MODE_LA57 (1 << 4) | |
332 | #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15) | |
333 | ||
334 | /* Bits of CR4 that do not affect the NPT page format. */ | |
335 | #define PG_MODE_WP (1 << 16) | |
336 | #define PG_MODE_PKE (1 << 17) | |
337 | #define PG_MODE_PKS (1 << 18) | |
338 | #define PG_MODE_SMEP (1 << 19) | |
339 | ||
340 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ | |
341 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
342 | #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ | |
343 | ||
344 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) | |
345 | #define MCE_BANKS_DEF 10 | |
346 | ||
347 | #define MCG_CAP_BANKS_MASK 0xff | |
348 | ||
349 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ | |
350 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
351 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ | |
352 | #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ | |
353 | ||
354 | #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ | |
355 | ||
356 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ | |
357 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
358 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
359 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ | |
360 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
361 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
362 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
363 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
364 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
365 | ||
366 | /* MISC register defines */ | |
367 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ | |
368 | #define MCM_ADDR_LINEAR 1 /* linear address */ | |
369 | #define MCM_ADDR_PHYS 2 /* physical address */ | |
370 | #define MCM_ADDR_MEM 3 /* memory address */ | |
371 | #define MCM_ADDR_GENERIC 7 /* generic */ | |
372 | ||
373 | #define MSR_IA32_TSC 0x10 | |
374 | #define MSR_IA32_APICBASE 0x1b | |
375 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
376 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
377 | #define MSR_IA32_APICBASE_EXTD (1 << 10) | |
378 | #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) | |
379 | #define MSR_IA32_APICBASE_RESERVED \ | |
380 | (~(uint64_t)(MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE \ | |
381 | | MSR_IA32_APICBASE_EXTD | MSR_IA32_APICBASE_BASE)) | |
382 | ||
383 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a | |
384 | #define MSR_TSC_ADJUST 0x0000003b | |
385 | #define MSR_IA32_SPEC_CTRL 0x48 | |
386 | #define MSR_VIRT_SSBD 0xc001011f | |
387 | #define MSR_IA32_PRED_CMD 0x49 | |
388 | #define MSR_IA32_UCODE_REV 0x8b | |
389 | #define MSR_IA32_CORE_CAPABILITY 0xcf | |
390 | ||
391 | #define MSR_IA32_ARCH_CAPABILITIES 0x10a | |
392 | #define ARCH_CAP_TSX_CTRL_MSR (1<<7) | |
393 | ||
394 | #define MSR_IA32_PERF_CAPABILITIES 0x345 | |
395 | #define PERF_CAP_LBR_FMT 0x3f | |
396 | ||
397 | #define MSR_IA32_TSX_CTRL 0x122 | |
398 | #define MSR_IA32_TSCDEADLINE 0x6e0 | |
399 | #define MSR_IA32_PKRS 0x6e1 | |
400 | #define MSR_ARCH_LBR_CTL 0x000014ce | |
401 | #define MSR_ARCH_LBR_DEPTH 0x000014cf | |
402 | #define MSR_ARCH_LBR_FROM_0 0x00001500 | |
403 | #define MSR_ARCH_LBR_TO_0 0x00001600 | |
404 | #define MSR_ARCH_LBR_INFO_0 0x00001200 | |
405 | ||
406 | #define FEATURE_CONTROL_LOCKED (1<<0) | |
407 | #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1) | |
408 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) | |
409 | #define FEATURE_CONTROL_SGX_LC (1ULL << 17) | |
410 | #define FEATURE_CONTROL_SGX (1ULL << 18) | |
411 | #define FEATURE_CONTROL_LMCE (1<<20) | |
412 | ||
413 | #define MSR_IA32_SGXLEPUBKEYHASH0 0x8c | |
414 | #define MSR_IA32_SGXLEPUBKEYHASH1 0x8d | |
415 | #define MSR_IA32_SGXLEPUBKEYHASH2 0x8e | |
416 | #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f | |
417 | ||
418 | #define MSR_P6_PERFCTR0 0xc1 | |
419 | ||
420 | #define MSR_IA32_SMBASE 0x9e | |
421 | #define MSR_SMI_COUNT 0x34 | |
422 | #define MSR_CORE_THREAD_COUNT 0x35 | |
423 | #define MSR_MTRRcap 0xfe | |
424 | #define MSR_MTRRcap_VCNT 8 | |
425 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) | |
426 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) | |
427 | ||
428 | #define MSR_IA32_SYSENTER_CS 0x174 | |
429 | #define MSR_IA32_SYSENTER_ESP 0x175 | |
430 | #define MSR_IA32_SYSENTER_EIP 0x176 | |
431 | ||
432 | #define MSR_MCG_CAP 0x179 | |
433 | #define MSR_MCG_STATUS 0x17a | |
434 | #define MSR_MCG_CTL 0x17b | |
435 | #define MSR_MCG_EXT_CTL 0x4d0 | |
436 | ||
437 | #define MSR_P6_EVNTSEL0 0x186 | |
438 | ||
439 | #define MSR_IA32_PERF_STATUS 0x198 | |
440 | ||
441 | #define MSR_IA32_MISC_ENABLE 0x1a0 | |
442 | /* Indicates good rep/movs microcode on some processors: */ | |
443 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 | |
444 | #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) | |
445 | ||
446 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) | |
447 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) | |
448 | ||
449 | #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) | |
450 | ||
451 | #define MSR_MTRRfix64K_00000 0x250 | |
452 | #define MSR_MTRRfix16K_80000 0x258 | |
453 | #define MSR_MTRRfix16K_A0000 0x259 | |
454 | #define MSR_MTRRfix4K_C0000 0x268 | |
455 | #define MSR_MTRRfix4K_C8000 0x269 | |
456 | #define MSR_MTRRfix4K_D0000 0x26a | |
457 | #define MSR_MTRRfix4K_D8000 0x26b | |
458 | #define MSR_MTRRfix4K_E0000 0x26c | |
459 | #define MSR_MTRRfix4K_E8000 0x26d | |
460 | #define MSR_MTRRfix4K_F0000 0x26e | |
461 | #define MSR_MTRRfix4K_F8000 0x26f | |
462 | ||
463 | #define MSR_PAT 0x277 | |
464 | ||
465 | #define MSR_MTRRdefType 0x2ff | |
466 | ||
467 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 | |
468 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | |
469 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | |
470 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | |
471 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | |
472 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | |
473 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | |
474 | ||
475 | #define MSR_MC0_CTL 0x400 | |
476 | #define MSR_MC0_STATUS 0x401 | |
477 | #define MSR_MC0_ADDR 0x402 | |
478 | #define MSR_MC0_MISC 0x403 | |
479 | ||
480 | #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 | |
481 | #define MSR_IA32_RTIT_OUTPUT_MASK 0x561 | |
482 | #define MSR_IA32_RTIT_CTL 0x570 | |
483 | #define MSR_IA32_RTIT_STATUS 0x571 | |
484 | #define MSR_IA32_RTIT_CR3_MATCH 0x572 | |
485 | #define MSR_IA32_RTIT_ADDR0_A 0x580 | |
486 | #define MSR_IA32_RTIT_ADDR0_B 0x581 | |
487 | #define MSR_IA32_RTIT_ADDR1_A 0x582 | |
488 | #define MSR_IA32_RTIT_ADDR1_B 0x583 | |
489 | #define MSR_IA32_RTIT_ADDR2_A 0x584 | |
490 | #define MSR_IA32_RTIT_ADDR2_B 0x585 | |
491 | #define MSR_IA32_RTIT_ADDR3_A 0x586 | |
492 | #define MSR_IA32_RTIT_ADDR3_B 0x587 | |
493 | #define MAX_RTIT_ADDRS 8 | |
494 | ||
495 | #define MSR_EFER 0xc0000080 | |
496 | ||
497 | #define MSR_EFER_SCE (1 << 0) | |
498 | #define MSR_EFER_LME (1 << 8) | |
499 | #define MSR_EFER_LMA (1 << 10) | |
500 | #define MSR_EFER_NXE (1 << 11) | |
501 | #define MSR_EFER_SVME (1 << 12) | |
502 | #define MSR_EFER_FFXSR (1 << 14) | |
503 | ||
504 | #define MSR_EFER_RESERVED\ | |
505 | (~(target_ulong)(MSR_EFER_SCE | MSR_EFER_LME\ | |
506 | | MSR_EFER_LMA | MSR_EFER_NXE | MSR_EFER_SVME\ | |
507 | | MSR_EFER_FFXSR)) | |
508 | ||
509 | #define MSR_STAR 0xc0000081 | |
510 | #define MSR_LSTAR 0xc0000082 | |
511 | #define MSR_CSTAR 0xc0000083 | |
512 | #define MSR_FMASK 0xc0000084 | |
513 | #define MSR_FSBASE 0xc0000100 | |
514 | #define MSR_GSBASE 0xc0000101 | |
515 | #define MSR_KERNELGSBASE 0xc0000102 | |
516 | #define MSR_TSC_AUX 0xc0000103 | |
517 | #define MSR_AMD64_TSC_RATIO 0xc0000104 | |
518 | ||
519 | #define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL | |
520 | ||
521 | #define MSR_VM_HSAVE_PA 0xc0010117 | |
522 | ||
523 | #define MSR_IA32_XFD 0x000001c4 | |
524 | #define MSR_IA32_XFD_ERR 0x000001c5 | |
525 | ||
526 | #define MSR_IA32_BNDCFGS 0x00000d90 | |
527 | #define MSR_IA32_XSS 0x00000da0 | |
528 | #define MSR_IA32_UMWAIT_CONTROL 0xe1 | |
529 | ||
530 | #define MSR_IA32_VMX_BASIC 0x00000480 | |
531 | #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 | |
532 | #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 | |
533 | #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 | |
534 | #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 | |
535 | #define MSR_IA32_VMX_MISC 0x00000485 | |
536 | #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 | |
537 | #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 | |
538 | #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 | |
539 | #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 | |
540 | #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a | |
541 | #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b | |
542 | #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c | |
543 | #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d | |
544 | #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e | |
545 | #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f | |
546 | #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 | |
547 | #define MSR_IA32_VMX_VMFUNC 0x00000491 | |
548 | ||
549 | #define MSR_APIC_START 0x00000800 | |
550 | #define MSR_APIC_END 0x000008ff | |
551 | ||
552 | #define XSTATE_FP_BIT 0 | |
553 | #define XSTATE_SSE_BIT 1 | |
554 | #define XSTATE_YMM_BIT 2 | |
555 | #define XSTATE_BNDREGS_BIT 3 | |
556 | #define XSTATE_BNDCSR_BIT 4 | |
557 | #define XSTATE_OPMASK_BIT 5 | |
558 | #define XSTATE_ZMM_Hi256_BIT 6 | |
559 | #define XSTATE_Hi16_ZMM_BIT 7 | |
560 | #define XSTATE_PKRU_BIT 9 | |
561 | #define XSTATE_ARCH_LBR_BIT 15 | |
562 | #define XSTATE_XTILE_CFG_BIT 17 | |
563 | #define XSTATE_XTILE_DATA_BIT 18 | |
564 | ||
565 | #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) | |
566 | #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) | |
567 | #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) | |
568 | #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) | |
569 | #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) | |
570 | #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) | |
571 | #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) | |
572 | #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) | |
573 | #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) | |
574 | #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT) | |
575 | #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) | |
576 | #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) | |
577 | ||
578 | #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK) | |
579 | ||
580 | #define ESA_FEATURE_ALIGN64_BIT 1 | |
581 | #define ESA_FEATURE_XFD_BIT 2 | |
582 | ||
583 | #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT) | |
584 | #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT) | |
585 | ||
586 | ||
587 | /* CPUID feature bits available in XCR0 */ | |
588 | #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ | |
589 | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \ | |
590 | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | \ | |
591 | XSTATE_ZMM_Hi256_MASK | \ | |
592 | XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK | \ | |
593 | XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_MASK) | |
594 | ||
595 | /* CPUID feature words */ | |
596 | typedef enum FeatureWord { | |
597 | FEAT_1_EDX, /* CPUID[1].EDX */ | |
598 | FEAT_1_ECX, /* CPUID[1].ECX */ | |
599 | FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ | |
600 | FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ | |
601 | FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */ | |
602 | FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */ | |
603 | FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ | |
604 | FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ | |
605 | FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ | |
606 | FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ | |
607 | FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */ | |
608 | FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ | |
609 | FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ | |
610 | FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */ | |
611 | FEAT_SVM, /* CPUID[8000_000A].EDX */ | |
612 | FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ | |
613 | FEAT_6_EAX, /* CPUID[6].EAX */ | |
614 | FEAT_XSAVE_XCR0_LO, /* CPUID[EAX=0xd,ECX=0].EAX */ | |
615 | FEAT_XSAVE_XCR0_HI, /* CPUID[EAX=0xd,ECX=0].EDX */ | |
616 | FEAT_ARCH_CAPABILITIES, | |
617 | FEAT_CORE_CAPABILITY, | |
618 | FEAT_PERF_CAPABILITIES, | |
619 | FEAT_VMX_PROCBASED_CTLS, | |
620 | FEAT_VMX_SECONDARY_CTLS, | |
621 | FEAT_VMX_PINBASED_CTLS, | |
622 | FEAT_VMX_EXIT_CTLS, | |
623 | FEAT_VMX_ENTRY_CTLS, | |
624 | FEAT_VMX_MISC, | |
625 | FEAT_VMX_EPT_VPID_CAPS, | |
626 | FEAT_VMX_BASIC, | |
627 | FEAT_VMX_VMFUNC, | |
628 | FEAT_14_0_ECX, | |
629 | FEAT_SGX_12_0_EAX, /* CPUID[EAX=0x12,ECX=0].EAX (SGX) */ | |
630 | FEAT_SGX_12_0_EBX, /* CPUID[EAX=0x12,ECX=0].EBX (SGX MISCSELECT[31:0]) */ | |
631 | FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */ | |
632 | FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */ | |
633 | FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */ | |
634 | FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */ | |
635 | FEAT_7_2_EDX, /* CPUID[EAX=7,ECX=2].EDX */ | |
636 | FEATURE_WORDS, | |
637 | } FeatureWord; | |
638 | ||
639 | typedef uint64_t FeatureWordArray[FEATURE_WORDS]; | |
640 | uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, | |
641 | bool migratable_only); | |
642 | ||
643 | /* cpuid_features bits */ | |
644 | #define CPUID_FP87 (1U << 0) | |
645 | #define CPUID_VME (1U << 1) | |
646 | #define CPUID_DE (1U << 2) | |
647 | #define CPUID_PSE (1U << 3) | |
648 | #define CPUID_TSC (1U << 4) | |
649 | #define CPUID_MSR (1U << 5) | |
650 | #define CPUID_PAE (1U << 6) | |
651 | #define CPUID_MCE (1U << 7) | |
652 | #define CPUID_CX8 (1U << 8) | |
653 | #define CPUID_APIC (1U << 9) | |
654 | #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ | |
655 | #define CPUID_MTRR (1U << 12) | |
656 | #define CPUID_PGE (1U << 13) | |
657 | #define CPUID_MCA (1U << 14) | |
658 | #define CPUID_CMOV (1U << 15) | |
659 | #define CPUID_PAT (1U << 16) | |
660 | #define CPUID_PSE36 (1U << 17) | |
661 | #define CPUID_PN (1U << 18) | |
662 | #define CPUID_CLFLUSH (1U << 19) | |
663 | #define CPUID_DTS (1U << 21) | |
664 | #define CPUID_ACPI (1U << 22) | |
665 | #define CPUID_MMX (1U << 23) | |
666 | #define CPUID_FXSR (1U << 24) | |
667 | #define CPUID_SSE (1U << 25) | |
668 | #define CPUID_SSE2 (1U << 26) | |
669 | #define CPUID_SS (1U << 27) | |
670 | #define CPUID_HT (1U << 28) | |
671 | #define CPUID_TM (1U << 29) | |
672 | #define CPUID_IA64 (1U << 30) | |
673 | #define CPUID_PBE (1U << 31) | |
674 | ||
675 | #define CPUID_EXT_SSE3 (1U << 0) | |
676 | #define CPUID_EXT_PCLMULQDQ (1U << 1) | |
677 | #define CPUID_EXT_DTES64 (1U << 2) | |
678 | #define CPUID_EXT_MONITOR (1U << 3) | |
679 | #define CPUID_EXT_DSCPL (1U << 4) | |
680 | #define CPUID_EXT_VMX (1U << 5) | |
681 | #define CPUID_EXT_SMX (1U << 6) | |
682 | #define CPUID_EXT_EST (1U << 7) | |
683 | #define CPUID_EXT_TM2 (1U << 8) | |
684 | #define CPUID_EXT_SSSE3 (1U << 9) | |
685 | #define CPUID_EXT_CID (1U << 10) | |
686 | #define CPUID_EXT_FMA (1U << 12) | |
687 | #define CPUID_EXT_CX16 (1U << 13) | |
688 | #define CPUID_EXT_XTPR (1U << 14) | |
689 | #define CPUID_EXT_PDCM (1U << 15) | |
690 | #define CPUID_EXT_PCID (1U << 17) | |
691 | #define CPUID_EXT_DCA (1U << 18) | |
692 | #define CPUID_EXT_SSE41 (1U << 19) | |
693 | #define CPUID_EXT_SSE42 (1U << 20) | |
694 | #define CPUID_EXT_X2APIC (1U << 21) | |
695 | #define CPUID_EXT_MOVBE (1U << 22) | |
696 | #define CPUID_EXT_POPCNT (1U << 23) | |
697 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) | |
698 | #define CPUID_EXT_AES (1U << 25) | |
699 | #define CPUID_EXT_XSAVE (1U << 26) | |
700 | #define CPUID_EXT_OSXSAVE (1U << 27) | |
701 | #define CPUID_EXT_AVX (1U << 28) | |
702 | #define CPUID_EXT_F16C (1U << 29) | |
703 | #define CPUID_EXT_RDRAND (1U << 30) | |
704 | #define CPUID_EXT_HYPERVISOR (1U << 31) | |
705 | ||
706 | #define CPUID_EXT2_FPU (1U << 0) | |
707 | #define CPUID_EXT2_VME (1U << 1) | |
708 | #define CPUID_EXT2_DE (1U << 2) | |
709 | #define CPUID_EXT2_PSE (1U << 3) | |
710 | #define CPUID_EXT2_TSC (1U << 4) | |
711 | #define CPUID_EXT2_MSR (1U << 5) | |
712 | #define CPUID_EXT2_PAE (1U << 6) | |
713 | #define CPUID_EXT2_MCE (1U << 7) | |
714 | #define CPUID_EXT2_CX8 (1U << 8) | |
715 | #define CPUID_EXT2_APIC (1U << 9) | |
716 | #define CPUID_EXT2_SYSCALL (1U << 11) | |
717 | #define CPUID_EXT2_MTRR (1U << 12) | |
718 | #define CPUID_EXT2_PGE (1U << 13) | |
719 | #define CPUID_EXT2_MCA (1U << 14) | |
720 | #define CPUID_EXT2_CMOV (1U << 15) | |
721 | #define CPUID_EXT2_PAT (1U << 16) | |
722 | #define CPUID_EXT2_PSE36 (1U << 17) | |
723 | #define CPUID_EXT2_MP (1U << 19) | |
724 | #define CPUID_EXT2_NX (1U << 20) | |
725 | #define CPUID_EXT2_MMXEXT (1U << 22) | |
726 | #define CPUID_EXT2_MMX (1U << 23) | |
727 | #define CPUID_EXT2_FXSR (1U << 24) | |
728 | #define CPUID_EXT2_FFXSR (1U << 25) | |
729 | #define CPUID_EXT2_PDPE1GB (1U << 26) | |
730 | #define CPUID_EXT2_RDTSCP (1U << 27) | |
731 | #define CPUID_EXT2_LM (1U << 29) | |
732 | #define CPUID_EXT2_3DNOWEXT (1U << 30) | |
733 | #define CPUID_EXT2_3DNOW (1U << 31) | |
734 | ||
735 | /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */ | |
736 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ | |
737 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ | |
738 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ | |
739 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ | |
740 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ | |
741 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ | |
742 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ | |
743 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ | |
744 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) | |
745 | ||
746 | #define CPUID_EXT3_LAHF_LM (1U << 0) | |
747 | #define CPUID_EXT3_CMP_LEG (1U << 1) | |
748 | #define CPUID_EXT3_SVM (1U << 2) | |
749 | #define CPUID_EXT3_EXTAPIC (1U << 3) | |
750 | #define CPUID_EXT3_CR8LEG (1U << 4) | |
751 | #define CPUID_EXT3_ABM (1U << 5) | |
752 | #define CPUID_EXT3_SSE4A (1U << 6) | |
753 | #define CPUID_EXT3_MISALIGNSSE (1U << 7) | |
754 | #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) | |
755 | #define CPUID_EXT3_OSVW (1U << 9) | |
756 | #define CPUID_EXT3_IBS (1U << 10) | |
757 | #define CPUID_EXT3_XOP (1U << 11) | |
758 | #define CPUID_EXT3_SKINIT (1U << 12) | |
759 | #define CPUID_EXT3_WDT (1U << 13) | |
760 | #define CPUID_EXT3_LWP (1U << 15) | |
761 | #define CPUID_EXT3_FMA4 (1U << 16) | |
762 | #define CPUID_EXT3_TCE (1U << 17) | |
763 | #define CPUID_EXT3_NODEID (1U << 19) | |
764 | #define CPUID_EXT3_TBM (1U << 21) | |
765 | #define CPUID_EXT3_TOPOEXT (1U << 22) | |
766 | #define CPUID_EXT3_PERFCORE (1U << 23) | |
767 | #define CPUID_EXT3_PERFNB (1U << 24) | |
768 | ||
769 | #define CPUID_SVM_NPT (1U << 0) | |
770 | #define CPUID_SVM_LBRV (1U << 1) | |
771 | #define CPUID_SVM_SVMLOCK (1U << 2) | |
772 | #define CPUID_SVM_NRIPSAVE (1U << 3) | |
773 | #define CPUID_SVM_TSCSCALE (1U << 4) | |
774 | #define CPUID_SVM_VMCBCLEAN (1U << 5) | |
775 | #define CPUID_SVM_FLUSHASID (1U << 6) | |
776 | #define CPUID_SVM_DECODEASSIST (1U << 7) | |
777 | #define CPUID_SVM_PAUSEFILTER (1U << 10) | |
778 | #define CPUID_SVM_PFTHRESHOLD (1U << 12) | |
779 | #define CPUID_SVM_AVIC (1U << 13) | |
780 | #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15) | |
781 | #define CPUID_SVM_VGIF (1U << 16) | |
782 | #define CPUID_SVM_VNMI (1U << 25) | |
783 | #define CPUID_SVM_SVME_ADDR_CHK (1U << 28) | |
784 | ||
785 | /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ | |
786 | #define CPUID_7_0_EBX_FSGSBASE (1U << 0) | |
787 | /* Support SGX */ | |
788 | #define CPUID_7_0_EBX_SGX (1U << 2) | |
789 | /* 1st Group of Advanced Bit Manipulation Extensions */ | |
790 | #define CPUID_7_0_EBX_BMI1 (1U << 3) | |
791 | /* Hardware Lock Elision */ | |
792 | #define CPUID_7_0_EBX_HLE (1U << 4) | |
793 | /* Intel Advanced Vector Extensions 2 */ | |
794 | #define CPUID_7_0_EBX_AVX2 (1U << 5) | |
795 | /* Supervisor-mode Execution Prevention */ | |
796 | #define CPUID_7_0_EBX_SMEP (1U << 7) | |
797 | /* 2nd Group of Advanced Bit Manipulation Extensions */ | |
798 | #define CPUID_7_0_EBX_BMI2 (1U << 8) | |
799 | /* Enhanced REP MOVSB/STOSB */ | |
800 | #define CPUID_7_0_EBX_ERMS (1U << 9) | |
801 | /* Invalidate Process-Context Identifier */ | |
802 | #define CPUID_7_0_EBX_INVPCID (1U << 10) | |
803 | /* Restricted Transactional Memory */ | |
804 | #define CPUID_7_0_EBX_RTM (1U << 11) | |
805 | /* Memory Protection Extension */ | |
806 | #define CPUID_7_0_EBX_MPX (1U << 14) | |
807 | /* AVX-512 Foundation */ | |
808 | #define CPUID_7_0_EBX_AVX512F (1U << 16) | |
809 | /* AVX-512 Doubleword & Quadword Instruction */ | |
810 | #define CPUID_7_0_EBX_AVX512DQ (1U << 17) | |
811 | /* Read Random SEED */ | |
812 | #define CPUID_7_0_EBX_RDSEED (1U << 18) | |
813 | /* ADCX and ADOX instructions */ | |
814 | #define CPUID_7_0_EBX_ADX (1U << 19) | |
815 | /* Supervisor Mode Access Prevention */ | |
816 | #define CPUID_7_0_EBX_SMAP (1U << 20) | |
817 | /* AVX-512 Integer Fused Multiply Add */ | |
818 | #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) | |
819 | /* Flush a Cache Line Optimized */ | |
820 | #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) | |
821 | /* Cache Line Write Back */ | |
822 | #define CPUID_7_0_EBX_CLWB (1U << 24) | |
823 | /* Intel Processor Trace */ | |
824 | #define CPUID_7_0_EBX_INTEL_PT (1U << 25) | |
825 | /* AVX-512 Prefetch */ | |
826 | #define CPUID_7_0_EBX_AVX512PF (1U << 26) | |
827 | /* AVX-512 Exponential and Reciprocal */ | |
828 | #define CPUID_7_0_EBX_AVX512ER (1U << 27) | |
829 | /* AVX-512 Conflict Detection */ | |
830 | #define CPUID_7_0_EBX_AVX512CD (1U << 28) | |
831 | /* SHA1/SHA256 Instruction Extensions */ | |
832 | #define CPUID_7_0_EBX_SHA_NI (1U << 29) | |
833 | /* AVX-512 Byte and Word Instructions */ | |
834 | #define CPUID_7_0_EBX_AVX512BW (1U << 30) | |
835 | /* AVX-512 Vector Length Extensions */ | |
836 | #define CPUID_7_0_EBX_AVX512VL (1U << 31) | |
837 | ||
838 | /* AVX-512 Vector Byte Manipulation Instruction */ | |
839 | #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1) | |
840 | /* User-Mode Instruction Prevention */ | |
841 | #define CPUID_7_0_ECX_UMIP (1U << 2) | |
842 | /* Protection Keys for User-mode Pages */ | |
843 | #define CPUID_7_0_ECX_PKU (1U << 3) | |
844 | /* OS Enable Protection Keys */ | |
845 | #define CPUID_7_0_ECX_OSPKE (1U << 4) | |
846 | /* UMONITOR/UMWAIT/TPAUSE Instructions */ | |
847 | #define CPUID_7_0_ECX_WAITPKG (1U << 5) | |
848 | /* Additional AVX-512 Vector Byte Manipulation Instruction */ | |
849 | #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) | |
850 | /* Galois Field New Instructions */ | |
851 | #define CPUID_7_0_ECX_GFNI (1U << 8) | |
852 | /* Vector AES Instructions */ | |
853 | #define CPUID_7_0_ECX_VAES (1U << 9) | |
854 | /* Carry-Less Multiplication Quadword */ | |
855 | #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10) | |
856 | /* Vector Neural Network Instructions */ | |
857 | #define CPUID_7_0_ECX_AVX512VNNI (1U << 11) | |
858 | /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */ | |
859 | #define CPUID_7_0_ECX_AVX512BITALG (1U << 12) | |
860 | /* POPCNT for vectors of DW/QW */ | |
861 | #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) | |
862 | /* 5-level Page Tables */ | |
863 | #define CPUID_7_0_ECX_LA57 (1U << 16) | |
864 | /* Read Processor ID */ | |
865 | #define CPUID_7_0_ECX_RDPID (1U << 22) | |
866 | /* Bus Lock Debug Exception */ | |
867 | #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24) | |
868 | /* Cache Line Demote Instruction */ | |
869 | #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) | |
870 | /* Move Doubleword as Direct Store Instruction */ | |
871 | #define CPUID_7_0_ECX_MOVDIRI (1U << 27) | |
872 | /* Move 64 Bytes as Direct Store Instruction */ | |
873 | #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) | |
874 | /* Support SGX Launch Control */ | |
875 | #define CPUID_7_0_ECX_SGX_LC (1U << 30) | |
876 | /* Protection Keys for Supervisor-mode Pages */ | |
877 | #define CPUID_7_0_ECX_PKS (1U << 31) | |
878 | ||
879 | /* AVX512 Neural Network Instructions */ | |
880 | #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) | |
881 | /* AVX512 Multiply Accumulation Single Precision */ | |
882 | #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) | |
883 | /* Fast Short Rep Mov */ | |
884 | #define CPUID_7_0_EDX_FSRM (1U << 4) | |
885 | /* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ | |
886 | #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) | |
887 | /* SERIALIZE instruction */ | |
888 | #define CPUID_7_0_EDX_SERIALIZE (1U << 14) | |
889 | /* TSX Suspend Load Address Tracking instruction */ | |
890 | #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) | |
891 | /* Architectural LBRs */ | |
892 | #define CPUID_7_0_EDX_ARCH_LBR (1U << 19) | |
893 | /* AMX_BF16 instruction */ | |
894 | #define CPUID_7_0_EDX_AMX_BF16 (1U << 22) | |
895 | /* AVX512_FP16 instruction */ | |
896 | #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) | |
897 | /* AMX tile (two-dimensional register) */ | |
898 | #define CPUID_7_0_EDX_AMX_TILE (1U << 24) | |
899 | /* AMX_INT8 instruction */ | |
900 | #define CPUID_7_0_EDX_AMX_INT8 (1U << 25) | |
901 | /* Speculation Control */ | |
902 | #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) | |
903 | /* Single Thread Indirect Branch Predictors */ | |
904 | #define CPUID_7_0_EDX_STIBP (1U << 27) | |
905 | /* Flush L1D cache */ | |
906 | #define CPUID_7_0_EDX_FLUSH_L1D (1U << 28) | |
907 | /* Arch Capabilities */ | |
908 | #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) | |
909 | /* Core Capability */ | |
910 | #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) | |
911 | /* Speculative Store Bypass Disable */ | |
912 | #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) | |
913 | ||
914 | /* AVX VNNI Instruction */ | |
915 | #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) | |
916 | /* AVX512 BFloat16 Instruction */ | |
917 | #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) | |
918 | /* CMPCCXADD Instructions */ | |
919 | #define CPUID_7_1_EAX_CMPCCXADD (1U << 7) | |
920 | /* Fast Zero REP MOVS */ | |
921 | #define CPUID_7_1_EAX_FZRM (1U << 10) | |
922 | /* Fast Short REP STOS */ | |
923 | #define CPUID_7_1_EAX_FSRS (1U << 11) | |
924 | /* Fast Short REP CMPS/SCAS */ | |
925 | #define CPUID_7_1_EAX_FSRC (1U << 12) | |
926 | /* Support Tile Computational Operations on FP16 Numbers */ | |
927 | #define CPUID_7_1_EAX_AMX_FP16 (1U << 21) | |
928 | /* Support for VPMADD52[H,L]UQ */ | |
929 | #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) | |
930 | ||
931 | /* Support for VPDPB[SU,UU,SS]D[,S] */ | |
932 | #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4) | |
933 | /* AVX NE CONVERT Instructions */ | |
934 | #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5) | |
935 | /* AMX COMPLEX Instructions */ | |
936 | #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8) | |
937 | /* PREFETCHIT0/1 Instructions */ | |
938 | #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) | |
939 | ||
940 | /* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */ | |
941 | #define CPUID_7_2_EDX_MCDT_NO (1U << 5) | |
942 | ||
943 | /* XFD Extend Feature Disabled */ | |
944 | #define CPUID_D_1_EAX_XFD (1U << 4) | |
945 | ||
946 | /* Packets which contain IP payload have LIP values */ | |
947 | #define CPUID_14_0_ECX_LIP (1U << 31) | |
948 | ||
949 | /* CLZERO instruction */ | |
950 | #define CPUID_8000_0008_EBX_CLZERO (1U << 0) | |
951 | /* Always save/restore FP error pointers */ | |
952 | #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2) | |
953 | /* Write back and do not invalidate cache */ | |
954 | #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) | |
955 | /* Indirect Branch Prediction Barrier */ | |
956 | #define CPUID_8000_0008_EBX_IBPB (1U << 12) | |
957 | /* Indirect Branch Restricted Speculation */ | |
958 | #define CPUID_8000_0008_EBX_IBRS (1U << 14) | |
959 | /* Single Thread Indirect Branch Predictors */ | |
960 | #define CPUID_8000_0008_EBX_STIBP (1U << 15) | |
961 | /* STIBP mode has enhanced performance and may be left always on */ | |
962 | #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17) | |
963 | /* Speculative Store Bypass Disable */ | |
964 | #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24) | |
965 | /* Predictive Store Forwarding Disable */ | |
966 | #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28) | |
967 | ||
968 | /* Processor ignores nested data breakpoints */ | |
969 | #define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0) | |
970 | /* LFENCE is always serializing */ | |
971 | #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2) | |
972 | /* Null Selector Clears Base */ | |
973 | #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6) | |
974 | /* Automatic IBRS */ | |
975 | #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8) | |
976 | ||
977 | #define CPUID_XSAVE_XSAVEOPT (1U << 0) | |
978 | #define CPUID_XSAVE_XSAVEC (1U << 1) | |
979 | #define CPUID_XSAVE_XGETBV1 (1U << 2) | |
980 | #define CPUID_XSAVE_XSAVES (1U << 3) | |
981 | ||
982 | #define CPUID_6_EAX_ARAT (1U << 2) | |
983 | ||
984 | /* CPUID[0x80000007].EDX flags: */ | |
985 | #define CPUID_APM_INVTSC (1U << 8) | |
986 | ||
987 | #define CPUID_VENDOR_SZ 12 | |
988 | ||
989 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ | |
990 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ | |
991 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ | |
992 | #define CPUID_VENDOR_INTEL "GenuineIntel" | |
993 | ||
994 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ | |
995 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ | |
996 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ | |
997 | #define CPUID_VENDOR_AMD "AuthenticAMD" | |
998 | ||
999 | #define CPUID_VENDOR_VIA "CentaurHauls" | |
1000 | ||
1001 | #define CPUID_VENDOR_HYGON "HygonGenuine" | |
1002 | ||
1003 | #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \ | |
1004 | (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \ | |
1005 | (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3) | |
1006 | #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \ | |
1007 | (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \ | |
1008 | (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3) | |
1009 | ||
1010 | #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ | |
1011 | #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ | |
1012 | ||
1013 | /* CPUID[0xB].ECX level types */ | |
1014 | #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) | |
1015 | #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) | |
1016 | #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) | |
1017 | #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8) | |
1018 | ||
1019 | /* MSR Feature Bits */ | |
1020 | #define MSR_ARCH_CAP_RDCL_NO (1U << 0) | |
1021 | #define MSR_ARCH_CAP_IBRS_ALL (1U << 1) | |
1022 | #define MSR_ARCH_CAP_RSBA (1U << 2) | |
1023 | #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) | |
1024 | #define MSR_ARCH_CAP_SSB_NO (1U << 4) | |
1025 | #define MSR_ARCH_CAP_MDS_NO (1U << 5) | |
1026 | #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6) | |
1027 | #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7) | |
1028 | #define MSR_ARCH_CAP_TAA_NO (1U << 8) | |
1029 | #define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13) | |
1030 | #define MSR_ARCH_CAP_FBSDP_NO (1U << 14) | |
1031 | #define MSR_ARCH_CAP_PSDP_NO (1U << 15) | |
1032 | #define MSR_ARCH_CAP_FB_CLEAR (1U << 17) | |
1033 | #define MSR_ARCH_CAP_PBRSB_NO (1U << 24) | |
1034 | ||
1035 | #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) | |
1036 | ||
1037 | /* VMX MSR features */ | |
1038 | #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull | |
1039 | #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32) | |
1040 | #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32) | |
1041 | #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) | |
1042 | #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) | |
1043 | #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) | |
1044 | #define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56) | |
1045 | ||
1046 | #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full | |
1047 | #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) | |
1048 | #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6) | |
1049 | #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7) | |
1050 | #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8) | |
1051 | #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull | |
1052 | #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29) | |
1053 | #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30) | |
1054 | ||
1055 | #define MSR_VMX_EPT_EXECONLY (1ULL << 0) | |
1056 | #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6) | |
1057 | #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7) | |
1058 | #define MSR_VMX_EPT_UC (1ULL << 8) | |
1059 | #define MSR_VMX_EPT_WB (1ULL << 14) | |
1060 | #define MSR_VMX_EPT_2MB (1ULL << 16) | |
1061 | #define MSR_VMX_EPT_1GB (1ULL << 17) | |
1062 | #define MSR_VMX_EPT_INVEPT (1ULL << 20) | |
1063 | #define MSR_VMX_EPT_AD_BITS (1ULL << 21) | |
1064 | #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22) | |
1065 | #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25) | |
1066 | #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26) | |
1067 | #define MSR_VMX_EPT_INVVPID (1ULL << 32) | |
1068 | #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40) | |
1069 | #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41) | |
1070 | #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42) | |
1071 | #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43) | |
1072 | ||
1073 | #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0) | |
1074 | ||
1075 | ||
1076 | /* VMX controls */ | |
1077 | #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 | |
1078 | #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008 | |
1079 | #define VMX_CPU_BASED_HLT_EXITING 0x00000080 | |
1080 | #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200 | |
1081 | #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400 | |
1082 | #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800 | |
1083 | #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000 | |
1084 | #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000 | |
1085 | #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000 | |
1086 | #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000 | |
1087 | #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000 | |
1088 | #define VMX_CPU_BASED_TPR_SHADOW 0x00200000 | |
1089 | #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 | |
1090 | #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000 | |
1091 | #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000 | |
1092 | #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000 | |
1093 | #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000 | |
1094 | #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000 | |
1095 | #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000 | |
1096 | #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000 | |
1097 | #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 | |
1098 | ||
1099 | #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 | |
1100 | #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002 | |
1101 | #define VMX_SECONDARY_EXEC_DESC 0x00000004 | |
1102 | #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008 | |
1103 | #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 | |
1104 | #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020 | |
1105 | #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040 | |
1106 | #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 | |
1107 | #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 | |
1108 | #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 | |
1109 | #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 | |
1110 | #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800 | |
1111 | #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 | |
1112 | #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000 | |
1113 | #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000 | |
1114 | #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000 | |
1115 | #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000 | |
1116 | #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000 | |
1117 | #define VMX_SECONDARY_EXEC_XSAVES 0x00100000 | |
1118 | #define VMX_SECONDARY_EXEC_TSC_SCALING 0x02000000 | |
1119 | #define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE 0x04000000 | |
1120 | ||
1121 | #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001 | |
1122 | #define VMX_PIN_BASED_NMI_EXITING 0x00000008 | |
1123 | #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020 | |
1124 | #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 | |
1125 | #define VMX_PIN_BASED_POSTED_INTR 0x00000080 | |
1126 | ||
1127 | #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 | |
1128 | #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 | |
1129 | #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 | |
1130 | #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 | |
1131 | #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000 | |
1132 | #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000 | |
1133 | #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000 | |
1134 | #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000 | |
1135 | #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 | |
1136 | #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000 | |
1137 | #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000 | |
1138 | #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 | |
1139 | #define VMX_VM_EXIT_LOAD_IA32_PKRS 0x20000000 | |
1140 | ||
1141 | #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 | |
1142 | #define VMX_VM_ENTRY_IA32E_MODE 0x00000200 | |
1143 | #define VMX_VM_ENTRY_SMM 0x00000400 | |
1144 | #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 | |
1145 | #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 | |
1146 | #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000 | |
1147 | #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000 | |
1148 | #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000 | |
1149 | #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000 | |
1150 | #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 | |
1151 | #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 | |
1152 | ||
1153 | /* Supported Hyper-V Enlightenments */ | |
1154 | #define HYPERV_FEAT_RELAXED 0 | |
1155 | #define HYPERV_FEAT_VAPIC 1 | |
1156 | #define HYPERV_FEAT_TIME 2 | |
1157 | #define HYPERV_FEAT_CRASH 3 | |
1158 | #define HYPERV_FEAT_RESET 4 | |
1159 | #define HYPERV_FEAT_VPINDEX 5 | |
1160 | #define HYPERV_FEAT_RUNTIME 6 | |
1161 | #define HYPERV_FEAT_SYNIC 7 | |
1162 | #define HYPERV_FEAT_STIMER 8 | |
1163 | #define HYPERV_FEAT_FREQUENCIES 9 | |
1164 | #define HYPERV_FEAT_REENLIGHTENMENT 10 | |
1165 | #define HYPERV_FEAT_TLBFLUSH 11 | |
1166 | #define HYPERV_FEAT_EVMCS 12 | |
1167 | #define HYPERV_FEAT_IPI 13 | |
1168 | #define HYPERV_FEAT_STIMER_DIRECT 14 | |
1169 | #define HYPERV_FEAT_AVIC 15 | |
1170 | #define HYPERV_FEAT_SYNDBG 16 | |
1171 | #define HYPERV_FEAT_MSR_BITMAP 17 | |
1172 | #define HYPERV_FEAT_XMM_INPUT 18 | |
1173 | #define HYPERV_FEAT_TLBFLUSH_EXT 19 | |
1174 | #define HYPERV_FEAT_TLBFLUSH_DIRECT 20 | |
1175 | ||
1176 | #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY | |
1177 | #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF | |
1178 | #endif | |
1179 | ||
1180 | #define EXCP00_DIVZ 0 | |
1181 | #define EXCP01_DB 1 | |
1182 | #define EXCP02_NMI 2 | |
1183 | #define EXCP03_INT3 3 | |
1184 | #define EXCP04_INTO 4 | |
1185 | #define EXCP05_BOUND 5 | |
1186 | #define EXCP06_ILLOP 6 | |
1187 | #define EXCP07_PREX 7 | |
1188 | #define EXCP08_DBLE 8 | |
1189 | #define EXCP09_XERR 9 | |
1190 | #define EXCP0A_TSS 10 | |
1191 | #define EXCP0B_NOSEG 11 | |
1192 | #define EXCP0C_STACK 12 | |
1193 | #define EXCP0D_GPF 13 | |
1194 | #define EXCP0E_PAGE 14 | |
1195 | #define EXCP10_COPR 16 | |
1196 | #define EXCP11_ALGN 17 | |
1197 | #define EXCP12_MCHK 18 | |
1198 | ||
1199 | #define EXCP_VMEXIT 0x100 /* only for system emulation */ | |
1200 | #define EXCP_SYSCALL 0x101 /* only for user emulation */ | |
1201 | #define EXCP_VSYSCALL 0x102 /* only for user emulation */ | |
1202 | ||
1203 | /* i386-specific interrupt pending bits. */ | |
1204 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 | |
1205 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 | |
1206 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 | |
1207 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 | |
1208 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 | |
1209 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 | |
1210 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 | |
1211 | ||
1212 | /* Use a clearer name for this. */ | |
1213 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET | |
1214 | ||
1215 | /* Instead of computing the condition codes after each x86 instruction, | |
1216 | * QEMU just stores one operand (called CC_SRC), the result | |
1217 | * (called CC_DST) and the type of operation (called CC_OP). When the | |
1218 | * condition codes are needed, the condition codes can be calculated | |
1219 | * using this information. Condition codes are not generated if they | |
1220 | * are only needed for conditional branches. | |
1221 | */ | |
1222 | typedef enum { | |
1223 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ | |
1224 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ | |
1225 | ||
1226 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ | |
1227 | CC_OP_MULW, | |
1228 | CC_OP_MULL, | |
1229 | CC_OP_MULQ, | |
1230 | ||
1231 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1232 | CC_OP_ADDW, | |
1233 | CC_OP_ADDL, | |
1234 | CC_OP_ADDQ, | |
1235 | ||
1236 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1237 | CC_OP_ADCW, | |
1238 | CC_OP_ADCL, | |
1239 | CC_OP_ADCQ, | |
1240 | ||
1241 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1242 | CC_OP_SUBW, | |
1243 | CC_OP_SUBL, | |
1244 | CC_OP_SUBQ, | |
1245 | ||
1246 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
1247 | CC_OP_SBBW, | |
1248 | CC_OP_SBBL, | |
1249 | CC_OP_SBBQ, | |
1250 | ||
1251 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ | |
1252 | CC_OP_LOGICW, | |
1253 | CC_OP_LOGICL, | |
1254 | CC_OP_LOGICQ, | |
1255 | ||
1256 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
1257 | CC_OP_INCW, | |
1258 | CC_OP_INCL, | |
1259 | CC_OP_INCQ, | |
1260 | ||
1261 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
1262 | CC_OP_DECW, | |
1263 | CC_OP_DECL, | |
1264 | CC_OP_DECQ, | |
1265 | ||
1266 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ | |
1267 | CC_OP_SHLW, | |
1268 | CC_OP_SHLL, | |
1269 | CC_OP_SHLQ, | |
1270 | ||
1271 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ | |
1272 | CC_OP_SARW, | |
1273 | CC_OP_SARL, | |
1274 | CC_OP_SARQ, | |
1275 | ||
1276 | CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ | |
1277 | CC_OP_BMILGW, | |
1278 | CC_OP_BMILGL, | |
1279 | CC_OP_BMILGQ, | |
1280 | ||
1281 | CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ | |
1282 | CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ | |
1283 | CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ | |
1284 | ||
1285 | CC_OP_CLR, /* Z set, all other flags clear. */ | |
1286 | CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ | |
1287 | ||
1288 | CC_OP_NB, | |
1289 | } CCOp; | |
1290 | QEMU_BUILD_BUG_ON(CC_OP_NB >= 128); | |
1291 | ||
1292 | typedef struct SegmentCache { | |
1293 | uint32_t selector; | |
1294 | target_ulong base; | |
1295 | uint32_t limit; | |
1296 | uint32_t flags; | |
1297 | } SegmentCache; | |
1298 | ||
1299 | typedef union MMXReg { | |
1300 | uint8_t _b_MMXReg[64 / 8]; | |
1301 | uint16_t _w_MMXReg[64 / 16]; | |
1302 | uint32_t _l_MMXReg[64 / 32]; | |
1303 | uint64_t _q_MMXReg[64 / 64]; | |
1304 | float32 _s_MMXReg[64 / 32]; | |
1305 | float64 _d_MMXReg[64 / 64]; | |
1306 | } MMXReg; | |
1307 | ||
1308 | typedef union XMMReg { | |
1309 | uint64_t _q_XMMReg[128 / 64]; | |
1310 | } XMMReg; | |
1311 | ||
1312 | typedef union YMMReg { | |
1313 | uint64_t _q_YMMReg[256 / 64]; | |
1314 | XMMReg _x_YMMReg[256 / 128]; | |
1315 | } YMMReg; | |
1316 | ||
1317 | typedef union ZMMReg { | |
1318 | uint8_t _b_ZMMReg[512 / 8]; | |
1319 | uint16_t _w_ZMMReg[512 / 16]; | |
1320 | uint32_t _l_ZMMReg[512 / 32]; | |
1321 | uint64_t _q_ZMMReg[512 / 64]; | |
1322 | float16 _h_ZMMReg[512 / 16]; | |
1323 | float32 _s_ZMMReg[512 / 32]; | |
1324 | float64 _d_ZMMReg[512 / 64]; | |
1325 | XMMReg _x_ZMMReg[512 / 128]; | |
1326 | YMMReg _y_ZMMReg[512 / 256]; | |
1327 | } ZMMReg; | |
1328 | ||
1329 | typedef struct BNDReg { | |
1330 | uint64_t lb; | |
1331 | uint64_t ub; | |
1332 | } BNDReg; | |
1333 | ||
1334 | typedef struct BNDCSReg { | |
1335 | uint64_t cfgu; | |
1336 | uint64_t sts; | |
1337 | } BNDCSReg; | |
1338 | ||
1339 | #define BNDCFG_ENABLE 1ULL | |
1340 | #define BNDCFG_BNDPRESERVE 2ULL | |
1341 | #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK | |
1342 | ||
1343 | #if HOST_BIG_ENDIAN | |
1344 | #define ZMM_B(n) _b_ZMMReg[63 - (n)] | |
1345 | #define ZMM_W(n) _w_ZMMReg[31 - (n)] | |
1346 | #define ZMM_L(n) _l_ZMMReg[15 - (n)] | |
1347 | #define ZMM_H(n) _h_ZMMReg[31 - (n)] | |
1348 | #define ZMM_S(n) _s_ZMMReg[15 - (n)] | |
1349 | #define ZMM_Q(n) _q_ZMMReg[7 - (n)] | |
1350 | #define ZMM_D(n) _d_ZMMReg[7 - (n)] | |
1351 | #define ZMM_X(n) _x_ZMMReg[3 - (n)] | |
1352 | #define ZMM_Y(n) _y_ZMMReg[1 - (n)] | |
1353 | ||
1354 | #define XMM_Q(n) _q_XMMReg[1 - (n)] | |
1355 | ||
1356 | #define YMM_Q(n) _q_YMMReg[3 - (n)] | |
1357 | #define YMM_X(n) _x_YMMReg[1 - (n)] | |
1358 | ||
1359 | #define MMX_B(n) _b_MMXReg[7 - (n)] | |
1360 | #define MMX_W(n) _w_MMXReg[3 - (n)] | |
1361 | #define MMX_L(n) _l_MMXReg[1 - (n)] | |
1362 | #define MMX_S(n) _s_MMXReg[1 - (n)] | |
1363 | #else | |
1364 | #define ZMM_B(n) _b_ZMMReg[n] | |
1365 | #define ZMM_W(n) _w_ZMMReg[n] | |
1366 | #define ZMM_L(n) _l_ZMMReg[n] | |
1367 | #define ZMM_H(n) _h_ZMMReg[n] | |
1368 | #define ZMM_S(n) _s_ZMMReg[n] | |
1369 | #define ZMM_Q(n) _q_ZMMReg[n] | |
1370 | #define ZMM_D(n) _d_ZMMReg[n] | |
1371 | #define ZMM_X(n) _x_ZMMReg[n] | |
1372 | #define ZMM_Y(n) _y_ZMMReg[n] | |
1373 | ||
1374 | #define XMM_Q(n) _q_XMMReg[n] | |
1375 | ||
1376 | #define YMM_Q(n) _q_YMMReg[n] | |
1377 | #define YMM_X(n) _x_YMMReg[n] | |
1378 | ||
1379 | #define MMX_B(n) _b_MMXReg[n] | |
1380 | #define MMX_W(n) _w_MMXReg[n] | |
1381 | #define MMX_L(n) _l_MMXReg[n] | |
1382 | #define MMX_S(n) _s_MMXReg[n] | |
1383 | #endif | |
1384 | #define MMX_Q(n) _q_MMXReg[n] | |
1385 | ||
1386 | typedef union { | |
1387 | floatx80 d __attribute__((aligned(16))); | |
1388 | MMXReg mmx; | |
1389 | } FPReg; | |
1390 | ||
1391 | typedef struct { | |
1392 | uint64_t base; | |
1393 | uint64_t mask; | |
1394 | } MTRRVar; | |
1395 | ||
1396 | #define CPU_NB_REGS64 16 | |
1397 | #define CPU_NB_REGS32 8 | |
1398 | ||
1399 | #ifdef TARGET_X86_64 | |
1400 | #define CPU_NB_REGS CPU_NB_REGS64 | |
1401 | #else | |
1402 | #define CPU_NB_REGS CPU_NB_REGS32 | |
1403 | #endif | |
1404 | ||
1405 | #define MAX_FIXED_COUNTERS 3 | |
1406 | #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) | |
1407 | ||
1408 | #define TARGET_INSN_START_EXTRA_WORDS 1 | |
1409 | ||
1410 | #define NB_OPMASK_REGS 8 | |
1411 | ||
1412 | /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish | |
1413 | * that APIC ID hasn't been set yet | |
1414 | */ | |
1415 | #define UNASSIGNED_APIC_ID 0xFFFFFFFF | |
1416 | ||
1417 | typedef union X86LegacyXSaveArea { | |
1418 | struct { | |
1419 | uint16_t fcw; | |
1420 | uint16_t fsw; | |
1421 | uint8_t ftw; | |
1422 | uint8_t reserved; | |
1423 | uint16_t fpop; | |
1424 | uint64_t fpip; | |
1425 | uint64_t fpdp; | |
1426 | uint32_t mxcsr; | |
1427 | uint32_t mxcsr_mask; | |
1428 | FPReg fpregs[8]; | |
1429 | uint8_t xmm_regs[16][16]; | |
1430 | }; | |
1431 | uint8_t data[512]; | |
1432 | } X86LegacyXSaveArea; | |
1433 | ||
1434 | typedef struct X86XSaveHeader { | |
1435 | uint64_t xstate_bv; | |
1436 | uint64_t xcomp_bv; | |
1437 | uint64_t reserve0; | |
1438 | uint8_t reserved[40]; | |
1439 | } X86XSaveHeader; | |
1440 | ||
1441 | /* Ext. save area 2: AVX State */ | |
1442 | typedef struct XSaveAVX { | |
1443 | uint8_t ymmh[16][16]; | |
1444 | } XSaveAVX; | |
1445 | ||
1446 | /* Ext. save area 3: BNDREG */ | |
1447 | typedef struct XSaveBNDREG { | |
1448 | BNDReg bnd_regs[4]; | |
1449 | } XSaveBNDREG; | |
1450 | ||
1451 | /* Ext. save area 4: BNDCSR */ | |
1452 | typedef union XSaveBNDCSR { | |
1453 | BNDCSReg bndcsr; | |
1454 | uint8_t data[64]; | |
1455 | } XSaveBNDCSR; | |
1456 | ||
1457 | /* Ext. save area 5: Opmask */ | |
1458 | typedef struct XSaveOpmask { | |
1459 | uint64_t opmask_regs[NB_OPMASK_REGS]; | |
1460 | } XSaveOpmask; | |
1461 | ||
1462 | /* Ext. save area 6: ZMM_Hi256 */ | |
1463 | typedef struct XSaveZMM_Hi256 { | |
1464 | uint8_t zmm_hi256[16][32]; | |
1465 | } XSaveZMM_Hi256; | |
1466 | ||
1467 | /* Ext. save area 7: Hi16_ZMM */ | |
1468 | typedef struct XSaveHi16_ZMM { | |
1469 | uint8_t hi16_zmm[16][64]; | |
1470 | } XSaveHi16_ZMM; | |
1471 | ||
1472 | /* Ext. save area 9: PKRU state */ | |
1473 | typedef struct XSavePKRU { | |
1474 | uint32_t pkru; | |
1475 | uint32_t padding; | |
1476 | } XSavePKRU; | |
1477 | ||
1478 | /* Ext. save area 17: AMX XTILECFG state */ | |
1479 | typedef struct XSaveXTILECFG { | |
1480 | uint8_t xtilecfg[64]; | |
1481 | } XSaveXTILECFG; | |
1482 | ||
1483 | /* Ext. save area 18: AMX XTILEDATA state */ | |
1484 | typedef struct XSaveXTILEDATA { | |
1485 | uint8_t xtiledata[8][1024]; | |
1486 | } XSaveXTILEDATA; | |
1487 | ||
1488 | typedef struct { | |
1489 | uint64_t from; | |
1490 | uint64_t to; | |
1491 | uint64_t info; | |
1492 | } LBREntry; | |
1493 | ||
1494 | #define ARCH_LBR_NR_ENTRIES 32 | |
1495 | ||
1496 | /* Ext. save area 19: Supervisor mode Arch LBR state */ | |
1497 | typedef struct XSavesArchLBR { | |
1498 | uint64_t lbr_ctl; | |
1499 | uint64_t lbr_depth; | |
1500 | uint64_t ler_from; | |
1501 | uint64_t ler_to; | |
1502 | uint64_t ler_info; | |
1503 | LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; | |
1504 | } XSavesArchLBR; | |
1505 | ||
1506 | QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); | |
1507 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); | |
1508 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); | |
1509 | QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); | |
1510 | QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); | |
1511 | QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); | |
1512 | QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); | |
1513 | QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40); | |
1514 | QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000); | |
1515 | QEMU_BUILD_BUG_ON(sizeof(XSavesArchLBR) != 0x328); | |
1516 | ||
1517 | typedef struct ExtSaveArea { | |
1518 | uint32_t feature, bits; | |
1519 | uint32_t offset, size; | |
1520 | uint32_t ecx; | |
1521 | } ExtSaveArea; | |
1522 | ||
1523 | #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) | |
1524 | ||
1525 | extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; | |
1526 | ||
1527 | typedef enum TPRAccess { | |
1528 | TPR_ACCESS_READ, | |
1529 | TPR_ACCESS_WRITE, | |
1530 | } TPRAccess; | |
1531 | ||
1532 | /* Cache information data structures: */ | |
1533 | ||
1534 | enum CacheType { | |
1535 | DATA_CACHE, | |
1536 | INSTRUCTION_CACHE, | |
1537 | UNIFIED_CACHE | |
1538 | }; | |
1539 | ||
1540 | typedef struct CPUCacheInfo { | |
1541 | enum CacheType type; | |
1542 | uint8_t level; | |
1543 | /* Size in bytes */ | |
1544 | uint32_t size; | |
1545 | /* Line size, in bytes */ | |
1546 | uint16_t line_size; | |
1547 | /* | |
1548 | * Associativity. | |
1549 | * Note: representation of fully-associative caches is not implemented | |
1550 | */ | |
1551 | uint8_t associativity; | |
1552 | /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */ | |
1553 | uint8_t partitions; | |
1554 | /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */ | |
1555 | uint32_t sets; | |
1556 | /* | |
1557 | * Lines per tag. | |
1558 | * AMD-specific: CPUID[0x80000005], CPUID[0x80000006]. | |
1559 | * (Is this synonym to @partitions?) | |
1560 | */ | |
1561 | uint8_t lines_per_tag; | |
1562 | ||
1563 | /* Self-initializing cache */ | |
1564 | bool self_init; | |
1565 | /* | |
1566 | * WBINVD/INVD is not guaranteed to act upon lower level caches of | |
1567 | * non-originating threads sharing this cache. | |
1568 | * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0] | |
1569 | */ | |
1570 | bool no_invd_sharing; | |
1571 | /* | |
1572 | * Cache is inclusive of lower cache levels. | |
1573 | * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1]. | |
1574 | */ | |
1575 | bool inclusive; | |
1576 | /* | |
1577 | * A complex function is used to index the cache, potentially using all | |
1578 | * address bits. CPUID[4].EDX[bit 2]. | |
1579 | */ | |
1580 | bool complex_indexing; | |
1581 | } CPUCacheInfo; | |
1582 | ||
1583 | ||
1584 | typedef struct CPUCaches { | |
1585 | CPUCacheInfo *l1d_cache; | |
1586 | CPUCacheInfo *l1i_cache; | |
1587 | CPUCacheInfo *l2_cache; | |
1588 | CPUCacheInfo *l3_cache; | |
1589 | } CPUCaches; | |
1590 | ||
1591 | typedef struct HVFX86LazyFlags { | |
1592 | target_ulong result; | |
1593 | target_ulong auxbits; | |
1594 | } HVFX86LazyFlags; | |
1595 | ||
1596 | typedef struct CPUArchState { | |
1597 | /* standard registers */ | |
1598 | target_ulong regs[CPU_NB_REGS]; | |
1599 | target_ulong eip; | |
1600 | target_ulong eflags; /* eflags register. During CPU emulation, CC | |
1601 | flags and DF are set to zero because they are | |
1602 | stored elsewhere */ | |
1603 | ||
1604 | /* emulator internal eflags handling */ | |
1605 | target_ulong cc_dst; | |
1606 | target_ulong cc_src; | |
1607 | target_ulong cc_src2; | |
1608 | uint32_t cc_op; | |
1609 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ | |
1610 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags | |
1611 | are known at translation time. */ | |
1612 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ | |
1613 | ||
1614 | /* segments */ | |
1615 | SegmentCache segs[6]; /* selector values */ | |
1616 | SegmentCache ldt; | |
1617 | SegmentCache tr; | |
1618 | SegmentCache gdt; /* only base and limit are used */ | |
1619 | SegmentCache idt; /* only base and limit are used */ | |
1620 | ||
1621 | target_ulong cr[5]; /* NOTE: cr1 is unused */ | |
1622 | ||
1623 | bool pdptrs_valid; | |
1624 | uint64_t pdptrs[4]; | |
1625 | int32_t a20_mask; | |
1626 | ||
1627 | BNDReg bnd_regs[4]; | |
1628 | BNDCSReg bndcs_regs; | |
1629 | uint64_t msr_bndcfgs; | |
1630 | uint64_t efer; | |
1631 | ||
1632 | /* Beginning of state preserved by INIT (dummy marker). */ | |
1633 | struct {} start_init_save; | |
1634 | ||
1635 | /* FPU state */ | |
1636 | unsigned int fpstt; /* top of stack index */ | |
1637 | uint16_t fpus; | |
1638 | uint16_t fpuc; | |
1639 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ | |
1640 | FPReg fpregs[8]; | |
1641 | /* KVM-only so far */ | |
1642 | uint16_t fpop; | |
1643 | uint16_t fpcs; | |
1644 | uint16_t fpds; | |
1645 | uint64_t fpip; | |
1646 | uint64_t fpdp; | |
1647 | ||
1648 | /* emulator internal variables */ | |
1649 | float_status fp_status; | |
1650 | floatx80 ft0; | |
1651 | ||
1652 | float_status mmx_status; /* for 3DNow! float ops */ | |
1653 | float_status sse_status; | |
1654 | uint32_t mxcsr; | |
1655 | ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16); | |
1656 | ZMMReg xmm_t0 QEMU_ALIGNED(16); | |
1657 | MMXReg mmx_t0; | |
1658 | ||
1659 | uint64_t opmask_regs[NB_OPMASK_REGS]; | |
1660 | #ifdef TARGET_X86_64 | |
1661 | uint8_t xtilecfg[64]; | |
1662 | uint8_t xtiledata[8192]; | |
1663 | #endif | |
1664 | ||
1665 | /* sysenter registers */ | |
1666 | uint32_t sysenter_cs; | |
1667 | target_ulong sysenter_esp; | |
1668 | target_ulong sysenter_eip; | |
1669 | uint64_t star; | |
1670 | ||
1671 | uint64_t vm_hsave; | |
1672 | ||
1673 | #ifdef TARGET_X86_64 | |
1674 | target_ulong lstar; | |
1675 | target_ulong cstar; | |
1676 | target_ulong fmask; | |
1677 | target_ulong kernelgsbase; | |
1678 | #endif | |
1679 | ||
1680 | uint64_t tsc_adjust; | |
1681 | uint64_t tsc_deadline; | |
1682 | uint64_t tsc_aux; | |
1683 | ||
1684 | uint64_t xcr0; | |
1685 | ||
1686 | uint64_t mcg_status; | |
1687 | uint64_t msr_ia32_misc_enable; | |
1688 | uint64_t msr_ia32_feature_control; | |
1689 | uint64_t msr_ia32_sgxlepubkeyhash[4]; | |
1690 | ||
1691 | uint64_t msr_fixed_ctr_ctrl; | |
1692 | uint64_t msr_global_ctrl; | |
1693 | uint64_t msr_global_status; | |
1694 | uint64_t msr_global_ovf_ctrl; | |
1695 | uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; | |
1696 | uint64_t msr_gp_counters[MAX_GP_COUNTERS]; | |
1697 | uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; | |
1698 | ||
1699 | uint64_t pat; | |
1700 | uint32_t smbase; | |
1701 | uint64_t msr_smi_count; | |
1702 | ||
1703 | uint32_t pkru; | |
1704 | uint32_t pkrs; | |
1705 | uint32_t tsx_ctrl; | |
1706 | ||
1707 | uint64_t spec_ctrl; | |
1708 | uint64_t amd_tsc_scale_msr; | |
1709 | uint64_t virt_ssbd; | |
1710 | ||
1711 | /* End of state preserved by INIT (dummy marker). */ | |
1712 | struct {} end_init_save; | |
1713 | ||
1714 | uint64_t system_time_msr; | |
1715 | uint64_t wall_clock_msr; | |
1716 | uint64_t steal_time_msr; | |
1717 | uint64_t async_pf_en_msr; | |
1718 | uint64_t async_pf_int_msr; | |
1719 | uint64_t pv_eoi_en_msr; | |
1720 | uint64_t poll_control_msr; | |
1721 | ||
1722 | /* Partition-wide HV MSRs, will be updated only on the first vcpu */ | |
1723 | uint64_t msr_hv_hypercall; | |
1724 | uint64_t msr_hv_guest_os_id; | |
1725 | uint64_t msr_hv_tsc; | |
1726 | uint64_t msr_hv_syndbg_control; | |
1727 | uint64_t msr_hv_syndbg_status; | |
1728 | uint64_t msr_hv_syndbg_send_page; | |
1729 | uint64_t msr_hv_syndbg_recv_page; | |
1730 | uint64_t msr_hv_syndbg_pending_page; | |
1731 | uint64_t msr_hv_syndbg_options; | |
1732 | ||
1733 | /* Per-VCPU HV MSRs */ | |
1734 | uint64_t msr_hv_vapic; | |
1735 | uint64_t msr_hv_crash_params[HV_CRASH_PARAMS]; | |
1736 | uint64_t msr_hv_runtime; | |
1737 | uint64_t msr_hv_synic_control; | |
1738 | uint64_t msr_hv_synic_evt_page; | |
1739 | uint64_t msr_hv_synic_msg_page; | |
1740 | uint64_t msr_hv_synic_sint[HV_SINT_COUNT]; | |
1741 | uint64_t msr_hv_stimer_config[HV_STIMER_COUNT]; | |
1742 | uint64_t msr_hv_stimer_count[HV_STIMER_COUNT]; | |
1743 | uint64_t msr_hv_reenlightenment_control; | |
1744 | uint64_t msr_hv_tsc_emulation_control; | |
1745 | uint64_t msr_hv_tsc_emulation_status; | |
1746 | ||
1747 | uint64_t msr_rtit_ctrl; | |
1748 | uint64_t msr_rtit_status; | |
1749 | uint64_t msr_rtit_output_base; | |
1750 | uint64_t msr_rtit_output_mask; | |
1751 | uint64_t msr_rtit_cr3_match; | |
1752 | uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; | |
1753 | ||
1754 | /* Per-VCPU XFD MSRs */ | |
1755 | uint64_t msr_xfd; | |
1756 | uint64_t msr_xfd_err; | |
1757 | ||
1758 | /* Per-VCPU Arch LBR MSRs */ | |
1759 | uint64_t msr_lbr_ctl; | |
1760 | uint64_t msr_lbr_depth; | |
1761 | LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; | |
1762 | ||
1763 | /* exception/interrupt handling */ | |
1764 | int error_code; | |
1765 | int exception_is_int; | |
1766 | target_ulong exception_next_eip; | |
1767 | target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ | |
1768 | union { | |
1769 | struct CPUBreakpoint *cpu_breakpoint[4]; | |
1770 | struct CPUWatchpoint *cpu_watchpoint[4]; | |
1771 | }; /* break/watchpoints for dr[0..3] */ | |
1772 | int old_exception; /* exception in flight */ | |
1773 | ||
1774 | uint64_t vm_vmcb; | |
1775 | uint64_t tsc_offset; | |
1776 | uint64_t intercept; | |
1777 | uint16_t intercept_cr_read; | |
1778 | uint16_t intercept_cr_write; | |
1779 | uint16_t intercept_dr_read; | |
1780 | uint16_t intercept_dr_write; | |
1781 | uint32_t intercept_exceptions; | |
1782 | uint64_t nested_cr3; | |
1783 | uint32_t nested_pg_mode; | |
1784 | uint8_t v_tpr; | |
1785 | uint32_t int_ctl; | |
1786 | ||
1787 | /* KVM states, automatically cleared on reset */ | |
1788 | uint8_t nmi_injected; | |
1789 | uint8_t nmi_pending; | |
1790 | ||
1791 | uintptr_t retaddr; | |
1792 | ||
1793 | /* Fields up to this point are cleared by a CPU reset */ | |
1794 | struct {} end_reset_fields; | |
1795 | ||
1796 | /* Fields after this point are preserved across CPU reset. */ | |
1797 | ||
1798 | /* processor features (e.g. for CPUID insn) */ | |
1799 | /* Minimum cpuid leaf 7 value */ | |
1800 | uint32_t cpuid_level_func7; | |
1801 | /* Actual cpuid leaf 7 value */ | |
1802 | uint32_t cpuid_min_level_func7; | |
1803 | /* Minimum level/xlevel/xlevel2, based on CPU model + features */ | |
1804 | uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2; | |
1805 | /* Maximum level/xlevel/xlevel2 value for auto-assignment: */ | |
1806 | uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2; | |
1807 | /* Actual level/xlevel/xlevel2 value: */ | |
1808 | uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2; | |
1809 | uint32_t cpuid_vendor1; | |
1810 | uint32_t cpuid_vendor2; | |
1811 | uint32_t cpuid_vendor3; | |
1812 | uint32_t cpuid_version; | |
1813 | FeatureWordArray features; | |
1814 | /* Features that were explicitly enabled/disabled */ | |
1815 | FeatureWordArray user_features; | |
1816 | uint32_t cpuid_model[12]; | |
1817 | /* Cache information for CPUID. When legacy-cache=on, the cache data | |
1818 | * on each CPUID leaf will be different, because we keep compatibility | |
1819 | * with old QEMU versions. | |
1820 | */ | |
1821 | CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd; | |
1822 | ||
1823 | /* MTRRs */ | |
1824 | uint64_t mtrr_fixed[11]; | |
1825 | uint64_t mtrr_deftype; | |
1826 | MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; | |
1827 | ||
1828 | /* For KVM */ | |
1829 | uint32_t mp_state; | |
1830 | int32_t exception_nr; | |
1831 | int32_t interrupt_injected; | |
1832 | uint8_t soft_interrupt; | |
1833 | uint8_t exception_pending; | |
1834 | uint8_t exception_injected; | |
1835 | uint8_t has_error_code; | |
1836 | uint8_t exception_has_payload; | |
1837 | uint64_t exception_payload; | |
1838 | uint8_t triple_fault_pending; | |
1839 | uint32_t ins_len; | |
1840 | uint32_t sipi_vector; | |
1841 | bool tsc_valid; | |
1842 | int64_t tsc_khz; | |
1843 | int64_t user_tsc_khz; /* for sanity check only */ | |
1844 | uint64_t apic_bus_freq; | |
1845 | uint64_t tsc; | |
1846 | #if defined(CONFIG_KVM) || defined(CONFIG_HVF) | |
1847 | void *xsave_buf; | |
1848 | uint32_t xsave_buf_len; | |
1849 | #endif | |
1850 | #if defined(CONFIG_KVM) | |
1851 | struct kvm_nested_state *nested_state; | |
1852 | MemoryRegion *xen_vcpu_info_mr; | |
1853 | void *xen_vcpu_info_hva; | |
1854 | uint64_t xen_vcpu_info_gpa; | |
1855 | uint64_t xen_vcpu_info_default_gpa; | |
1856 | uint64_t xen_vcpu_time_info_gpa; | |
1857 | uint64_t xen_vcpu_runstate_gpa; | |
1858 | uint8_t xen_vcpu_callback_vector; | |
1859 | bool xen_callback_asserted; | |
1860 | uint16_t xen_virq[XEN_NR_VIRQS]; | |
1861 | uint64_t xen_singleshot_timer_ns; | |
1862 | QEMUTimer *xen_singleshot_timer; | |
1863 | uint64_t xen_periodic_timer_period; | |
1864 | QEMUTimer *xen_periodic_timer; | |
1865 | QemuMutex xen_timers_lock; | |
1866 | #endif | |
1867 | #if defined(CONFIG_HVF) | |
1868 | HVFX86LazyFlags hvf_lflags; | |
1869 | void *hvf_mmio_buf; | |
1870 | #endif | |
1871 | ||
1872 | uint64_t mcg_cap; | |
1873 | uint64_t mcg_ctl; | |
1874 | uint64_t mcg_ext_ctl; | |
1875 | uint64_t mce_banks[MCE_BANKS_DEF*4]; | |
1876 | uint64_t xstate_bv; | |
1877 | ||
1878 | /* vmstate */ | |
1879 | uint16_t fpus_vmstate; | |
1880 | uint16_t fptag_vmstate; | |
1881 | uint16_t fpregs_format_vmstate; | |
1882 | ||
1883 | uint64_t xss; | |
1884 | uint32_t umwait; | |
1885 | ||
1886 | TPRAccess tpr_access_type; | |
1887 | ||
1888 | /* Number of dies within this CPU package. */ | |
1889 | unsigned nr_dies; | |
1890 | } CPUX86State; | |
1891 | ||
1892 | struct kvm_msrs; | |
1893 | ||
1894 | /** | |
1895 | * X86CPU: | |
1896 | * @env: #CPUX86State | |
1897 | * @migratable: If set, only migratable flags will be accepted when "enforce" | |
1898 | * mode is used, and only migratable flags will be included in the "host" | |
1899 | * CPU model. | |
1900 | * | |
1901 | * An x86 CPU. | |
1902 | */ | |
1903 | struct ArchCPU { | |
1904 | CPUState parent_obj; | |
1905 | ||
1906 | CPUX86State env; | |
1907 | VMChangeStateEntry *vmsentry; | |
1908 | ||
1909 | uint64_t ucode_rev; | |
1910 | ||
1911 | uint32_t hyperv_spinlock_attempts; | |
1912 | char *hyperv_vendor; | |
1913 | bool hyperv_synic_kvm_only; | |
1914 | uint64_t hyperv_features; | |
1915 | bool hyperv_passthrough; | |
1916 | OnOffAuto hyperv_no_nonarch_cs; | |
1917 | uint32_t hyperv_vendor_id[3]; | |
1918 | uint32_t hyperv_interface_id[4]; | |
1919 | uint32_t hyperv_limits[3]; | |
1920 | bool hyperv_enforce_cpuid; | |
1921 | uint32_t hyperv_ver_id_build; | |
1922 | uint16_t hyperv_ver_id_major; | |
1923 | uint16_t hyperv_ver_id_minor; | |
1924 | uint32_t hyperv_ver_id_sp; | |
1925 | uint8_t hyperv_ver_id_sb; | |
1926 | uint32_t hyperv_ver_id_sn; | |
1927 | ||
1928 | bool check_cpuid; | |
1929 | bool enforce_cpuid; | |
1930 | /* | |
1931 | * Force features to be enabled even if the host doesn't support them. | |
1932 | * This is dangerous and should be done only for testing CPUID | |
1933 | * compatibility. | |
1934 | */ | |
1935 | bool force_features; | |
1936 | bool expose_kvm; | |
1937 | bool expose_tcg; | |
1938 | bool migratable; | |
1939 | bool migrate_smi_count; | |
1940 | bool max_features; /* Enable all supported features automatically */ | |
1941 | uint32_t apic_id; | |
1942 | ||
1943 | /* Enables publishing of TSC increment and Local APIC bus frequencies to | |
1944 | * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */ | |
1945 | bool vmware_cpuid_freq; | |
1946 | ||
1947 | /* if true the CPUID code directly forward host cache leaves to the guest */ | |
1948 | bool cache_info_passthrough; | |
1949 | ||
1950 | /* if true the CPUID code directly forwards | |
1951 | * host monitor/mwait leaves to the guest */ | |
1952 | struct { | |
1953 | uint32_t eax; | |
1954 | uint32_t ebx; | |
1955 | uint32_t ecx; | |
1956 | uint32_t edx; | |
1957 | } mwait; | |
1958 | ||
1959 | /* Features that were filtered out because of missing host capabilities */ | |
1960 | FeatureWordArray filtered_features; | |
1961 | ||
1962 | /* Enable PMU CPUID bits. This can't be enabled by default yet because | |
1963 | * it doesn't have ABI stability guarantees, as it passes all PMU CPUID | |
1964 | * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel | |
1965 | * capabilities) directly to the guest. | |
1966 | */ | |
1967 | bool enable_pmu; | |
1968 | ||
1969 | /* | |
1970 | * Enable LBR_FMT bits of IA32_PERF_CAPABILITIES MSR. | |
1971 | * This can't be initialized with a default because it doesn't have | |
1972 | * stable ABI support yet. It is only allowed to pass all LBR_FMT bits | |
1973 | * returned by kvm_arch_get_supported_msr_feature()(which depends on both | |
1974 | * host CPU and kernel capabilities) to the guest. | |
1975 | */ | |
1976 | uint64_t lbr_fmt; | |
1977 | ||
1978 | /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is | |
1979 | * disabled by default to avoid breaking migration between QEMU with | |
1980 | * different LMCE configurations. | |
1981 | */ | |
1982 | bool enable_lmce; | |
1983 | ||
1984 | /* Compatibility bits for old machine types. | |
1985 | * If true present virtual l3 cache for VM, the vcpus in the same virtual | |
1986 | * socket share an virtual l3 cache. | |
1987 | */ | |
1988 | bool enable_l3_cache; | |
1989 | ||
1990 | /* Compatibility bits for old machine types. | |
1991 | * If true present the old cache topology information | |
1992 | */ | |
1993 | bool legacy_cache; | |
1994 | ||
1995 | /* Compatibility bits for old machine types. | |
1996 | * If true decode the CPUID Function 0x8000001E_ECX to support multiple | |
1997 | * nodes per processor | |
1998 | */ | |
1999 | bool legacy_multi_node; | |
2000 | ||
2001 | /* Compatibility bits for old machine types: */ | |
2002 | bool enable_cpuid_0xb; | |
2003 | ||
2004 | /* Enable auto level-increase for all CPUID leaves */ | |
2005 | bool full_cpuid_auto_level; | |
2006 | ||
2007 | /* Only advertise CPUID leaves defined by the vendor */ | |
2008 | bool vendor_cpuid_only; | |
2009 | ||
2010 | /* Enable auto level-increase for Intel Processor Trace leave */ | |
2011 | bool intel_pt_auto_level; | |
2012 | ||
2013 | /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ | |
2014 | bool fill_mtrr_mask; | |
2015 | ||
2016 | /* if true override the phys_bits value with a value read from the host */ | |
2017 | bool host_phys_bits; | |
2018 | ||
2019 | /* if set, limit maximum value for phys_bits when host_phys_bits is true */ | |
2020 | uint8_t host_phys_bits_limit; | |
2021 | ||
2022 | /* Stop SMI delivery for migration compatibility with old machines */ | |
2023 | bool kvm_no_smi_migration; | |
2024 | ||
2025 | /* Forcefully disable KVM PV features not exposed in guest CPUIDs */ | |
2026 | bool kvm_pv_enforce_cpuid; | |
2027 | ||
2028 | /* Number of physical address bits supported */ | |
2029 | uint32_t phys_bits; | |
2030 | ||
2031 | /* | |
2032 | * Number of guest physical address bits available. Usually this is | |
2033 | * identical to host physical address bits. With NPT or EPT 4-level | |
2034 | * paging, guest physical address space might be restricted to 48 bits | |
2035 | * even if the host cpu supports more physical address bits. | |
2036 | */ | |
2037 | uint32_t guest_phys_bits; | |
2038 | ||
2039 | /* in order to simplify APIC support, we leave this pointer to the | |
2040 | user */ | |
2041 | struct DeviceState *apic_state; | |
2042 | struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; | |
2043 | Notifier machine_done; | |
2044 | ||
2045 | struct kvm_msrs *kvm_msr_buf; | |
2046 | ||
2047 | int32_t node_id; /* NUMA node this CPU belongs to */ | |
2048 | int32_t socket_id; | |
2049 | int32_t die_id; | |
2050 | int32_t core_id; | |
2051 | int32_t thread_id; | |
2052 | ||
2053 | int32_t hv_max_vps; | |
2054 | ||
2055 | bool xen_vapic; | |
2056 | }; | |
2057 | ||
2058 | typedef struct X86CPUModel X86CPUModel; | |
2059 | ||
2060 | /** | |
2061 | * X86CPUClass: | |
2062 | * @cpu_def: CPU model definition | |
2063 | * @host_cpuid_required: Whether CPU model requires cpuid from host. | |
2064 | * @ordering: Ordering on the "-cpu help" CPU model list. | |
2065 | * @migration_safe: See CpuDefinitionInfo::migration_safe | |
2066 | * @static_model: See CpuDefinitionInfo::static | |
2067 | * @parent_realize: The parent class' realize handler. | |
2068 | * @parent_phases: The parent class' reset phase handlers. | |
2069 | * | |
2070 | * An x86 CPU model or family. | |
2071 | */ | |
2072 | struct X86CPUClass { | |
2073 | CPUClass parent_class; | |
2074 | ||
2075 | /* | |
2076 | * CPU definition, automatically loaded by instance_init if not NULL. | |
2077 | * Should be eventually replaced by subclass-specific property defaults. | |
2078 | */ | |
2079 | X86CPUModel *model; | |
2080 | ||
2081 | bool host_cpuid_required; | |
2082 | int ordering; | |
2083 | bool migration_safe; | |
2084 | bool static_model; | |
2085 | ||
2086 | /* | |
2087 | * Optional description of CPU model. | |
2088 | * If unavailable, cpu_def->model_id is used. | |
2089 | */ | |
2090 | const char *model_description; | |
2091 | ||
2092 | DeviceRealize parent_realize; | |
2093 | DeviceUnrealize parent_unrealize; | |
2094 | ResettablePhases parent_phases; | |
2095 | }; | |
2096 | ||
2097 | #ifndef CONFIG_USER_ONLY | |
2098 | extern const VMStateDescription vmstate_x86_cpu; | |
2099 | #endif | |
2100 | ||
2101 | int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); | |
2102 | ||
2103 | int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
2104 | int cpuid, DumpState *s); | |
2105 | int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
2106 | int cpuid, DumpState *s); | |
2107 | int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
2108 | DumpState *s); | |
2109 | int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
2110 | DumpState *s); | |
2111 | ||
2112 | bool x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
2113 | Error **errp); | |
2114 | ||
2115 | void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); | |
2116 | ||
2117 | int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); | |
2118 | int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); | |
2119 | ||
2120 | void x86_cpu_list(void); | |
2121 | int cpu_x86_support_mca_broadcast(CPUX86State *env); | |
2122 | ||
2123 | #ifndef CONFIG_USER_ONLY | |
2124 | hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, | |
2125 | MemTxAttrs *attrs); | |
2126 | int cpu_get_pic_interrupt(CPUX86State *s); | |
2127 | ||
2128 | /* MS-DOS compatibility mode FPU exception support */ | |
2129 | void x86_register_ferr_irq(qemu_irq irq); | |
2130 | void fpu_check_raise_ferr_irq(CPUX86State *s); | |
2131 | void cpu_set_ignne(void); | |
2132 | void cpu_clear_ignne(void); | |
2133 | #endif | |
2134 | ||
2135 | /* mpx_helper.c */ | |
2136 | void cpu_sync_bndcs_hflags(CPUX86State *env); | |
2137 | ||
2138 | /* this function must always be used to load data in the segment | |
2139 | cache: it synchronizes the hflags with the segment cache values */ | |
2140 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, | |
2141 | X86Seg seg_reg, unsigned int selector, | |
2142 | target_ulong base, | |
2143 | unsigned int limit, | |
2144 | unsigned int flags) | |
2145 | { | |
2146 | SegmentCache *sc; | |
2147 | unsigned int new_hflags; | |
2148 | ||
2149 | sc = &env->segs[seg_reg]; | |
2150 | sc->selector = selector; | |
2151 | sc->base = base; | |
2152 | sc->limit = limit; | |
2153 | sc->flags = flags; | |
2154 | ||
2155 | /* update the hidden flags */ | |
2156 | { | |
2157 | if (seg_reg == R_CS) { | |
2158 | #ifdef TARGET_X86_64 | |
2159 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { | |
2160 | /* long mode */ | |
2161 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
2162 | env->hflags &= ~(HF_ADDSEG_MASK); | |
2163 | } else | |
2164 | #endif | |
2165 | { | |
2166 | /* legacy / compatibility case */ | |
2167 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) | |
2168 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); | |
2169 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | | |
2170 | new_hflags; | |
2171 | } | |
2172 | } | |
2173 | if (seg_reg == R_SS) { | |
2174 | int cpl = (flags >> DESC_DPL_SHIFT) & 3; | |
2175 | #if HF_CPL_MASK != 3 | |
2176 | #error HF_CPL_MASK is hardcoded | |
2177 | #endif | |
2178 | env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; | |
2179 | /* Possibly switch between BNDCFGS and BNDCFGU */ | |
2180 | cpu_sync_bndcs_hflags(env); | |
2181 | } | |
2182 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) | |
2183 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); | |
2184 | if (env->hflags & HF_CS64_MASK) { | |
2185 | /* zero base assumed for DS, ES and SS in long mode */ | |
2186 | } else if (!(env->cr[0] & CR0_PE_MASK) || | |
2187 | (env->eflags & VM_MASK) || | |
2188 | !(env->hflags & HF_CS32_MASK)) { | |
2189 | /* XXX: try to avoid this test. The problem comes from the | |
2190 | fact that is real mode or vm86 mode we only modify the | |
2191 | 'base' and 'selector' fields of the segment cache to go | |
2192 | faster. A solution may be to force addseg to one in | |
2193 | translate-i386.c. */ | |
2194 | new_hflags |= HF_ADDSEG_MASK; | |
2195 | } else { | |
2196 | new_hflags |= ((env->segs[R_DS].base | | |
2197 | env->segs[R_ES].base | | |
2198 | env->segs[R_SS].base) != 0) << | |
2199 | HF_ADDSEG_SHIFT; | |
2200 | } | |
2201 | env->hflags = (env->hflags & | |
2202 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; | |
2203 | } | |
2204 | } | |
2205 | ||
2206 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, | |
2207 | uint8_t sipi_vector) | |
2208 | { | |
2209 | CPUState *cs = CPU(cpu); | |
2210 | CPUX86State *env = &cpu->env; | |
2211 | ||
2212 | env->eip = 0; | |
2213 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, | |
2214 | sipi_vector << 12, | |
2215 | env->segs[R_CS].limit, | |
2216 | env->segs[R_CS].flags); | |
2217 | cs->halted = 0; | |
2218 | } | |
2219 | ||
2220 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, | |
2221 | target_ulong *base, unsigned int *limit, | |
2222 | unsigned int *flags); | |
2223 | ||
2224 | /* op_helper.c */ | |
2225 | /* used for debug or cpu save/restore */ | |
2226 | ||
2227 | /* cpu-exec.c */ | |
2228 | /* the following helpers are only usable in user mode simulation as | |
2229 | they can trigger unexpected exceptions */ | |
2230 | void cpu_x86_load_seg(CPUX86State *s, X86Seg seg_reg, int selector); | |
2231 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); | |
2232 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); | |
2233 | void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr); | |
2234 | void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr); | |
2235 | void cpu_x86_xsave(CPUX86State *s, target_ulong ptr); | |
2236 | void cpu_x86_xrstor(CPUX86State *s, target_ulong ptr); | |
2237 | ||
2238 | /* cpu.c */ | |
2239 | void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, | |
2240 | uint32_t vendor2, uint32_t vendor3); | |
2241 | typedef struct PropValue { | |
2242 | const char *prop, *value; | |
2243 | } PropValue; | |
2244 | void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); | |
2245 | ||
2246 | void x86_cpu_after_reset(X86CPU *cpu); | |
2247 | ||
2248 | uint32_t cpu_x86_virtual_addr_width(CPUX86State *env); | |
2249 | ||
2250 | /* cpu.c other functions (cpuid) */ | |
2251 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, | |
2252 | uint32_t *eax, uint32_t *ebx, | |
2253 | uint32_t *ecx, uint32_t *edx); | |
2254 | void cpu_clear_apic_feature(CPUX86State *env); | |
2255 | void cpu_set_apic_feature(CPUX86State *env); | |
2256 | void host_cpuid(uint32_t function, uint32_t count, | |
2257 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); | |
2258 | bool cpu_has_x2apic_feature(CPUX86State *env); | |
2259 | ||
2260 | /* helper.c */ | |
2261 | void x86_cpu_set_a20(X86CPU *cpu, int a20_state); | |
2262 | void cpu_sync_avx_hflag(CPUX86State *env); | |
2263 | ||
2264 | #ifndef CONFIG_USER_ONLY | |
2265 | static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) | |
2266 | { | |
2267 | return !!attrs.secure; | |
2268 | } | |
2269 | ||
2270 | static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs) | |
2271 | { | |
2272 | return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs)); | |
2273 | } | |
2274 | ||
2275 | /* | |
2276 | * load efer and update the corresponding hflags. XXX: do consistency | |
2277 | * checks with cpuid bits? | |
2278 | */ | |
2279 | void cpu_load_efer(CPUX86State *env, uint64_t val); | |
2280 | uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); | |
2281 | uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); | |
2282 | uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); | |
2283 | uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); | |
2284 | void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); | |
2285 | void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); | |
2286 | void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
2287 | void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); | |
2288 | void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); | |
2289 | #endif | |
2290 | ||
2291 | /* will be suppressed */ | |
2292 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); | |
2293 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); | |
2294 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); | |
2295 | void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); | |
2296 | ||
2297 | /* hw/pc.c */ | |
2298 | uint64_t cpu_get_tsc(CPUX86State *env); | |
2299 | ||
2300 | #define CPU_RESOLVING_TYPE TYPE_X86_CPU | |
2301 | ||
2302 | #ifdef TARGET_X86_64 | |
2303 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") | |
2304 | #else | |
2305 | #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") | |
2306 | #endif | |
2307 | ||
2308 | #define cpu_list x86_cpu_list | |
2309 | ||
2310 | /* MMU modes definitions */ | |
2311 | #define MMU_KSMAP64_IDX 0 | |
2312 | #define MMU_KSMAP32_IDX 1 | |
2313 | #define MMU_USER64_IDX 2 | |
2314 | #define MMU_USER32_IDX 3 | |
2315 | #define MMU_KNOSMAP64_IDX 4 | |
2316 | #define MMU_KNOSMAP32_IDX 5 | |
2317 | #define MMU_PHYS_IDX 6 | |
2318 | #define MMU_NESTED_IDX 7 | |
2319 | ||
2320 | #ifdef CONFIG_USER_ONLY | |
2321 | #ifdef TARGET_X86_64 | |
2322 | #define MMU_USER_IDX MMU_USER64_IDX | |
2323 | #else | |
2324 | #define MMU_USER_IDX MMU_USER32_IDX | |
2325 | #endif | |
2326 | #endif | |
2327 | ||
2328 | static inline bool is_mmu_index_smap(int mmu_index) | |
2329 | { | |
2330 | return (mmu_index & ~1) == MMU_KSMAP64_IDX; | |
2331 | } | |
2332 | ||
2333 | static inline bool is_mmu_index_user(int mmu_index) | |
2334 | { | |
2335 | return (mmu_index & ~1) == MMU_USER64_IDX; | |
2336 | } | |
2337 | ||
2338 | static inline bool is_mmu_index_32(int mmu_index) | |
2339 | { | |
2340 | assert(mmu_index < MMU_PHYS_IDX); | |
2341 | return mmu_index & 1; | |
2342 | } | |
2343 | ||
2344 | static inline int cpu_mmu_index_kernel(CPUX86State *env) | |
2345 | { | |
2346 | int mmu_index_32 = (env->hflags & HF_LMA_MASK) ? 0 : 1; | |
2347 | int mmu_index_base = | |
2348 | !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX : | |
2349 | ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX; | |
2350 | ||
2351 | return mmu_index_base + mmu_index_32; | |
2352 | } | |
2353 | ||
2354 | #define CC_DST (env->cc_dst) | |
2355 | #define CC_SRC (env->cc_src) | |
2356 | #define CC_SRC2 (env->cc_src2) | |
2357 | #define CC_OP (env->cc_op) | |
2358 | ||
2359 | #include "exec/cpu-all.h" | |
2360 | #include "svm.h" | |
2361 | ||
2362 | #if !defined(CONFIG_USER_ONLY) | |
2363 | #include "hw/i386/apic.h" | |
2364 | #endif | |
2365 | ||
2366 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, | |
2367 | uint64_t *cs_base, uint32_t *flags) | |
2368 | { | |
2369 | *flags = env->hflags | | |
2370 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); | |
2371 | if (env->hflags & HF_CS64_MASK) { | |
2372 | *cs_base = 0; | |
2373 | *pc = env->eip; | |
2374 | } else { | |
2375 | *cs_base = env->segs[R_CS].base; | |
2376 | *pc = (uint32_t)(*cs_base + env->eip); | |
2377 | } | |
2378 | } | |
2379 | ||
2380 | void do_cpu_init(X86CPU *cpu); | |
2381 | ||
2382 | #define MCE_INJECT_BROADCAST 1 | |
2383 | #define MCE_INJECT_UNCOND_AO 2 | |
2384 | ||
2385 | void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, | |
2386 | uint64_t status, uint64_t mcg_status, uint64_t addr, | |
2387 | uint64_t misc, int flags); | |
2388 | ||
2389 | uint32_t cpu_cc_compute_all(CPUX86State *env1); | |
2390 | ||
2391 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) | |
2392 | { | |
2393 | uint32_t eflags = env->eflags; | |
2394 | if (tcg_enabled()) { | |
2395 | eflags |= cpu_cc_compute_all(env) | (env->df & DF_MASK); | |
2396 | } | |
2397 | return eflags; | |
2398 | } | |
2399 | ||
2400 | static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) | |
2401 | { | |
2402 | return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); | |
2403 | } | |
2404 | ||
2405 | static inline int32_t x86_get_a20_mask(CPUX86State *env) | |
2406 | { | |
2407 | if (env->hflags & HF_SMM_MASK) { | |
2408 | return -1; | |
2409 | } else { | |
2410 | return env->a20_mask; | |
2411 | } | |
2412 | } | |
2413 | ||
2414 | static inline bool cpu_has_vmx(CPUX86State *env) | |
2415 | { | |
2416 | return env->features[FEAT_1_ECX] & CPUID_EXT_VMX; | |
2417 | } | |
2418 | ||
2419 | static inline bool cpu_has_svm(CPUX86State *env) | |
2420 | { | |
2421 | return env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM; | |
2422 | } | |
2423 | ||
2424 | /* | |
2425 | * In order for a vCPU to enter VMX operation it must have CR4.VMXE set. | |
2426 | * Since it was set, CR4.VMXE must remain set as long as vCPU is in | |
2427 | * VMX operation. This is because CR4.VMXE is one of the bits set | |
2428 | * in MSR_IA32_VMX_CR4_FIXED1. | |
2429 | * | |
2430 | * There is one exception to above statement when vCPU enters SMM mode. | |
2431 | * When a vCPU enters SMM mode, it temporarily exit VMX operation and | |
2432 | * may also reset CR4.VMXE during execution in SMM mode. | |
2433 | * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation | |
2434 | * and CR4.VMXE is restored to it's original value of being set. | |
2435 | * | |
2436 | * Therefore, when vCPU is not in SMM mode, we can infer whether | |
2437 | * VMX is being used by examining CR4.VMXE. Otherwise, we cannot | |
2438 | * know for certain. | |
2439 | */ | |
2440 | static inline bool cpu_vmx_maybe_enabled(CPUX86State *env) | |
2441 | { | |
2442 | return cpu_has_vmx(env) && | |
2443 | ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK)); | |
2444 | } | |
2445 | ||
2446 | /* excp_helper.c */ | |
2447 | int get_pg_mode(CPUX86State *env); | |
2448 | ||
2449 | /* fpu_helper.c */ | |
2450 | void update_fp_status(CPUX86State *env); | |
2451 | void update_mxcsr_status(CPUX86State *env); | |
2452 | void update_mxcsr_from_sse_status(CPUX86State *env); | |
2453 | ||
2454 | static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr) | |
2455 | { | |
2456 | env->mxcsr = mxcsr; | |
2457 | if (tcg_enabled()) { | |
2458 | update_mxcsr_status(env); | |
2459 | } | |
2460 | } | |
2461 | ||
2462 | static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc) | |
2463 | { | |
2464 | env->fpuc = fpuc; | |
2465 | if (tcg_enabled()) { | |
2466 | update_fp_status(env); | |
2467 | } | |
2468 | } | |
2469 | ||
2470 | /* svm_helper.c */ | |
2471 | #ifdef CONFIG_USER_ONLY | |
2472 | static inline void | |
2473 | cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, | |
2474 | uint64_t param, uintptr_t retaddr) | |
2475 | { /* no-op */ } | |
2476 | static inline bool | |
2477 | cpu_svm_has_intercept(CPUX86State *env, uint32_t type) | |
2478 | { return false; } | |
2479 | #else | |
2480 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, | |
2481 | uint64_t param, uintptr_t retaddr); | |
2482 | bool cpu_svm_has_intercept(CPUX86State *env, uint32_t type); | |
2483 | #endif | |
2484 | ||
2485 | /* apic.c */ | |
2486 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); | |
2487 | void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, | |
2488 | TPRAccess access); | |
2489 | ||
2490 | /* Special values for X86CPUVersion: */ | |
2491 | ||
2492 | /* Resolve to latest CPU version */ | |
2493 | #define CPU_VERSION_LATEST -1 | |
2494 | ||
2495 | /* | |
2496 | * Resolve to version defined by current machine type. | |
2497 | * See x86_cpu_set_default_version() | |
2498 | */ | |
2499 | #define CPU_VERSION_AUTO -2 | |
2500 | ||
2501 | /* Don't resolve to any versioned CPU models, like old QEMU versions */ | |
2502 | #define CPU_VERSION_LEGACY 0 | |
2503 | ||
2504 | typedef int X86CPUVersion; | |
2505 | ||
2506 | /* | |
2507 | * Set default CPU model version for CPU models having | |
2508 | * version == CPU_VERSION_AUTO. | |
2509 | */ | |
2510 | void x86_cpu_set_default_version(X86CPUVersion version); | |
2511 | ||
2512 | #ifndef CONFIG_USER_ONLY | |
2513 | ||
2514 | void do_cpu_sipi(X86CPU *cpu); | |
2515 | ||
2516 | #define APIC_DEFAULT_ADDRESS 0xfee00000 | |
2517 | #define APIC_SPACE_SIZE 0x100000 | |
2518 | ||
2519 | /* cpu-dump.c */ | |
2520 | void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); | |
2521 | ||
2522 | #endif | |
2523 | ||
2524 | /* cpu.c */ | |
2525 | bool cpu_is_bsp(X86CPU *cpu); | |
2526 | ||
2527 | void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void *buf, uint32_t buflen); | |
2528 | void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen); | |
2529 | uint32_t xsave_area_size(uint64_t mask, bool compacted); | |
2530 | void x86_update_hflags(CPUX86State* env); | |
2531 | ||
2532 | static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat) | |
2533 | { | |
2534 | return !!(cpu->hyperv_features & BIT(feat)); | |
2535 | } | |
2536 | ||
2537 | static inline uint64_t cr4_reserved_bits(CPUX86State *env) | |
2538 | { | |
2539 | uint64_t reserved_bits = CR4_RESERVED_MASK; | |
2540 | if (!env->features[FEAT_XSAVE]) { | |
2541 | reserved_bits |= CR4_OSXSAVE_MASK; | |
2542 | } | |
2543 | if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMEP)) { | |
2544 | reserved_bits |= CR4_SMEP_MASK; | |
2545 | } | |
2546 | if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) { | |
2547 | reserved_bits |= CR4_SMAP_MASK; | |
2548 | } | |
2549 | if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE)) { | |
2550 | reserved_bits |= CR4_FSGSBASE_MASK; | |
2551 | } | |
2552 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) { | |
2553 | reserved_bits |= CR4_PKE_MASK; | |
2554 | } | |
2555 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57)) { | |
2556 | reserved_bits |= CR4_LA57_MASK; | |
2557 | } | |
2558 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) { | |
2559 | reserved_bits |= CR4_UMIP_MASK; | |
2560 | } | |
2561 | if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) { | |
2562 | reserved_bits |= CR4_PKS_MASK; | |
2563 | } | |
2564 | return reserved_bits; | |
2565 | } | |
2566 | ||
2567 | static inline bool ctl_has_irq(CPUX86State *env) | |
2568 | { | |
2569 | uint32_t int_prio; | |
2570 | uint32_t tpr; | |
2571 | ||
2572 | int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT; | |
2573 | tpr = env->int_ctl & V_TPR_MASK; | |
2574 | ||
2575 | if (env->int_ctl & V_IGN_TPR_MASK) { | |
2576 | return (env->int_ctl & V_IRQ_MASK); | |
2577 | } | |
2578 | ||
2579 | return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr); | |
2580 | } | |
2581 | ||
2582 | #if defined(TARGET_X86_64) && \ | |
2583 | defined(CONFIG_USER_ONLY) && \ | |
2584 | defined(CONFIG_LINUX) | |
2585 | # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20) | |
2586 | #endif | |
2587 | ||
2588 | #endif /* I386_CPU_H */ |