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1 | /* | |
2 | * m68k translation | |
3 | * | |
4 | * Copyright (c) 2005-2007 CodeSourcery | |
5 | * Written by Paul Brook | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
22 | #include "cpu.h" | |
23 | #include "disas/disas.h" | |
24 | #include "exec/exec-all.h" | |
25 | #include "tcg-op.h" | |
26 | #include "qemu/log.h" | |
27 | #include "exec/cpu_ldst.h" | |
28 | ||
29 | #include "exec/helper-proto.h" | |
30 | #include "exec/helper-gen.h" | |
31 | ||
32 | #include "trace-tcg.h" | |
33 | #include "exec/log.h" | |
34 | ||
35 | ||
36 | //#define DEBUG_DISPATCH 1 | |
37 | ||
38 | /* Fake floating point. */ | |
39 | #define tcg_gen_mov_f64 tcg_gen_mov_i64 | |
40 | #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64 | |
41 | #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64 | |
42 | ||
43 | #define DEFO32(name, offset) static TCGv QREG_##name; | |
44 | #define DEFO64(name, offset) static TCGv_i64 QREG_##name; | |
45 | #define DEFF64(name, offset) static TCGv_i64 QREG_##name; | |
46 | #include "qregs.def" | |
47 | #undef DEFO32 | |
48 | #undef DEFO64 | |
49 | #undef DEFF64 | |
50 | ||
51 | static TCGv_i32 cpu_halted; | |
52 | static TCGv_i32 cpu_exception_index; | |
53 | ||
54 | static TCGv_env cpu_env; | |
55 | ||
56 | static char cpu_reg_names[3*8*3 + 5*4]; | |
57 | static TCGv cpu_dregs[8]; | |
58 | static TCGv cpu_aregs[8]; | |
59 | static TCGv_i64 cpu_fregs[8]; | |
60 | static TCGv_i64 cpu_macc[4]; | |
61 | ||
62 | #define REG(insn, pos) (((insn) >> (pos)) & 7) | |
63 | #define DREG(insn, pos) cpu_dregs[REG(insn, pos)] | |
64 | #define AREG(insn, pos) get_areg(s, REG(insn, pos)) | |
65 | #define FREG(insn, pos) cpu_fregs[REG(insn, pos)] | |
66 | #define MACREG(acc) cpu_macc[acc] | |
67 | #define QREG_SP get_areg(s, 7) | |
68 | ||
69 | static TCGv NULL_QREG; | |
70 | #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG)) | |
71 | /* Used to distinguish stores from bad addressing modes. */ | |
72 | static TCGv store_dummy; | |
73 | ||
74 | #include "exec/gen-icount.h" | |
75 | ||
76 | void m68k_tcg_init(void) | |
77 | { | |
78 | char *p; | |
79 | int i; | |
80 | ||
81 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
82 | tcg_ctx.tcg_env = cpu_env; | |
83 | ||
84 | #define DEFO32(name, offset) \ | |
85 | QREG_##name = tcg_global_mem_new_i32(cpu_env, \ | |
86 | offsetof(CPUM68KState, offset), #name); | |
87 | #define DEFO64(name, offset) \ | |
88 | QREG_##name = tcg_global_mem_new_i64(cpu_env, \ | |
89 | offsetof(CPUM68KState, offset), #name); | |
90 | #define DEFF64(name, offset) DEFO64(name, offset) | |
91 | #include "qregs.def" | |
92 | #undef DEFO32 | |
93 | #undef DEFO64 | |
94 | #undef DEFF64 | |
95 | ||
96 | cpu_halted = tcg_global_mem_new_i32(cpu_env, | |
97 | -offsetof(M68kCPU, env) + | |
98 | offsetof(CPUState, halted), "HALTED"); | |
99 | cpu_exception_index = tcg_global_mem_new_i32(cpu_env, | |
100 | -offsetof(M68kCPU, env) + | |
101 | offsetof(CPUState, exception_index), | |
102 | "EXCEPTION"); | |
103 | ||
104 | p = cpu_reg_names; | |
105 | for (i = 0; i < 8; i++) { | |
106 | sprintf(p, "D%d", i); | |
107 | cpu_dregs[i] = tcg_global_mem_new(cpu_env, | |
108 | offsetof(CPUM68KState, dregs[i]), p); | |
109 | p += 3; | |
110 | sprintf(p, "A%d", i); | |
111 | cpu_aregs[i] = tcg_global_mem_new(cpu_env, | |
112 | offsetof(CPUM68KState, aregs[i]), p); | |
113 | p += 3; | |
114 | sprintf(p, "F%d", i); | |
115 | cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env, | |
116 | offsetof(CPUM68KState, fregs[i]), p); | |
117 | p += 3; | |
118 | } | |
119 | for (i = 0; i < 4; i++) { | |
120 | sprintf(p, "ACC%d", i); | |
121 | cpu_macc[i] = tcg_global_mem_new_i64(cpu_env, | |
122 | offsetof(CPUM68KState, macc[i]), p); | |
123 | p += 5; | |
124 | } | |
125 | ||
126 | NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL"); | |
127 | store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL"); | |
128 | } | |
129 | ||
130 | /* internal defines */ | |
131 | typedef struct DisasContext { | |
132 | CPUM68KState *env; | |
133 | target_ulong insn_pc; /* Start of the current instruction. */ | |
134 | target_ulong pc; | |
135 | int is_jmp; | |
136 | CCOp cc_op; /* Current CC operation */ | |
137 | int cc_op_synced; | |
138 | int user; | |
139 | uint32_t fpcr; | |
140 | struct TranslationBlock *tb; | |
141 | int singlestep_enabled; | |
142 | TCGv_i64 mactmp; | |
143 | int done_mac; | |
144 | int writeback_mask; | |
145 | TCGv writeback[8]; | |
146 | } DisasContext; | |
147 | ||
148 | static TCGv get_areg(DisasContext *s, unsigned regno) | |
149 | { | |
150 | if (s->writeback_mask & (1 << regno)) { | |
151 | return s->writeback[regno]; | |
152 | } else { | |
153 | return cpu_aregs[regno]; | |
154 | } | |
155 | } | |
156 | ||
157 | static void delay_set_areg(DisasContext *s, unsigned regno, | |
158 | TCGv val, bool give_temp) | |
159 | { | |
160 | if (s->writeback_mask & (1 << regno)) { | |
161 | if (give_temp) { | |
162 | tcg_temp_free(s->writeback[regno]); | |
163 | s->writeback[regno] = val; | |
164 | } else { | |
165 | tcg_gen_mov_i32(s->writeback[regno], val); | |
166 | } | |
167 | } else { | |
168 | s->writeback_mask |= 1 << regno; | |
169 | if (give_temp) { | |
170 | s->writeback[regno] = val; | |
171 | } else { | |
172 | TCGv tmp = tcg_temp_new(); | |
173 | s->writeback[regno] = tmp; | |
174 | tcg_gen_mov_i32(tmp, val); | |
175 | } | |
176 | } | |
177 | } | |
178 | ||
179 | static void do_writebacks(DisasContext *s) | |
180 | { | |
181 | unsigned mask = s->writeback_mask; | |
182 | if (mask) { | |
183 | s->writeback_mask = 0; | |
184 | do { | |
185 | unsigned regno = ctz32(mask); | |
186 | tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]); | |
187 | tcg_temp_free(s->writeback[regno]); | |
188 | mask &= mask - 1; | |
189 | } while (mask); | |
190 | } | |
191 | } | |
192 | ||
193 | #define DISAS_JUMP_NEXT 4 | |
194 | ||
195 | #if defined(CONFIG_USER_ONLY) | |
196 | #define IS_USER(s) 1 | |
197 | #else | |
198 | #define IS_USER(s) s->user | |
199 | #endif | |
200 | ||
201 | /* XXX: move that elsewhere */ | |
202 | /* ??? Fix exceptions. */ | |
203 | static void *gen_throws_exception; | |
204 | #define gen_last_qop NULL | |
205 | ||
206 | typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); | |
207 | ||
208 | #ifdef DEBUG_DISPATCH | |
209 | #define DISAS_INSN(name) \ | |
210 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
211 | uint16_t insn); \ | |
212 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
213 | uint16_t insn) \ | |
214 | { \ | |
215 | qemu_log("Dispatch " #name "\n"); \ | |
216 | real_disas_##name(env, s, insn); \ | |
217 | } \ | |
218 | static void real_disas_##name(CPUM68KState *env, DisasContext *s, \ | |
219 | uint16_t insn) | |
220 | #else | |
221 | #define DISAS_INSN(name) \ | |
222 | static void disas_##name(CPUM68KState *env, DisasContext *s, \ | |
223 | uint16_t insn) | |
224 | #endif | |
225 | ||
226 | static const uint8_t cc_op_live[CC_OP_NB] = { | |
227 | [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X, | |
228 | [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V, | |
229 | [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V, | |
230 | [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V, | |
231 | [CC_OP_LOGIC] = CCF_X | CCF_N | |
232 | }; | |
233 | ||
234 | static void set_cc_op(DisasContext *s, CCOp op) | |
235 | { | |
236 | CCOp old_op = s->cc_op; | |
237 | int dead; | |
238 | ||
239 | if (old_op == op) { | |
240 | return; | |
241 | } | |
242 | s->cc_op = op; | |
243 | s->cc_op_synced = 0; | |
244 | ||
245 | /* Discard CC computation that will no longer be used. | |
246 | Note that X and N are never dead. */ | |
247 | dead = cc_op_live[old_op] & ~cc_op_live[op]; | |
248 | if (dead & CCF_C) { | |
249 | tcg_gen_discard_i32(QREG_CC_C); | |
250 | } | |
251 | if (dead & CCF_Z) { | |
252 | tcg_gen_discard_i32(QREG_CC_Z); | |
253 | } | |
254 | if (dead & CCF_V) { | |
255 | tcg_gen_discard_i32(QREG_CC_V); | |
256 | } | |
257 | } | |
258 | ||
259 | /* Update the CPU env CC_OP state. */ | |
260 | static void update_cc_op(DisasContext *s) | |
261 | { | |
262 | if (!s->cc_op_synced) { | |
263 | s->cc_op_synced = 1; | |
264 | tcg_gen_movi_i32(QREG_CC_OP, s->cc_op); | |
265 | } | |
266 | } | |
267 | ||
268 | /* Generate a load from the specified address. Narrow values are | |
269 | sign extended to full register width. */ | |
270 | static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) | |
271 | { | |
272 | TCGv tmp; | |
273 | int index = IS_USER(s); | |
274 | tmp = tcg_temp_new_i32(); | |
275 | switch(opsize) { | |
276 | case OS_BYTE: | |
277 | if (sign) | |
278 | tcg_gen_qemu_ld8s(tmp, addr, index); | |
279 | else | |
280 | tcg_gen_qemu_ld8u(tmp, addr, index); | |
281 | break; | |
282 | case OS_WORD: | |
283 | if (sign) | |
284 | tcg_gen_qemu_ld16s(tmp, addr, index); | |
285 | else | |
286 | tcg_gen_qemu_ld16u(tmp, addr, index); | |
287 | break; | |
288 | case OS_LONG: | |
289 | case OS_SINGLE: | |
290 | tcg_gen_qemu_ld32u(tmp, addr, index); | |
291 | break; | |
292 | default: | |
293 | g_assert_not_reached(); | |
294 | } | |
295 | gen_throws_exception = gen_last_qop; | |
296 | return tmp; | |
297 | } | |
298 | ||
299 | static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr) | |
300 | { | |
301 | TCGv_i64 tmp; | |
302 | int index = IS_USER(s); | |
303 | tmp = tcg_temp_new_i64(); | |
304 | tcg_gen_qemu_ldf64(tmp, addr, index); | |
305 | gen_throws_exception = gen_last_qop; | |
306 | return tmp; | |
307 | } | |
308 | ||
309 | /* Generate a store. */ | |
310 | static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) | |
311 | { | |
312 | int index = IS_USER(s); | |
313 | switch(opsize) { | |
314 | case OS_BYTE: | |
315 | tcg_gen_qemu_st8(val, addr, index); | |
316 | break; | |
317 | case OS_WORD: | |
318 | tcg_gen_qemu_st16(val, addr, index); | |
319 | break; | |
320 | case OS_LONG: | |
321 | case OS_SINGLE: | |
322 | tcg_gen_qemu_st32(val, addr, index); | |
323 | break; | |
324 | default: | |
325 | g_assert_not_reached(); | |
326 | } | |
327 | gen_throws_exception = gen_last_qop; | |
328 | } | |
329 | ||
330 | static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) | |
331 | { | |
332 | int index = IS_USER(s); | |
333 | tcg_gen_qemu_stf64(val, addr, index); | |
334 | gen_throws_exception = gen_last_qop; | |
335 | } | |
336 | ||
337 | typedef enum { | |
338 | EA_STORE, | |
339 | EA_LOADU, | |
340 | EA_LOADS | |
341 | } ea_what; | |
342 | ||
343 | /* Generate an unsigned load if VAL is 0 a signed load if val is -1, | |
344 | otherwise generate a store. */ | |
345 | static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val, | |
346 | ea_what what) | |
347 | { | |
348 | if (what == EA_STORE) { | |
349 | gen_store(s, opsize, addr, val); | |
350 | return store_dummy; | |
351 | } else { | |
352 | return gen_load(s, opsize, addr, what == EA_LOADS); | |
353 | } | |
354 | } | |
355 | ||
356 | /* Read a 16-bit immediate constant */ | |
357 | static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s) | |
358 | { | |
359 | uint16_t im; | |
360 | im = cpu_lduw_code(env, s->pc); | |
361 | s->pc += 2; | |
362 | return im; | |
363 | } | |
364 | ||
365 | /* Read an 8-bit immediate constant */ | |
366 | static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s) | |
367 | { | |
368 | return read_im16(env, s); | |
369 | } | |
370 | ||
371 | /* Read a 32-bit immediate constant. */ | |
372 | static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s) | |
373 | { | |
374 | uint32_t im; | |
375 | im = read_im16(env, s) << 16; | |
376 | im |= 0xffff & read_im16(env, s); | |
377 | return im; | |
378 | } | |
379 | ||
380 | /* Calculate and address index. */ | |
381 | static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp) | |
382 | { | |
383 | TCGv add; | |
384 | int scale; | |
385 | ||
386 | add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12); | |
387 | if ((ext & 0x800) == 0) { | |
388 | tcg_gen_ext16s_i32(tmp, add); | |
389 | add = tmp; | |
390 | } | |
391 | scale = (ext >> 9) & 3; | |
392 | if (scale != 0) { | |
393 | tcg_gen_shli_i32(tmp, add, scale); | |
394 | add = tmp; | |
395 | } | |
396 | return add; | |
397 | } | |
398 | ||
399 | /* Handle a base + index + displacement effective addresss. | |
400 | A NULL_QREG base means pc-relative. */ | |
401 | static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) | |
402 | { | |
403 | uint32_t offset; | |
404 | uint16_t ext; | |
405 | TCGv add; | |
406 | TCGv tmp; | |
407 | uint32_t bd, od; | |
408 | ||
409 | offset = s->pc; | |
410 | ext = read_im16(env, s); | |
411 | ||
412 | if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX)) | |
413 | return NULL_QREG; | |
414 | ||
415 | if (m68k_feature(s->env, M68K_FEATURE_M68000) && | |
416 | !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) { | |
417 | ext &= ~(3 << 9); | |
418 | } | |
419 | ||
420 | if (ext & 0x100) { | |
421 | /* full extension word format */ | |
422 | if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) | |
423 | return NULL_QREG; | |
424 | ||
425 | if ((ext & 0x30) > 0x10) { | |
426 | /* base displacement */ | |
427 | if ((ext & 0x30) == 0x20) { | |
428 | bd = (int16_t)read_im16(env, s); | |
429 | } else { | |
430 | bd = read_im32(env, s); | |
431 | } | |
432 | } else { | |
433 | bd = 0; | |
434 | } | |
435 | tmp = tcg_temp_new(); | |
436 | if ((ext & 0x44) == 0) { | |
437 | /* pre-index */ | |
438 | add = gen_addr_index(s, ext, tmp); | |
439 | } else { | |
440 | add = NULL_QREG; | |
441 | } | |
442 | if ((ext & 0x80) == 0) { | |
443 | /* base not suppressed */ | |
444 | if (IS_NULL_QREG(base)) { | |
445 | base = tcg_const_i32(offset + bd); | |
446 | bd = 0; | |
447 | } | |
448 | if (!IS_NULL_QREG(add)) { | |
449 | tcg_gen_add_i32(tmp, add, base); | |
450 | add = tmp; | |
451 | } else { | |
452 | add = base; | |
453 | } | |
454 | } | |
455 | if (!IS_NULL_QREG(add)) { | |
456 | if (bd != 0) { | |
457 | tcg_gen_addi_i32(tmp, add, bd); | |
458 | add = tmp; | |
459 | } | |
460 | } else { | |
461 | add = tcg_const_i32(bd); | |
462 | } | |
463 | if ((ext & 3) != 0) { | |
464 | /* memory indirect */ | |
465 | base = gen_load(s, OS_LONG, add, 0); | |
466 | if ((ext & 0x44) == 4) { | |
467 | add = gen_addr_index(s, ext, tmp); | |
468 | tcg_gen_add_i32(tmp, add, base); | |
469 | add = tmp; | |
470 | } else { | |
471 | add = base; | |
472 | } | |
473 | if ((ext & 3) > 1) { | |
474 | /* outer displacement */ | |
475 | if ((ext & 3) == 2) { | |
476 | od = (int16_t)read_im16(env, s); | |
477 | } else { | |
478 | od = read_im32(env, s); | |
479 | } | |
480 | } else { | |
481 | od = 0; | |
482 | } | |
483 | if (od != 0) { | |
484 | tcg_gen_addi_i32(tmp, add, od); | |
485 | add = tmp; | |
486 | } | |
487 | } | |
488 | } else { | |
489 | /* brief extension word format */ | |
490 | tmp = tcg_temp_new(); | |
491 | add = gen_addr_index(s, ext, tmp); | |
492 | if (!IS_NULL_QREG(base)) { | |
493 | tcg_gen_add_i32(tmp, add, base); | |
494 | if ((int8_t)ext) | |
495 | tcg_gen_addi_i32(tmp, tmp, (int8_t)ext); | |
496 | } else { | |
497 | tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext); | |
498 | } | |
499 | add = tmp; | |
500 | } | |
501 | return add; | |
502 | } | |
503 | ||
504 | /* Sign or zero extend a value. */ | |
505 | ||
506 | static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign) | |
507 | { | |
508 | switch (opsize) { | |
509 | case OS_BYTE: | |
510 | if (sign) { | |
511 | tcg_gen_ext8s_i32(res, val); | |
512 | } else { | |
513 | tcg_gen_ext8u_i32(res, val); | |
514 | } | |
515 | break; | |
516 | case OS_WORD: | |
517 | if (sign) { | |
518 | tcg_gen_ext16s_i32(res, val); | |
519 | } else { | |
520 | tcg_gen_ext16u_i32(res, val); | |
521 | } | |
522 | break; | |
523 | case OS_LONG: | |
524 | tcg_gen_mov_i32(res, val); | |
525 | break; | |
526 | default: | |
527 | g_assert_not_reached(); | |
528 | } | |
529 | } | |
530 | ||
531 | /* Evaluate all the CC flags. */ | |
532 | ||
533 | static void gen_flush_flags(DisasContext *s) | |
534 | { | |
535 | TCGv t0, t1; | |
536 | ||
537 | switch (s->cc_op) { | |
538 | case CC_OP_FLAGS: | |
539 | return; | |
540 | ||
541 | case CC_OP_ADDB: | |
542 | case CC_OP_ADDW: | |
543 | case CC_OP_ADDL: | |
544 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
545 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
546 | /* Compute signed overflow for addition. */ | |
547 | t0 = tcg_temp_new(); | |
548 | t1 = tcg_temp_new(); | |
549 | tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V); | |
550 | gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1); | |
551 | tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V); | |
552 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); | |
553 | tcg_temp_free(t0); | |
554 | tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V); | |
555 | tcg_temp_free(t1); | |
556 | break; | |
557 | ||
558 | case CC_OP_SUBB: | |
559 | case CC_OP_SUBW: | |
560 | case CC_OP_SUBL: | |
561 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
562 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
563 | /* Compute signed overflow for subtraction. */ | |
564 | t0 = tcg_temp_new(); | |
565 | t1 = tcg_temp_new(); | |
566 | tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V); | |
567 | gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1); | |
568 | tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V); | |
569 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0); | |
570 | tcg_temp_free(t0); | |
571 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1); | |
572 | tcg_temp_free(t1); | |
573 | break; | |
574 | ||
575 | case CC_OP_CMPB: | |
576 | case CC_OP_CMPW: | |
577 | case CC_OP_CMPL: | |
578 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V); | |
579 | tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V); | |
580 | gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1); | |
581 | /* Compute signed overflow for subtraction. */ | |
582 | t0 = tcg_temp_new(); | |
583 | tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N); | |
584 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N); | |
585 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0); | |
586 | tcg_temp_free(t0); | |
587 | tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z); | |
588 | break; | |
589 | ||
590 | case CC_OP_LOGIC: | |
591 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
592 | tcg_gen_movi_i32(QREG_CC_C, 0); | |
593 | tcg_gen_movi_i32(QREG_CC_V, 0); | |
594 | break; | |
595 | ||
596 | case CC_OP_DYNAMIC: | |
597 | gen_helper_flush_flags(cpu_env, QREG_CC_OP); | |
598 | break; | |
599 | ||
600 | default: | |
601 | t0 = tcg_const_i32(s->cc_op); | |
602 | gen_helper_flush_flags(cpu_env, t0); | |
603 | tcg_temp_free(t0); | |
604 | break; | |
605 | } | |
606 | ||
607 | /* Note that flush_flags also assigned to env->cc_op. */ | |
608 | s->cc_op = CC_OP_FLAGS; | |
609 | s->cc_op_synced = 1; | |
610 | } | |
611 | ||
612 | static inline TCGv gen_extend(TCGv val, int opsize, int sign) | |
613 | { | |
614 | TCGv tmp; | |
615 | ||
616 | if (opsize == OS_LONG) { | |
617 | tmp = val; | |
618 | } else { | |
619 | tmp = tcg_temp_new(); | |
620 | gen_ext(tmp, val, opsize, sign); | |
621 | } | |
622 | ||
623 | return tmp; | |
624 | } | |
625 | ||
626 | static void gen_logic_cc(DisasContext *s, TCGv val, int opsize) | |
627 | { | |
628 | gen_ext(QREG_CC_N, val, opsize, 1); | |
629 | set_cc_op(s, CC_OP_LOGIC); | |
630 | } | |
631 | ||
632 | static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize) | |
633 | { | |
634 | tcg_gen_mov_i32(QREG_CC_N, dest); | |
635 | tcg_gen_mov_i32(QREG_CC_V, src); | |
636 | set_cc_op(s, CC_OP_CMPB + opsize); | |
637 | } | |
638 | ||
639 | static void gen_update_cc_add(TCGv dest, TCGv src, int opsize) | |
640 | { | |
641 | gen_ext(QREG_CC_N, dest, opsize, 1); | |
642 | tcg_gen_mov_i32(QREG_CC_V, src); | |
643 | } | |
644 | ||
645 | static inline int opsize_bytes(int opsize) | |
646 | { | |
647 | switch (opsize) { | |
648 | case OS_BYTE: return 1; | |
649 | case OS_WORD: return 2; | |
650 | case OS_LONG: return 4; | |
651 | case OS_SINGLE: return 4; | |
652 | case OS_DOUBLE: return 8; | |
653 | case OS_EXTENDED: return 12; | |
654 | case OS_PACKED: return 12; | |
655 | default: | |
656 | g_assert_not_reached(); | |
657 | } | |
658 | } | |
659 | ||
660 | static inline int insn_opsize(int insn) | |
661 | { | |
662 | switch ((insn >> 6) & 3) { | |
663 | case 0: return OS_BYTE; | |
664 | case 1: return OS_WORD; | |
665 | case 2: return OS_LONG; | |
666 | default: | |
667 | g_assert_not_reached(); | |
668 | } | |
669 | } | |
670 | ||
671 | /* Assign value to a register. If the width is less than the register width | |
672 | only the low part of the register is set. */ | |
673 | static void gen_partset_reg(int opsize, TCGv reg, TCGv val) | |
674 | { | |
675 | TCGv tmp; | |
676 | switch (opsize) { | |
677 | case OS_BYTE: | |
678 | tcg_gen_andi_i32(reg, reg, 0xffffff00); | |
679 | tmp = tcg_temp_new(); | |
680 | tcg_gen_ext8u_i32(tmp, val); | |
681 | tcg_gen_or_i32(reg, reg, tmp); | |
682 | break; | |
683 | case OS_WORD: | |
684 | tcg_gen_andi_i32(reg, reg, 0xffff0000); | |
685 | tmp = tcg_temp_new(); | |
686 | tcg_gen_ext16u_i32(tmp, val); | |
687 | tcg_gen_or_i32(reg, reg, tmp); | |
688 | break; | |
689 | case OS_LONG: | |
690 | case OS_SINGLE: | |
691 | tcg_gen_mov_i32(reg, val); | |
692 | break; | |
693 | default: | |
694 | g_assert_not_reached(); | |
695 | } | |
696 | } | |
697 | ||
698 | /* Generate code for an "effective address". Does not adjust the base | |
699 | register for autoincrement addressing modes. */ | |
700 | static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s, | |
701 | int mode, int reg0, int opsize) | |
702 | { | |
703 | TCGv reg; | |
704 | TCGv tmp; | |
705 | uint16_t ext; | |
706 | uint32_t offset; | |
707 | ||
708 | switch (mode) { | |
709 | case 0: /* Data register direct. */ | |
710 | case 1: /* Address register direct. */ | |
711 | return NULL_QREG; | |
712 | case 2: /* Indirect register */ | |
713 | case 3: /* Indirect postincrement. */ | |
714 | return get_areg(s, reg0); | |
715 | case 4: /* Indirect predecrememnt. */ | |
716 | reg = get_areg(s, reg0); | |
717 | tmp = tcg_temp_new(); | |
718 | tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); | |
719 | return tmp; | |
720 | case 5: /* Indirect displacement. */ | |
721 | reg = get_areg(s, reg0); | |
722 | tmp = tcg_temp_new(); | |
723 | ext = read_im16(env, s); | |
724 | tcg_gen_addi_i32(tmp, reg, (int16_t)ext); | |
725 | return tmp; | |
726 | case 6: /* Indirect index + displacement. */ | |
727 | reg = get_areg(s, reg0); | |
728 | return gen_lea_indexed(env, s, reg); | |
729 | case 7: /* Other */ | |
730 | switch (reg0) { | |
731 | case 0: /* Absolute short. */ | |
732 | offset = (int16_t)read_im16(env, s); | |
733 | return tcg_const_i32(offset); | |
734 | case 1: /* Absolute long. */ | |
735 | offset = read_im32(env, s); | |
736 | return tcg_const_i32(offset); | |
737 | case 2: /* pc displacement */ | |
738 | offset = s->pc; | |
739 | offset += (int16_t)read_im16(env, s); | |
740 | return tcg_const_i32(offset); | |
741 | case 3: /* pc index+displacement. */ | |
742 | return gen_lea_indexed(env, s, NULL_QREG); | |
743 | case 4: /* Immediate. */ | |
744 | default: | |
745 | return NULL_QREG; | |
746 | } | |
747 | } | |
748 | /* Should never happen. */ | |
749 | return NULL_QREG; | |
750 | } | |
751 | ||
752 | static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn, | |
753 | int opsize) | |
754 | { | |
755 | int mode = extract32(insn, 3, 3); | |
756 | int reg0 = REG(insn, 0); | |
757 | return gen_lea_mode(env, s, mode, reg0, opsize); | |
758 | } | |
759 | ||
760 | /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is | |
761 | a write otherwise it is a read (0 == sign extend, -1 == zero extend). | |
762 | ADDRP is non-null for readwrite operands. */ | |
763 | static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0, | |
764 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
765 | { | |
766 | TCGv reg, tmp, result; | |
767 | int32_t offset; | |
768 | ||
769 | switch (mode) { | |
770 | case 0: /* Data register direct. */ | |
771 | reg = cpu_dregs[reg0]; | |
772 | if (what == EA_STORE) { | |
773 | gen_partset_reg(opsize, reg, val); | |
774 | return store_dummy; | |
775 | } else { | |
776 | return gen_extend(reg, opsize, what == EA_LOADS); | |
777 | } | |
778 | case 1: /* Address register direct. */ | |
779 | reg = get_areg(s, reg0); | |
780 | if (what == EA_STORE) { | |
781 | tcg_gen_mov_i32(reg, val); | |
782 | return store_dummy; | |
783 | } else { | |
784 | return gen_extend(reg, opsize, what == EA_LOADS); | |
785 | } | |
786 | case 2: /* Indirect register */ | |
787 | reg = get_areg(s, reg0); | |
788 | return gen_ldst(s, opsize, reg, val, what); | |
789 | case 3: /* Indirect postincrement. */ | |
790 | reg = get_areg(s, reg0); | |
791 | result = gen_ldst(s, opsize, reg, val, what); | |
792 | if (what == EA_STORE || !addrp) { | |
793 | TCGv tmp = tcg_temp_new(); | |
794 | tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize)); | |
795 | delay_set_areg(s, reg0, tmp, true); | |
796 | } | |
797 | return result; | |
798 | case 4: /* Indirect predecrememnt. */ | |
799 | if (addrp && what == EA_STORE) { | |
800 | tmp = *addrp; | |
801 | } else { | |
802 | tmp = gen_lea_mode(env, s, mode, reg0, opsize); | |
803 | if (IS_NULL_QREG(tmp)) { | |
804 | return tmp; | |
805 | } | |
806 | if (addrp) { | |
807 | *addrp = tmp; | |
808 | } | |
809 | } | |
810 | result = gen_ldst(s, opsize, tmp, val, what); | |
811 | if (what == EA_STORE || !addrp) { | |
812 | delay_set_areg(s, reg0, tmp, false); | |
813 | } | |
814 | return result; | |
815 | case 5: /* Indirect displacement. */ | |
816 | case 6: /* Indirect index + displacement. */ | |
817 | do_indirect: | |
818 | if (addrp && what == EA_STORE) { | |
819 | tmp = *addrp; | |
820 | } else { | |
821 | tmp = gen_lea_mode(env, s, mode, reg0, opsize); | |
822 | if (IS_NULL_QREG(tmp)) { | |
823 | return tmp; | |
824 | } | |
825 | if (addrp) { | |
826 | *addrp = tmp; | |
827 | } | |
828 | } | |
829 | return gen_ldst(s, opsize, tmp, val, what); | |
830 | case 7: /* Other */ | |
831 | switch (reg0) { | |
832 | case 0: /* Absolute short. */ | |
833 | case 1: /* Absolute long. */ | |
834 | case 2: /* pc displacement */ | |
835 | case 3: /* pc index+displacement. */ | |
836 | goto do_indirect; | |
837 | case 4: /* Immediate. */ | |
838 | /* Sign extend values for consistency. */ | |
839 | switch (opsize) { | |
840 | case OS_BYTE: | |
841 | if (what == EA_LOADS) { | |
842 | offset = (int8_t)read_im8(env, s); | |
843 | } else { | |
844 | offset = read_im8(env, s); | |
845 | } | |
846 | break; | |
847 | case OS_WORD: | |
848 | if (what == EA_LOADS) { | |
849 | offset = (int16_t)read_im16(env, s); | |
850 | } else { | |
851 | offset = read_im16(env, s); | |
852 | } | |
853 | break; | |
854 | case OS_LONG: | |
855 | offset = read_im32(env, s); | |
856 | break; | |
857 | default: | |
858 | g_assert_not_reached(); | |
859 | } | |
860 | return tcg_const_i32(offset); | |
861 | default: | |
862 | return NULL_QREG; | |
863 | } | |
864 | } | |
865 | /* Should never happen. */ | |
866 | return NULL_QREG; | |
867 | } | |
868 | ||
869 | static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn, | |
870 | int opsize, TCGv val, TCGv *addrp, ea_what what) | |
871 | { | |
872 | int mode = extract32(insn, 3, 3); | |
873 | int reg0 = REG(insn, 0); | |
874 | return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what); | |
875 | } | |
876 | ||
877 | typedef struct { | |
878 | TCGCond tcond; | |
879 | bool g1; | |
880 | bool g2; | |
881 | TCGv v1; | |
882 | TCGv v2; | |
883 | } DisasCompare; | |
884 | ||
885 | static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond) | |
886 | { | |
887 | TCGv tmp, tmp2; | |
888 | TCGCond tcond; | |
889 | CCOp op = s->cc_op; | |
890 | ||
891 | /* The CC_OP_CMP form can handle most normal comparisons directly. */ | |
892 | if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) { | |
893 | c->g1 = c->g2 = 1; | |
894 | c->v1 = QREG_CC_N; | |
895 | c->v2 = QREG_CC_V; | |
896 | switch (cond) { | |
897 | case 2: /* HI */ | |
898 | case 3: /* LS */ | |
899 | tcond = TCG_COND_LEU; | |
900 | goto done; | |
901 | case 4: /* CC */ | |
902 | case 5: /* CS */ | |
903 | tcond = TCG_COND_LTU; | |
904 | goto done; | |
905 | case 6: /* NE */ | |
906 | case 7: /* EQ */ | |
907 | tcond = TCG_COND_EQ; | |
908 | goto done; | |
909 | case 10: /* PL */ | |
910 | case 11: /* MI */ | |
911 | c->g1 = c->g2 = 0; | |
912 | c->v2 = tcg_const_i32(0); | |
913 | c->v1 = tmp = tcg_temp_new(); | |
914 | tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V); | |
915 | gen_ext(tmp, tmp, op - CC_OP_CMPB, 1); | |
916 | /* fallthru */ | |
917 | case 12: /* GE */ | |
918 | case 13: /* LT */ | |
919 | tcond = TCG_COND_LT; | |
920 | goto done; | |
921 | case 14: /* GT */ | |
922 | case 15: /* LE */ | |
923 | tcond = TCG_COND_LE; | |
924 | goto done; | |
925 | } | |
926 | } | |
927 | ||
928 | c->g1 = 1; | |
929 | c->g2 = 0; | |
930 | c->v2 = tcg_const_i32(0); | |
931 | ||
932 | switch (cond) { | |
933 | case 0: /* T */ | |
934 | case 1: /* F */ | |
935 | c->v1 = c->v2; | |
936 | tcond = TCG_COND_NEVER; | |
937 | goto done; | |
938 | case 14: /* GT (!(Z || (N ^ V))) */ | |
939 | case 15: /* LE (Z || (N ^ V)) */ | |
940 | /* Logic operations clear V, which simplifies LE to (Z || N), | |
941 | and since Z and N are co-located, this becomes a normal | |
942 | comparison vs N. */ | |
943 | if (op == CC_OP_LOGIC) { | |
944 | c->v1 = QREG_CC_N; | |
945 | tcond = TCG_COND_LE; | |
946 | goto done; | |
947 | } | |
948 | break; | |
949 | case 12: /* GE (!(N ^ V)) */ | |
950 | case 13: /* LT (N ^ V) */ | |
951 | /* Logic operations clear V, which simplifies this to N. */ | |
952 | if (op != CC_OP_LOGIC) { | |
953 | break; | |
954 | } | |
955 | /* fallthru */ | |
956 | case 10: /* PL (!N) */ | |
957 | case 11: /* MI (N) */ | |
958 | /* Several cases represent N normally. */ | |
959 | if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || | |
960 | op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL || | |
961 | op == CC_OP_LOGIC) { | |
962 | c->v1 = QREG_CC_N; | |
963 | tcond = TCG_COND_LT; | |
964 | goto done; | |
965 | } | |
966 | break; | |
967 | case 6: /* NE (!Z) */ | |
968 | case 7: /* EQ (Z) */ | |
969 | /* Some cases fold Z into N. */ | |
970 | if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || | |
971 | op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL || | |
972 | op == CC_OP_LOGIC) { | |
973 | tcond = TCG_COND_EQ; | |
974 | c->v1 = QREG_CC_N; | |
975 | goto done; | |
976 | } | |
977 | break; | |
978 | case 4: /* CC (!C) */ | |
979 | case 5: /* CS (C) */ | |
980 | /* Some cases fold C into X. */ | |
981 | if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || | |
982 | op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL) { | |
983 | tcond = TCG_COND_NE; | |
984 | c->v1 = QREG_CC_X; | |
985 | goto done; | |
986 | } | |
987 | /* fallthru */ | |
988 | case 8: /* VC (!V) */ | |
989 | case 9: /* VS (V) */ | |
990 | /* Logic operations clear V and C. */ | |
991 | if (op == CC_OP_LOGIC) { | |
992 | tcond = TCG_COND_NEVER; | |
993 | c->v1 = c->v2; | |
994 | goto done; | |
995 | } | |
996 | break; | |
997 | } | |
998 | ||
999 | /* Otherwise, flush flag state to CC_OP_FLAGS. */ | |
1000 | gen_flush_flags(s); | |
1001 | ||
1002 | switch (cond) { | |
1003 | case 0: /* T */ | |
1004 | case 1: /* F */ | |
1005 | default: | |
1006 | /* Invalid, or handled above. */ | |
1007 | abort(); | |
1008 | case 2: /* HI (!C && !Z) -> !(C || Z)*/ | |
1009 | case 3: /* LS (C || Z) */ | |
1010 | c->v1 = tmp = tcg_temp_new(); | |
1011 | c->g1 = 0; | |
1012 | tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); | |
1013 | tcg_gen_or_i32(tmp, tmp, QREG_CC_C); | |
1014 | tcond = TCG_COND_NE; | |
1015 | break; | |
1016 | case 4: /* CC (!C) */ | |
1017 | case 5: /* CS (C) */ | |
1018 | c->v1 = QREG_CC_C; | |
1019 | tcond = TCG_COND_NE; | |
1020 | break; | |
1021 | case 6: /* NE (!Z) */ | |
1022 | case 7: /* EQ (Z) */ | |
1023 | c->v1 = QREG_CC_Z; | |
1024 | tcond = TCG_COND_EQ; | |
1025 | break; | |
1026 | case 8: /* VC (!V) */ | |
1027 | case 9: /* VS (V) */ | |
1028 | c->v1 = QREG_CC_V; | |
1029 | tcond = TCG_COND_LT; | |
1030 | break; | |
1031 | case 10: /* PL (!N) */ | |
1032 | case 11: /* MI (N) */ | |
1033 | c->v1 = QREG_CC_N; | |
1034 | tcond = TCG_COND_LT; | |
1035 | break; | |
1036 | case 12: /* GE (!(N ^ V)) */ | |
1037 | case 13: /* LT (N ^ V) */ | |
1038 | c->v1 = tmp = tcg_temp_new(); | |
1039 | c->g1 = 0; | |
1040 | tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V); | |
1041 | tcond = TCG_COND_LT; | |
1042 | break; | |
1043 | case 14: /* GT (!(Z || (N ^ V))) */ | |
1044 | case 15: /* LE (Z || (N ^ V)) */ | |
1045 | c->v1 = tmp = tcg_temp_new(); | |
1046 | c->g1 = 0; | |
1047 | tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); | |
1048 | tcg_gen_neg_i32(tmp, tmp); | |
1049 | tmp2 = tcg_temp_new(); | |
1050 | tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); | |
1051 | tcg_gen_or_i32(tmp, tmp, tmp2); | |
1052 | tcg_temp_free(tmp2); | |
1053 | tcond = TCG_COND_LT; | |
1054 | break; | |
1055 | } | |
1056 | ||
1057 | done: | |
1058 | if ((cond & 1) == 0) { | |
1059 | tcond = tcg_invert_cond(tcond); | |
1060 | } | |
1061 | c->tcond = tcond; | |
1062 | } | |
1063 | ||
1064 | static void free_cond(DisasCompare *c) | |
1065 | { | |
1066 | if (!c->g1) { | |
1067 | tcg_temp_free(c->v1); | |
1068 | } | |
1069 | if (!c->g2) { | |
1070 | tcg_temp_free(c->v2); | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) | |
1075 | { | |
1076 | DisasCompare c; | |
1077 | ||
1078 | gen_cc_cond(&c, s, cond); | |
1079 | update_cc_op(s); | |
1080 | tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); | |
1081 | free_cond(&c); | |
1082 | } | |
1083 | ||
1084 | /* Force a TB lookup after an instruction that changes the CPU state. */ | |
1085 | static void gen_lookup_tb(DisasContext *s) | |
1086 | { | |
1087 | update_cc_op(s); | |
1088 | tcg_gen_movi_i32(QREG_PC, s->pc); | |
1089 | s->is_jmp = DISAS_UPDATE; | |
1090 | } | |
1091 | ||
1092 | /* Generate a jump to an immediate address. */ | |
1093 | static void gen_jmp_im(DisasContext *s, uint32_t dest) | |
1094 | { | |
1095 | update_cc_op(s); | |
1096 | tcg_gen_movi_i32(QREG_PC, dest); | |
1097 | s->is_jmp = DISAS_JUMP; | |
1098 | } | |
1099 | ||
1100 | /* Generate a jump to the address in qreg DEST. */ | |
1101 | static void gen_jmp(DisasContext *s, TCGv dest) | |
1102 | { | |
1103 | update_cc_op(s); | |
1104 | tcg_gen_mov_i32(QREG_PC, dest); | |
1105 | s->is_jmp = DISAS_JUMP; | |
1106 | } | |
1107 | ||
1108 | static void gen_exception(DisasContext *s, uint32_t where, int nr) | |
1109 | { | |
1110 | update_cc_op(s); | |
1111 | gen_jmp_im(s, where); | |
1112 | gen_helper_raise_exception(cpu_env, tcg_const_i32(nr)); | |
1113 | } | |
1114 | ||
1115 | static inline void gen_addr_fault(DisasContext *s) | |
1116 | { | |
1117 | gen_exception(s, s->insn_pc, EXCP_ADDRESS); | |
1118 | } | |
1119 | ||
1120 | #define SRC_EA(env, result, opsize, op_sign, addrp) do { \ | |
1121 | result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \ | |
1122 | op_sign ? EA_LOADS : EA_LOADU); \ | |
1123 | if (IS_NULL_QREG(result)) { \ | |
1124 | gen_addr_fault(s); \ | |
1125 | return; \ | |
1126 | } \ | |
1127 | } while (0) | |
1128 | ||
1129 | #define DEST_EA(env, insn, opsize, val, addrp) do { \ | |
1130 | TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \ | |
1131 | if (IS_NULL_QREG(ea_result)) { \ | |
1132 | gen_addr_fault(s); \ | |
1133 | return; \ | |
1134 | } \ | |
1135 | } while (0) | |
1136 | ||
1137 | static inline bool use_goto_tb(DisasContext *s, uint32_t dest) | |
1138 | { | |
1139 | #ifndef CONFIG_USER_ONLY | |
1140 | return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) || | |
1141 | (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
1142 | #else | |
1143 | return true; | |
1144 | #endif | |
1145 | } | |
1146 | ||
1147 | /* Generate a jump to an immediate address. */ | |
1148 | static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) | |
1149 | { | |
1150 | if (unlikely(s->singlestep_enabled)) { | |
1151 | gen_exception(s, dest, EXCP_DEBUG); | |
1152 | } else if (use_goto_tb(s, dest)) { | |
1153 | tcg_gen_goto_tb(n); | |
1154 | tcg_gen_movi_i32(QREG_PC, dest); | |
1155 | tcg_gen_exit_tb((uintptr_t)s->tb + n); | |
1156 | } else { | |
1157 | gen_jmp_im(s, dest); | |
1158 | tcg_gen_exit_tb(0); | |
1159 | } | |
1160 | s->is_jmp = DISAS_TB_JUMP; | |
1161 | } | |
1162 | ||
1163 | DISAS_INSN(scc) | |
1164 | { | |
1165 | DisasCompare c; | |
1166 | int cond; | |
1167 | TCGv tmp; | |
1168 | ||
1169 | cond = (insn >> 8) & 0xf; | |
1170 | gen_cc_cond(&c, s, cond); | |
1171 | ||
1172 | tmp = tcg_temp_new(); | |
1173 | tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); | |
1174 | free_cond(&c); | |
1175 | ||
1176 | tcg_gen_neg_i32(tmp, tmp); | |
1177 | DEST_EA(env, insn, OS_BYTE, tmp, NULL); | |
1178 | tcg_temp_free(tmp); | |
1179 | } | |
1180 | ||
1181 | DISAS_INSN(dbcc) | |
1182 | { | |
1183 | TCGLabel *l1; | |
1184 | TCGv reg; | |
1185 | TCGv tmp; | |
1186 | int16_t offset; | |
1187 | uint32_t base; | |
1188 | ||
1189 | reg = DREG(insn, 0); | |
1190 | base = s->pc; | |
1191 | offset = (int16_t)read_im16(env, s); | |
1192 | l1 = gen_new_label(); | |
1193 | gen_jmpcc(s, (insn >> 8) & 0xf, l1); | |
1194 | ||
1195 | tmp = tcg_temp_new(); | |
1196 | tcg_gen_ext16s_i32(tmp, reg); | |
1197 | tcg_gen_addi_i32(tmp, tmp, -1); | |
1198 | gen_partset_reg(OS_WORD, reg, tmp); | |
1199 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1); | |
1200 | gen_jmp_tb(s, 1, base + offset); | |
1201 | gen_set_label(l1); | |
1202 | gen_jmp_tb(s, 0, s->pc); | |
1203 | } | |
1204 | ||
1205 | DISAS_INSN(undef_mac) | |
1206 | { | |
1207 | gen_exception(s, s->pc - 2, EXCP_LINEA); | |
1208 | } | |
1209 | ||
1210 | DISAS_INSN(undef_fpu) | |
1211 | { | |
1212 | gen_exception(s, s->pc - 2, EXCP_LINEF); | |
1213 | } | |
1214 | ||
1215 | DISAS_INSN(undef) | |
1216 | { | |
1217 | M68kCPU *cpu = m68k_env_get_cpu(env); | |
1218 | ||
1219 | gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED); | |
1220 | cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2); | |
1221 | } | |
1222 | ||
1223 | DISAS_INSN(mulw) | |
1224 | { | |
1225 | TCGv reg; | |
1226 | TCGv tmp; | |
1227 | TCGv src; | |
1228 | int sign; | |
1229 | ||
1230 | sign = (insn & 0x100) != 0; | |
1231 | reg = DREG(insn, 9); | |
1232 | tmp = tcg_temp_new(); | |
1233 | if (sign) | |
1234 | tcg_gen_ext16s_i32(tmp, reg); | |
1235 | else | |
1236 | tcg_gen_ext16u_i32(tmp, reg); | |
1237 | SRC_EA(env, src, OS_WORD, sign, NULL); | |
1238 | tcg_gen_mul_i32(tmp, tmp, src); | |
1239 | tcg_gen_mov_i32(reg, tmp); | |
1240 | gen_logic_cc(s, tmp, OS_LONG); | |
1241 | } | |
1242 | ||
1243 | DISAS_INSN(divw) | |
1244 | { | |
1245 | int sign; | |
1246 | TCGv src; | |
1247 | TCGv destr; | |
1248 | ||
1249 | /* divX.w <EA>,Dn 32/16 -> 16r:16q */ | |
1250 | ||
1251 | sign = (insn & 0x100) != 0; | |
1252 | ||
1253 | /* dest.l / src.w */ | |
1254 | ||
1255 | SRC_EA(env, src, OS_WORD, sign, NULL); | |
1256 | destr = tcg_const_i32(REG(insn, 9)); | |
1257 | if (sign) { | |
1258 | gen_helper_divsw(cpu_env, destr, src); | |
1259 | } else { | |
1260 | gen_helper_divuw(cpu_env, destr, src); | |
1261 | } | |
1262 | tcg_temp_free(destr); | |
1263 | ||
1264 | set_cc_op(s, CC_OP_FLAGS); | |
1265 | } | |
1266 | ||
1267 | DISAS_INSN(divl) | |
1268 | { | |
1269 | TCGv num, reg, den; | |
1270 | int sign; | |
1271 | uint16_t ext; | |
1272 | ||
1273 | ext = read_im16(env, s); | |
1274 | ||
1275 | sign = (ext & 0x0800) != 0; | |
1276 | ||
1277 | if (ext & 0x400) { | |
1278 | if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) { | |
1279 | gen_exception(s, s->insn_pc, EXCP_ILLEGAL); | |
1280 | return; | |
1281 | } | |
1282 | ||
1283 | /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */ | |
1284 | ||
1285 | SRC_EA(env, den, OS_LONG, 0, NULL); | |
1286 | num = tcg_const_i32(REG(ext, 12)); | |
1287 | reg = tcg_const_i32(REG(ext, 0)); | |
1288 | if (sign) { | |
1289 | gen_helper_divsll(cpu_env, num, reg, den); | |
1290 | } else { | |
1291 | gen_helper_divull(cpu_env, num, reg, den); | |
1292 | } | |
1293 | tcg_temp_free(reg); | |
1294 | tcg_temp_free(num); | |
1295 | set_cc_op(s, CC_OP_FLAGS); | |
1296 | return; | |
1297 | } | |
1298 | ||
1299 | /* divX.l <EA>, Dq 32/32 -> 32q */ | |
1300 | /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */ | |
1301 | ||
1302 | SRC_EA(env, den, OS_LONG, 0, NULL); | |
1303 | num = tcg_const_i32(REG(ext, 12)); | |
1304 | reg = tcg_const_i32(REG(ext, 0)); | |
1305 | if (sign) { | |
1306 | gen_helper_divsl(cpu_env, num, reg, den); | |
1307 | } else { | |
1308 | gen_helper_divul(cpu_env, num, reg, den); | |
1309 | } | |
1310 | tcg_temp_free(reg); | |
1311 | tcg_temp_free(num); | |
1312 | ||
1313 | set_cc_op(s, CC_OP_FLAGS); | |
1314 | } | |
1315 | ||
1316 | static void bcd_add(TCGv dest, TCGv src) | |
1317 | { | |
1318 | TCGv t0, t1; | |
1319 | ||
1320 | /* dest10 = dest10 + src10 + X | |
1321 | * | |
1322 | * t1 = src | |
1323 | * t2 = t1 + 0x066 | |
1324 | * t3 = t2 + dest + X | |
1325 | * t4 = t2 ^ dest | |
1326 | * t5 = t3 ^ t4 | |
1327 | * t6 = ~t5 & 0x110 | |
1328 | * t7 = (t6 >> 2) | (t6 >> 3) | |
1329 | * return t3 - t7 | |
1330 | */ | |
1331 | ||
1332 | /* t1 = (src + 0x066) + dest + X | |
1333 | * = result with some possible exceding 0x6 | |
1334 | */ | |
1335 | ||
1336 | t0 = tcg_const_i32(0x066); | |
1337 | tcg_gen_add_i32(t0, t0, src); | |
1338 | ||
1339 | t1 = tcg_temp_new(); | |
1340 | tcg_gen_add_i32(t1, t0, dest); | |
1341 | tcg_gen_add_i32(t1, t1, QREG_CC_X); | |
1342 | ||
1343 | /* we will remove exceding 0x6 where there is no carry */ | |
1344 | ||
1345 | /* t0 = (src + 0x0066) ^ dest | |
1346 | * = t1 without carries | |
1347 | */ | |
1348 | ||
1349 | tcg_gen_xor_i32(t0, t0, dest); | |
1350 | ||
1351 | /* extract the carries | |
1352 | * t0 = t0 ^ t1 | |
1353 | * = only the carries | |
1354 | */ | |
1355 | ||
1356 | tcg_gen_xor_i32(t0, t0, t1); | |
1357 | ||
1358 | /* generate 0x1 where there is no carry | |
1359 | * and for each 0x10, generate a 0x6 | |
1360 | */ | |
1361 | ||
1362 | tcg_gen_shri_i32(t0, t0, 3); | |
1363 | tcg_gen_not_i32(t0, t0); | |
1364 | tcg_gen_andi_i32(t0, t0, 0x22); | |
1365 | tcg_gen_add_i32(dest, t0, t0); | |
1366 | tcg_gen_add_i32(dest, dest, t0); | |
1367 | tcg_temp_free(t0); | |
1368 | ||
1369 | /* remove the exceding 0x6 | |
1370 | * for digits that have not generated a carry | |
1371 | */ | |
1372 | ||
1373 | tcg_gen_sub_i32(dest, t1, dest); | |
1374 | tcg_temp_free(t1); | |
1375 | } | |
1376 | ||
1377 | static void bcd_sub(TCGv dest, TCGv src) | |
1378 | { | |
1379 | TCGv t0, t1, t2; | |
1380 | ||
1381 | /* dest10 = dest10 - src10 - X | |
1382 | * = bcd_add(dest + 1 - X, 0x199 - src) | |
1383 | */ | |
1384 | ||
1385 | /* t0 = 0x066 + (0x199 - src) */ | |
1386 | ||
1387 | t0 = tcg_temp_new(); | |
1388 | tcg_gen_subfi_i32(t0, 0x1ff, src); | |
1389 | ||
1390 | /* t1 = t0 + dest + 1 - X*/ | |
1391 | ||
1392 | t1 = tcg_temp_new(); | |
1393 | tcg_gen_add_i32(t1, t0, dest); | |
1394 | tcg_gen_addi_i32(t1, t1, 1); | |
1395 | tcg_gen_sub_i32(t1, t1, QREG_CC_X); | |
1396 | ||
1397 | /* t2 = t0 ^ dest */ | |
1398 | ||
1399 | t2 = tcg_temp_new(); | |
1400 | tcg_gen_xor_i32(t2, t0, dest); | |
1401 | ||
1402 | /* t0 = t1 ^ t2 */ | |
1403 | ||
1404 | tcg_gen_xor_i32(t0, t1, t2); | |
1405 | ||
1406 | /* t2 = ~t0 & 0x110 | |
1407 | * t0 = (t2 >> 2) | (t2 >> 3) | |
1408 | * | |
1409 | * to fit on 8bit operands, changed in: | |
1410 | * | |
1411 | * t2 = ~(t0 >> 3) & 0x22 | |
1412 | * t0 = t2 + t2 | |
1413 | * t0 = t0 + t2 | |
1414 | */ | |
1415 | ||
1416 | tcg_gen_shri_i32(t2, t0, 3); | |
1417 | tcg_gen_not_i32(t2, t2); | |
1418 | tcg_gen_andi_i32(t2, t2, 0x22); | |
1419 | tcg_gen_add_i32(t0, t2, t2); | |
1420 | tcg_gen_add_i32(t0, t0, t2); | |
1421 | tcg_temp_free(t2); | |
1422 | ||
1423 | /* return t1 - t0 */ | |
1424 | ||
1425 | tcg_gen_sub_i32(dest, t1, t0); | |
1426 | tcg_temp_free(t0); | |
1427 | tcg_temp_free(t1); | |
1428 | } | |
1429 | ||
1430 | static void bcd_flags(TCGv val) | |
1431 | { | |
1432 | tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff); | |
1433 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C); | |
1434 | ||
1435 | tcg_gen_shri_i32(QREG_CC_C, val, 8); | |
1436 | tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1); | |
1437 | ||
1438 | tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C); | |
1439 | } | |
1440 | ||
1441 | DISAS_INSN(abcd_reg) | |
1442 | { | |
1443 | TCGv src; | |
1444 | TCGv dest; | |
1445 | ||
1446 | gen_flush_flags(s); /* !Z is sticky */ | |
1447 | ||
1448 | src = gen_extend(DREG(insn, 0), OS_BYTE, 0); | |
1449 | dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); | |
1450 | bcd_add(dest, src); | |
1451 | gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); | |
1452 | ||
1453 | bcd_flags(dest); | |
1454 | } | |
1455 | ||
1456 | DISAS_INSN(abcd_mem) | |
1457 | { | |
1458 | TCGv src, dest, addr; | |
1459 | ||
1460 | gen_flush_flags(s); /* !Z is sticky */ | |
1461 | ||
1462 | /* Indirect pre-decrement load (mode 4) */ | |
1463 | ||
1464 | src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, | |
1465 | NULL_QREG, NULL, EA_LOADU); | |
1466 | dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, | |
1467 | NULL_QREG, &addr, EA_LOADU); | |
1468 | ||
1469 | bcd_add(dest, src); | |
1470 | ||
1471 | gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); | |
1472 | ||
1473 | bcd_flags(dest); | |
1474 | } | |
1475 | ||
1476 | DISAS_INSN(sbcd_reg) | |
1477 | { | |
1478 | TCGv src, dest; | |
1479 | ||
1480 | gen_flush_flags(s); /* !Z is sticky */ | |
1481 | ||
1482 | src = gen_extend(DREG(insn, 0), OS_BYTE, 0); | |
1483 | dest = gen_extend(DREG(insn, 9), OS_BYTE, 0); | |
1484 | ||
1485 | bcd_sub(dest, src); | |
1486 | ||
1487 | gen_partset_reg(OS_BYTE, DREG(insn, 9), dest); | |
1488 | ||
1489 | bcd_flags(dest); | |
1490 | } | |
1491 | ||
1492 | DISAS_INSN(sbcd_mem) | |
1493 | { | |
1494 | TCGv src, dest, addr; | |
1495 | ||
1496 | gen_flush_flags(s); /* !Z is sticky */ | |
1497 | ||
1498 | /* Indirect pre-decrement load (mode 4) */ | |
1499 | ||
1500 | src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE, | |
1501 | NULL_QREG, NULL, EA_LOADU); | |
1502 | dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, | |
1503 | NULL_QREG, &addr, EA_LOADU); | |
1504 | ||
1505 | bcd_sub(dest, src); | |
1506 | ||
1507 | gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE); | |
1508 | ||
1509 | bcd_flags(dest); | |
1510 | } | |
1511 | ||
1512 | DISAS_INSN(nbcd) | |
1513 | { | |
1514 | TCGv src, dest; | |
1515 | TCGv addr; | |
1516 | ||
1517 | gen_flush_flags(s); /* !Z is sticky */ | |
1518 | ||
1519 | SRC_EA(env, src, OS_BYTE, 0, &addr); | |
1520 | ||
1521 | dest = tcg_const_i32(0); | |
1522 | bcd_sub(dest, src); | |
1523 | ||
1524 | DEST_EA(env, insn, OS_BYTE, dest, &addr); | |
1525 | ||
1526 | bcd_flags(dest); | |
1527 | ||
1528 | tcg_temp_free(dest); | |
1529 | } | |
1530 | ||
1531 | DISAS_INSN(addsub) | |
1532 | { | |
1533 | TCGv reg; | |
1534 | TCGv dest; | |
1535 | TCGv src; | |
1536 | TCGv tmp; | |
1537 | TCGv addr; | |
1538 | int add; | |
1539 | int opsize; | |
1540 | ||
1541 | add = (insn & 0x4000) != 0; | |
1542 | opsize = insn_opsize(insn); | |
1543 | reg = gen_extend(DREG(insn, 9), opsize, 1); | |
1544 | dest = tcg_temp_new(); | |
1545 | if (insn & 0x100) { | |
1546 | SRC_EA(env, tmp, opsize, 1, &addr); | |
1547 | src = reg; | |
1548 | } else { | |
1549 | tmp = reg; | |
1550 | SRC_EA(env, src, opsize, 1, NULL); | |
1551 | } | |
1552 | if (add) { | |
1553 | tcg_gen_add_i32(dest, tmp, src); | |
1554 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); | |
1555 | set_cc_op(s, CC_OP_ADDB + opsize); | |
1556 | } else { | |
1557 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); | |
1558 | tcg_gen_sub_i32(dest, tmp, src); | |
1559 | set_cc_op(s, CC_OP_SUBB + opsize); | |
1560 | } | |
1561 | gen_update_cc_add(dest, src, opsize); | |
1562 | if (insn & 0x100) { | |
1563 | DEST_EA(env, insn, opsize, dest, &addr); | |
1564 | } else { | |
1565 | gen_partset_reg(opsize, DREG(insn, 9), dest); | |
1566 | } | |
1567 | tcg_temp_free(dest); | |
1568 | } | |
1569 | ||
1570 | /* Reverse the order of the bits in REG. */ | |
1571 | DISAS_INSN(bitrev) | |
1572 | { | |
1573 | TCGv reg; | |
1574 | reg = DREG(insn, 0); | |
1575 | gen_helper_bitrev(reg, reg); | |
1576 | } | |
1577 | ||
1578 | DISAS_INSN(bitop_reg) | |
1579 | { | |
1580 | int opsize; | |
1581 | int op; | |
1582 | TCGv src1; | |
1583 | TCGv src2; | |
1584 | TCGv tmp; | |
1585 | TCGv addr; | |
1586 | TCGv dest; | |
1587 | ||
1588 | if ((insn & 0x38) != 0) | |
1589 | opsize = OS_BYTE; | |
1590 | else | |
1591 | opsize = OS_LONG; | |
1592 | op = (insn >> 6) & 3; | |
1593 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); | |
1594 | ||
1595 | gen_flush_flags(s); | |
1596 | src2 = tcg_temp_new(); | |
1597 | if (opsize == OS_BYTE) | |
1598 | tcg_gen_andi_i32(src2, DREG(insn, 9), 7); | |
1599 | else | |
1600 | tcg_gen_andi_i32(src2, DREG(insn, 9), 31); | |
1601 | ||
1602 | tmp = tcg_const_i32(1); | |
1603 | tcg_gen_shl_i32(tmp, tmp, src2); | |
1604 | tcg_temp_free(src2); | |
1605 | ||
1606 | tcg_gen_and_i32(QREG_CC_Z, src1, tmp); | |
1607 | ||
1608 | dest = tcg_temp_new(); | |
1609 | switch (op) { | |
1610 | case 1: /* bchg */ | |
1611 | tcg_gen_xor_i32(dest, src1, tmp); | |
1612 | break; | |
1613 | case 2: /* bclr */ | |
1614 | tcg_gen_andc_i32(dest, src1, tmp); | |
1615 | break; | |
1616 | case 3: /* bset */ | |
1617 | tcg_gen_or_i32(dest, src1, tmp); | |
1618 | break; | |
1619 | default: /* btst */ | |
1620 | break; | |
1621 | } | |
1622 | tcg_temp_free(tmp); | |
1623 | if (op) { | |
1624 | DEST_EA(env, insn, opsize, dest, &addr); | |
1625 | } | |
1626 | tcg_temp_free(dest); | |
1627 | } | |
1628 | ||
1629 | DISAS_INSN(sats) | |
1630 | { | |
1631 | TCGv reg; | |
1632 | reg = DREG(insn, 0); | |
1633 | gen_flush_flags(s); | |
1634 | gen_helper_sats(reg, reg, QREG_CC_V); | |
1635 | gen_logic_cc(s, reg, OS_LONG); | |
1636 | } | |
1637 | ||
1638 | static void gen_push(DisasContext *s, TCGv val) | |
1639 | { | |
1640 | TCGv tmp; | |
1641 | ||
1642 | tmp = tcg_temp_new(); | |
1643 | tcg_gen_subi_i32(tmp, QREG_SP, 4); | |
1644 | gen_store(s, OS_LONG, tmp, val); | |
1645 | tcg_gen_mov_i32(QREG_SP, tmp); | |
1646 | } | |
1647 | ||
1648 | DISAS_INSN(movem) | |
1649 | { | |
1650 | TCGv addr; | |
1651 | int i; | |
1652 | uint16_t mask; | |
1653 | TCGv reg; | |
1654 | TCGv tmp; | |
1655 | int is_load; | |
1656 | ||
1657 | mask = read_im16(env, s); | |
1658 | tmp = gen_lea(env, s, insn, OS_LONG); | |
1659 | if (IS_NULL_QREG(tmp)) { | |
1660 | gen_addr_fault(s); | |
1661 | return; | |
1662 | } | |
1663 | addr = tcg_temp_new(); | |
1664 | tcg_gen_mov_i32(addr, tmp); | |
1665 | is_load = ((insn & 0x0400) != 0); | |
1666 | for (i = 0; i < 16; i++, mask >>= 1) { | |
1667 | if (mask & 1) { | |
1668 | if (i < 8) | |
1669 | reg = DREG(i, 0); | |
1670 | else | |
1671 | reg = AREG(i, 0); | |
1672 | if (is_load) { | |
1673 | tmp = gen_load(s, OS_LONG, addr, 0); | |
1674 | tcg_gen_mov_i32(reg, tmp); | |
1675 | } else { | |
1676 | gen_store(s, OS_LONG, addr, reg); | |
1677 | } | |
1678 | if (mask != 1) | |
1679 | tcg_gen_addi_i32(addr, addr, 4); | |
1680 | } | |
1681 | } | |
1682 | } | |
1683 | ||
1684 | DISAS_INSN(bitop_im) | |
1685 | { | |
1686 | int opsize; | |
1687 | int op; | |
1688 | TCGv src1; | |
1689 | uint32_t mask; | |
1690 | int bitnum; | |
1691 | TCGv tmp; | |
1692 | TCGv addr; | |
1693 | ||
1694 | if ((insn & 0x38) != 0) | |
1695 | opsize = OS_BYTE; | |
1696 | else | |
1697 | opsize = OS_LONG; | |
1698 | op = (insn >> 6) & 3; | |
1699 | ||
1700 | bitnum = read_im16(env, s); | |
1701 | if (bitnum & 0xff00) { | |
1702 | disas_undef(env, s, insn); | |
1703 | return; | |
1704 | } | |
1705 | ||
1706 | SRC_EA(env, src1, opsize, 0, op ? &addr: NULL); | |
1707 | ||
1708 | gen_flush_flags(s); | |
1709 | if (opsize == OS_BYTE) | |
1710 | bitnum &= 7; | |
1711 | else | |
1712 | bitnum &= 31; | |
1713 | mask = 1 << bitnum; | |
1714 | ||
1715 | tcg_gen_andi_i32(QREG_CC_Z, src1, mask); | |
1716 | ||
1717 | if (op) { | |
1718 | tmp = tcg_temp_new(); | |
1719 | switch (op) { | |
1720 | case 1: /* bchg */ | |
1721 | tcg_gen_xori_i32(tmp, src1, mask); | |
1722 | break; | |
1723 | case 2: /* bclr */ | |
1724 | tcg_gen_andi_i32(tmp, src1, ~mask); | |
1725 | break; | |
1726 | case 3: /* bset */ | |
1727 | tcg_gen_ori_i32(tmp, src1, mask); | |
1728 | break; | |
1729 | default: /* btst */ | |
1730 | break; | |
1731 | } | |
1732 | DEST_EA(env, insn, opsize, tmp, &addr); | |
1733 | tcg_temp_free(tmp); | |
1734 | } | |
1735 | } | |
1736 | ||
1737 | DISAS_INSN(arith_im) | |
1738 | { | |
1739 | int op; | |
1740 | TCGv im; | |
1741 | TCGv src1; | |
1742 | TCGv dest; | |
1743 | TCGv addr; | |
1744 | int opsize; | |
1745 | ||
1746 | op = (insn >> 9) & 7; | |
1747 | opsize = insn_opsize(insn); | |
1748 | switch (opsize) { | |
1749 | case OS_BYTE: | |
1750 | im = tcg_const_i32((int8_t)read_im8(env, s)); | |
1751 | break; | |
1752 | case OS_WORD: | |
1753 | im = tcg_const_i32((int16_t)read_im16(env, s)); | |
1754 | break; | |
1755 | case OS_LONG: | |
1756 | im = tcg_const_i32(read_im32(env, s)); | |
1757 | break; | |
1758 | default: | |
1759 | abort(); | |
1760 | } | |
1761 | SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr); | |
1762 | dest = tcg_temp_new(); | |
1763 | switch (op) { | |
1764 | case 0: /* ori */ | |
1765 | tcg_gen_or_i32(dest, src1, im); | |
1766 | gen_logic_cc(s, dest, opsize); | |
1767 | break; | |
1768 | case 1: /* andi */ | |
1769 | tcg_gen_and_i32(dest, src1, im); | |
1770 | gen_logic_cc(s, dest, opsize); | |
1771 | break; | |
1772 | case 2: /* subi */ | |
1773 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im); | |
1774 | tcg_gen_sub_i32(dest, src1, im); | |
1775 | gen_update_cc_add(dest, im, opsize); | |
1776 | set_cc_op(s, CC_OP_SUBB + opsize); | |
1777 | break; | |
1778 | case 3: /* addi */ | |
1779 | tcg_gen_add_i32(dest, src1, im); | |
1780 | gen_update_cc_add(dest, im, opsize); | |
1781 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im); | |
1782 | set_cc_op(s, CC_OP_ADDB + opsize); | |
1783 | break; | |
1784 | case 5: /* eori */ | |
1785 | tcg_gen_xor_i32(dest, src1, im); | |
1786 | gen_logic_cc(s, dest, opsize); | |
1787 | break; | |
1788 | case 6: /* cmpi */ | |
1789 | gen_update_cc_cmp(s, src1, im, opsize); | |
1790 | break; | |
1791 | default: | |
1792 | abort(); | |
1793 | } | |
1794 | tcg_temp_free(im); | |
1795 | if (op != 6) { | |
1796 | DEST_EA(env, insn, opsize, dest, &addr); | |
1797 | } | |
1798 | tcg_temp_free(dest); | |
1799 | } | |
1800 | ||
1801 | DISAS_INSN(byterev) | |
1802 | { | |
1803 | TCGv reg; | |
1804 | ||
1805 | reg = DREG(insn, 0); | |
1806 | tcg_gen_bswap32_i32(reg, reg); | |
1807 | } | |
1808 | ||
1809 | DISAS_INSN(move) | |
1810 | { | |
1811 | TCGv src; | |
1812 | TCGv dest; | |
1813 | int op; | |
1814 | int opsize; | |
1815 | ||
1816 | switch (insn >> 12) { | |
1817 | case 1: /* move.b */ | |
1818 | opsize = OS_BYTE; | |
1819 | break; | |
1820 | case 2: /* move.l */ | |
1821 | opsize = OS_LONG; | |
1822 | break; | |
1823 | case 3: /* move.w */ | |
1824 | opsize = OS_WORD; | |
1825 | break; | |
1826 | default: | |
1827 | abort(); | |
1828 | } | |
1829 | SRC_EA(env, src, opsize, 1, NULL); | |
1830 | op = (insn >> 6) & 7; | |
1831 | if (op == 1) { | |
1832 | /* movea */ | |
1833 | /* The value will already have been sign extended. */ | |
1834 | dest = AREG(insn, 9); | |
1835 | tcg_gen_mov_i32(dest, src); | |
1836 | } else { | |
1837 | /* normal move */ | |
1838 | uint16_t dest_ea; | |
1839 | dest_ea = ((insn >> 9) & 7) | (op << 3); | |
1840 | DEST_EA(env, dest_ea, opsize, src, NULL); | |
1841 | /* This will be correct because loads sign extend. */ | |
1842 | gen_logic_cc(s, src, opsize); | |
1843 | } | |
1844 | } | |
1845 | ||
1846 | DISAS_INSN(negx) | |
1847 | { | |
1848 | TCGv z; | |
1849 | TCGv src; | |
1850 | TCGv addr; | |
1851 | int opsize; | |
1852 | ||
1853 | opsize = insn_opsize(insn); | |
1854 | SRC_EA(env, src, opsize, 1, &addr); | |
1855 | ||
1856 | gen_flush_flags(s); /* compute old Z */ | |
1857 | ||
1858 | /* Perform substract with borrow. | |
1859 | * (X, N) = -(src + X); | |
1860 | */ | |
1861 | ||
1862 | z = tcg_const_i32(0); | |
1863 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z); | |
1864 | tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X); | |
1865 | tcg_temp_free(z); | |
1866 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
1867 | ||
1868 | tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); | |
1869 | ||
1870 | /* Compute signed-overflow for negation. The normal formula for | |
1871 | * subtraction is (res ^ src) & (src ^ dest), but with dest==0 | |
1872 | * this simplies to res & src. | |
1873 | */ | |
1874 | ||
1875 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src); | |
1876 | ||
1877 | /* Copy the rest of the results into place. */ | |
1878 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ | |
1879 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
1880 | ||
1881 | set_cc_op(s, CC_OP_FLAGS); | |
1882 | ||
1883 | /* result is in QREG_CC_N */ | |
1884 | ||
1885 | DEST_EA(env, insn, opsize, QREG_CC_N, &addr); | |
1886 | } | |
1887 | ||
1888 | DISAS_INSN(lea) | |
1889 | { | |
1890 | TCGv reg; | |
1891 | TCGv tmp; | |
1892 | ||
1893 | reg = AREG(insn, 9); | |
1894 | tmp = gen_lea(env, s, insn, OS_LONG); | |
1895 | if (IS_NULL_QREG(tmp)) { | |
1896 | gen_addr_fault(s); | |
1897 | return; | |
1898 | } | |
1899 | tcg_gen_mov_i32(reg, tmp); | |
1900 | } | |
1901 | ||
1902 | DISAS_INSN(clr) | |
1903 | { | |
1904 | int opsize; | |
1905 | ||
1906 | opsize = insn_opsize(insn); | |
1907 | DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL); | |
1908 | gen_logic_cc(s, tcg_const_i32(0), opsize); | |
1909 | } | |
1910 | ||
1911 | static TCGv gen_get_ccr(DisasContext *s) | |
1912 | { | |
1913 | TCGv dest; | |
1914 | ||
1915 | gen_flush_flags(s); | |
1916 | update_cc_op(s); | |
1917 | dest = tcg_temp_new(); | |
1918 | gen_helper_get_ccr(dest, cpu_env); | |
1919 | return dest; | |
1920 | } | |
1921 | ||
1922 | DISAS_INSN(move_from_ccr) | |
1923 | { | |
1924 | TCGv ccr; | |
1925 | ||
1926 | ccr = gen_get_ccr(s); | |
1927 | DEST_EA(env, insn, OS_WORD, ccr, NULL); | |
1928 | } | |
1929 | ||
1930 | DISAS_INSN(neg) | |
1931 | { | |
1932 | TCGv src1; | |
1933 | TCGv dest; | |
1934 | TCGv addr; | |
1935 | int opsize; | |
1936 | ||
1937 | opsize = insn_opsize(insn); | |
1938 | SRC_EA(env, src1, opsize, 1, &addr); | |
1939 | dest = tcg_temp_new(); | |
1940 | tcg_gen_neg_i32(dest, src1); | |
1941 | set_cc_op(s, CC_OP_SUBB + opsize); | |
1942 | gen_update_cc_add(dest, src1, opsize); | |
1943 | tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0); | |
1944 | DEST_EA(env, insn, opsize, dest, &addr); | |
1945 | tcg_temp_free(dest); | |
1946 | } | |
1947 | ||
1948 | static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only) | |
1949 | { | |
1950 | if (ccr_only) { | |
1951 | tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0); | |
1952 | tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0); | |
1953 | tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1); | |
1954 | tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0); | |
1955 | tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0); | |
1956 | } else { | |
1957 | gen_helper_set_sr(cpu_env, tcg_const_i32(val)); | |
1958 | } | |
1959 | set_cc_op(s, CC_OP_FLAGS); | |
1960 | } | |
1961 | ||
1962 | static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn, | |
1963 | int ccr_only) | |
1964 | { | |
1965 | if ((insn & 0x38) == 0) { | |
1966 | if (ccr_only) { | |
1967 | gen_helper_set_ccr(cpu_env, DREG(insn, 0)); | |
1968 | } else { | |
1969 | gen_helper_set_sr(cpu_env, DREG(insn, 0)); | |
1970 | } | |
1971 | set_cc_op(s, CC_OP_FLAGS); | |
1972 | } else if ((insn & 0x3f) == 0x3c) { | |
1973 | uint16_t val; | |
1974 | val = read_im16(env, s); | |
1975 | gen_set_sr_im(s, val, ccr_only); | |
1976 | } else { | |
1977 | disas_undef(env, s, insn); | |
1978 | } | |
1979 | } | |
1980 | ||
1981 | ||
1982 | DISAS_INSN(move_to_ccr) | |
1983 | { | |
1984 | gen_set_sr(env, s, insn, 1); | |
1985 | } | |
1986 | ||
1987 | DISAS_INSN(not) | |
1988 | { | |
1989 | TCGv src1; | |
1990 | TCGv dest; | |
1991 | TCGv addr; | |
1992 | int opsize; | |
1993 | ||
1994 | opsize = insn_opsize(insn); | |
1995 | SRC_EA(env, src1, opsize, 1, &addr); | |
1996 | dest = tcg_temp_new(); | |
1997 | tcg_gen_not_i32(dest, src1); | |
1998 | DEST_EA(env, insn, opsize, dest, &addr); | |
1999 | gen_logic_cc(s, dest, opsize); | |
2000 | } | |
2001 | ||
2002 | DISAS_INSN(swap) | |
2003 | { | |
2004 | TCGv src1; | |
2005 | TCGv src2; | |
2006 | TCGv reg; | |
2007 | ||
2008 | src1 = tcg_temp_new(); | |
2009 | src2 = tcg_temp_new(); | |
2010 | reg = DREG(insn, 0); | |
2011 | tcg_gen_shli_i32(src1, reg, 16); | |
2012 | tcg_gen_shri_i32(src2, reg, 16); | |
2013 | tcg_gen_or_i32(reg, src1, src2); | |
2014 | gen_logic_cc(s, reg, OS_LONG); | |
2015 | } | |
2016 | ||
2017 | DISAS_INSN(bkpt) | |
2018 | { | |
2019 | gen_exception(s, s->pc - 2, EXCP_DEBUG); | |
2020 | } | |
2021 | ||
2022 | DISAS_INSN(pea) | |
2023 | { | |
2024 | TCGv tmp; | |
2025 | ||
2026 | tmp = gen_lea(env, s, insn, OS_LONG); | |
2027 | if (IS_NULL_QREG(tmp)) { | |
2028 | gen_addr_fault(s); | |
2029 | return; | |
2030 | } | |
2031 | gen_push(s, tmp); | |
2032 | } | |
2033 | ||
2034 | DISAS_INSN(ext) | |
2035 | { | |
2036 | int op; | |
2037 | TCGv reg; | |
2038 | TCGv tmp; | |
2039 | ||
2040 | reg = DREG(insn, 0); | |
2041 | op = (insn >> 6) & 7; | |
2042 | tmp = tcg_temp_new(); | |
2043 | if (op == 3) | |
2044 | tcg_gen_ext16s_i32(tmp, reg); | |
2045 | else | |
2046 | tcg_gen_ext8s_i32(tmp, reg); | |
2047 | if (op == 2) | |
2048 | gen_partset_reg(OS_WORD, reg, tmp); | |
2049 | else | |
2050 | tcg_gen_mov_i32(reg, tmp); | |
2051 | gen_logic_cc(s, tmp, OS_LONG); | |
2052 | } | |
2053 | ||
2054 | DISAS_INSN(tst) | |
2055 | { | |
2056 | int opsize; | |
2057 | TCGv tmp; | |
2058 | ||
2059 | opsize = insn_opsize(insn); | |
2060 | SRC_EA(env, tmp, opsize, 1, NULL); | |
2061 | gen_logic_cc(s, tmp, opsize); | |
2062 | } | |
2063 | ||
2064 | DISAS_INSN(pulse) | |
2065 | { | |
2066 | /* Implemented as a NOP. */ | |
2067 | } | |
2068 | ||
2069 | DISAS_INSN(illegal) | |
2070 | { | |
2071 | gen_exception(s, s->pc - 2, EXCP_ILLEGAL); | |
2072 | } | |
2073 | ||
2074 | /* ??? This should be atomic. */ | |
2075 | DISAS_INSN(tas) | |
2076 | { | |
2077 | TCGv dest; | |
2078 | TCGv src1; | |
2079 | TCGv addr; | |
2080 | ||
2081 | dest = tcg_temp_new(); | |
2082 | SRC_EA(env, src1, OS_BYTE, 1, &addr); | |
2083 | gen_logic_cc(s, src1, OS_BYTE); | |
2084 | tcg_gen_ori_i32(dest, src1, 0x80); | |
2085 | DEST_EA(env, insn, OS_BYTE, dest, &addr); | |
2086 | } | |
2087 | ||
2088 | DISAS_INSN(mull) | |
2089 | { | |
2090 | uint16_t ext; | |
2091 | TCGv src1; | |
2092 | int sign; | |
2093 | ||
2094 | ext = read_im16(env, s); | |
2095 | ||
2096 | sign = ext & 0x800; | |
2097 | ||
2098 | if (ext & 0x400) { | |
2099 | if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) { | |
2100 | gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED); | |
2101 | return; | |
2102 | } | |
2103 | ||
2104 | SRC_EA(env, src1, OS_LONG, 0, NULL); | |
2105 | ||
2106 | if (sign) { | |
2107 | tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12)); | |
2108 | } else { | |
2109 | tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12)); | |
2110 | } | |
2111 | /* if Dl == Dh, 68040 returns low word */ | |
2112 | tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N); | |
2113 | tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z); | |
2114 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); | |
2115 | ||
2116 | tcg_gen_movi_i32(QREG_CC_V, 0); | |
2117 | tcg_gen_movi_i32(QREG_CC_C, 0); | |
2118 | ||
2119 | set_cc_op(s, CC_OP_FLAGS); | |
2120 | return; | |
2121 | } | |
2122 | SRC_EA(env, src1, OS_LONG, 0, NULL); | |
2123 | if (m68k_feature(s->env, M68K_FEATURE_M68000)) { | |
2124 | tcg_gen_movi_i32(QREG_CC_C, 0); | |
2125 | if (sign) { | |
2126 | tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); | |
2127 | /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */ | |
2128 | tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31); | |
2129 | tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z); | |
2130 | } else { | |
2131 | tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); | |
2132 | /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */ | |
2133 | tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C); | |
2134 | } | |
2135 | tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); | |
2136 | tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N); | |
2137 | ||
2138 | tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); | |
2139 | ||
2140 | set_cc_op(s, CC_OP_FLAGS); | |
2141 | } else { | |
2142 | /* The upper 32 bits of the product are discarded, so | |
2143 | muls.l and mulu.l are functionally equivalent. */ | |
2144 | tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12)); | |
2145 | gen_logic_cc(s, DREG(ext, 12), OS_LONG); | |
2146 | } | |
2147 | } | |
2148 | ||
2149 | static void gen_link(DisasContext *s, uint16_t insn, int32_t offset) | |
2150 | { | |
2151 | TCGv reg; | |
2152 | TCGv tmp; | |
2153 | ||
2154 | reg = AREG(insn, 0); | |
2155 | tmp = tcg_temp_new(); | |
2156 | tcg_gen_subi_i32(tmp, QREG_SP, 4); | |
2157 | gen_store(s, OS_LONG, tmp, reg); | |
2158 | if ((insn & 7) != 7) { | |
2159 | tcg_gen_mov_i32(reg, tmp); | |
2160 | } | |
2161 | tcg_gen_addi_i32(QREG_SP, tmp, offset); | |
2162 | tcg_temp_free(tmp); | |
2163 | } | |
2164 | ||
2165 | DISAS_INSN(link) | |
2166 | { | |
2167 | int16_t offset; | |
2168 | ||
2169 | offset = read_im16(env, s); | |
2170 | gen_link(s, insn, offset); | |
2171 | } | |
2172 | ||
2173 | DISAS_INSN(linkl) | |
2174 | { | |
2175 | int32_t offset; | |
2176 | ||
2177 | offset = read_im32(env, s); | |
2178 | gen_link(s, insn, offset); | |
2179 | } | |
2180 | ||
2181 | DISAS_INSN(unlk) | |
2182 | { | |
2183 | TCGv src; | |
2184 | TCGv reg; | |
2185 | TCGv tmp; | |
2186 | ||
2187 | src = tcg_temp_new(); | |
2188 | reg = AREG(insn, 0); | |
2189 | tcg_gen_mov_i32(src, reg); | |
2190 | tmp = gen_load(s, OS_LONG, src, 0); | |
2191 | tcg_gen_mov_i32(reg, tmp); | |
2192 | tcg_gen_addi_i32(QREG_SP, src, 4); | |
2193 | } | |
2194 | ||
2195 | DISAS_INSN(nop) | |
2196 | { | |
2197 | } | |
2198 | ||
2199 | DISAS_INSN(rts) | |
2200 | { | |
2201 | TCGv tmp; | |
2202 | ||
2203 | tmp = gen_load(s, OS_LONG, QREG_SP, 0); | |
2204 | tcg_gen_addi_i32(QREG_SP, QREG_SP, 4); | |
2205 | gen_jmp(s, tmp); | |
2206 | } | |
2207 | ||
2208 | DISAS_INSN(jump) | |
2209 | { | |
2210 | TCGv tmp; | |
2211 | ||
2212 | /* Load the target address first to ensure correct exception | |
2213 | behavior. */ | |
2214 | tmp = gen_lea(env, s, insn, OS_LONG); | |
2215 | if (IS_NULL_QREG(tmp)) { | |
2216 | gen_addr_fault(s); | |
2217 | return; | |
2218 | } | |
2219 | if ((insn & 0x40) == 0) { | |
2220 | /* jsr */ | |
2221 | gen_push(s, tcg_const_i32(s->pc)); | |
2222 | } | |
2223 | gen_jmp(s, tmp); | |
2224 | } | |
2225 | ||
2226 | DISAS_INSN(addsubq) | |
2227 | { | |
2228 | TCGv src; | |
2229 | TCGv dest; | |
2230 | TCGv val; | |
2231 | int imm; | |
2232 | TCGv addr; | |
2233 | int opsize; | |
2234 | ||
2235 | if ((insn & 070) == 010) { | |
2236 | /* Operation on address register is always long. */ | |
2237 | opsize = OS_LONG; | |
2238 | } else { | |
2239 | opsize = insn_opsize(insn); | |
2240 | } | |
2241 | SRC_EA(env, src, opsize, 1, &addr); | |
2242 | imm = (insn >> 9) & 7; | |
2243 | if (imm == 0) { | |
2244 | imm = 8; | |
2245 | } | |
2246 | val = tcg_const_i32(imm); | |
2247 | dest = tcg_temp_new(); | |
2248 | tcg_gen_mov_i32(dest, src); | |
2249 | if ((insn & 0x38) == 0x08) { | |
2250 | /* Don't update condition codes if the destination is an | |
2251 | address register. */ | |
2252 | if (insn & 0x0100) { | |
2253 | tcg_gen_sub_i32(dest, dest, val); | |
2254 | } else { | |
2255 | tcg_gen_add_i32(dest, dest, val); | |
2256 | } | |
2257 | } else { | |
2258 | if (insn & 0x0100) { | |
2259 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); | |
2260 | tcg_gen_sub_i32(dest, dest, val); | |
2261 | set_cc_op(s, CC_OP_SUBB + opsize); | |
2262 | } else { | |
2263 | tcg_gen_add_i32(dest, dest, val); | |
2264 | tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); | |
2265 | set_cc_op(s, CC_OP_ADDB + opsize); | |
2266 | } | |
2267 | gen_update_cc_add(dest, val, opsize); | |
2268 | } | |
2269 | DEST_EA(env, insn, opsize, dest, &addr); | |
2270 | } | |
2271 | ||
2272 | DISAS_INSN(tpf) | |
2273 | { | |
2274 | switch (insn & 7) { | |
2275 | case 2: /* One extension word. */ | |
2276 | s->pc += 2; | |
2277 | break; | |
2278 | case 3: /* Two extension words. */ | |
2279 | s->pc += 4; | |
2280 | break; | |
2281 | case 4: /* No extension words. */ | |
2282 | break; | |
2283 | default: | |
2284 | disas_undef(env, s, insn); | |
2285 | } | |
2286 | } | |
2287 | ||
2288 | DISAS_INSN(branch) | |
2289 | { | |
2290 | int32_t offset; | |
2291 | uint32_t base; | |
2292 | int op; | |
2293 | TCGLabel *l1; | |
2294 | ||
2295 | base = s->pc; | |
2296 | op = (insn >> 8) & 0xf; | |
2297 | offset = (int8_t)insn; | |
2298 | if (offset == 0) { | |
2299 | offset = (int16_t)read_im16(env, s); | |
2300 | } else if (offset == -1) { | |
2301 | offset = read_im32(env, s); | |
2302 | } | |
2303 | if (op == 1) { | |
2304 | /* bsr */ | |
2305 | gen_push(s, tcg_const_i32(s->pc)); | |
2306 | } | |
2307 | if (op > 1) { | |
2308 | /* Bcc */ | |
2309 | l1 = gen_new_label(); | |
2310 | gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); | |
2311 | gen_jmp_tb(s, 1, base + offset); | |
2312 | gen_set_label(l1); | |
2313 | gen_jmp_tb(s, 0, s->pc); | |
2314 | } else { | |
2315 | /* Unconditional branch. */ | |
2316 | gen_jmp_tb(s, 0, base + offset); | |
2317 | } | |
2318 | } | |
2319 | ||
2320 | DISAS_INSN(moveq) | |
2321 | { | |
2322 | uint32_t val; | |
2323 | ||
2324 | val = (int8_t)insn; | |
2325 | tcg_gen_movi_i32(DREG(insn, 9), val); | |
2326 | gen_logic_cc(s, tcg_const_i32(val), OS_LONG); | |
2327 | } | |
2328 | ||
2329 | DISAS_INSN(mvzs) | |
2330 | { | |
2331 | int opsize; | |
2332 | TCGv src; | |
2333 | TCGv reg; | |
2334 | ||
2335 | if (insn & 0x40) | |
2336 | opsize = OS_WORD; | |
2337 | else | |
2338 | opsize = OS_BYTE; | |
2339 | SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL); | |
2340 | reg = DREG(insn, 9); | |
2341 | tcg_gen_mov_i32(reg, src); | |
2342 | gen_logic_cc(s, src, opsize); | |
2343 | } | |
2344 | ||
2345 | DISAS_INSN(or) | |
2346 | { | |
2347 | TCGv reg; | |
2348 | TCGv dest; | |
2349 | TCGv src; | |
2350 | TCGv addr; | |
2351 | int opsize; | |
2352 | ||
2353 | opsize = insn_opsize(insn); | |
2354 | reg = gen_extend(DREG(insn, 9), opsize, 0); | |
2355 | dest = tcg_temp_new(); | |
2356 | if (insn & 0x100) { | |
2357 | SRC_EA(env, src, opsize, 0, &addr); | |
2358 | tcg_gen_or_i32(dest, src, reg); | |
2359 | DEST_EA(env, insn, opsize, dest, &addr); | |
2360 | } else { | |
2361 | SRC_EA(env, src, opsize, 0, NULL); | |
2362 | tcg_gen_or_i32(dest, src, reg); | |
2363 | gen_partset_reg(opsize, DREG(insn, 9), dest); | |
2364 | } | |
2365 | gen_logic_cc(s, dest, opsize); | |
2366 | } | |
2367 | ||
2368 | DISAS_INSN(suba) | |
2369 | { | |
2370 | TCGv src; | |
2371 | TCGv reg; | |
2372 | ||
2373 | SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL); | |
2374 | reg = AREG(insn, 9); | |
2375 | tcg_gen_sub_i32(reg, reg, src); | |
2376 | } | |
2377 | ||
2378 | static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize) | |
2379 | { | |
2380 | TCGv tmp; | |
2381 | ||
2382 | gen_flush_flags(s); /* compute old Z */ | |
2383 | ||
2384 | /* Perform substract with borrow. | |
2385 | * (X, N) = dest - (src + X); | |
2386 | */ | |
2387 | ||
2388 | tmp = tcg_const_i32(0); | |
2389 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp); | |
2390 | tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X); | |
2391 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
2392 | tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); | |
2393 | ||
2394 | /* Compute signed-overflow for substract. */ | |
2395 | ||
2396 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest); | |
2397 | tcg_gen_xor_i32(tmp, dest, src); | |
2398 | tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp); | |
2399 | tcg_temp_free(tmp); | |
2400 | ||
2401 | /* Copy the rest of the results into place. */ | |
2402 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ | |
2403 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
2404 | ||
2405 | set_cc_op(s, CC_OP_FLAGS); | |
2406 | ||
2407 | /* result is in QREG_CC_N */ | |
2408 | } | |
2409 | ||
2410 | DISAS_INSN(subx_reg) | |
2411 | { | |
2412 | TCGv dest; | |
2413 | TCGv src; | |
2414 | int opsize; | |
2415 | ||
2416 | opsize = insn_opsize(insn); | |
2417 | ||
2418 | src = gen_extend(DREG(insn, 0), opsize, 1); | |
2419 | dest = gen_extend(DREG(insn, 9), opsize, 1); | |
2420 | ||
2421 | gen_subx(s, src, dest, opsize); | |
2422 | ||
2423 | gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N); | |
2424 | } | |
2425 | ||
2426 | DISAS_INSN(subx_mem) | |
2427 | { | |
2428 | TCGv src; | |
2429 | TCGv addr_src; | |
2430 | TCGv dest; | |
2431 | TCGv addr_dest; | |
2432 | int opsize; | |
2433 | ||
2434 | opsize = insn_opsize(insn); | |
2435 | ||
2436 | addr_src = AREG(insn, 0); | |
2437 | tcg_gen_subi_i32(addr_src, addr_src, opsize); | |
2438 | src = gen_load(s, opsize, addr_src, 1); | |
2439 | ||
2440 | addr_dest = AREG(insn, 9); | |
2441 | tcg_gen_subi_i32(addr_dest, addr_dest, opsize); | |
2442 | dest = gen_load(s, opsize, addr_dest, 1); | |
2443 | ||
2444 | gen_subx(s, src, dest, opsize); | |
2445 | ||
2446 | gen_store(s, opsize, addr_dest, QREG_CC_N); | |
2447 | } | |
2448 | ||
2449 | DISAS_INSN(mov3q) | |
2450 | { | |
2451 | TCGv src; | |
2452 | int val; | |
2453 | ||
2454 | val = (insn >> 9) & 7; | |
2455 | if (val == 0) | |
2456 | val = -1; | |
2457 | src = tcg_const_i32(val); | |
2458 | gen_logic_cc(s, src, OS_LONG); | |
2459 | DEST_EA(env, insn, OS_LONG, src, NULL); | |
2460 | } | |
2461 | ||
2462 | DISAS_INSN(cmp) | |
2463 | { | |
2464 | TCGv src; | |
2465 | TCGv reg; | |
2466 | int opsize; | |
2467 | ||
2468 | opsize = insn_opsize(insn); | |
2469 | SRC_EA(env, src, opsize, 1, NULL); | |
2470 | reg = gen_extend(DREG(insn, 9), opsize, 1); | |
2471 | gen_update_cc_cmp(s, reg, src, opsize); | |
2472 | } | |
2473 | ||
2474 | DISAS_INSN(cmpa) | |
2475 | { | |
2476 | int opsize; | |
2477 | TCGv src; | |
2478 | TCGv reg; | |
2479 | ||
2480 | if (insn & 0x100) { | |
2481 | opsize = OS_LONG; | |
2482 | } else { | |
2483 | opsize = OS_WORD; | |
2484 | } | |
2485 | SRC_EA(env, src, opsize, 1, NULL); | |
2486 | reg = AREG(insn, 9); | |
2487 | gen_update_cc_cmp(s, reg, src, OS_LONG); | |
2488 | } | |
2489 | ||
2490 | DISAS_INSN(cmpm) | |
2491 | { | |
2492 | int opsize = insn_opsize(insn); | |
2493 | TCGv src, dst; | |
2494 | ||
2495 | /* Post-increment load (mode 3) from Ay. */ | |
2496 | src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize, | |
2497 | NULL_QREG, NULL, EA_LOADS); | |
2498 | /* Post-increment load (mode 3) from Ax. */ | |
2499 | dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize, | |
2500 | NULL_QREG, NULL, EA_LOADS); | |
2501 | ||
2502 | gen_update_cc_cmp(s, dst, src, opsize); | |
2503 | } | |
2504 | ||
2505 | DISAS_INSN(eor) | |
2506 | { | |
2507 | TCGv src; | |
2508 | TCGv dest; | |
2509 | TCGv addr; | |
2510 | int opsize; | |
2511 | ||
2512 | opsize = insn_opsize(insn); | |
2513 | ||
2514 | SRC_EA(env, src, opsize, 0, &addr); | |
2515 | dest = tcg_temp_new(); | |
2516 | tcg_gen_xor_i32(dest, src, DREG(insn, 9)); | |
2517 | gen_logic_cc(s, dest, opsize); | |
2518 | DEST_EA(env, insn, opsize, dest, &addr); | |
2519 | } | |
2520 | ||
2521 | static void do_exg(TCGv reg1, TCGv reg2) | |
2522 | { | |
2523 | TCGv temp = tcg_temp_new(); | |
2524 | tcg_gen_mov_i32(temp, reg1); | |
2525 | tcg_gen_mov_i32(reg1, reg2); | |
2526 | tcg_gen_mov_i32(reg2, temp); | |
2527 | tcg_temp_free(temp); | |
2528 | } | |
2529 | ||
2530 | DISAS_INSN(exg_dd) | |
2531 | { | |
2532 | /* exchange Dx and Dy */ | |
2533 | do_exg(DREG(insn, 9), DREG(insn, 0)); | |
2534 | } | |
2535 | ||
2536 | DISAS_INSN(exg_aa) | |
2537 | { | |
2538 | /* exchange Ax and Ay */ | |
2539 | do_exg(AREG(insn, 9), AREG(insn, 0)); | |
2540 | } | |
2541 | ||
2542 | DISAS_INSN(exg_da) | |
2543 | { | |
2544 | /* exchange Dx and Ay */ | |
2545 | do_exg(DREG(insn, 9), AREG(insn, 0)); | |
2546 | } | |
2547 | ||
2548 | DISAS_INSN(and) | |
2549 | { | |
2550 | TCGv src; | |
2551 | TCGv reg; | |
2552 | TCGv dest; | |
2553 | TCGv addr; | |
2554 | int opsize; | |
2555 | ||
2556 | dest = tcg_temp_new(); | |
2557 | ||
2558 | opsize = insn_opsize(insn); | |
2559 | reg = DREG(insn, 9); | |
2560 | if (insn & 0x100) { | |
2561 | SRC_EA(env, src, opsize, 0, &addr); | |
2562 | tcg_gen_and_i32(dest, src, reg); | |
2563 | DEST_EA(env, insn, opsize, dest, &addr); | |
2564 | } else { | |
2565 | SRC_EA(env, src, opsize, 0, NULL); | |
2566 | tcg_gen_and_i32(dest, src, reg); | |
2567 | gen_partset_reg(opsize, reg, dest); | |
2568 | } | |
2569 | tcg_temp_free(dest); | |
2570 | gen_logic_cc(s, dest, opsize); | |
2571 | } | |
2572 | ||
2573 | DISAS_INSN(adda) | |
2574 | { | |
2575 | TCGv src; | |
2576 | TCGv reg; | |
2577 | ||
2578 | SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL); | |
2579 | reg = AREG(insn, 9); | |
2580 | tcg_gen_add_i32(reg, reg, src); | |
2581 | } | |
2582 | ||
2583 | static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize) | |
2584 | { | |
2585 | TCGv tmp; | |
2586 | ||
2587 | gen_flush_flags(s); /* compute old Z */ | |
2588 | ||
2589 | /* Perform addition with carry. | |
2590 | * (X, N) = src + dest + X; | |
2591 | */ | |
2592 | ||
2593 | tmp = tcg_const_i32(0); | |
2594 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp); | |
2595 | tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp); | |
2596 | gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); | |
2597 | ||
2598 | /* Compute signed-overflow for addition. */ | |
2599 | ||
2600 | tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src); | |
2601 | tcg_gen_xor_i32(tmp, dest, src); | |
2602 | tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp); | |
2603 | tcg_temp_free(tmp); | |
2604 | ||
2605 | /* Copy the rest of the results into place. */ | |
2606 | tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */ | |
2607 | tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X); | |
2608 | ||
2609 | set_cc_op(s, CC_OP_FLAGS); | |
2610 | ||
2611 | /* result is in QREG_CC_N */ | |
2612 | } | |
2613 | ||
2614 | DISAS_INSN(addx_reg) | |
2615 | { | |
2616 | TCGv dest; | |
2617 | TCGv src; | |
2618 | int opsize; | |
2619 | ||
2620 | opsize = insn_opsize(insn); | |
2621 | ||
2622 | dest = gen_extend(DREG(insn, 9), opsize, 1); | |
2623 | src = gen_extend(DREG(insn, 0), opsize, 1); | |
2624 | ||
2625 | gen_addx(s, src, dest, opsize); | |
2626 | ||
2627 | gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N); | |
2628 | } | |
2629 | ||
2630 | DISAS_INSN(addx_mem) | |
2631 | { | |
2632 | TCGv src; | |
2633 | TCGv addr_src; | |
2634 | TCGv dest; | |
2635 | TCGv addr_dest; | |
2636 | int opsize; | |
2637 | ||
2638 | opsize = insn_opsize(insn); | |
2639 | ||
2640 | addr_src = AREG(insn, 0); | |
2641 | tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize)); | |
2642 | src = gen_load(s, opsize, addr_src, 1); | |
2643 | ||
2644 | addr_dest = AREG(insn, 9); | |
2645 | tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize)); | |
2646 | dest = gen_load(s, opsize, addr_dest, 1); | |
2647 | ||
2648 | gen_addx(s, src, dest, opsize); | |
2649 | ||
2650 | gen_store(s, opsize, addr_dest, QREG_CC_N); | |
2651 | } | |
2652 | ||
2653 | /* TODO: This could be implemented without helper functions. */ | |
2654 | DISAS_INSN(shift_im) | |
2655 | { | |
2656 | TCGv reg; | |
2657 | int tmp; | |
2658 | TCGv shift; | |
2659 | ||
2660 | set_cc_op(s, CC_OP_FLAGS); | |
2661 | ||
2662 | reg = DREG(insn, 0); | |
2663 | tmp = (insn >> 9) & 7; | |
2664 | if (tmp == 0) | |
2665 | tmp = 8; | |
2666 | shift = tcg_const_i32(tmp); | |
2667 | /* No need to flush flags becuse we know we will set C flag. */ | |
2668 | if (insn & 0x100) { | |
2669 | gen_helper_shl_cc(reg, cpu_env, reg, shift); | |
2670 | } else { | |
2671 | if (insn & 8) { | |
2672 | gen_helper_shr_cc(reg, cpu_env, reg, shift); | |
2673 | } else { | |
2674 | gen_helper_sar_cc(reg, cpu_env, reg, shift); | |
2675 | } | |
2676 | } | |
2677 | } | |
2678 | ||
2679 | DISAS_INSN(shift_reg) | |
2680 | { | |
2681 | TCGv reg; | |
2682 | TCGv shift; | |
2683 | ||
2684 | reg = DREG(insn, 0); | |
2685 | shift = DREG(insn, 9); | |
2686 | if (insn & 0x100) { | |
2687 | gen_helper_shl_cc(reg, cpu_env, reg, shift); | |
2688 | } else { | |
2689 | if (insn & 8) { | |
2690 | gen_helper_shr_cc(reg, cpu_env, reg, shift); | |
2691 | } else { | |
2692 | gen_helper_sar_cc(reg, cpu_env, reg, shift); | |
2693 | } | |
2694 | } | |
2695 | set_cc_op(s, CC_OP_FLAGS); | |
2696 | } | |
2697 | ||
2698 | DISAS_INSN(ff1) | |
2699 | { | |
2700 | TCGv reg; | |
2701 | reg = DREG(insn, 0); | |
2702 | gen_logic_cc(s, reg, OS_LONG); | |
2703 | gen_helper_ff1(reg, reg); | |
2704 | } | |
2705 | ||
2706 | static TCGv gen_get_sr(DisasContext *s) | |
2707 | { | |
2708 | TCGv ccr; | |
2709 | TCGv sr; | |
2710 | ||
2711 | ccr = gen_get_ccr(s); | |
2712 | sr = tcg_temp_new(); | |
2713 | tcg_gen_andi_i32(sr, QREG_SR, 0xffe0); | |
2714 | tcg_gen_or_i32(sr, sr, ccr); | |
2715 | return sr; | |
2716 | } | |
2717 | ||
2718 | DISAS_INSN(strldsr) | |
2719 | { | |
2720 | uint16_t ext; | |
2721 | uint32_t addr; | |
2722 | ||
2723 | addr = s->pc - 2; | |
2724 | ext = read_im16(env, s); | |
2725 | if (ext != 0x46FC) { | |
2726 | gen_exception(s, addr, EXCP_UNSUPPORTED); | |
2727 | return; | |
2728 | } | |
2729 | ext = read_im16(env, s); | |
2730 | if (IS_USER(s) || (ext & SR_S) == 0) { | |
2731 | gen_exception(s, addr, EXCP_PRIVILEGE); | |
2732 | return; | |
2733 | } | |
2734 | gen_push(s, gen_get_sr(s)); | |
2735 | gen_set_sr_im(s, ext, 0); | |
2736 | } | |
2737 | ||
2738 | DISAS_INSN(move_from_sr) | |
2739 | { | |
2740 | TCGv sr; | |
2741 | ||
2742 | if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) { | |
2743 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2744 | return; | |
2745 | } | |
2746 | sr = gen_get_sr(s); | |
2747 | DEST_EA(env, insn, OS_WORD, sr, NULL); | |
2748 | } | |
2749 | ||
2750 | DISAS_INSN(move_to_sr) | |
2751 | { | |
2752 | if (IS_USER(s)) { | |
2753 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2754 | return; | |
2755 | } | |
2756 | gen_set_sr(env, s, insn, 0); | |
2757 | gen_lookup_tb(s); | |
2758 | } | |
2759 | ||
2760 | DISAS_INSN(move_from_usp) | |
2761 | { | |
2762 | if (IS_USER(s)) { | |
2763 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2764 | return; | |
2765 | } | |
2766 | tcg_gen_ld_i32(AREG(insn, 0), cpu_env, | |
2767 | offsetof(CPUM68KState, sp[M68K_USP])); | |
2768 | } | |
2769 | ||
2770 | DISAS_INSN(move_to_usp) | |
2771 | { | |
2772 | if (IS_USER(s)) { | |
2773 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2774 | return; | |
2775 | } | |
2776 | tcg_gen_st_i32(AREG(insn, 0), cpu_env, | |
2777 | offsetof(CPUM68KState, sp[M68K_USP])); | |
2778 | } | |
2779 | ||
2780 | DISAS_INSN(halt) | |
2781 | { | |
2782 | gen_exception(s, s->pc, EXCP_HALT_INSN); | |
2783 | } | |
2784 | ||
2785 | DISAS_INSN(stop) | |
2786 | { | |
2787 | uint16_t ext; | |
2788 | ||
2789 | if (IS_USER(s)) { | |
2790 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2791 | return; | |
2792 | } | |
2793 | ||
2794 | ext = read_im16(env, s); | |
2795 | ||
2796 | gen_set_sr_im(s, ext, 0); | |
2797 | tcg_gen_movi_i32(cpu_halted, 1); | |
2798 | gen_exception(s, s->pc, EXCP_HLT); | |
2799 | } | |
2800 | ||
2801 | DISAS_INSN(rte) | |
2802 | { | |
2803 | if (IS_USER(s)) { | |
2804 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2805 | return; | |
2806 | } | |
2807 | gen_exception(s, s->pc - 2, EXCP_RTE); | |
2808 | } | |
2809 | ||
2810 | DISAS_INSN(movec) | |
2811 | { | |
2812 | uint16_t ext; | |
2813 | TCGv reg; | |
2814 | ||
2815 | if (IS_USER(s)) { | |
2816 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2817 | return; | |
2818 | } | |
2819 | ||
2820 | ext = read_im16(env, s); | |
2821 | ||
2822 | if (ext & 0x8000) { | |
2823 | reg = AREG(ext, 12); | |
2824 | } else { | |
2825 | reg = DREG(ext, 12); | |
2826 | } | |
2827 | gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg); | |
2828 | gen_lookup_tb(s); | |
2829 | } | |
2830 | ||
2831 | DISAS_INSN(intouch) | |
2832 | { | |
2833 | if (IS_USER(s)) { | |
2834 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2835 | return; | |
2836 | } | |
2837 | /* ICache fetch. Implement as no-op. */ | |
2838 | } | |
2839 | ||
2840 | DISAS_INSN(cpushl) | |
2841 | { | |
2842 | if (IS_USER(s)) { | |
2843 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2844 | return; | |
2845 | } | |
2846 | /* Cache push/invalidate. Implement as no-op. */ | |
2847 | } | |
2848 | ||
2849 | DISAS_INSN(wddata) | |
2850 | { | |
2851 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2852 | } | |
2853 | ||
2854 | DISAS_INSN(wdebug) | |
2855 | { | |
2856 | M68kCPU *cpu = m68k_env_get_cpu(env); | |
2857 | ||
2858 | if (IS_USER(s)) { | |
2859 | gen_exception(s, s->pc - 2, EXCP_PRIVILEGE); | |
2860 | return; | |
2861 | } | |
2862 | /* TODO: Implement wdebug. */ | |
2863 | cpu_abort(CPU(cpu), "WDEBUG not implemented"); | |
2864 | } | |
2865 | ||
2866 | DISAS_INSN(trap) | |
2867 | { | |
2868 | gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf)); | |
2869 | } | |
2870 | ||
2871 | /* ??? FP exceptions are not implemented. Most exceptions are deferred until | |
2872 | immediately before the next FP instruction is executed. */ | |
2873 | DISAS_INSN(fpu) | |
2874 | { | |
2875 | uint16_t ext; | |
2876 | int32_t offset; | |
2877 | int opmode; | |
2878 | TCGv_i64 src; | |
2879 | TCGv_i64 dest; | |
2880 | TCGv_i64 res; | |
2881 | TCGv tmp32; | |
2882 | int round; | |
2883 | int set_dest; | |
2884 | int opsize; | |
2885 | ||
2886 | ext = read_im16(env, s); | |
2887 | opmode = ext & 0x7f; | |
2888 | switch ((ext >> 13) & 7) { | |
2889 | case 0: case 2: | |
2890 | break; | |
2891 | case 1: | |
2892 | goto undef; | |
2893 | case 3: /* fmove out */ | |
2894 | src = FREG(ext, 7); | |
2895 | tmp32 = tcg_temp_new_i32(); | |
2896 | /* fmove */ | |
2897 | /* ??? TODO: Proper behavior on overflow. */ | |
2898 | switch ((ext >> 10) & 7) { | |
2899 | case 0: | |
2900 | opsize = OS_LONG; | |
2901 | gen_helper_f64_to_i32(tmp32, cpu_env, src); | |
2902 | break; | |
2903 | case 1: | |
2904 | opsize = OS_SINGLE; | |
2905 | gen_helper_f64_to_f32(tmp32, cpu_env, src); | |
2906 | break; | |
2907 | case 4: | |
2908 | opsize = OS_WORD; | |
2909 | gen_helper_f64_to_i32(tmp32, cpu_env, src); | |
2910 | break; | |
2911 | case 5: /* OS_DOUBLE */ | |
2912 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
2913 | switch ((insn >> 3) & 7) { | |
2914 | case 2: | |
2915 | case 3: | |
2916 | break; | |
2917 | case 4: | |
2918 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
2919 | break; | |
2920 | case 5: | |
2921 | offset = cpu_ldsw_code(env, s->pc); | |
2922 | s->pc += 2; | |
2923 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
2924 | break; | |
2925 | default: | |
2926 | goto undef; | |
2927 | } | |
2928 | gen_store64(s, tmp32, src); | |
2929 | switch ((insn >> 3) & 7) { | |
2930 | case 3: | |
2931 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
2932 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2933 | break; | |
2934 | case 4: | |
2935 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
2936 | break; | |
2937 | } | |
2938 | tcg_temp_free_i32(tmp32); | |
2939 | return; | |
2940 | case 6: | |
2941 | opsize = OS_BYTE; | |
2942 | gen_helper_f64_to_i32(tmp32, cpu_env, src); | |
2943 | break; | |
2944 | default: | |
2945 | goto undef; | |
2946 | } | |
2947 | DEST_EA(env, insn, opsize, tmp32, NULL); | |
2948 | tcg_temp_free_i32(tmp32); | |
2949 | return; | |
2950 | case 4: /* fmove to control register. */ | |
2951 | switch ((ext >> 10) & 7) { | |
2952 | case 4: /* FPCR */ | |
2953 | /* Not implemented. Ignore writes. */ | |
2954 | break; | |
2955 | case 1: /* FPIAR */ | |
2956 | case 2: /* FPSR */ | |
2957 | default: | |
2958 | cpu_abort(NULL, "Unimplemented: fmove to control %d", | |
2959 | (ext >> 10) & 7); | |
2960 | } | |
2961 | break; | |
2962 | case 5: /* fmove from control register. */ | |
2963 | switch ((ext >> 10) & 7) { | |
2964 | case 4: /* FPCR */ | |
2965 | /* Not implemented. Always return zero. */ | |
2966 | tmp32 = tcg_const_i32(0); | |
2967 | break; | |
2968 | case 1: /* FPIAR */ | |
2969 | case 2: /* FPSR */ | |
2970 | default: | |
2971 | cpu_abort(NULL, "Unimplemented: fmove from control %d", | |
2972 | (ext >> 10) & 7); | |
2973 | goto undef; | |
2974 | } | |
2975 | DEST_EA(env, insn, OS_LONG, tmp32, NULL); | |
2976 | break; | |
2977 | case 6: /* fmovem */ | |
2978 | case 7: | |
2979 | { | |
2980 | TCGv addr; | |
2981 | uint16_t mask; | |
2982 | int i; | |
2983 | if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0) | |
2984 | goto undef; | |
2985 | tmp32 = gen_lea(env, s, insn, OS_LONG); | |
2986 | if (IS_NULL_QREG(tmp32)) { | |
2987 | gen_addr_fault(s); | |
2988 | return; | |
2989 | } | |
2990 | addr = tcg_temp_new_i32(); | |
2991 | tcg_gen_mov_i32(addr, tmp32); | |
2992 | mask = 0x80; | |
2993 | for (i = 0; i < 8; i++) { | |
2994 | if (ext & mask) { | |
2995 | dest = FREG(i, 0); | |
2996 | if (ext & (1 << 13)) { | |
2997 | /* store */ | |
2998 | tcg_gen_qemu_stf64(dest, addr, IS_USER(s)); | |
2999 | } else { | |
3000 | /* load */ | |
3001 | tcg_gen_qemu_ldf64(dest, addr, IS_USER(s)); | |
3002 | } | |
3003 | if (ext & (mask - 1)) | |
3004 | tcg_gen_addi_i32(addr, addr, 8); | |
3005 | } | |
3006 | mask >>= 1; | |
3007 | } | |
3008 | tcg_temp_free_i32(addr); | |
3009 | } | |
3010 | return; | |
3011 | } | |
3012 | if (ext & (1 << 14)) { | |
3013 | /* Source effective address. */ | |
3014 | switch ((ext >> 10) & 7) { | |
3015 | case 0: opsize = OS_LONG; break; | |
3016 | case 1: opsize = OS_SINGLE; break; | |
3017 | case 4: opsize = OS_WORD; break; | |
3018 | case 5: opsize = OS_DOUBLE; break; | |
3019 | case 6: opsize = OS_BYTE; break; | |
3020 | default: | |
3021 | goto undef; | |
3022 | } | |
3023 | if (opsize == OS_DOUBLE) { | |
3024 | tmp32 = tcg_temp_new_i32(); | |
3025 | tcg_gen_mov_i32(tmp32, AREG(insn, 0)); | |
3026 | switch ((insn >> 3) & 7) { | |
3027 | case 2: | |
3028 | case 3: | |
3029 | break; | |
3030 | case 4: | |
3031 | tcg_gen_addi_i32(tmp32, tmp32, -8); | |
3032 | break; | |
3033 | case 5: | |
3034 | offset = cpu_ldsw_code(env, s->pc); | |
3035 | s->pc += 2; | |
3036 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
3037 | break; | |
3038 | case 7: | |
3039 | offset = cpu_ldsw_code(env, s->pc); | |
3040 | offset += s->pc - 2; | |
3041 | s->pc += 2; | |
3042 | tcg_gen_addi_i32(tmp32, tmp32, offset); | |
3043 | break; | |
3044 | default: | |
3045 | goto undef; | |
3046 | } | |
3047 | src = gen_load64(s, tmp32); | |
3048 | switch ((insn >> 3) & 7) { | |
3049 | case 3: | |
3050 | tcg_gen_addi_i32(tmp32, tmp32, 8); | |
3051 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
3052 | break; | |
3053 | case 4: | |
3054 | tcg_gen_mov_i32(AREG(insn, 0), tmp32); | |
3055 | break; | |
3056 | } | |
3057 | tcg_temp_free_i32(tmp32); | |
3058 | } else { | |
3059 | SRC_EA(env, tmp32, opsize, 1, NULL); | |
3060 | src = tcg_temp_new_i64(); | |
3061 | switch (opsize) { | |
3062 | case OS_LONG: | |
3063 | case OS_WORD: | |
3064 | case OS_BYTE: | |
3065 | gen_helper_i32_to_f64(src, cpu_env, tmp32); | |
3066 | break; | |
3067 | case OS_SINGLE: | |
3068 | gen_helper_f32_to_f64(src, cpu_env, tmp32); | |
3069 | break; | |
3070 | } | |
3071 | } | |
3072 | } else { | |
3073 | /* Source register. */ | |
3074 | src = FREG(ext, 10); | |
3075 | } | |
3076 | dest = FREG(ext, 7); | |
3077 | res = tcg_temp_new_i64(); | |
3078 | if (opmode != 0x3a) | |
3079 | tcg_gen_mov_f64(res, dest); | |
3080 | round = 1; | |
3081 | set_dest = 1; | |
3082 | switch (opmode) { | |
3083 | case 0: case 0x40: case 0x44: /* fmove */ | |
3084 | tcg_gen_mov_f64(res, src); | |
3085 | break; | |
3086 | case 1: /* fint */ | |
3087 | gen_helper_iround_f64(res, cpu_env, src); | |
3088 | round = 0; | |
3089 | break; | |
3090 | case 3: /* fintrz */ | |
3091 | gen_helper_itrunc_f64(res, cpu_env, src); | |
3092 | round = 0; | |
3093 | break; | |
3094 | case 4: case 0x41: case 0x45: /* fsqrt */ | |
3095 | gen_helper_sqrt_f64(res, cpu_env, src); | |
3096 | break; | |
3097 | case 0x18: case 0x58: case 0x5c: /* fabs */ | |
3098 | gen_helper_abs_f64(res, src); | |
3099 | break; | |
3100 | case 0x1a: case 0x5a: case 0x5e: /* fneg */ | |
3101 | gen_helper_chs_f64(res, src); | |
3102 | break; | |
3103 | case 0x20: case 0x60: case 0x64: /* fdiv */ | |
3104 | gen_helper_div_f64(res, cpu_env, res, src); | |
3105 | break; | |
3106 | case 0x22: case 0x62: case 0x66: /* fadd */ | |
3107 | gen_helper_add_f64(res, cpu_env, res, src); | |
3108 | break; | |
3109 | case 0x23: case 0x63: case 0x67: /* fmul */ | |
3110 | gen_helper_mul_f64(res, cpu_env, res, src); | |
3111 | break; | |
3112 | case 0x28: case 0x68: case 0x6c: /* fsub */ | |
3113 | gen_helper_sub_f64(res, cpu_env, res, src); | |
3114 | break; | |
3115 | case 0x38: /* fcmp */ | |
3116 | gen_helper_sub_cmp_f64(res, cpu_env, res, src); | |
3117 | set_dest = 0; | |
3118 | round = 0; | |
3119 | break; | |
3120 | case 0x3a: /* ftst */ | |
3121 | tcg_gen_mov_f64(res, src); | |
3122 | set_dest = 0; | |
3123 | round = 0; | |
3124 | break; | |
3125 | default: | |
3126 | goto undef; | |
3127 | } | |
3128 | if (ext & (1 << 14)) { | |
3129 | tcg_temp_free_i64(src); | |
3130 | } | |
3131 | if (round) { | |
3132 | if (opmode & 0x40) { | |
3133 | if ((opmode & 0x4) != 0) | |
3134 | round = 0; | |
3135 | } else if ((s->fpcr & M68K_FPCR_PREC) == 0) { | |
3136 | round = 0; | |
3137 | } | |
3138 | } | |
3139 | if (round) { | |
3140 | TCGv tmp = tcg_temp_new_i32(); | |
3141 | gen_helper_f64_to_f32(tmp, cpu_env, res); | |
3142 | gen_helper_f32_to_f64(res, cpu_env, tmp); | |
3143 | tcg_temp_free_i32(tmp); | |
3144 | } | |
3145 | tcg_gen_mov_f64(QREG_FP_RESULT, res); | |
3146 | if (set_dest) { | |
3147 | tcg_gen_mov_f64(dest, res); | |
3148 | } | |
3149 | tcg_temp_free_i64(res); | |
3150 | return; | |
3151 | undef: | |
3152 | /* FIXME: Is this right for offset addressing modes? */ | |
3153 | s->pc -= 2; | |
3154 | disas_undef_fpu(env, s, insn); | |
3155 | } | |
3156 | ||
3157 | DISAS_INSN(fbcc) | |
3158 | { | |
3159 | uint32_t offset; | |
3160 | uint32_t addr; | |
3161 | TCGv flag; | |
3162 | TCGLabel *l1; | |
3163 | ||
3164 | addr = s->pc; | |
3165 | offset = cpu_ldsw_code(env, s->pc); | |
3166 | s->pc += 2; | |
3167 | if (insn & (1 << 6)) { | |
3168 | offset = (offset << 16) | read_im16(env, s); | |
3169 | } | |
3170 | ||
3171 | l1 = gen_new_label(); | |
3172 | /* TODO: Raise BSUN exception. */ | |
3173 | flag = tcg_temp_new(); | |
3174 | gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT); | |
3175 | /* Jump to l1 if condition is true. */ | |
3176 | switch (insn & 0xf) { | |
3177 | case 0: /* f */ | |
3178 | break; | |
3179 | case 1: /* eq (=0) */ | |
3180 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
3181 | break; | |
3182 | case 2: /* ogt (=1) */ | |
3183 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1); | |
3184 | break; | |
3185 | case 3: /* oge (=0 or =1) */ | |
3186 | tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1); | |
3187 | break; | |
3188 | case 4: /* olt (=-1) */ | |
3189 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1); | |
3190 | break; | |
3191 | case 5: /* ole (=-1 or =0) */ | |
3192 | tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1); | |
3193 | break; | |
3194 | case 6: /* ogl (=-1 or =1) */ | |
3195 | tcg_gen_andi_i32(flag, flag, 1); | |
3196 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
3197 | break; | |
3198 | case 7: /* or (=2) */ | |
3199 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1); | |
3200 | break; | |
3201 | case 8: /* un (<2) */ | |
3202 | tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1); | |
3203 | break; | |
3204 | case 9: /* ueq (=0 or =2) */ | |
3205 | tcg_gen_andi_i32(flag, flag, 1); | |
3206 | tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1); | |
3207 | break; | |
3208 | case 10: /* ugt (>0) */ | |
3209 | tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1); | |
3210 | break; | |
3211 | case 11: /* uge (>=0) */ | |
3212 | tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1); | |
3213 | break; | |
3214 | case 12: /* ult (=-1 or =2) */ | |
3215 | tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1); | |
3216 | break; | |
3217 | case 13: /* ule (!=1) */ | |
3218 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1); | |
3219 | break; | |
3220 | case 14: /* ne (!=0) */ | |
3221 | tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1); | |
3222 | break; | |
3223 | case 15: /* t */ | |
3224 | tcg_gen_br(l1); | |
3225 | break; | |
3226 | } | |
3227 | gen_jmp_tb(s, 0, s->pc); | |
3228 | gen_set_label(l1); | |
3229 | gen_jmp_tb(s, 1, addr + offset); | |
3230 | } | |
3231 | ||
3232 | DISAS_INSN(frestore) | |
3233 | { | |
3234 | M68kCPU *cpu = m68k_env_get_cpu(env); | |
3235 | ||
3236 | /* TODO: Implement frestore. */ | |
3237 | cpu_abort(CPU(cpu), "FRESTORE not implemented"); | |
3238 | } | |
3239 | ||
3240 | DISAS_INSN(fsave) | |
3241 | { | |
3242 | M68kCPU *cpu = m68k_env_get_cpu(env); | |
3243 | ||
3244 | /* TODO: Implement fsave. */ | |
3245 | cpu_abort(CPU(cpu), "FSAVE not implemented"); | |
3246 | } | |
3247 | ||
3248 | static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper) | |
3249 | { | |
3250 | TCGv tmp = tcg_temp_new(); | |
3251 | if (s->env->macsr & MACSR_FI) { | |
3252 | if (upper) | |
3253 | tcg_gen_andi_i32(tmp, val, 0xffff0000); | |
3254 | else | |
3255 | tcg_gen_shli_i32(tmp, val, 16); | |
3256 | } else if (s->env->macsr & MACSR_SU) { | |
3257 | if (upper) | |
3258 | tcg_gen_sari_i32(tmp, val, 16); | |
3259 | else | |
3260 | tcg_gen_ext16s_i32(tmp, val); | |
3261 | } else { | |
3262 | if (upper) | |
3263 | tcg_gen_shri_i32(tmp, val, 16); | |
3264 | else | |
3265 | tcg_gen_ext16u_i32(tmp, val); | |
3266 | } | |
3267 | return tmp; | |
3268 | } | |
3269 | ||
3270 | static void gen_mac_clear_flags(void) | |
3271 | { | |
3272 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, | |
3273 | ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV)); | |
3274 | } | |
3275 | ||
3276 | DISAS_INSN(mac) | |
3277 | { | |
3278 | TCGv rx; | |
3279 | TCGv ry; | |
3280 | uint16_t ext; | |
3281 | int acc; | |
3282 | TCGv tmp; | |
3283 | TCGv addr; | |
3284 | TCGv loadval; | |
3285 | int dual; | |
3286 | TCGv saved_flags; | |
3287 | ||
3288 | if (!s->done_mac) { | |
3289 | s->mactmp = tcg_temp_new_i64(); | |
3290 | s->done_mac = 1; | |
3291 | } | |
3292 | ||
3293 | ext = read_im16(env, s); | |
3294 | ||
3295 | acc = ((insn >> 7) & 1) | ((ext >> 3) & 2); | |
3296 | dual = ((insn & 0x30) != 0 && (ext & 3) != 0); | |
3297 | if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) { | |
3298 | disas_undef(env, s, insn); | |
3299 | return; | |
3300 | } | |
3301 | if (insn & 0x30) { | |
3302 | /* MAC with load. */ | |
3303 | tmp = gen_lea(env, s, insn, OS_LONG); | |
3304 | addr = tcg_temp_new(); | |
3305 | tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK); | |
3306 | /* Load the value now to ensure correct exception behavior. | |
3307 | Perform writeback after reading the MAC inputs. */ | |
3308 | loadval = gen_load(s, OS_LONG, addr, 0); | |
3309 | ||
3310 | acc ^= 1; | |
3311 | rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12); | |
3312 | ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0); | |
3313 | } else { | |
3314 | loadval = addr = NULL_QREG; | |
3315 | rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); | |
3316 | ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
3317 | } | |
3318 | ||
3319 | gen_mac_clear_flags(); | |
3320 | #if 0 | |
3321 | l1 = -1; | |
3322 | /* Disabled because conditional branches clobber temporary vars. */ | |
3323 | if ((s->env->macsr & MACSR_OMC) != 0 && !dual) { | |
3324 | /* Skip the multiply if we know we will ignore it. */ | |
3325 | l1 = gen_new_label(); | |
3326 | tmp = tcg_temp_new(); | |
3327 | tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8)); | |
3328 | gen_op_jmp_nz32(tmp, l1); | |
3329 | } | |
3330 | #endif | |
3331 | ||
3332 | if ((ext & 0x0800) == 0) { | |
3333 | /* Word. */ | |
3334 | rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0); | |
3335 | ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0); | |
3336 | } | |
3337 | if (s->env->macsr & MACSR_FI) { | |
3338 | gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); | |
3339 | } else { | |
3340 | if (s->env->macsr & MACSR_SU) | |
3341 | gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); | |
3342 | else | |
3343 | gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); | |
3344 | switch ((ext >> 9) & 3) { | |
3345 | case 1: | |
3346 | tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); | |
3347 | break; | |
3348 | case 3: | |
3349 | tcg_gen_shri_i64(s->mactmp, s->mactmp, 1); | |
3350 | break; | |
3351 | } | |
3352 | } | |
3353 | ||
3354 | if (dual) { | |
3355 | /* Save the overflow flag from the multiply. */ | |
3356 | saved_flags = tcg_temp_new(); | |
3357 | tcg_gen_mov_i32(saved_flags, QREG_MACSR); | |
3358 | } else { | |
3359 | saved_flags = NULL_QREG; | |
3360 | } | |
3361 | ||
3362 | #if 0 | |
3363 | /* Disabled because conditional branches clobber temporary vars. */ | |
3364 | if ((s->env->macsr & MACSR_OMC) != 0 && dual) { | |
3365 | /* Skip the accumulate if the value is already saturated. */ | |
3366 | l1 = gen_new_label(); | |
3367 | tmp = tcg_temp_new(); | |
3368 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); | |
3369 | gen_op_jmp_nz32(tmp, l1); | |
3370 | } | |
3371 | #endif | |
3372 | ||
3373 | if (insn & 0x100) | |
3374 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); | |
3375 | else | |
3376 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); | |
3377 | ||
3378 | if (s->env->macsr & MACSR_FI) | |
3379 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); | |
3380 | else if (s->env->macsr & MACSR_SU) | |
3381 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); | |
3382 | else | |
3383 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); | |
3384 | ||
3385 | #if 0 | |
3386 | /* Disabled because conditional branches clobber temporary vars. */ | |
3387 | if (l1 != -1) | |
3388 | gen_set_label(l1); | |
3389 | #endif | |
3390 | ||
3391 | if (dual) { | |
3392 | /* Dual accumulate variant. */ | |
3393 | acc = (ext >> 2) & 3; | |
3394 | /* Restore the overflow flag from the multiplier. */ | |
3395 | tcg_gen_mov_i32(QREG_MACSR, saved_flags); | |
3396 | #if 0 | |
3397 | /* Disabled because conditional branches clobber temporary vars. */ | |
3398 | if ((s->env->macsr & MACSR_OMC) != 0) { | |
3399 | /* Skip the accumulate if the value is already saturated. */ | |
3400 | l1 = gen_new_label(); | |
3401 | tmp = tcg_temp_new(); | |
3402 | gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc)); | |
3403 | gen_op_jmp_nz32(tmp, l1); | |
3404 | } | |
3405 | #endif | |
3406 | if (ext & 2) | |
3407 | tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp); | |
3408 | else | |
3409 | tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); | |
3410 | if (s->env->macsr & MACSR_FI) | |
3411 | gen_helper_macsatf(cpu_env, tcg_const_i32(acc)); | |
3412 | else if (s->env->macsr & MACSR_SU) | |
3413 | gen_helper_macsats(cpu_env, tcg_const_i32(acc)); | |
3414 | else | |
3415 | gen_helper_macsatu(cpu_env, tcg_const_i32(acc)); | |
3416 | #if 0 | |
3417 | /* Disabled because conditional branches clobber temporary vars. */ | |
3418 | if (l1 != -1) | |
3419 | gen_set_label(l1); | |
3420 | #endif | |
3421 | } | |
3422 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc)); | |
3423 | ||
3424 | if (insn & 0x30) { | |
3425 | TCGv rw; | |
3426 | rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9); | |
3427 | tcg_gen_mov_i32(rw, loadval); | |
3428 | /* FIXME: Should address writeback happen with the masked or | |
3429 | unmasked value? */ | |
3430 | switch ((insn >> 3) & 7) { | |
3431 | case 3: /* Post-increment. */ | |
3432 | tcg_gen_addi_i32(AREG(insn, 0), addr, 4); | |
3433 | break; | |
3434 | case 4: /* Pre-decrement. */ | |
3435 | tcg_gen_mov_i32(AREG(insn, 0), addr); | |
3436 | } | |
3437 | } | |
3438 | } | |
3439 | ||
3440 | DISAS_INSN(from_mac) | |
3441 | { | |
3442 | TCGv rx; | |
3443 | TCGv_i64 acc; | |
3444 | int accnum; | |
3445 | ||
3446 | rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
3447 | accnum = (insn >> 9) & 3; | |
3448 | acc = MACREG(accnum); | |
3449 | if (s->env->macsr & MACSR_FI) { | |
3450 | gen_helper_get_macf(rx, cpu_env, acc); | |
3451 | } else if ((s->env->macsr & MACSR_OMC) == 0) { | |
3452 | tcg_gen_extrl_i64_i32(rx, acc); | |
3453 | } else if (s->env->macsr & MACSR_SU) { | |
3454 | gen_helper_get_macs(rx, acc); | |
3455 | } else { | |
3456 | gen_helper_get_macu(rx, acc); | |
3457 | } | |
3458 | if (insn & 0x40) { | |
3459 | tcg_gen_movi_i64(acc, 0); | |
3460 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
3461 | } | |
3462 | } | |
3463 | ||
3464 | DISAS_INSN(move_mac) | |
3465 | { | |
3466 | /* FIXME: This can be done without a helper. */ | |
3467 | int src; | |
3468 | TCGv dest; | |
3469 | src = insn & 3; | |
3470 | dest = tcg_const_i32((insn >> 9) & 3); | |
3471 | gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src)); | |
3472 | gen_mac_clear_flags(); | |
3473 | gen_helper_mac_set_flags(cpu_env, dest); | |
3474 | } | |
3475 | ||
3476 | DISAS_INSN(from_macsr) | |
3477 | { | |
3478 | TCGv reg; | |
3479 | ||
3480 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
3481 | tcg_gen_mov_i32(reg, QREG_MACSR); | |
3482 | } | |
3483 | ||
3484 | DISAS_INSN(from_mask) | |
3485 | { | |
3486 | TCGv reg; | |
3487 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
3488 | tcg_gen_mov_i32(reg, QREG_MAC_MASK); | |
3489 | } | |
3490 | ||
3491 | DISAS_INSN(from_mext) | |
3492 | { | |
3493 | TCGv reg; | |
3494 | TCGv acc; | |
3495 | reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); | |
3496 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); | |
3497 | if (s->env->macsr & MACSR_FI) | |
3498 | gen_helper_get_mac_extf(reg, cpu_env, acc); | |
3499 | else | |
3500 | gen_helper_get_mac_exti(reg, cpu_env, acc); | |
3501 | } | |
3502 | ||
3503 | DISAS_INSN(macsr_to_ccr) | |
3504 | { | |
3505 | TCGv tmp = tcg_temp_new(); | |
3506 | tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf); | |
3507 | gen_helper_set_sr(cpu_env, tmp); | |
3508 | tcg_temp_free(tmp); | |
3509 | set_cc_op(s, CC_OP_FLAGS); | |
3510 | } | |
3511 | ||
3512 | DISAS_INSN(to_mac) | |
3513 | { | |
3514 | TCGv_i64 acc; | |
3515 | TCGv val; | |
3516 | int accnum; | |
3517 | accnum = (insn >> 9) & 3; | |
3518 | acc = MACREG(accnum); | |
3519 | SRC_EA(env, val, OS_LONG, 0, NULL); | |
3520 | if (s->env->macsr & MACSR_FI) { | |
3521 | tcg_gen_ext_i32_i64(acc, val); | |
3522 | tcg_gen_shli_i64(acc, acc, 8); | |
3523 | } else if (s->env->macsr & MACSR_SU) { | |
3524 | tcg_gen_ext_i32_i64(acc, val); | |
3525 | } else { | |
3526 | tcg_gen_extu_i32_i64(acc, val); | |
3527 | } | |
3528 | tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); | |
3529 | gen_mac_clear_flags(); | |
3530 | gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum)); | |
3531 | } | |
3532 | ||
3533 | DISAS_INSN(to_macsr) | |
3534 | { | |
3535 | TCGv val; | |
3536 | SRC_EA(env, val, OS_LONG, 0, NULL); | |
3537 | gen_helper_set_macsr(cpu_env, val); | |
3538 | gen_lookup_tb(s); | |
3539 | } | |
3540 | ||
3541 | DISAS_INSN(to_mask) | |
3542 | { | |
3543 | TCGv val; | |
3544 | SRC_EA(env, val, OS_LONG, 0, NULL); | |
3545 | tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000); | |
3546 | } | |
3547 | ||
3548 | DISAS_INSN(to_mext) | |
3549 | { | |
3550 | TCGv val; | |
3551 | TCGv acc; | |
3552 | SRC_EA(env, val, OS_LONG, 0, NULL); | |
3553 | acc = tcg_const_i32((insn & 0x400) ? 2 : 0); | |
3554 | if (s->env->macsr & MACSR_FI) | |
3555 | gen_helper_set_mac_extf(cpu_env, val, acc); | |
3556 | else if (s->env->macsr & MACSR_SU) | |
3557 | gen_helper_set_mac_exts(cpu_env, val, acc); | |
3558 | else | |
3559 | gen_helper_set_mac_extu(cpu_env, val, acc); | |
3560 | } | |
3561 | ||
3562 | static disas_proc opcode_table[65536]; | |
3563 | ||
3564 | static void | |
3565 | register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask) | |
3566 | { | |
3567 | int i; | |
3568 | int from; | |
3569 | int to; | |
3570 | ||
3571 | /* Sanity check. All set bits must be included in the mask. */ | |
3572 | if (opcode & ~mask) { | |
3573 | fprintf(stderr, | |
3574 | "qemu internal error: bogus opcode definition %04x/%04x\n", | |
3575 | opcode, mask); | |
3576 | abort(); | |
3577 | } | |
3578 | /* This could probably be cleverer. For now just optimize the case where | |
3579 | the top bits are known. */ | |
3580 | /* Find the first zero bit in the mask. */ | |
3581 | i = 0x8000; | |
3582 | while ((i & mask) != 0) | |
3583 | i >>= 1; | |
3584 | /* Iterate over all combinations of this and lower bits. */ | |
3585 | if (i == 0) | |
3586 | i = 1; | |
3587 | else | |
3588 | i <<= 1; | |
3589 | from = opcode & ~(i - 1); | |
3590 | to = from + i; | |
3591 | for (i = from; i < to; i++) { | |
3592 | if ((i & mask) == opcode) | |
3593 | opcode_table[i] = proc; | |
3594 | } | |
3595 | } | |
3596 | ||
3597 | /* Register m68k opcode handlers. Order is important. | |
3598 | Later insn override earlier ones. */ | |
3599 | void register_m68k_insns (CPUM68KState *env) | |
3600 | { | |
3601 | /* Build the opcode table only once to avoid | |
3602 | multithreading issues. */ | |
3603 | if (opcode_table[0] != NULL) { | |
3604 | return; | |
3605 | } | |
3606 | ||
3607 | /* use BASE() for instruction available | |
3608 | * for CF_ISA_A and M68000. | |
3609 | */ | |
3610 | #define BASE(name, opcode, mask) \ | |
3611 | register_opcode(disas_##name, 0x##opcode, 0x##mask) | |
3612 | #define INSN(name, opcode, mask, feature) do { \ | |
3613 | if (m68k_feature(env, M68K_FEATURE_##feature)) \ | |
3614 | BASE(name, opcode, mask); \ | |
3615 | } while(0) | |
3616 | BASE(undef, 0000, 0000); | |
3617 | INSN(arith_im, 0080, fff8, CF_ISA_A); | |
3618 | INSN(arith_im, 0000, ff00, M68000); | |
3619 | INSN(undef, 00c0, ffc0, M68000); | |
3620 | INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC); | |
3621 | BASE(bitop_reg, 0100, f1c0); | |
3622 | BASE(bitop_reg, 0140, f1c0); | |
3623 | BASE(bitop_reg, 0180, f1c0); | |
3624 | BASE(bitop_reg, 01c0, f1c0); | |
3625 | INSN(arith_im, 0280, fff8, CF_ISA_A); | |
3626 | INSN(arith_im, 0200, ff00, M68000); | |
3627 | INSN(undef, 02c0, ffc0, M68000); | |
3628 | INSN(byterev, 02c0, fff8, CF_ISA_APLUSC); | |
3629 | INSN(arith_im, 0480, fff8, CF_ISA_A); | |
3630 | INSN(arith_im, 0400, ff00, M68000); | |
3631 | INSN(undef, 04c0, ffc0, M68000); | |
3632 | INSN(arith_im, 0600, ff00, M68000); | |
3633 | INSN(undef, 06c0, ffc0, M68000); | |
3634 | INSN(ff1, 04c0, fff8, CF_ISA_APLUSC); | |
3635 | INSN(arith_im, 0680, fff8, CF_ISA_A); | |
3636 | INSN(arith_im, 0c00, ff38, CF_ISA_A); | |
3637 | INSN(arith_im, 0c00, ff00, M68000); | |
3638 | BASE(bitop_im, 0800, ffc0); | |
3639 | BASE(bitop_im, 0840, ffc0); | |
3640 | BASE(bitop_im, 0880, ffc0); | |
3641 | BASE(bitop_im, 08c0, ffc0); | |
3642 | INSN(arith_im, 0a80, fff8, CF_ISA_A); | |
3643 | INSN(arith_im, 0a00, ff00, M68000); | |
3644 | BASE(move, 1000, f000); | |
3645 | BASE(move, 2000, f000); | |
3646 | BASE(move, 3000, f000); | |
3647 | INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC); | |
3648 | INSN(negx, 4080, fff8, CF_ISA_A); | |
3649 | INSN(negx, 4000, ff00, M68000); | |
3650 | INSN(undef, 40c0, ffc0, M68000); | |
3651 | INSN(move_from_sr, 40c0, fff8, CF_ISA_A); | |
3652 | INSN(move_from_sr, 40c0, ffc0, M68000); | |
3653 | BASE(lea, 41c0, f1c0); | |
3654 | BASE(clr, 4200, ff00); | |
3655 | BASE(undef, 42c0, ffc0); | |
3656 | INSN(move_from_ccr, 42c0, fff8, CF_ISA_A); | |
3657 | INSN(move_from_ccr, 42c0, ffc0, M68000); | |
3658 | INSN(neg, 4480, fff8, CF_ISA_A); | |
3659 | INSN(neg, 4400, ff00, M68000); | |
3660 | INSN(undef, 44c0, ffc0, M68000); | |
3661 | BASE(move_to_ccr, 44c0, ffc0); | |
3662 | INSN(not, 4680, fff8, CF_ISA_A); | |
3663 | INSN(not, 4600, ff00, M68000); | |
3664 | INSN(undef, 46c0, ffc0, M68000); | |
3665 | INSN(move_to_sr, 46c0, ffc0, CF_ISA_A); | |
3666 | INSN(nbcd, 4800, ffc0, M68000); | |
3667 | INSN(linkl, 4808, fff8, M68000); | |
3668 | BASE(pea, 4840, ffc0); | |
3669 | BASE(swap, 4840, fff8); | |
3670 | INSN(bkpt, 4848, fff8, BKPT); | |
3671 | BASE(movem, 48c0, fbc0); | |
3672 | BASE(ext, 4880, fff8); | |
3673 | BASE(ext, 48c0, fff8); | |
3674 | BASE(ext, 49c0, fff8); | |
3675 | BASE(tst, 4a00, ff00); | |
3676 | INSN(tas, 4ac0, ffc0, CF_ISA_B); | |
3677 | INSN(tas, 4ac0, ffc0, M68000); | |
3678 | INSN(halt, 4ac8, ffff, CF_ISA_A); | |
3679 | INSN(pulse, 4acc, ffff, CF_ISA_A); | |
3680 | BASE(illegal, 4afc, ffff); | |
3681 | INSN(mull, 4c00, ffc0, CF_ISA_A); | |
3682 | INSN(mull, 4c00, ffc0, LONG_MULDIV); | |
3683 | INSN(divl, 4c40, ffc0, CF_ISA_A); | |
3684 | INSN(divl, 4c40, ffc0, LONG_MULDIV); | |
3685 | INSN(sats, 4c80, fff8, CF_ISA_B); | |
3686 | BASE(trap, 4e40, fff0); | |
3687 | BASE(link, 4e50, fff8); | |
3688 | BASE(unlk, 4e58, fff8); | |
3689 | INSN(move_to_usp, 4e60, fff8, USP); | |
3690 | INSN(move_from_usp, 4e68, fff8, USP); | |
3691 | BASE(nop, 4e71, ffff); | |
3692 | BASE(stop, 4e72, ffff); | |
3693 | BASE(rte, 4e73, ffff); | |
3694 | BASE(rts, 4e75, ffff); | |
3695 | INSN(movec, 4e7b, ffff, CF_ISA_A); | |
3696 | BASE(jump, 4e80, ffc0); | |
3697 | BASE(jump, 4ec0, ffc0); | |
3698 | INSN(addsubq, 5000, f080, M68000); | |
3699 | BASE(addsubq, 5080, f0c0); | |
3700 | INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ | |
3701 | INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */ | |
3702 | INSN(dbcc, 50c8, f0f8, M68000); | |
3703 | INSN(tpf, 51f8, fff8, CF_ISA_A); | |
3704 | ||
3705 | /* Branch instructions. */ | |
3706 | BASE(branch, 6000, f000); | |
3707 | /* Disable long branch instructions, then add back the ones we want. */ | |
3708 | BASE(undef, 60ff, f0ff); /* All long branches. */ | |
3709 | INSN(branch, 60ff, f0ff, CF_ISA_B); | |
3710 | INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */ | |
3711 | INSN(branch, 60ff, ffff, BRAL); | |
3712 | INSN(branch, 60ff, f0ff, BCCL); | |
3713 | ||
3714 | BASE(moveq, 7000, f100); | |
3715 | INSN(mvzs, 7100, f100, CF_ISA_B); | |
3716 | BASE(or, 8000, f000); | |
3717 | BASE(divw, 80c0, f0c0); | |
3718 | INSN(sbcd_reg, 8100, f1f8, M68000); | |
3719 | INSN(sbcd_mem, 8108, f1f8, M68000); | |
3720 | BASE(addsub, 9000, f000); | |
3721 | INSN(undef, 90c0, f0c0, CF_ISA_A); | |
3722 | INSN(subx_reg, 9180, f1f8, CF_ISA_A); | |
3723 | INSN(subx_reg, 9100, f138, M68000); | |
3724 | INSN(subx_mem, 9108, f138, M68000); | |
3725 | INSN(suba, 91c0, f1c0, CF_ISA_A); | |
3726 | INSN(suba, 90c0, f0c0, M68000); | |
3727 | ||
3728 | BASE(undef_mac, a000, f000); | |
3729 | INSN(mac, a000, f100, CF_EMAC); | |
3730 | INSN(from_mac, a180, f9b0, CF_EMAC); | |
3731 | INSN(move_mac, a110, f9fc, CF_EMAC); | |
3732 | INSN(from_macsr,a980, f9f0, CF_EMAC); | |
3733 | INSN(from_mask, ad80, fff0, CF_EMAC); | |
3734 | INSN(from_mext, ab80, fbf0, CF_EMAC); | |
3735 | INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC); | |
3736 | INSN(to_mac, a100, f9c0, CF_EMAC); | |
3737 | INSN(to_macsr, a900, ffc0, CF_EMAC); | |
3738 | INSN(to_mext, ab00, fbc0, CF_EMAC); | |
3739 | INSN(to_mask, ad00, ffc0, CF_EMAC); | |
3740 | ||
3741 | INSN(mov3q, a140, f1c0, CF_ISA_B); | |
3742 | INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */ | |
3743 | INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */ | |
3744 | INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */ | |
3745 | INSN(cmp, b080, f1c0, CF_ISA_A); | |
3746 | INSN(cmpa, b1c0, f1c0, CF_ISA_A); | |
3747 | INSN(cmp, b000, f100, M68000); | |
3748 | INSN(eor, b100, f100, M68000); | |
3749 | INSN(cmpm, b108, f138, M68000); | |
3750 | INSN(cmpa, b0c0, f0c0, M68000); | |
3751 | INSN(eor, b180, f1c0, CF_ISA_A); | |
3752 | BASE(and, c000, f000); | |
3753 | INSN(exg_dd, c140, f1f8, M68000); | |
3754 | INSN(exg_aa, c148, f1f8, M68000); | |
3755 | INSN(exg_da, c188, f1f8, M68000); | |
3756 | BASE(mulw, c0c0, f0c0); | |
3757 | INSN(abcd_reg, c100, f1f8, M68000); | |
3758 | INSN(abcd_mem, c108, f1f8, M68000); | |
3759 | BASE(addsub, d000, f000); | |
3760 | INSN(undef, d0c0, f0c0, CF_ISA_A); | |
3761 | INSN(addx_reg, d180, f1f8, CF_ISA_A); | |
3762 | INSN(addx_reg, d100, f138, M68000); | |
3763 | INSN(addx_mem, d108, f138, M68000); | |
3764 | INSN(adda, d1c0, f1c0, CF_ISA_A); | |
3765 | INSN(adda, d0c0, f0c0, M68000); | |
3766 | INSN(shift_im, e080, f0f0, CF_ISA_A); | |
3767 | INSN(shift_reg, e0a0, f0f0, CF_ISA_A); | |
3768 | INSN(undef_fpu, f000, f000, CF_ISA_A); | |
3769 | INSN(fpu, f200, ffc0, CF_FPU); | |
3770 | INSN(fbcc, f280, ffc0, CF_FPU); | |
3771 | INSN(frestore, f340, ffc0, CF_FPU); | |
3772 | INSN(fsave, f340, ffc0, CF_FPU); | |
3773 | INSN(intouch, f340, ffc0, CF_ISA_A); | |
3774 | INSN(cpushl, f428, ff38, CF_ISA_A); | |
3775 | INSN(wddata, fb00, ff00, CF_ISA_A); | |
3776 | INSN(wdebug, fbc0, ffc0, CF_ISA_A); | |
3777 | #undef INSN | |
3778 | } | |
3779 | ||
3780 | /* ??? Some of this implementation is not exception safe. We should always | |
3781 | write back the result to memory before setting the condition codes. */ | |
3782 | static void disas_m68k_insn(CPUM68KState * env, DisasContext *s) | |
3783 | { | |
3784 | uint16_t insn = read_im16(env, s); | |
3785 | opcode_table[insn](env, s, insn); | |
3786 | do_writebacks(s); | |
3787 | } | |
3788 | ||
3789 | /* generate intermediate code for basic block 'tb'. */ | |
3790 | void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb) | |
3791 | { | |
3792 | M68kCPU *cpu = m68k_env_get_cpu(env); | |
3793 | CPUState *cs = CPU(cpu); | |
3794 | DisasContext dc1, *dc = &dc1; | |
3795 | target_ulong pc_start; | |
3796 | int pc_offset; | |
3797 | int num_insns; | |
3798 | int max_insns; | |
3799 | ||
3800 | /* generate intermediate code */ | |
3801 | pc_start = tb->pc; | |
3802 | ||
3803 | dc->tb = tb; | |
3804 | ||
3805 | dc->env = env; | |
3806 | dc->is_jmp = DISAS_NEXT; | |
3807 | dc->pc = pc_start; | |
3808 | dc->cc_op = CC_OP_DYNAMIC; | |
3809 | dc->cc_op_synced = 1; | |
3810 | dc->singlestep_enabled = cs->singlestep_enabled; | |
3811 | dc->fpcr = env->fpcr; | |
3812 | dc->user = (env->sr & SR_S) == 0; | |
3813 | dc->done_mac = 0; | |
3814 | dc->writeback_mask = 0; | |
3815 | num_insns = 0; | |
3816 | max_insns = tb->cflags & CF_COUNT_MASK; | |
3817 | if (max_insns == 0) { | |
3818 | max_insns = CF_COUNT_MASK; | |
3819 | } | |
3820 | if (max_insns > TCG_MAX_INSNS) { | |
3821 | max_insns = TCG_MAX_INSNS; | |
3822 | } | |
3823 | ||
3824 | gen_tb_start(tb); | |
3825 | do { | |
3826 | pc_offset = dc->pc - pc_start; | |
3827 | gen_throws_exception = NULL; | |
3828 | tcg_gen_insn_start(dc->pc, dc->cc_op); | |
3829 | num_insns++; | |
3830 | ||
3831 | if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { | |
3832 | gen_exception(dc, dc->pc, EXCP_DEBUG); | |
3833 | dc->is_jmp = DISAS_JUMP; | |
3834 | /* The address covered by the breakpoint must be included in | |
3835 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
3836 | properly cleared -- thus we increment the PC here so that | |
3837 | the logic setting tb->size below does the right thing. */ | |
3838 | dc->pc += 2; | |
3839 | break; | |
3840 | } | |
3841 | ||
3842 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { | |
3843 | gen_io_start(); | |
3844 | } | |
3845 | ||
3846 | dc->insn_pc = dc->pc; | |
3847 | disas_m68k_insn(env, dc); | |
3848 | } while (!dc->is_jmp && !tcg_op_buf_full() && | |
3849 | !cs->singlestep_enabled && | |
3850 | !singlestep && | |
3851 | (pc_offset) < (TARGET_PAGE_SIZE - 32) && | |
3852 | num_insns < max_insns); | |
3853 | ||
3854 | if (tb->cflags & CF_LAST_IO) | |
3855 | gen_io_end(); | |
3856 | if (unlikely(cs->singlestep_enabled)) { | |
3857 | /* Make sure the pc is updated, and raise a debug exception. */ | |
3858 | if (!dc->is_jmp) { | |
3859 | update_cc_op(dc); | |
3860 | tcg_gen_movi_i32(QREG_PC, dc->pc); | |
3861 | } | |
3862 | gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG)); | |
3863 | } else { | |
3864 | switch(dc->is_jmp) { | |
3865 | case DISAS_NEXT: | |
3866 | update_cc_op(dc); | |
3867 | gen_jmp_tb(dc, 0, dc->pc); | |
3868 | break; | |
3869 | default: | |
3870 | case DISAS_JUMP: | |
3871 | case DISAS_UPDATE: | |
3872 | update_cc_op(dc); | |
3873 | /* indicate that the hash table must be used to find the next TB */ | |
3874 | tcg_gen_exit_tb(0); | |
3875 | break; | |
3876 | case DISAS_TB_JUMP: | |
3877 | /* nothing more to generate */ | |
3878 | break; | |
3879 | } | |
3880 | } | |
3881 | gen_tb_end(tb, num_insns); | |
3882 | ||
3883 | #ifdef DEBUG_DISAS | |
3884 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) | |
3885 | && qemu_log_in_addr_range(pc_start)) { | |
3886 | qemu_log_lock(); | |
3887 | qemu_log("----------------\n"); | |
3888 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
3889 | log_target_disas(cs, pc_start, dc->pc - pc_start, 0); | |
3890 | qemu_log("\n"); | |
3891 | qemu_log_unlock(); | |
3892 | } | |
3893 | #endif | |
3894 | tb->size = dc->pc - pc_start; | |
3895 | tb->icount = num_insns; | |
3896 | } | |
3897 | ||
3898 | void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, | |
3899 | int flags) | |
3900 | { | |
3901 | M68kCPU *cpu = M68K_CPU(cs); | |
3902 | CPUM68KState *env = &cpu->env; | |
3903 | int i; | |
3904 | uint16_t sr; | |
3905 | CPU_DoubleU u; | |
3906 | for (i = 0; i < 8; i++) | |
3907 | { | |
3908 | u.d = env->fregs[i]; | |
3909 | cpu_fprintf(f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n", | |
3910 | i, env->dregs[i], i, env->aregs[i], | |
3911 | i, u.l.upper, u.l.lower, *(double *)&u.d); | |
3912 | } | |
3913 | cpu_fprintf (f, "PC = %08x ", env->pc); | |
3914 | sr = env->sr | cpu_m68k_get_ccr(env); | |
3915 | cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-', | |
3916 | (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-', | |
3917 | (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-'); | |
3918 | cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result); | |
3919 | } | |
3920 | ||
3921 | void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, | |
3922 | target_ulong *data) | |
3923 | { | |
3924 | int cc_op = data[1]; | |
3925 | env->pc = data[0]; | |
3926 | if (cc_op != CC_OP_DYNAMIC) { | |
3927 | env->cc_op = cc_op; | |
3928 | } | |
3929 | } |