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1 | /* | |
2 | * PowerPC emulation for qemu: main translation routines. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
22 | #include "cpu.h" | |
23 | #include "internal.h" | |
24 | #include "disas/disas.h" | |
25 | #include "exec/exec-all.h" | |
26 | #include "tcg/tcg-op.h" | |
27 | #include "tcg/tcg-op-gvec.h" | |
28 | #include "qemu/host-utils.h" | |
29 | ||
30 | #include "exec/helper-proto.h" | |
31 | #include "exec/helper-gen.h" | |
32 | ||
33 | #include "exec/translator.h" | |
34 | #include "exec/log.h" | |
35 | #include "qemu/atomic128.h" | |
36 | #include "spr_common.h" | |
37 | #include "power8-pmu.h" | |
38 | ||
39 | #include "qemu/qemu-print.h" | |
40 | #include "qapi/error.h" | |
41 | ||
42 | #define HELPER_H "helper.h" | |
43 | #include "exec/helper-info.c.inc" | |
44 | #undef HELPER_H | |
45 | ||
46 | #define CPU_SINGLE_STEP 0x1 | |
47 | #define CPU_BRANCH_STEP 0x2 | |
48 | ||
49 | /* Include definitions for instructions classes and implementations flags */ | |
50 | /* #define PPC_DEBUG_DISAS */ | |
51 | ||
52 | #ifdef PPC_DEBUG_DISAS | |
53 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) | |
54 | #else | |
55 | # define LOG_DISAS(...) do { } while (0) | |
56 | #endif | |
57 | /*****************************************************************************/ | |
58 | /* Code translation helpers */ | |
59 | ||
60 | /* global register indexes */ | |
61 | static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ | |
62 | + 10 * 4 + 22 * 5 /* SPE GPRh */ | |
63 | + 8 * 5 /* CRF */]; | |
64 | static TCGv cpu_gpr[32]; | |
65 | static TCGv cpu_gprh[32]; | |
66 | static TCGv_i32 cpu_crf[8]; | |
67 | static TCGv cpu_nip; | |
68 | static TCGv cpu_msr; | |
69 | static TCGv cpu_ctr; | |
70 | static TCGv cpu_lr; | |
71 | #if defined(TARGET_PPC64) | |
72 | static TCGv cpu_cfar; | |
73 | #endif | |
74 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; | |
75 | static TCGv cpu_reserve; | |
76 | static TCGv cpu_reserve_length; | |
77 | static TCGv cpu_reserve_val; | |
78 | #if defined(TARGET_PPC64) | |
79 | static TCGv cpu_reserve_val2; | |
80 | #endif | |
81 | static TCGv cpu_fpscr; | |
82 | static TCGv_i32 cpu_access_type; | |
83 | ||
84 | void ppc_translate_init(void) | |
85 | { | |
86 | int i; | |
87 | char *p; | |
88 | size_t cpu_reg_names_size; | |
89 | ||
90 | p = cpu_reg_names; | |
91 | cpu_reg_names_size = sizeof(cpu_reg_names); | |
92 | ||
93 | for (i = 0; i < 8; i++) { | |
94 | snprintf(p, cpu_reg_names_size, "crf%d", i); | |
95 | cpu_crf[i] = tcg_global_mem_new_i32(tcg_env, | |
96 | offsetof(CPUPPCState, crf[i]), p); | |
97 | p += 5; | |
98 | cpu_reg_names_size -= 5; | |
99 | } | |
100 | ||
101 | for (i = 0; i < 32; i++) { | |
102 | snprintf(p, cpu_reg_names_size, "r%d", i); | |
103 | cpu_gpr[i] = tcg_global_mem_new(tcg_env, | |
104 | offsetof(CPUPPCState, gpr[i]), p); | |
105 | p += (i < 10) ? 3 : 4; | |
106 | cpu_reg_names_size -= (i < 10) ? 3 : 4; | |
107 | snprintf(p, cpu_reg_names_size, "r%dH", i); | |
108 | cpu_gprh[i] = tcg_global_mem_new(tcg_env, | |
109 | offsetof(CPUPPCState, gprh[i]), p); | |
110 | p += (i < 10) ? 4 : 5; | |
111 | cpu_reg_names_size -= (i < 10) ? 4 : 5; | |
112 | } | |
113 | ||
114 | cpu_nip = tcg_global_mem_new(tcg_env, | |
115 | offsetof(CPUPPCState, nip), "nip"); | |
116 | ||
117 | cpu_msr = tcg_global_mem_new(tcg_env, | |
118 | offsetof(CPUPPCState, msr), "msr"); | |
119 | ||
120 | cpu_ctr = tcg_global_mem_new(tcg_env, | |
121 | offsetof(CPUPPCState, ctr), "ctr"); | |
122 | ||
123 | cpu_lr = tcg_global_mem_new(tcg_env, | |
124 | offsetof(CPUPPCState, lr), "lr"); | |
125 | ||
126 | #if defined(TARGET_PPC64) | |
127 | cpu_cfar = tcg_global_mem_new(tcg_env, | |
128 | offsetof(CPUPPCState, cfar), "cfar"); | |
129 | #endif | |
130 | ||
131 | cpu_xer = tcg_global_mem_new(tcg_env, | |
132 | offsetof(CPUPPCState, xer), "xer"); | |
133 | cpu_so = tcg_global_mem_new(tcg_env, | |
134 | offsetof(CPUPPCState, so), "SO"); | |
135 | cpu_ov = tcg_global_mem_new(tcg_env, | |
136 | offsetof(CPUPPCState, ov), "OV"); | |
137 | cpu_ca = tcg_global_mem_new(tcg_env, | |
138 | offsetof(CPUPPCState, ca), "CA"); | |
139 | cpu_ov32 = tcg_global_mem_new(tcg_env, | |
140 | offsetof(CPUPPCState, ov32), "OV32"); | |
141 | cpu_ca32 = tcg_global_mem_new(tcg_env, | |
142 | offsetof(CPUPPCState, ca32), "CA32"); | |
143 | ||
144 | cpu_reserve = tcg_global_mem_new(tcg_env, | |
145 | offsetof(CPUPPCState, reserve_addr), | |
146 | "reserve_addr"); | |
147 | cpu_reserve_length = tcg_global_mem_new(tcg_env, | |
148 | offsetof(CPUPPCState, | |
149 | reserve_length), | |
150 | "reserve_length"); | |
151 | cpu_reserve_val = tcg_global_mem_new(tcg_env, | |
152 | offsetof(CPUPPCState, reserve_val), | |
153 | "reserve_val"); | |
154 | #if defined(TARGET_PPC64) | |
155 | cpu_reserve_val2 = tcg_global_mem_new(tcg_env, | |
156 | offsetof(CPUPPCState, reserve_val2), | |
157 | "reserve_val2"); | |
158 | #endif | |
159 | ||
160 | cpu_fpscr = tcg_global_mem_new(tcg_env, | |
161 | offsetof(CPUPPCState, fpscr), "fpscr"); | |
162 | ||
163 | cpu_access_type = tcg_global_mem_new_i32(tcg_env, | |
164 | offsetof(CPUPPCState, access_type), | |
165 | "access_type"); | |
166 | } | |
167 | ||
168 | /* internal defines */ | |
169 | struct DisasContext { | |
170 | DisasContextBase base; | |
171 | target_ulong cia; /* current instruction address */ | |
172 | uint32_t opcode; | |
173 | /* Routine used to access memory */ | |
174 | bool pr, hv, dr, le_mode; | |
175 | bool lazy_tlb_flush; | |
176 | bool need_access_type; | |
177 | int mem_idx; | |
178 | int access_type; | |
179 | /* Translation flags */ | |
180 | MemOp default_tcg_memop_mask; | |
181 | #if defined(TARGET_PPC64) | |
182 | bool sf_mode; | |
183 | bool has_cfar; | |
184 | #endif | |
185 | bool fpu_enabled; | |
186 | bool altivec_enabled; | |
187 | bool vsx_enabled; | |
188 | bool spe_enabled; | |
189 | bool tm_enabled; | |
190 | bool gtse; | |
191 | bool hr; | |
192 | bool mmcr0_pmcc0; | |
193 | bool mmcr0_pmcc1; | |
194 | bool mmcr0_pmcjce; | |
195 | bool pmc_other; | |
196 | bool pmu_insn_cnt; | |
197 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ | |
198 | int singlestep_enabled; | |
199 | uint32_t flags; | |
200 | uint64_t insns_flags; | |
201 | uint64_t insns_flags2; | |
202 | }; | |
203 | ||
204 | #define DISAS_EXIT DISAS_TARGET_0 /* exit to main loop, pc updated */ | |
205 | #define DISAS_EXIT_UPDATE DISAS_TARGET_1 /* exit to main loop, pc stale */ | |
206 | #define DISAS_CHAIN DISAS_TARGET_2 /* lookup next tb, pc updated */ | |
207 | #define DISAS_CHAIN_UPDATE DISAS_TARGET_3 /* lookup next tb, pc stale */ | |
208 | ||
209 | /* Return true iff byteswap is needed in a scalar memop */ | |
210 | static inline bool need_byteswap(const DisasContext *ctx) | |
211 | { | |
212 | #if TARGET_BIG_ENDIAN | |
213 | return ctx->le_mode; | |
214 | #else | |
215 | return !ctx->le_mode; | |
216 | #endif | |
217 | } | |
218 | ||
219 | /* True when active word size < size of target_long. */ | |
220 | #ifdef TARGET_PPC64 | |
221 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
222 | #else | |
223 | # define NARROW_MODE(C) 0 | |
224 | #endif | |
225 | ||
226 | struct opc_handler_t { | |
227 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ | |
228 | uint32_t inval1; | |
229 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
230 | uint32_t inval2; | |
231 | /* instruction type */ | |
232 | uint64_t type; | |
233 | /* extended instruction type */ | |
234 | uint64_t type2; | |
235 | /* handler */ | |
236 | void (*handler)(DisasContext *ctx); | |
237 | }; | |
238 | ||
239 | static inline bool gen_serialize(DisasContext *ctx) | |
240 | { | |
241 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
242 | /* Restart with exclusive lock. */ | |
243 | gen_helper_exit_atomic(tcg_env); | |
244 | ctx->base.is_jmp = DISAS_NORETURN; | |
245 | return false; | |
246 | } | |
247 | return true; | |
248 | } | |
249 | ||
250 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
251 | static inline bool gen_serialize_core_lpar(DisasContext *ctx) | |
252 | { | |
253 | if (ctx->flags & POWERPC_FLAG_SMT_1LPAR) { | |
254 | return gen_serialize(ctx); | |
255 | } | |
256 | ||
257 | return true; | |
258 | } | |
259 | #endif | |
260 | ||
261 | /* SPR load/store helpers */ | |
262 | static inline void gen_load_spr(TCGv t, int reg) | |
263 | { | |
264 | tcg_gen_ld_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); | |
265 | } | |
266 | ||
267 | static inline void gen_store_spr(int reg, TCGv t) | |
268 | { | |
269 | tcg_gen_st_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); | |
270 | } | |
271 | ||
272 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) | |
273 | { | |
274 | if (ctx->need_access_type && ctx->access_type != access_type) { | |
275 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
276 | ctx->access_type = access_type; | |
277 | } | |
278 | } | |
279 | ||
280 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) | |
281 | { | |
282 | if (NARROW_MODE(ctx)) { | |
283 | nip = (uint32_t)nip; | |
284 | } | |
285 | tcg_gen_movi_tl(cpu_nip, nip); | |
286 | } | |
287 | ||
288 | static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) | |
289 | { | |
290 | TCGv_i32 t0, t1; | |
291 | ||
292 | /* | |
293 | * These are all synchronous exceptions, we set the PC back to the | |
294 | * faulting instruction | |
295 | */ | |
296 | gen_update_nip(ctx, ctx->cia); | |
297 | t0 = tcg_constant_i32(excp); | |
298 | t1 = tcg_constant_i32(error); | |
299 | gen_helper_raise_exception_err(tcg_env, t0, t1); | |
300 | ctx->base.is_jmp = DISAS_NORETURN; | |
301 | } | |
302 | ||
303 | static void gen_exception(DisasContext *ctx, uint32_t excp) | |
304 | { | |
305 | TCGv_i32 t0; | |
306 | ||
307 | /* | |
308 | * These are all synchronous exceptions, we set the PC back to the | |
309 | * faulting instruction | |
310 | */ | |
311 | gen_update_nip(ctx, ctx->cia); | |
312 | t0 = tcg_constant_i32(excp); | |
313 | gen_helper_raise_exception(tcg_env, t0); | |
314 | ctx->base.is_jmp = DISAS_NORETURN; | |
315 | } | |
316 | ||
317 | static void gen_exception_nip(DisasContext *ctx, uint32_t excp, | |
318 | target_ulong nip) | |
319 | { | |
320 | TCGv_i32 t0; | |
321 | ||
322 | gen_update_nip(ctx, nip); | |
323 | t0 = tcg_constant_i32(excp); | |
324 | gen_helper_raise_exception(tcg_env, t0); | |
325 | ctx->base.is_jmp = DISAS_NORETURN; | |
326 | } | |
327 | ||
328 | #if !defined(CONFIG_USER_ONLY) | |
329 | static void gen_ppc_maybe_interrupt(DisasContext *ctx) | |
330 | { | |
331 | translator_io_start(&ctx->base); | |
332 | gen_helper_ppc_maybe_interrupt(tcg_env); | |
333 | } | |
334 | #endif | |
335 | ||
336 | /* | |
337 | * Tells the caller what is the appropriate exception to generate and prepares | |
338 | * SPR registers for this exception. | |
339 | * | |
340 | * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or | |
341 | * POWERPC_EXCP_DEBUG (on BookE). | |
342 | */ | |
343 | static void gen_debug_exception(DisasContext *ctx, bool rfi_type) | |
344 | { | |
345 | #if !defined(CONFIG_USER_ONLY) | |
346 | if (ctx->flags & POWERPC_FLAG_DE) { | |
347 | target_ulong dbsr = 0; | |
348 | if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { | |
349 | dbsr = DBCR0_ICMP; | |
350 | } else { | |
351 | /* Must have been branch */ | |
352 | dbsr = DBCR0_BRT; | |
353 | } | |
354 | TCGv t0 = tcg_temp_new(); | |
355 | gen_load_spr(t0, SPR_BOOKE_DBSR); | |
356 | tcg_gen_ori_tl(t0, t0, dbsr); | |
357 | gen_store_spr(SPR_BOOKE_DBSR, t0); | |
358 | gen_helper_raise_exception(tcg_env, | |
359 | tcg_constant_i32(POWERPC_EXCP_DEBUG)); | |
360 | ctx->base.is_jmp = DISAS_NORETURN; | |
361 | } else { | |
362 | if (!rfi_type) { /* BookS does not single step rfi type instructions */ | |
363 | TCGv t0 = tcg_temp_new(); | |
364 | tcg_gen_movi_tl(t0, ctx->cia); | |
365 | gen_helper_book3s_trace(tcg_env, t0); | |
366 | ctx->base.is_jmp = DISAS_NORETURN; | |
367 | } | |
368 | } | |
369 | #endif | |
370 | } | |
371 | ||
372 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) | |
373 | { | |
374 | /* Will be converted to program check if needed */ | |
375 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); | |
376 | } | |
377 | ||
378 | static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) | |
379 | { | |
380 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); | |
381 | } | |
382 | ||
383 | static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) | |
384 | { | |
385 | /* Will be converted to program check if needed */ | |
386 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); | |
387 | } | |
388 | ||
389 | /*****************************************************************************/ | |
390 | /* SPR READ/WRITE CALLBACKS */ | |
391 | ||
392 | void spr_noaccess(DisasContext *ctx, int gprn, int sprn) | |
393 | { | |
394 | #if 0 | |
395 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
396 | printf("ERROR: try to access SPR %d !\n", sprn); | |
397 | #endif | |
398 | } | |
399 | ||
400 | /* #define PPC_DUMP_SPR_ACCESSES */ | |
401 | ||
402 | /* | |
403 | * Generic callbacks: | |
404 | * do nothing but store/retrieve spr value | |
405 | */ | |
406 | static void spr_load_dump_spr(int sprn) | |
407 | { | |
408 | #ifdef PPC_DUMP_SPR_ACCESSES | |
409 | TCGv_i32 t0 = tcg_constant_i32(sprn); | |
410 | gen_helper_load_dump_spr(tcg_env, t0); | |
411 | #endif | |
412 | } | |
413 | ||
414 | void spr_read_generic(DisasContext *ctx, int gprn, int sprn) | |
415 | { | |
416 | gen_load_spr(cpu_gpr[gprn], sprn); | |
417 | spr_load_dump_spr(sprn); | |
418 | } | |
419 | ||
420 | static void spr_store_dump_spr(int sprn) | |
421 | { | |
422 | #ifdef PPC_DUMP_SPR_ACCESSES | |
423 | TCGv_i32 t0 = tcg_constant_i32(sprn); | |
424 | gen_helper_store_dump_spr(tcg_env, t0); | |
425 | #endif | |
426 | } | |
427 | ||
428 | void spr_write_generic(DisasContext *ctx, int sprn, int gprn) | |
429 | { | |
430 | gen_store_spr(sprn, cpu_gpr[gprn]); | |
431 | spr_store_dump_spr(sprn); | |
432 | } | |
433 | ||
434 | void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) | |
435 | { | |
436 | #ifdef TARGET_PPC64 | |
437 | TCGv t0 = tcg_temp_new(); | |
438 | tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); | |
439 | gen_store_spr(sprn, t0); | |
440 | spr_store_dump_spr(sprn); | |
441 | #else | |
442 | spr_write_generic(ctx, sprn, gprn); | |
443 | #endif | |
444 | } | |
445 | ||
446 | void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn) | |
447 | { | |
448 | if (!(ctx->flags & POWERPC_FLAG_SMT)) { | |
449 | spr_write_generic(ctx, sprn, gprn); | |
450 | return; | |
451 | } | |
452 | ||
453 | if (!gen_serialize(ctx)) { | |
454 | return; | |
455 | } | |
456 | ||
457 | gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), | |
458 | cpu_gpr[gprn]); | |
459 | spr_store_dump_spr(sprn); | |
460 | } | |
461 | ||
462 | static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn) | |
463 | { | |
464 | /* This does not implement >1 thread */ | |
465 | TCGv t0 = tcg_temp_new(); | |
466 | TCGv t1 = tcg_temp_new(); | |
467 | tcg_gen_extract_tl(t0, cpu_gpr[gprn], 0, 1); /* Extract RUN field */ | |
468 | tcg_gen_shli_tl(t1, t0, 8); /* Duplicate the bit in TS */ | |
469 | tcg_gen_or_tl(t1, t1, t0); | |
470 | gen_store_spr(sprn, t1); | |
471 | } | |
472 | ||
473 | void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn) | |
474 | { | |
475 | if (!(ctx->flags & POWERPC_FLAG_SMT_1LPAR)) { | |
476 | /* CTRL behaves as 1-thread in LPAR-per-thread mode */ | |
477 | spr_write_CTRL_ST(ctx, sprn, gprn); | |
478 | goto out; | |
479 | } | |
480 | ||
481 | if (!gen_serialize(ctx)) { | |
482 | return; | |
483 | } | |
484 | ||
485 | gen_helper_spr_write_CTRL(tcg_env, tcg_constant_i32(sprn), | |
486 | cpu_gpr[gprn]); | |
487 | out: | |
488 | spr_store_dump_spr(sprn); | |
489 | ||
490 | /* | |
491 | * SPR_CTRL writes must force a new translation block, | |
492 | * allowing the PMU to calculate the run latch events with | |
493 | * more accuracy. | |
494 | */ | |
495 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
496 | } | |
497 | ||
498 | #if !defined(CONFIG_USER_ONLY) | |
499 | void spr_write_clear(DisasContext *ctx, int sprn, int gprn) | |
500 | { | |
501 | TCGv t0 = tcg_temp_new(); | |
502 | TCGv t1 = tcg_temp_new(); | |
503 | gen_load_spr(t0, sprn); | |
504 | tcg_gen_neg_tl(t1, cpu_gpr[gprn]); | |
505 | tcg_gen_and_tl(t0, t0, t1); | |
506 | gen_store_spr(sprn, t0); | |
507 | } | |
508 | ||
509 | void spr_access_nop(DisasContext *ctx, int sprn, int gprn) | |
510 | { | |
511 | } | |
512 | ||
513 | #endif | |
514 | ||
515 | /* SPR common to all PowerPC */ | |
516 | /* XER */ | |
517 | void spr_read_xer(DisasContext *ctx, int gprn, int sprn) | |
518 | { | |
519 | TCGv dst = cpu_gpr[gprn]; | |
520 | TCGv t0 = tcg_temp_new(); | |
521 | TCGv t1 = tcg_temp_new(); | |
522 | TCGv t2 = tcg_temp_new(); | |
523 | tcg_gen_mov_tl(dst, cpu_xer); | |
524 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
525 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
526 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
527 | tcg_gen_or_tl(t0, t0, t1); | |
528 | tcg_gen_or_tl(dst, dst, t2); | |
529 | tcg_gen_or_tl(dst, dst, t0); | |
530 | if (is_isa300(ctx)) { | |
531 | tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); | |
532 | tcg_gen_or_tl(dst, dst, t0); | |
533 | tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); | |
534 | tcg_gen_or_tl(dst, dst, t0); | |
535 | } | |
536 | } | |
537 | ||
538 | void spr_write_xer(DisasContext *ctx, int sprn, int gprn) | |
539 | { | |
540 | TCGv src = cpu_gpr[gprn]; | |
541 | /* Write all flags, while reading back check for isa300 */ | |
542 | tcg_gen_andi_tl(cpu_xer, src, | |
543 | ~((1u << XER_SO) | | |
544 | (1u << XER_OV) | (1u << XER_OV32) | | |
545 | (1u << XER_CA) | (1u << XER_CA32))); | |
546 | tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); | |
547 | tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); | |
548 | tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); | |
549 | tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); | |
550 | tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); | |
551 | } | |
552 | ||
553 | /* LR */ | |
554 | void spr_read_lr(DisasContext *ctx, int gprn, int sprn) | |
555 | { | |
556 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); | |
557 | } | |
558 | ||
559 | void spr_write_lr(DisasContext *ctx, int sprn, int gprn) | |
560 | { | |
561 | tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); | |
562 | } | |
563 | ||
564 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
565 | /* Debug facilities */ | |
566 | /* CFAR */ | |
567 | void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) | |
568 | { | |
569 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); | |
570 | } | |
571 | ||
572 | void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) | |
573 | { | |
574 | tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); | |
575 | } | |
576 | ||
577 | /* Breakpoint */ | |
578 | void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) | |
579 | { | |
580 | translator_io_start(&ctx->base); | |
581 | gen_helper_store_ciabr(tcg_env, cpu_gpr[gprn]); | |
582 | } | |
583 | ||
584 | /* Watchpoint */ | |
585 | void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn) | |
586 | { | |
587 | translator_io_start(&ctx->base); | |
588 | gen_helper_store_dawr0(tcg_env, cpu_gpr[gprn]); | |
589 | } | |
590 | ||
591 | void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) | |
592 | { | |
593 | translator_io_start(&ctx->base); | |
594 | gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]); | |
595 | } | |
596 | #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ | |
597 | ||
598 | /* CTR */ | |
599 | void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) | |
600 | { | |
601 | tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); | |
602 | } | |
603 | ||
604 | void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) | |
605 | { | |
606 | tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); | |
607 | } | |
608 | ||
609 | /* User read access to SPR */ | |
610 | /* USPRx */ | |
611 | /* UMMCRx */ | |
612 | /* UPMCx */ | |
613 | /* USIA */ | |
614 | /* UDECR */ | |
615 | void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) | |
616 | { | |
617 | gen_load_spr(cpu_gpr[gprn], sprn + 0x10); | |
618 | } | |
619 | ||
620 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
621 | void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) | |
622 | { | |
623 | gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); | |
624 | } | |
625 | #endif | |
626 | ||
627 | /* SPR common to all non-embedded PowerPC */ | |
628 | /* DECR */ | |
629 | #if !defined(CONFIG_USER_ONLY) | |
630 | void spr_read_decr(DisasContext *ctx, int gprn, int sprn) | |
631 | { | |
632 | translator_io_start(&ctx->base); | |
633 | gen_helper_load_decr(cpu_gpr[gprn], tcg_env); | |
634 | } | |
635 | ||
636 | void spr_write_decr(DisasContext *ctx, int sprn, int gprn) | |
637 | { | |
638 | translator_io_start(&ctx->base); | |
639 | gen_helper_store_decr(tcg_env, cpu_gpr[gprn]); | |
640 | } | |
641 | #endif | |
642 | ||
643 | /* SPR common to all non-embedded PowerPC, except 601 */ | |
644 | /* Time base */ | |
645 | void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) | |
646 | { | |
647 | translator_io_start(&ctx->base); | |
648 | gen_helper_load_tbl(cpu_gpr[gprn], tcg_env); | |
649 | } | |
650 | ||
651 | void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) | |
652 | { | |
653 | translator_io_start(&ctx->base); | |
654 | gen_helper_load_tbu(cpu_gpr[gprn], tcg_env); | |
655 | } | |
656 | ||
657 | void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) | |
658 | { | |
659 | gen_helper_load_atbl(cpu_gpr[gprn], tcg_env); | |
660 | } | |
661 | ||
662 | void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) | |
663 | { | |
664 | gen_helper_load_atbu(cpu_gpr[gprn], tcg_env); | |
665 | } | |
666 | ||
667 | #if !defined(CONFIG_USER_ONLY) | |
668 | void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) | |
669 | { | |
670 | translator_io_start(&ctx->base); | |
671 | gen_helper_store_tbl(tcg_env, cpu_gpr[gprn]); | |
672 | } | |
673 | ||
674 | void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) | |
675 | { | |
676 | translator_io_start(&ctx->base); | |
677 | gen_helper_store_tbu(tcg_env, cpu_gpr[gprn]); | |
678 | } | |
679 | ||
680 | void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) | |
681 | { | |
682 | gen_helper_store_atbl(tcg_env, cpu_gpr[gprn]); | |
683 | } | |
684 | ||
685 | void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) | |
686 | { | |
687 | gen_helper_store_atbu(tcg_env, cpu_gpr[gprn]); | |
688 | } | |
689 | ||
690 | #if defined(TARGET_PPC64) | |
691 | void spr_read_purr(DisasContext *ctx, int gprn, int sprn) | |
692 | { | |
693 | translator_io_start(&ctx->base); | |
694 | gen_helper_load_purr(cpu_gpr[gprn], tcg_env); | |
695 | } | |
696 | ||
697 | void spr_write_purr(DisasContext *ctx, int sprn, int gprn) | |
698 | { | |
699 | translator_io_start(&ctx->base); | |
700 | gen_helper_store_purr(tcg_env, cpu_gpr[gprn]); | |
701 | } | |
702 | ||
703 | /* HDECR */ | |
704 | void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) | |
705 | { | |
706 | translator_io_start(&ctx->base); | |
707 | gen_helper_load_hdecr(cpu_gpr[gprn], tcg_env); | |
708 | } | |
709 | ||
710 | void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) | |
711 | { | |
712 | translator_io_start(&ctx->base); | |
713 | gen_helper_store_hdecr(tcg_env, cpu_gpr[gprn]); | |
714 | } | |
715 | ||
716 | void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) | |
717 | { | |
718 | translator_io_start(&ctx->base); | |
719 | gen_helper_load_vtb(cpu_gpr[gprn], tcg_env); | |
720 | } | |
721 | ||
722 | void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) | |
723 | { | |
724 | translator_io_start(&ctx->base); | |
725 | gen_helper_store_vtb(tcg_env, cpu_gpr[gprn]); | |
726 | } | |
727 | ||
728 | void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) | |
729 | { | |
730 | translator_io_start(&ctx->base); | |
731 | gen_helper_store_tbu40(tcg_env, cpu_gpr[gprn]); | |
732 | } | |
733 | ||
734 | #endif | |
735 | #endif | |
736 | ||
737 | #if !defined(CONFIG_USER_ONLY) | |
738 | /* IBAT0U...IBAT0U */ | |
739 | /* IBAT0L...IBAT7L */ | |
740 | void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) | |
741 | { | |
742 | tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, | |
743 | offsetof(CPUPPCState, | |
744 | IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); | |
745 | } | |
746 | ||
747 | void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) | |
748 | { | |
749 | tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, | |
750 | offsetof(CPUPPCState, | |
751 | IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); | |
752 | } | |
753 | ||
754 | void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) | |
755 | { | |
756 | TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2); | |
757 | gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); | |
758 | } | |
759 | ||
760 | void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) | |
761 | { | |
762 | TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); | |
763 | gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); | |
764 | } | |
765 | ||
766 | void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) | |
767 | { | |
768 | TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2); | |
769 | gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); | |
770 | } | |
771 | ||
772 | void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) | |
773 | { | |
774 | TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); | |
775 | gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); | |
776 | } | |
777 | ||
778 | /* DBAT0U...DBAT7U */ | |
779 | /* DBAT0L...DBAT7L */ | |
780 | void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) | |
781 | { | |
782 | tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, | |
783 | offsetof(CPUPPCState, | |
784 | DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); | |
785 | } | |
786 | ||
787 | void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) | |
788 | { | |
789 | tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, | |
790 | offsetof(CPUPPCState, | |
791 | DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); | |
792 | } | |
793 | ||
794 | void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) | |
795 | { | |
796 | TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2); | |
797 | gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); | |
798 | } | |
799 | ||
800 | void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) | |
801 | { | |
802 | TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); | |
803 | gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); | |
804 | } | |
805 | ||
806 | void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) | |
807 | { | |
808 | TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2); | |
809 | gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); | |
810 | } | |
811 | ||
812 | void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) | |
813 | { | |
814 | TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); | |
815 | gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); | |
816 | } | |
817 | ||
818 | /* SDR1 */ | |
819 | void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) | |
820 | { | |
821 | gen_helper_store_sdr1(tcg_env, cpu_gpr[gprn]); | |
822 | } | |
823 | ||
824 | #if defined(TARGET_PPC64) | |
825 | /* 64 bits PowerPC specific SPRs */ | |
826 | /* PIDR */ | |
827 | void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) | |
828 | { | |
829 | gen_helper_store_pidr(tcg_env, cpu_gpr[gprn]); | |
830 | } | |
831 | ||
832 | void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) | |
833 | { | |
834 | gen_helper_store_lpidr(tcg_env, cpu_gpr[gprn]); | |
835 | } | |
836 | ||
837 | void spr_read_hior(DisasContext *ctx, int gprn, int sprn) | |
838 | { | |
839 | tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, excp_prefix)); | |
840 | } | |
841 | ||
842 | void spr_write_hior(DisasContext *ctx, int sprn, int gprn) | |
843 | { | |
844 | TCGv t0 = tcg_temp_new(); | |
845 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); | |
846 | tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); | |
847 | } | |
848 | void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) | |
849 | { | |
850 | gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]); | |
851 | } | |
852 | ||
853 | void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) | |
854 | { | |
855 | gen_helper_store_pcr(tcg_env, cpu_gpr[gprn]); | |
856 | } | |
857 | ||
858 | /* DPDES */ | |
859 | void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) | |
860 | { | |
861 | if (!gen_serialize_core_lpar(ctx)) { | |
862 | return; | |
863 | } | |
864 | ||
865 | gen_helper_load_dpdes(cpu_gpr[gprn], tcg_env); | |
866 | } | |
867 | ||
868 | void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) | |
869 | { | |
870 | if (!gen_serialize_core_lpar(ctx)) { | |
871 | return; | |
872 | } | |
873 | ||
874 | gen_helper_store_dpdes(tcg_env, cpu_gpr[gprn]); | |
875 | } | |
876 | #endif | |
877 | #endif | |
878 | ||
879 | /* PowerPC 40x specific registers */ | |
880 | #if !defined(CONFIG_USER_ONLY) | |
881 | void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) | |
882 | { | |
883 | translator_io_start(&ctx->base); | |
884 | gen_helper_load_40x_pit(cpu_gpr[gprn], tcg_env); | |
885 | } | |
886 | ||
887 | void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) | |
888 | { | |
889 | translator_io_start(&ctx->base); | |
890 | gen_helper_store_40x_pit(tcg_env, cpu_gpr[gprn]); | |
891 | } | |
892 | ||
893 | void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) | |
894 | { | |
895 | translator_io_start(&ctx->base); | |
896 | gen_store_spr(sprn, cpu_gpr[gprn]); | |
897 | gen_helper_store_40x_dbcr0(tcg_env, cpu_gpr[gprn]); | |
898 | /* We must stop translation as we may have rebooted */ | |
899 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
900 | } | |
901 | ||
902 | void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) | |
903 | { | |
904 | translator_io_start(&ctx->base); | |
905 | gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]); | |
906 | } | |
907 | ||
908 | void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) | |
909 | { | |
910 | translator_io_start(&ctx->base); | |
911 | gen_helper_store_40x_tcr(tcg_env, cpu_gpr[gprn]); | |
912 | } | |
913 | ||
914 | void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) | |
915 | { | |
916 | translator_io_start(&ctx->base); | |
917 | gen_helper_store_40x_tsr(tcg_env, cpu_gpr[gprn]); | |
918 | } | |
919 | ||
920 | void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) | |
921 | { | |
922 | TCGv t0 = tcg_temp_new(); | |
923 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); | |
924 | gen_helper_store_40x_pid(tcg_env, t0); | |
925 | } | |
926 | ||
927 | void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) | |
928 | { | |
929 | translator_io_start(&ctx->base); | |
930 | gen_helper_store_booke_tcr(tcg_env, cpu_gpr[gprn]); | |
931 | } | |
932 | ||
933 | void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) | |
934 | { | |
935 | translator_io_start(&ctx->base); | |
936 | gen_helper_store_booke_tsr(tcg_env, cpu_gpr[gprn]); | |
937 | } | |
938 | #endif | |
939 | ||
940 | /* PIR */ | |
941 | #if !defined(CONFIG_USER_ONLY) | |
942 | void spr_write_pir(DisasContext *ctx, int sprn, int gprn) | |
943 | { | |
944 | TCGv t0 = tcg_temp_new(); | |
945 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); | |
946 | gen_store_spr(SPR_PIR, t0); | |
947 | } | |
948 | #endif | |
949 | ||
950 | /* SPE specific registers */ | |
951 | void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) | |
952 | { | |
953 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
954 | tcg_gen_ld_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); | |
955 | tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); | |
956 | } | |
957 | ||
958 | void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) | |
959 | { | |
960 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
961 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); | |
962 | tcg_gen_st_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); | |
963 | } | |
964 | ||
965 | #if !defined(CONFIG_USER_ONLY) | |
966 | /* Callback used to write the exception vector base */ | |
967 | void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) | |
968 | { | |
969 | TCGv t0 = tcg_temp_new(); | |
970 | tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivpr_mask)); | |
971 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); | |
972 | tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); | |
973 | gen_store_spr(sprn, t0); | |
974 | } | |
975 | ||
976 | void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) | |
977 | { | |
978 | int sprn_offs; | |
979 | ||
980 | if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { | |
981 | sprn_offs = sprn - SPR_BOOKE_IVOR0; | |
982 | } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { | |
983 | sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; | |
984 | } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { | |
985 | sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; | |
986 | } else { | |
987 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception" | |
988 | " vector 0x%03x\n", sprn); | |
989 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
990 | return; | |
991 | } | |
992 | ||
993 | TCGv t0 = tcg_temp_new(); | |
994 | tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivor_mask)); | |
995 | tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); | |
996 | tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); | |
997 | gen_store_spr(sprn, t0); | |
998 | } | |
999 | #endif | |
1000 | ||
1001 | #ifdef TARGET_PPC64 | |
1002 | #ifndef CONFIG_USER_ONLY | |
1003 | void spr_write_amr(DisasContext *ctx, int sprn, int gprn) | |
1004 | { | |
1005 | TCGv t0 = tcg_temp_new(); | |
1006 | TCGv t1 = tcg_temp_new(); | |
1007 | TCGv t2 = tcg_temp_new(); | |
1008 | ||
1009 | /* | |
1010 | * Note, the HV=1 PR=0 case is handled earlier by simply using | |
1011 | * spr_write_generic for HV mode in the SPR table | |
1012 | */ | |
1013 | ||
1014 | /* Build insertion mask into t1 based on context */ | |
1015 | if (ctx->pr) { | |
1016 | gen_load_spr(t1, SPR_UAMOR); | |
1017 | } else { | |
1018 | gen_load_spr(t1, SPR_AMOR); | |
1019 | } | |
1020 | ||
1021 | /* Mask new bits into t2 */ | |
1022 | tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); | |
1023 | ||
1024 | /* Load AMR and clear new bits in t0 */ | |
1025 | gen_load_spr(t0, SPR_AMR); | |
1026 | tcg_gen_andc_tl(t0, t0, t1); | |
1027 | ||
1028 | /* Or'in new bits and write it out */ | |
1029 | tcg_gen_or_tl(t0, t0, t2); | |
1030 | gen_store_spr(SPR_AMR, t0); | |
1031 | spr_store_dump_spr(SPR_AMR); | |
1032 | } | |
1033 | ||
1034 | void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) | |
1035 | { | |
1036 | TCGv t0 = tcg_temp_new(); | |
1037 | TCGv t1 = tcg_temp_new(); | |
1038 | TCGv t2 = tcg_temp_new(); | |
1039 | ||
1040 | /* | |
1041 | * Note, the HV=1 case is handled earlier by simply using | |
1042 | * spr_write_generic for HV mode in the SPR table | |
1043 | */ | |
1044 | ||
1045 | /* Build insertion mask into t1 based on context */ | |
1046 | gen_load_spr(t1, SPR_AMOR); | |
1047 | ||
1048 | /* Mask new bits into t2 */ | |
1049 | tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); | |
1050 | ||
1051 | /* Load AMR and clear new bits in t0 */ | |
1052 | gen_load_spr(t0, SPR_UAMOR); | |
1053 | tcg_gen_andc_tl(t0, t0, t1); | |
1054 | ||
1055 | /* Or'in new bits and write it out */ | |
1056 | tcg_gen_or_tl(t0, t0, t2); | |
1057 | gen_store_spr(SPR_UAMOR, t0); | |
1058 | spr_store_dump_spr(SPR_UAMOR); | |
1059 | } | |
1060 | ||
1061 | void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) | |
1062 | { | |
1063 | TCGv t0 = tcg_temp_new(); | |
1064 | TCGv t1 = tcg_temp_new(); | |
1065 | TCGv t2 = tcg_temp_new(); | |
1066 | ||
1067 | /* | |
1068 | * Note, the HV=1 case is handled earlier by simply using | |
1069 | * spr_write_generic for HV mode in the SPR table | |
1070 | */ | |
1071 | ||
1072 | /* Build insertion mask into t1 based on context */ | |
1073 | gen_load_spr(t1, SPR_AMOR); | |
1074 | ||
1075 | /* Mask new bits into t2 */ | |
1076 | tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); | |
1077 | ||
1078 | /* Load AMR and clear new bits in t0 */ | |
1079 | gen_load_spr(t0, SPR_IAMR); | |
1080 | tcg_gen_andc_tl(t0, t0, t1); | |
1081 | ||
1082 | /* Or'in new bits and write it out */ | |
1083 | tcg_gen_or_tl(t0, t0, t2); | |
1084 | gen_store_spr(SPR_IAMR, t0); | |
1085 | spr_store_dump_spr(SPR_IAMR); | |
1086 | } | |
1087 | #endif | |
1088 | #endif | |
1089 | ||
1090 | #ifndef CONFIG_USER_ONLY | |
1091 | void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) | |
1092 | { | |
1093 | gen_helper_fixup_thrm(tcg_env); | |
1094 | gen_load_spr(cpu_gpr[gprn], sprn); | |
1095 | spr_load_dump_spr(sprn); | |
1096 | } | |
1097 | #endif /* !CONFIG_USER_ONLY */ | |
1098 | ||
1099 | #if !defined(CONFIG_USER_ONLY) | |
1100 | void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) | |
1101 | { | |
1102 | TCGv t0 = tcg_temp_new(); | |
1103 | ||
1104 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); | |
1105 | gen_store_spr(sprn, t0); | |
1106 | } | |
1107 | ||
1108 | void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) | |
1109 | { | |
1110 | TCGv t0 = tcg_temp_new(); | |
1111 | ||
1112 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); | |
1113 | gen_store_spr(sprn, t0); | |
1114 | } | |
1115 | ||
1116 | void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) | |
1117 | { | |
1118 | TCGv t0 = tcg_temp_new(); | |
1119 | ||
1120 | tcg_gen_andi_tl(t0, cpu_gpr[gprn], | |
1121 | ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); | |
1122 | gen_store_spr(sprn, t0); | |
1123 | } | |
1124 | ||
1125 | void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) | |
1126 | { | |
1127 | gen_helper_booke206_tlbflush(tcg_env, cpu_gpr[gprn]); | |
1128 | } | |
1129 | ||
1130 | void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) | |
1131 | { | |
1132 | TCGv_i32 t0 = tcg_constant_i32(sprn); | |
1133 | gen_helper_booke_setpid(tcg_env, t0, cpu_gpr[gprn]); | |
1134 | } | |
1135 | ||
1136 | void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) | |
1137 | { | |
1138 | gen_helper_booke_set_eplc(tcg_env, cpu_gpr[gprn]); | |
1139 | } | |
1140 | ||
1141 | void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) | |
1142 | { | |
1143 | gen_helper_booke_set_epsc(tcg_env, cpu_gpr[gprn]); | |
1144 | } | |
1145 | ||
1146 | #endif | |
1147 | ||
1148 | #if !defined(CONFIG_USER_ONLY) | |
1149 | void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) | |
1150 | { | |
1151 | TCGv val = tcg_temp_new(); | |
1152 | tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); | |
1153 | gen_store_spr(SPR_BOOKE_MAS3, val); | |
1154 | tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); | |
1155 | gen_store_spr(SPR_BOOKE_MAS7, val); | |
1156 | } | |
1157 | ||
1158 | void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) | |
1159 | { | |
1160 | TCGv mas7 = tcg_temp_new(); | |
1161 | TCGv mas3 = tcg_temp_new(); | |
1162 | gen_load_spr(mas7, SPR_BOOKE_MAS7); | |
1163 | tcg_gen_shli_tl(mas7, mas7, 32); | |
1164 | gen_load_spr(mas3, SPR_BOOKE_MAS3); | |
1165 | tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); | |
1166 | } | |
1167 | ||
1168 | #endif | |
1169 | ||
1170 | #ifdef TARGET_PPC64 | |
1171 | static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, | |
1172 | int bit, int sprn, int cause) | |
1173 | { | |
1174 | TCGv_i32 t1 = tcg_constant_i32(bit); | |
1175 | TCGv_i32 t2 = tcg_constant_i32(sprn); | |
1176 | TCGv_i32 t3 = tcg_constant_i32(cause); | |
1177 | ||
1178 | gen_helper_fscr_facility_check(tcg_env, t1, t2, t3); | |
1179 | } | |
1180 | ||
1181 | static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, | |
1182 | int bit, int sprn, int cause) | |
1183 | { | |
1184 | TCGv_i32 t1 = tcg_constant_i32(bit); | |
1185 | TCGv_i32 t2 = tcg_constant_i32(sprn); | |
1186 | TCGv_i32 t3 = tcg_constant_i32(cause); | |
1187 | ||
1188 | gen_helper_msr_facility_check(tcg_env, t1, t2, t3); | |
1189 | } | |
1190 | ||
1191 | void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) | |
1192 | { | |
1193 | TCGv spr_up = tcg_temp_new(); | |
1194 | TCGv spr = tcg_temp_new(); | |
1195 | ||
1196 | gen_load_spr(spr, sprn - 1); | |
1197 | tcg_gen_shri_tl(spr_up, spr, 32); | |
1198 | tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); | |
1199 | } | |
1200 | ||
1201 | void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) | |
1202 | { | |
1203 | TCGv spr = tcg_temp_new(); | |
1204 | ||
1205 | gen_load_spr(spr, sprn - 1); | |
1206 | tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); | |
1207 | gen_store_spr(sprn - 1, spr); | |
1208 | } | |
1209 | ||
1210 | #if !defined(CONFIG_USER_ONLY) | |
1211 | void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) | |
1212 | { | |
1213 | TCGv hmer = tcg_temp_new(); | |
1214 | ||
1215 | gen_load_spr(hmer, sprn); | |
1216 | tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); | |
1217 | gen_store_spr(sprn, hmer); | |
1218 | spr_store_dump_spr(sprn); | |
1219 | } | |
1220 | ||
1221 | void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) | |
1222 | { | |
1223 | gen_helper_load_tfmr(cpu_gpr[gprn], tcg_env); | |
1224 | } | |
1225 | ||
1226 | void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) | |
1227 | { | |
1228 | gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]); | |
1229 | } | |
1230 | ||
1231 | void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) | |
1232 | { | |
1233 | translator_io_start(&ctx->base); | |
1234 | gen_helper_store_lpcr(tcg_env, cpu_gpr[gprn]); | |
1235 | } | |
1236 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
1237 | ||
1238 | void spr_read_tar(DisasContext *ctx, int gprn, int sprn) | |
1239 | { | |
1240 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); | |
1241 | spr_read_generic(ctx, gprn, sprn); | |
1242 | } | |
1243 | ||
1244 | void spr_write_tar(DisasContext *ctx, int sprn, int gprn) | |
1245 | { | |
1246 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); | |
1247 | spr_write_generic(ctx, sprn, gprn); | |
1248 | } | |
1249 | ||
1250 | void spr_read_tm(DisasContext *ctx, int gprn, int sprn) | |
1251 | { | |
1252 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); | |
1253 | spr_read_generic(ctx, gprn, sprn); | |
1254 | } | |
1255 | ||
1256 | void spr_write_tm(DisasContext *ctx, int sprn, int gprn) | |
1257 | { | |
1258 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); | |
1259 | spr_write_generic(ctx, sprn, gprn); | |
1260 | } | |
1261 | ||
1262 | void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) | |
1263 | { | |
1264 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); | |
1265 | spr_read_prev_upper32(ctx, gprn, sprn); | |
1266 | } | |
1267 | ||
1268 | void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) | |
1269 | { | |
1270 | gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); | |
1271 | spr_write_prev_upper32(ctx, sprn, gprn); | |
1272 | } | |
1273 | ||
1274 | void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) | |
1275 | { | |
1276 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); | |
1277 | spr_read_generic(ctx, gprn, sprn); | |
1278 | } | |
1279 | ||
1280 | void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) | |
1281 | { | |
1282 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); | |
1283 | spr_write_generic(ctx, sprn, gprn); | |
1284 | } | |
1285 | ||
1286 | void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) | |
1287 | { | |
1288 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); | |
1289 | spr_read_prev_upper32(ctx, gprn, sprn); | |
1290 | } | |
1291 | ||
1292 | void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) | |
1293 | { | |
1294 | gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); | |
1295 | spr_write_prev_upper32(ctx, sprn, gprn); | |
1296 | } | |
1297 | ||
1298 | void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn) | |
1299 | { | |
1300 | TCGv t0 = tcg_temp_new(); | |
1301 | ||
1302 | /* | |
1303 | * Access to the (H)DEXCR in problem state is done using separated | |
1304 | * SPR indexes which are 16 below the SPR indexes which have full | |
1305 | * access to the (H)DEXCR in privileged state. Problem state can | |
1306 | * only read bits 32:63, bits 0:31 return 0. | |
1307 | * | |
1308 | * See section 9.3.1-9.3.2 of PowerISA v3.1B | |
1309 | */ | |
1310 | ||
1311 | gen_load_spr(t0, sprn + 16); | |
1312 | tcg_gen_ext32u_tl(cpu_gpr[gprn], t0); | |
1313 | } | |
1314 | #endif | |
1315 | ||
1316 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ | |
1317 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) | |
1318 | ||
1319 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
1320 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
1321 | ||
1322 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ | |
1323 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) | |
1324 | ||
1325 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
1326 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
1327 | ||
1328 | #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ | |
1329 | GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) | |
1330 | ||
1331 | #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ | |
1332 | GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) | |
1333 | ||
1334 | typedef struct opcode_t { | |
1335 | unsigned char opc1, opc2, opc3, opc4; | |
1336 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ | |
1337 | unsigned char pad[4]; | |
1338 | #endif | |
1339 | opc_handler_t handler; | |
1340 | const char *oname; | |
1341 | } opcode_t; | |
1342 | ||
1343 | static void gen_priv_opc(DisasContext *ctx) | |
1344 | { | |
1345 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
1346 | } | |
1347 | ||
1348 | /* Helpers for priv. check */ | |
1349 | #define GEN_PRIV(CTX) \ | |
1350 | do { \ | |
1351 | gen_priv_opc(CTX); return; \ | |
1352 | } while (0) | |
1353 | ||
1354 | #if defined(CONFIG_USER_ONLY) | |
1355 | #define CHK_HV(CTX) GEN_PRIV(CTX) | |
1356 | #define CHK_SV(CTX) GEN_PRIV(CTX) | |
1357 | #define CHK_HVRM(CTX) GEN_PRIV(CTX) | |
1358 | #else | |
1359 | #define CHK_HV(CTX) \ | |
1360 | do { \ | |
1361 | if (unlikely(ctx->pr || !ctx->hv)) {\ | |
1362 | GEN_PRIV(CTX); \ | |
1363 | } \ | |
1364 | } while (0) | |
1365 | #define CHK_SV(CTX) \ | |
1366 | do { \ | |
1367 | if (unlikely(ctx->pr)) { \ | |
1368 | GEN_PRIV(CTX); \ | |
1369 | } \ | |
1370 | } while (0) | |
1371 | #define CHK_HVRM(CTX) \ | |
1372 | do { \ | |
1373 | if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ | |
1374 | GEN_PRIV(CTX); \ | |
1375 | } \ | |
1376 | } while (0) | |
1377 | #endif | |
1378 | ||
1379 | #define CHK_NONE(CTX) | |
1380 | ||
1381 | /*****************************************************************************/ | |
1382 | /* PowerPC instructions table */ | |
1383 | ||
1384 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ | |
1385 | { \ | |
1386 | .opc1 = op1, \ | |
1387 | .opc2 = op2, \ | |
1388 | .opc3 = op3, \ | |
1389 | .opc4 = 0xff, \ | |
1390 | .handler = { \ | |
1391 | .inval1 = invl, \ | |
1392 | .type = _typ, \ | |
1393 | .type2 = _typ2, \ | |
1394 | .handler = &gen_##name, \ | |
1395 | }, \ | |
1396 | .oname = stringify(name), \ | |
1397 | } | |
1398 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
1399 | { \ | |
1400 | .opc1 = op1, \ | |
1401 | .opc2 = op2, \ | |
1402 | .opc3 = op3, \ | |
1403 | .opc4 = 0xff, \ | |
1404 | .handler = { \ | |
1405 | .inval1 = invl1, \ | |
1406 | .inval2 = invl2, \ | |
1407 | .type = _typ, \ | |
1408 | .type2 = _typ2, \ | |
1409 | .handler = &gen_##name, \ | |
1410 | }, \ | |
1411 | .oname = stringify(name), \ | |
1412 | } | |
1413 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ | |
1414 | { \ | |
1415 | .opc1 = op1, \ | |
1416 | .opc2 = op2, \ | |
1417 | .opc3 = op3, \ | |
1418 | .opc4 = 0xff, \ | |
1419 | .handler = { \ | |
1420 | .inval1 = invl, \ | |
1421 | .type = _typ, \ | |
1422 | .type2 = _typ2, \ | |
1423 | .handler = &gen_##name, \ | |
1424 | }, \ | |
1425 | .oname = onam, \ | |
1426 | } | |
1427 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ | |
1428 | { \ | |
1429 | .opc1 = op1, \ | |
1430 | .opc2 = op2, \ | |
1431 | .opc3 = op3, \ | |
1432 | .opc4 = op4, \ | |
1433 | .handler = { \ | |
1434 | .inval1 = invl, \ | |
1435 | .type = _typ, \ | |
1436 | .type2 = _typ2, \ | |
1437 | .handler = &gen_##name, \ | |
1438 | }, \ | |
1439 | .oname = stringify(name), \ | |
1440 | } | |
1441 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ | |
1442 | { \ | |
1443 | .opc1 = op1, \ | |
1444 | .opc2 = op2, \ | |
1445 | .opc3 = op3, \ | |
1446 | .opc4 = op4, \ | |
1447 | .handler = { \ | |
1448 | .inval1 = invl, \ | |
1449 | .type = _typ, \ | |
1450 | .type2 = _typ2, \ | |
1451 | .handler = &gen_##name, \ | |
1452 | }, \ | |
1453 | .oname = onam, \ | |
1454 | } | |
1455 | ||
1456 | /* Invalid instruction */ | |
1457 | static void gen_invalid(DisasContext *ctx) | |
1458 | { | |
1459 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
1460 | } | |
1461 | ||
1462 | static opc_handler_t invalid_handler = { | |
1463 | .inval1 = 0xFFFFFFFF, | |
1464 | .inval2 = 0xFFFFFFFF, | |
1465 | .type = PPC_NONE, | |
1466 | .type2 = PPC_NONE, | |
1467 | .handler = gen_invalid, | |
1468 | }; | |
1469 | ||
1470 | /*** Integer comparison ***/ | |
1471 | ||
1472 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) | |
1473 | { | |
1474 | TCGv t0 = tcg_temp_new(); | |
1475 | TCGv t1 = tcg_temp_new(); | |
1476 | TCGv_i32 t = tcg_temp_new_i32(); | |
1477 | ||
1478 | tcg_gen_movi_tl(t0, CRF_EQ); | |
1479 | tcg_gen_movi_tl(t1, CRF_LT); | |
1480 | tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), | |
1481 | t0, arg0, arg1, t1, t0); | |
1482 | tcg_gen_movi_tl(t1, CRF_GT); | |
1483 | tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), | |
1484 | t0, arg0, arg1, t1, t0); | |
1485 | ||
1486 | tcg_gen_trunc_tl_i32(t, t0); | |
1487 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); | |
1488 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); | |
1489 | } | |
1490 | ||
1491 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) | |
1492 | { | |
1493 | TCGv t0 = tcg_constant_tl(arg1); | |
1494 | gen_op_cmp(arg0, t0, s, crf); | |
1495 | } | |
1496 | ||
1497 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) | |
1498 | { | |
1499 | TCGv t0, t1; | |
1500 | t0 = tcg_temp_new(); | |
1501 | t1 = tcg_temp_new(); | |
1502 | if (s) { | |
1503 | tcg_gen_ext32s_tl(t0, arg0); | |
1504 | tcg_gen_ext32s_tl(t1, arg1); | |
1505 | } else { | |
1506 | tcg_gen_ext32u_tl(t0, arg0); | |
1507 | tcg_gen_ext32u_tl(t1, arg1); | |
1508 | } | |
1509 | gen_op_cmp(t0, t1, s, crf); | |
1510 | } | |
1511 | ||
1512 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) | |
1513 | { | |
1514 | TCGv t0 = tcg_constant_tl(arg1); | |
1515 | gen_op_cmp32(arg0, t0, s, crf); | |
1516 | } | |
1517 | ||
1518 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) | |
1519 | { | |
1520 | if (NARROW_MODE(ctx)) { | |
1521 | gen_op_cmpi32(reg, 0, 1, 0); | |
1522 | } else { | |
1523 | gen_op_cmpi(reg, 0, 1, 0); | |
1524 | } | |
1525 | } | |
1526 | ||
1527 | /* cmprb - range comparison: isupper, isaplha, islower*/ | |
1528 | static void gen_cmprb(DisasContext *ctx) | |
1529 | { | |
1530 | TCGv_i32 src1 = tcg_temp_new_i32(); | |
1531 | TCGv_i32 src2 = tcg_temp_new_i32(); | |
1532 | TCGv_i32 src2lo = tcg_temp_new_i32(); | |
1533 | TCGv_i32 src2hi = tcg_temp_new_i32(); | |
1534 | TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; | |
1535 | ||
1536 | tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); | |
1537 | tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); | |
1538 | ||
1539 | tcg_gen_andi_i32(src1, src1, 0xFF); | |
1540 | tcg_gen_ext8u_i32(src2lo, src2); | |
1541 | tcg_gen_shri_i32(src2, src2, 8); | |
1542 | tcg_gen_ext8u_i32(src2hi, src2); | |
1543 | ||
1544 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
1545 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
1546 | tcg_gen_and_i32(crf, src2lo, src2hi); | |
1547 | ||
1548 | if (ctx->opcode & 0x00200000) { | |
1549 | tcg_gen_shri_i32(src2, src2, 8); | |
1550 | tcg_gen_ext8u_i32(src2lo, src2); | |
1551 | tcg_gen_shri_i32(src2, src2, 8); | |
1552 | tcg_gen_ext8u_i32(src2hi, src2); | |
1553 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
1554 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
1555 | tcg_gen_and_i32(src2lo, src2lo, src2hi); | |
1556 | tcg_gen_or_i32(crf, crf, src2lo); | |
1557 | } | |
1558 | tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); | |
1559 | } | |
1560 | ||
1561 | #if defined(TARGET_PPC64) | |
1562 | /* cmpeqb */ | |
1563 | static void gen_cmpeqb(DisasContext *ctx) | |
1564 | { | |
1565 | gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1566 | cpu_gpr[rB(ctx->opcode)]); | |
1567 | } | |
1568 | #endif | |
1569 | ||
1570 | /* isel (PowerPC 2.03 specification) */ | |
1571 | static void gen_isel(DisasContext *ctx) | |
1572 | { | |
1573 | uint32_t bi = rC(ctx->opcode); | |
1574 | uint32_t mask = 0x08 >> (bi & 0x03); | |
1575 | TCGv t0 = tcg_temp_new(); | |
1576 | TCGv zr; | |
1577 | ||
1578 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); | |
1579 | tcg_gen_andi_tl(t0, t0, mask); | |
1580 | ||
1581 | zr = tcg_constant_tl(0); | |
1582 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, | |
1583 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, | |
1584 | cpu_gpr[rB(ctx->opcode)]); | |
1585 | } | |
1586 | ||
1587 | /* cmpb: PowerPC 2.05 specification */ | |
1588 | static void gen_cmpb(DisasContext *ctx) | |
1589 | { | |
1590 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
1591 | cpu_gpr[rB(ctx->opcode)]); | |
1592 | } | |
1593 | ||
1594 | /*** Integer arithmetic ***/ | |
1595 | ||
1596 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, | |
1597 | TCGv arg1, TCGv arg2, int sub) | |
1598 | { | |
1599 | TCGv t0 = tcg_temp_new(); | |
1600 | ||
1601 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); | |
1602 | tcg_gen_xor_tl(t0, arg1, arg2); | |
1603 | if (sub) { | |
1604 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
1605 | } else { | |
1606 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
1607 | } | |
1608 | if (NARROW_MODE(ctx)) { | |
1609 | tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); | |
1610 | if (is_isa300(ctx)) { | |
1611 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
1612 | } | |
1613 | } else { | |
1614 | if (is_isa300(ctx)) { | |
1615 | tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); | |
1616 | } | |
1617 | tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); | |
1618 | } | |
1619 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1620 | } | |
1621 | ||
1622 | static inline void gen_op_arith_compute_ca32(DisasContext *ctx, | |
1623 | TCGv res, TCGv arg0, TCGv arg1, | |
1624 | TCGv ca32, int sub) | |
1625 | { | |
1626 | TCGv t0; | |
1627 | ||
1628 | if (!is_isa300(ctx)) { | |
1629 | return; | |
1630 | } | |
1631 | ||
1632 | t0 = tcg_temp_new(); | |
1633 | if (sub) { | |
1634 | tcg_gen_eqv_tl(t0, arg0, arg1); | |
1635 | } else { | |
1636 | tcg_gen_xor_tl(t0, arg0, arg1); | |
1637 | } | |
1638 | tcg_gen_xor_tl(t0, t0, res); | |
1639 | tcg_gen_extract_tl(ca32, t0, 32, 1); | |
1640 | } | |
1641 | ||
1642 | /* Common add function */ | |
1643 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1644 | TCGv arg2, TCGv ca, TCGv ca32, | |
1645 | bool add_ca, bool compute_ca, | |
1646 | bool compute_ov, bool compute_rc0) | |
1647 | { | |
1648 | TCGv t0 = ret; | |
1649 | ||
1650 | if (compute_ca || compute_ov) { | |
1651 | t0 = tcg_temp_new(); | |
1652 | } | |
1653 | ||
1654 | if (compute_ca) { | |
1655 | if (NARROW_MODE(ctx)) { | |
1656 | /* | |
1657 | * Caution: a non-obvious corner case of the spec is that | |
1658 | * we must produce the *entire* 64-bit addition, but | |
1659 | * produce the carry into bit 32. | |
1660 | */ | |
1661 | TCGv t1 = tcg_temp_new(); | |
1662 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ | |
1663 | tcg_gen_add_tl(t0, arg1, arg2); | |
1664 | if (add_ca) { | |
1665 | tcg_gen_add_tl(t0, t0, ca); | |
1666 | } | |
1667 | tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ | |
1668 | tcg_gen_extract_tl(ca, ca, 32, 1); | |
1669 | if (is_isa300(ctx)) { | |
1670 | tcg_gen_mov_tl(ca32, ca); | |
1671 | } | |
1672 | } else { | |
1673 | TCGv zero = tcg_constant_tl(0); | |
1674 | if (add_ca) { | |
1675 | tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); | |
1676 | tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); | |
1677 | } else { | |
1678 | tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); | |
1679 | } | |
1680 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); | |
1681 | } | |
1682 | } else { | |
1683 | tcg_gen_add_tl(t0, arg1, arg2); | |
1684 | if (add_ca) { | |
1685 | tcg_gen_add_tl(t0, t0, ca); | |
1686 | } | |
1687 | } | |
1688 | ||
1689 | if (compute_ov) { | |
1690 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
1691 | } | |
1692 | if (unlikely(compute_rc0)) { | |
1693 | gen_set_Rc0(ctx, t0); | |
1694 | } | |
1695 | ||
1696 | if (t0 != ret) { | |
1697 | tcg_gen_mov_tl(ret, t0); | |
1698 | } | |
1699 | } | |
1700 | /* Add functions with two operands */ | |
1701 | #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ | |
1702 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1703 | { \ | |
1704 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1705 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1706 | ca, glue(ca, 32), \ | |
1707 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ | |
1708 | } | |
1709 | /* Add functions with one operand and one immediate */ | |
1710 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ | |
1711 | add_ca, compute_ca, compute_ov) \ | |
1712 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1713 | { \ | |
1714 | TCGv t0 = tcg_constant_tl(const_val); \ | |
1715 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1716 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
1717 | ca, glue(ca, 32), \ | |
1718 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ | |
1719 | } | |
1720 | ||
1721 | /* add add. addo addo. */ | |
1722 | GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) | |
1723 | GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) | |
1724 | /* addc addc. addco addco. */ | |
1725 | GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) | |
1726 | GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) | |
1727 | /* adde adde. addeo addeo. */ | |
1728 | GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) | |
1729 | GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) | |
1730 | /* addme addme. addmeo addmeo. */ | |
1731 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) | |
1732 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) | |
1733 | /* addex */ | |
1734 | GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); | |
1735 | /* addze addze. addzeo addzeo.*/ | |
1736 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) | |
1737 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) | |
1738 | /* addic addic.*/ | |
1739 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) | |
1740 | { | |
1741 | TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); | |
1742 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1743 | c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); | |
1744 | } | |
1745 | ||
1746 | static void gen_addic(DisasContext *ctx) | |
1747 | { | |
1748 | gen_op_addic(ctx, 0); | |
1749 | } | |
1750 | ||
1751 | static void gen_addic_(DisasContext *ctx) | |
1752 | { | |
1753 | gen_op_addic(ctx, 1); | |
1754 | } | |
1755 | ||
1756 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1757 | TCGv arg2, int sign, int compute_ov) | |
1758 | { | |
1759 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1760 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1761 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1762 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1763 | ||
1764 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1765 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1766 | if (sign) { | |
1767 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); | |
1768 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1769 | tcg_gen_and_i32(t2, t2, t3); | |
1770 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1771 | tcg_gen_or_i32(t2, t2, t3); | |
1772 | tcg_gen_movi_i32(t3, 0); | |
1773 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1774 | tcg_gen_div_i32(t3, t0, t1); | |
1775 | tcg_gen_extu_i32_tl(ret, t3); | |
1776 | } else { | |
1777 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); | |
1778 | tcg_gen_movi_i32(t3, 0); | |
1779 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1780 | tcg_gen_divu_i32(t3, t0, t1); | |
1781 | tcg_gen_extu_i32_tl(ret, t3); | |
1782 | } | |
1783 | if (compute_ov) { | |
1784 | tcg_gen_extu_i32_tl(cpu_ov, t2); | |
1785 | if (is_isa300(ctx)) { | |
1786 | tcg_gen_extu_i32_tl(cpu_ov32, t2); | |
1787 | } | |
1788 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1789 | } | |
1790 | ||
1791 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1792 | gen_set_Rc0(ctx, ret); | |
1793 | } | |
1794 | } | |
1795 | /* Div functions */ | |
1796 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
1797 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1798 | { \ | |
1799 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1800 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1801 | sign, compute_ov); \ | |
1802 | } | |
1803 | /* divwu divwu. divwuo divwuo. */ | |
1804 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1805 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1806 | /* divw divw. divwo divwo. */ | |
1807 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1808 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
1809 | ||
1810 | /* div[wd]eu[o][.] */ | |
1811 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1812 | static void gen_##name(DisasContext *ctx) \ | |
1813 | { \ | |
1814 | TCGv_i32 t0 = tcg_constant_i32(compute_ov); \ | |
1815 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], tcg_env, \ | |
1816 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1817 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1818 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1819 | } \ | |
1820 | } | |
1821 | ||
1822 | GEN_DIVE(divweu, divweu, 0); | |
1823 | GEN_DIVE(divweuo, divweu, 1); | |
1824 | GEN_DIVE(divwe, divwe, 0); | |
1825 | GEN_DIVE(divweo, divwe, 1); | |
1826 | ||
1827 | #if defined(TARGET_PPC64) | |
1828 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1829 | TCGv arg2, int sign, int compute_ov) | |
1830 | { | |
1831 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1832 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1833 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1834 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1835 | ||
1836 | tcg_gen_mov_i64(t0, arg1); | |
1837 | tcg_gen_mov_i64(t1, arg2); | |
1838 | if (sign) { | |
1839 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); | |
1840 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1841 | tcg_gen_and_i64(t2, t2, t3); | |
1842 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1843 | tcg_gen_or_i64(t2, t2, t3); | |
1844 | tcg_gen_movi_i64(t3, 0); | |
1845 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1846 | tcg_gen_div_i64(ret, t0, t1); | |
1847 | } else { | |
1848 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); | |
1849 | tcg_gen_movi_i64(t3, 0); | |
1850 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1851 | tcg_gen_divu_i64(ret, t0, t1); | |
1852 | } | |
1853 | if (compute_ov) { | |
1854 | tcg_gen_mov_tl(cpu_ov, t2); | |
1855 | if (is_isa300(ctx)) { | |
1856 | tcg_gen_mov_tl(cpu_ov32, t2); | |
1857 | } | |
1858 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1859 | } | |
1860 | ||
1861 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1862 | gen_set_Rc0(ctx, ret); | |
1863 | } | |
1864 | } | |
1865 | ||
1866 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
1867 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1868 | { \ | |
1869 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1870 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1871 | sign, compute_ov); \ | |
1872 | } | |
1873 | /* divdu divdu. divduo divduo. */ | |
1874 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1875 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1876 | /* divd divd. divdo divdo. */ | |
1877 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1878 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
1879 | ||
1880 | GEN_DIVE(divdeu, divdeu, 0); | |
1881 | GEN_DIVE(divdeuo, divdeu, 1); | |
1882 | GEN_DIVE(divde, divde, 0); | |
1883 | GEN_DIVE(divdeo, divde, 1); | |
1884 | #endif | |
1885 | ||
1886 | static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1887 | TCGv arg2, int sign) | |
1888 | { | |
1889 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1890 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1891 | ||
1892 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1893 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1894 | if (sign) { | |
1895 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1896 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1897 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); | |
1898 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1899 | tcg_gen_and_i32(t2, t2, t3); | |
1900 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1901 | tcg_gen_or_i32(t2, t2, t3); | |
1902 | tcg_gen_movi_i32(t3, 0); | |
1903 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1904 | tcg_gen_rem_i32(t3, t0, t1); | |
1905 | tcg_gen_ext_i32_tl(ret, t3); | |
1906 | } else { | |
1907 | TCGv_i32 t2 = tcg_constant_i32(1); | |
1908 | TCGv_i32 t3 = tcg_constant_i32(0); | |
1909 | tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1910 | tcg_gen_remu_i32(t0, t0, t1); | |
1911 | tcg_gen_extu_i32_tl(ret, t0); | |
1912 | } | |
1913 | } | |
1914 | ||
1915 | #define GEN_INT_ARITH_MODW(name, opc3, sign) \ | |
1916 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1917 | { \ | |
1918 | gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1919 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1920 | sign); \ | |
1921 | } | |
1922 | ||
1923 | GEN_INT_ARITH_MODW(moduw, 0x08, 0); | |
1924 | GEN_INT_ARITH_MODW(modsw, 0x18, 1); | |
1925 | ||
1926 | #if defined(TARGET_PPC64) | |
1927 | static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1928 | TCGv arg2, int sign) | |
1929 | { | |
1930 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1931 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1932 | ||
1933 | tcg_gen_mov_i64(t0, arg1); | |
1934 | tcg_gen_mov_i64(t1, arg2); | |
1935 | if (sign) { | |
1936 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1937 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1938 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); | |
1939 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1940 | tcg_gen_and_i64(t2, t2, t3); | |
1941 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1942 | tcg_gen_or_i64(t2, t2, t3); | |
1943 | tcg_gen_movi_i64(t3, 0); | |
1944 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1945 | tcg_gen_rem_i64(ret, t0, t1); | |
1946 | } else { | |
1947 | TCGv_i64 t2 = tcg_constant_i64(1); | |
1948 | TCGv_i64 t3 = tcg_constant_i64(0); | |
1949 | tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1950 | tcg_gen_remu_i64(ret, t0, t1); | |
1951 | } | |
1952 | } | |
1953 | ||
1954 | #define GEN_INT_ARITH_MODD(name, opc3, sign) \ | |
1955 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1956 | { \ | |
1957 | gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1958 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1959 | sign); \ | |
1960 | } | |
1961 | ||
1962 | GEN_INT_ARITH_MODD(modud, 0x08, 0); | |
1963 | GEN_INT_ARITH_MODD(modsd, 0x18, 1); | |
1964 | #endif | |
1965 | ||
1966 | /* mulhw mulhw. */ | |
1967 | static void gen_mulhw(DisasContext *ctx) | |
1968 | { | |
1969 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1970 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1971 | ||
1972 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); | |
1973 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1974 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1975 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1976 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1977 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1978 | } | |
1979 | } | |
1980 | ||
1981 | /* mulhwu mulhwu. */ | |
1982 | static void gen_mulhwu(DisasContext *ctx) | |
1983 | { | |
1984 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1985 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1986 | ||
1987 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); | |
1988 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1989 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1990 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1991 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1992 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1993 | } | |
1994 | } | |
1995 | ||
1996 | /* mullw mullw. */ | |
1997 | static void gen_mullw(DisasContext *ctx) | |
1998 | { | |
1999 | #if defined(TARGET_PPC64) | |
2000 | TCGv_i64 t0, t1; | |
2001 | t0 = tcg_temp_new_i64(); | |
2002 | t1 = tcg_temp_new_i64(); | |
2003 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
2004 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
2005 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
2006 | #else | |
2007 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
2008 | cpu_gpr[rB(ctx->opcode)]); | |
2009 | #endif | |
2010 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2011 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
2012 | } | |
2013 | } | |
2014 | ||
2015 | /* mullwo mullwo. */ | |
2016 | static void gen_mullwo(DisasContext *ctx) | |
2017 | { | |
2018 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
2019 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
2020 | ||
2021 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); | |
2022 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
2023 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
2024 | #if defined(TARGET_PPC64) | |
2025 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
2026 | #else | |
2027 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
2028 | #endif | |
2029 | ||
2030 | tcg_gen_sari_i32(t0, t0, 31); | |
2031 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
2032 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
2033 | if (is_isa300(ctx)) { | |
2034 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
2035 | } | |
2036 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
2037 | ||
2038 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2039 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
2040 | } | |
2041 | } | |
2042 | ||
2043 | /* mulli */ | |
2044 | static void gen_mulli(DisasContext *ctx) | |
2045 | { | |
2046 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
2047 | SIMM(ctx->opcode)); | |
2048 | } | |
2049 | ||
2050 | #if defined(TARGET_PPC64) | |
2051 | /* mulhd mulhd. */ | |
2052 | static void gen_mulhd(DisasContext *ctx) | |
2053 | { | |
2054 | TCGv lo = tcg_temp_new(); | |
2055 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
2056 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
2057 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2058 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
2059 | } | |
2060 | } | |
2061 | ||
2062 | /* mulhdu mulhdu. */ | |
2063 | static void gen_mulhdu(DisasContext *ctx) | |
2064 | { | |
2065 | TCGv lo = tcg_temp_new(); | |
2066 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
2067 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
2068 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2069 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
2070 | } | |
2071 | } | |
2072 | ||
2073 | /* mulld mulld. */ | |
2074 | static void gen_mulld(DisasContext *ctx) | |
2075 | { | |
2076 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
2077 | cpu_gpr[rB(ctx->opcode)]); | |
2078 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2079 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
2080 | } | |
2081 | } | |
2082 | ||
2083 | /* mulldo mulldo. */ | |
2084 | static void gen_mulldo(DisasContext *ctx) | |
2085 | { | |
2086 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
2087 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
2088 | ||
2089 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], | |
2090 | cpu_gpr[rB(ctx->opcode)]); | |
2091 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
2092 | ||
2093 | tcg_gen_sari_i64(t0, t0, 63); | |
2094 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); | |
2095 | if (is_isa300(ctx)) { | |
2096 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); | |
2097 | } | |
2098 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
2099 | ||
2100 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2101 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
2102 | } | |
2103 | } | |
2104 | #endif | |
2105 | ||
2106 | /* Common subf function */ | |
2107 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, | |
2108 | TCGv arg2, bool add_ca, bool compute_ca, | |
2109 | bool compute_ov, bool compute_rc0) | |
2110 | { | |
2111 | TCGv t0 = ret; | |
2112 | ||
2113 | if (compute_ca || compute_ov) { | |
2114 | t0 = tcg_temp_new(); | |
2115 | } | |
2116 | ||
2117 | if (compute_ca) { | |
2118 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
2119 | if (NARROW_MODE(ctx)) { | |
2120 | /* | |
2121 | * Caution: a non-obvious corner case of the spec is that | |
2122 | * we must produce the *entire* 64-bit addition, but | |
2123 | * produce the carry into bit 32. | |
2124 | */ | |
2125 | TCGv inv1 = tcg_temp_new(); | |
2126 | TCGv t1 = tcg_temp_new(); | |
2127 | tcg_gen_not_tl(inv1, arg1); | |
2128 | if (add_ca) { | |
2129 | tcg_gen_add_tl(t0, arg2, cpu_ca); | |
2130 | } else { | |
2131 | tcg_gen_addi_tl(t0, arg2, 1); | |
2132 | } | |
2133 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ | |
2134 | tcg_gen_add_tl(t0, t0, inv1); | |
2135 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ | |
2136 | tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); | |
2137 | if (is_isa300(ctx)) { | |
2138 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2139 | } | |
2140 | } else if (add_ca) { | |
2141 | TCGv zero, inv1 = tcg_temp_new(); | |
2142 | tcg_gen_not_tl(inv1, arg1); | |
2143 | zero = tcg_constant_tl(0); | |
2144 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
2145 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); | |
2146 | gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); | |
2147 | } else { | |
2148 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); | |
2149 | tcg_gen_sub_tl(t0, arg2, arg1); | |
2150 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); | |
2151 | } | |
2152 | } else if (add_ca) { | |
2153 | /* | |
2154 | * Since we're ignoring carry-out, we can simplify the | |
2155 | * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. | |
2156 | */ | |
2157 | tcg_gen_sub_tl(t0, arg2, arg1); | |
2158 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
2159 | tcg_gen_subi_tl(t0, t0, 1); | |
2160 | } else { | |
2161 | tcg_gen_sub_tl(t0, arg2, arg1); | |
2162 | } | |
2163 | ||
2164 | if (compute_ov) { | |
2165 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
2166 | } | |
2167 | if (unlikely(compute_rc0)) { | |
2168 | gen_set_Rc0(ctx, t0); | |
2169 | } | |
2170 | ||
2171 | if (t0 != ret) { | |
2172 | tcg_gen_mov_tl(ret, t0); | |
2173 | } | |
2174 | } | |
2175 | /* Sub functions with Two operands functions */ | |
2176 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
2177 | static void glue(gen_, name)(DisasContext *ctx) \ | |
2178 | { \ | |
2179 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
2180 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
2181 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ | |
2182 | } | |
2183 | /* Sub functions with one operand and one immediate */ | |
2184 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
2185 | add_ca, compute_ca, compute_ov) \ | |
2186 | static void glue(gen_, name)(DisasContext *ctx) \ | |
2187 | { \ | |
2188 | TCGv t0 = tcg_constant_tl(const_val); \ | |
2189 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
2190 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
2191 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ | |
2192 | } | |
2193 | /* subf subf. subfo subfo. */ | |
2194 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
2195 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
2196 | /* subfc subfc. subfco subfco. */ | |
2197 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
2198 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
2199 | /* subfe subfe. subfeo subfo. */ | |
2200 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
2201 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
2202 | /* subfme subfme. subfmeo subfmeo. */ | |
2203 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
2204 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
2205 | /* subfze subfze. subfzeo subfzeo.*/ | |
2206 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
2207 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
2208 | ||
2209 | /* subfic */ | |
2210 | static void gen_subfic(DisasContext *ctx) | |
2211 | { | |
2212 | TCGv c = tcg_constant_tl(SIMM(ctx->opcode)); | |
2213 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
2214 | c, 0, 1, 0, 0); | |
2215 | } | |
2216 | ||
2217 | /* neg neg. nego nego. */ | |
2218 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
2219 | { | |
2220 | TCGv zero = tcg_constant_tl(0); | |
2221 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
2222 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
2223 | } | |
2224 | ||
2225 | static void gen_neg(DisasContext *ctx) | |
2226 | { | |
2227 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
2228 | if (unlikely(Rc(ctx->opcode))) { | |
2229 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
2230 | } | |
2231 | } | |
2232 | ||
2233 | static void gen_nego(DisasContext *ctx) | |
2234 | { | |
2235 | gen_op_arith_neg(ctx, 1); | |
2236 | } | |
2237 | ||
2238 | /*** Integer logical ***/ | |
2239 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
2240 | static void glue(gen_, name)(DisasContext *ctx) \ | |
2241 | { \ | |
2242 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ | |
2243 | cpu_gpr[rB(ctx->opcode)]); \ | |
2244 | if (unlikely(Rc(ctx->opcode) != 0)) \ | |
2245 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ | |
2246 | } | |
2247 | ||
2248 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
2249 | static void glue(gen_, name)(DisasContext *ctx) \ | |
2250 | { \ | |
2251 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ | |
2252 | if (unlikely(Rc(ctx->opcode) != 0)) \ | |
2253 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ | |
2254 | } | |
2255 | ||
2256 | /* and & and. */ | |
2257 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); | |
2258 | /* andc & andc. */ | |
2259 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); | |
2260 | ||
2261 | /* andi. */ | |
2262 | static void gen_andi_(DisasContext *ctx) | |
2263 | { | |
2264 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
2265 | UIMM(ctx->opcode)); | |
2266 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2267 | } | |
2268 | ||
2269 | /* andis. */ | |
2270 | static void gen_andis_(DisasContext *ctx) | |
2271 | { | |
2272 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
2273 | UIMM(ctx->opcode) << 16); | |
2274 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2275 | } | |
2276 | ||
2277 | /* cntlzw */ | |
2278 | static void gen_cntlzw(DisasContext *ctx) | |
2279 | { | |
2280 | TCGv_i32 t = tcg_temp_new_i32(); | |
2281 | ||
2282 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
2283 | tcg_gen_clzi_i32(t, t, 32); | |
2284 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
2285 | ||
2286 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2287 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2288 | } | |
2289 | } | |
2290 | ||
2291 | /* cnttzw */ | |
2292 | static void gen_cnttzw(DisasContext *ctx) | |
2293 | { | |
2294 | TCGv_i32 t = tcg_temp_new_i32(); | |
2295 | ||
2296 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); | |
2297 | tcg_gen_ctzi_i32(t, t, 32); | |
2298 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); | |
2299 | ||
2300 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2301 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2302 | } | |
2303 | } | |
2304 | ||
2305 | /* eqv & eqv. */ | |
2306 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); | |
2307 | /* extsb & extsb. */ | |
2308 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); | |
2309 | /* extsh & extsh. */ | |
2310 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); | |
2311 | /* nand & nand. */ | |
2312 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); | |
2313 | /* nor & nor. */ | |
2314 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); | |
2315 | ||
2316 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
2317 | static void gen_pause(DisasContext *ctx) | |
2318 | { | |
2319 | TCGv_i32 t0 = tcg_constant_i32(0); | |
2320 | tcg_gen_st_i32(t0, tcg_env, | |
2321 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
2322 | ||
2323 | /* Stop translation, this gives other CPUs a chance to run */ | |
2324 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
2325 | } | |
2326 | #endif /* defined(TARGET_PPC64) */ | |
2327 | ||
2328 | /* or & or. */ | |
2329 | static void gen_or(DisasContext *ctx) | |
2330 | { | |
2331 | int rs, ra, rb; | |
2332 | ||
2333 | rs = rS(ctx->opcode); | |
2334 | ra = rA(ctx->opcode); | |
2335 | rb = rB(ctx->opcode); | |
2336 | /* Optimisation for mr. ri case */ | |
2337 | if (rs != ra || rs != rb) { | |
2338 | if (rs != rb) { | |
2339 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
2340 | } else { | |
2341 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
2342 | } | |
2343 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2344 | gen_set_Rc0(ctx, cpu_gpr[ra]); | |
2345 | } | |
2346 | } else if (unlikely(Rc(ctx->opcode) != 0)) { | |
2347 | gen_set_Rc0(ctx, cpu_gpr[rs]); | |
2348 | #if defined(TARGET_PPC64) | |
2349 | } else if (rs != 0) { /* 0 is nop */ | |
2350 | int prio = 0; | |
2351 | ||
2352 | switch (rs) { | |
2353 | case 1: | |
2354 | /* Set process priority to low */ | |
2355 | prio = 2; | |
2356 | break; | |
2357 | case 6: | |
2358 | /* Set process priority to medium-low */ | |
2359 | prio = 3; | |
2360 | break; | |
2361 | case 2: | |
2362 | /* Set process priority to normal */ | |
2363 | prio = 4; | |
2364 | break; | |
2365 | #if !defined(CONFIG_USER_ONLY) | |
2366 | case 31: | |
2367 | if (!ctx->pr) { | |
2368 | /* Set process priority to very low */ | |
2369 | prio = 1; | |
2370 | } | |
2371 | break; | |
2372 | case 5: | |
2373 | if (!ctx->pr) { | |
2374 | /* Set process priority to medium-hight */ | |
2375 | prio = 5; | |
2376 | } | |
2377 | break; | |
2378 | case 3: | |
2379 | if (!ctx->pr) { | |
2380 | /* Set process priority to high */ | |
2381 | prio = 6; | |
2382 | } | |
2383 | break; | |
2384 | case 7: | |
2385 | if (ctx->hv && !ctx->pr) { | |
2386 | /* Set process priority to very high */ | |
2387 | prio = 7; | |
2388 | } | |
2389 | break; | |
2390 | #endif | |
2391 | default: | |
2392 | break; | |
2393 | } | |
2394 | if (prio) { | |
2395 | TCGv t0 = tcg_temp_new(); | |
2396 | gen_load_spr(t0, SPR_PPR); | |
2397 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); | |
2398 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
2399 | gen_store_spr(SPR_PPR, t0); | |
2400 | } | |
2401 | #if !defined(CONFIG_USER_ONLY) | |
2402 | /* | |
2403 | * Pause out of TCG otherwise spin loops with smt_low eat too | |
2404 | * much CPU and the kernel hangs. This applies to all | |
2405 | * encodings other than no-op, e.g., miso(rs=26), yield(27), | |
2406 | * mdoio(29), mdoom(30), and all currently undefined. | |
2407 | */ | |
2408 | gen_pause(ctx); | |
2409 | #endif | |
2410 | #endif | |
2411 | } | |
2412 | } | |
2413 | /* orc & orc. */ | |
2414 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); | |
2415 | ||
2416 | /* xor & xor. */ | |
2417 | static void gen_xor(DisasContext *ctx) | |
2418 | { | |
2419 | /* Optimisation for "set to zero" case */ | |
2420 | if (rS(ctx->opcode) != rB(ctx->opcode)) { | |
2421 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
2422 | cpu_gpr[rB(ctx->opcode)]); | |
2423 | } else { | |
2424 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
2425 | } | |
2426 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2427 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2428 | } | |
2429 | } | |
2430 | ||
2431 | /* ori */ | |
2432 | static void gen_ori(DisasContext *ctx) | |
2433 | { | |
2434 | target_ulong uimm = UIMM(ctx->opcode); | |
2435 | ||
2436 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
2437 | return; | |
2438 | } | |
2439 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); | |
2440 | } | |
2441 | ||
2442 | /* oris */ | |
2443 | static void gen_oris(DisasContext *ctx) | |
2444 | { | |
2445 | target_ulong uimm = UIMM(ctx->opcode); | |
2446 | ||
2447 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
2448 | /* NOP */ | |
2449 | return; | |
2450 | } | |
2451 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
2452 | uimm << 16); | |
2453 | } | |
2454 | ||
2455 | /* xori */ | |
2456 | static void gen_xori(DisasContext *ctx) | |
2457 | { | |
2458 | target_ulong uimm = UIMM(ctx->opcode); | |
2459 | ||
2460 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
2461 | /* NOP */ | |
2462 | return; | |
2463 | } | |
2464 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); | |
2465 | } | |
2466 | ||
2467 | /* xoris */ | |
2468 | static void gen_xoris(DisasContext *ctx) | |
2469 | { | |
2470 | target_ulong uimm = UIMM(ctx->opcode); | |
2471 | ||
2472 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
2473 | /* NOP */ | |
2474 | return; | |
2475 | } | |
2476 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
2477 | uimm << 16); | |
2478 | } | |
2479 | ||
2480 | /* popcntb : PowerPC 2.03 specification */ | |
2481 | static void gen_popcntb(DisasContext *ctx) | |
2482 | { | |
2483 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
2484 | } | |
2485 | ||
2486 | static void gen_popcntw(DisasContext *ctx) | |
2487 | { | |
2488 | #if defined(TARGET_PPC64) | |
2489 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
2490 | #else | |
2491 | tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
2492 | #endif | |
2493 | } | |
2494 | ||
2495 | #if defined(TARGET_PPC64) | |
2496 | /* popcntd: PowerPC 2.06 specification */ | |
2497 | static void gen_popcntd(DisasContext *ctx) | |
2498 | { | |
2499 | tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
2500 | } | |
2501 | #endif | |
2502 | ||
2503 | /* prtyw: PowerPC 2.05 specification */ | |
2504 | static void gen_prtyw(DisasContext *ctx) | |
2505 | { | |
2506 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
2507 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
2508 | TCGv t0 = tcg_temp_new(); | |
2509 | tcg_gen_shri_tl(t0, rs, 16); | |
2510 | tcg_gen_xor_tl(ra, rs, t0); | |
2511 | tcg_gen_shri_tl(t0, ra, 8); | |
2512 | tcg_gen_xor_tl(ra, ra, t0); | |
2513 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
2514 | } | |
2515 | ||
2516 | #if defined(TARGET_PPC64) | |
2517 | /* prtyd: PowerPC 2.05 specification */ | |
2518 | static void gen_prtyd(DisasContext *ctx) | |
2519 | { | |
2520 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
2521 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
2522 | TCGv t0 = tcg_temp_new(); | |
2523 | tcg_gen_shri_tl(t0, rs, 32); | |
2524 | tcg_gen_xor_tl(ra, rs, t0); | |
2525 | tcg_gen_shri_tl(t0, ra, 16); | |
2526 | tcg_gen_xor_tl(ra, ra, t0); | |
2527 | tcg_gen_shri_tl(t0, ra, 8); | |
2528 | tcg_gen_xor_tl(ra, ra, t0); | |
2529 | tcg_gen_andi_tl(ra, ra, 1); | |
2530 | } | |
2531 | #endif | |
2532 | ||
2533 | #if defined(TARGET_PPC64) | |
2534 | /* bpermd */ | |
2535 | static void gen_bpermd(DisasContext *ctx) | |
2536 | { | |
2537 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
2538 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
2539 | } | |
2540 | #endif | |
2541 | ||
2542 | #if defined(TARGET_PPC64) | |
2543 | /* extsw & extsw. */ | |
2544 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); | |
2545 | ||
2546 | /* cntlzd */ | |
2547 | static void gen_cntlzd(DisasContext *ctx) | |
2548 | { | |
2549 | tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); | |
2550 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2551 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2552 | } | |
2553 | } | |
2554 | ||
2555 | /* cnttzd */ | |
2556 | static void gen_cnttzd(DisasContext *ctx) | |
2557 | { | |
2558 | tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); | |
2559 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2560 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2561 | } | |
2562 | } | |
2563 | ||
2564 | /* darn */ | |
2565 | static void gen_darn(DisasContext *ctx) | |
2566 | { | |
2567 | int l = L(ctx->opcode); | |
2568 | ||
2569 | if (l > 2) { | |
2570 | tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); | |
2571 | } else { | |
2572 | translator_io_start(&ctx->base); | |
2573 | if (l == 0) { | |
2574 | gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); | |
2575 | } else { | |
2576 | /* Return 64-bit random for both CRN and RRN */ | |
2577 | gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); | |
2578 | } | |
2579 | } | |
2580 | } | |
2581 | #endif | |
2582 | ||
2583 | /*** Integer rotate ***/ | |
2584 | ||
2585 | /* rlwimi & rlwimi. */ | |
2586 | static void gen_rlwimi(DisasContext *ctx) | |
2587 | { | |
2588 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; | |
2589 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2590 | uint32_t sh = SH(ctx->opcode); | |
2591 | uint32_t mb = MB(ctx->opcode); | |
2592 | uint32_t me = ME(ctx->opcode); | |
2593 | ||
2594 | if (sh == (31 - me) && mb <= me) { | |
2595 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
2596 | } else { | |
2597 | target_ulong mask; | |
2598 | bool mask_in_32b = true; | |
2599 | TCGv t1; | |
2600 | ||
2601 | #if defined(TARGET_PPC64) | |
2602 | mb += 32; | |
2603 | me += 32; | |
2604 | #endif | |
2605 | mask = MASK(mb, me); | |
2606 | ||
2607 | #if defined(TARGET_PPC64) | |
2608 | if (mask > 0xffffffffu) { | |
2609 | mask_in_32b = false; | |
2610 | } | |
2611 | #endif | |
2612 | t1 = tcg_temp_new(); | |
2613 | if (mask_in_32b) { | |
2614 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
2615 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
2616 | tcg_gen_rotli_i32(t0, t0, sh); | |
2617 | tcg_gen_extu_i32_tl(t1, t0); | |
2618 | } else { | |
2619 | #if defined(TARGET_PPC64) | |
2620 | tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); | |
2621 | tcg_gen_rotli_i64(t1, t1, sh); | |
2622 | #else | |
2623 | g_assert_not_reached(); | |
2624 | #endif | |
2625 | } | |
2626 | ||
2627 | tcg_gen_andi_tl(t1, t1, mask); | |
2628 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2629 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
2630 | } | |
2631 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2632 | gen_set_Rc0(ctx, t_ra); | |
2633 | } | |
2634 | } | |
2635 | ||
2636 | /* rlwinm & rlwinm. */ | |
2637 | static void gen_rlwinm(DisasContext *ctx) | |
2638 | { | |
2639 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; | |
2640 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2641 | int sh = SH(ctx->opcode); | |
2642 | int mb = MB(ctx->opcode); | |
2643 | int me = ME(ctx->opcode); | |
2644 | int len = me - mb + 1; | |
2645 | int rsh = (32 - sh) & 31; | |
2646 | ||
2647 | if (sh != 0 && len > 0 && me == (31 - sh)) { | |
2648 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
2649 | } else if (me == 31 && rsh + len <= 32) { | |
2650 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
2651 | } else { | |
2652 | target_ulong mask; | |
2653 | bool mask_in_32b = true; | |
2654 | #if defined(TARGET_PPC64) | |
2655 | mb += 32; | |
2656 | me += 32; | |
2657 | #endif | |
2658 | mask = MASK(mb, me); | |
2659 | #if defined(TARGET_PPC64) | |
2660 | if (mask > 0xffffffffu) { | |
2661 | mask_in_32b = false; | |
2662 | } | |
2663 | #endif | |
2664 | if (mask_in_32b) { | |
2665 | if (sh == 0) { | |
2666 | tcg_gen_andi_tl(t_ra, t_rs, mask); | |
2667 | } else { | |
2668 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
2669 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
2670 | tcg_gen_rotli_i32(t0, t0, sh); | |
2671 | tcg_gen_andi_i32(t0, t0, mask); | |
2672 | tcg_gen_extu_i32_tl(t_ra, t0); | |
2673 | } | |
2674 | } else { | |
2675 | #if defined(TARGET_PPC64) | |
2676 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
2677 | tcg_gen_rotli_i64(t_ra, t_ra, sh); | |
2678 | tcg_gen_andi_i64(t_ra, t_ra, mask); | |
2679 | #else | |
2680 | g_assert_not_reached(); | |
2681 | #endif | |
2682 | } | |
2683 | } | |
2684 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2685 | gen_set_Rc0(ctx, t_ra); | |
2686 | } | |
2687 | } | |
2688 | ||
2689 | /* rlwnm & rlwnm. */ | |
2690 | static void gen_rlwnm(DisasContext *ctx) | |
2691 | { | |
2692 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; | |
2693 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2694 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
2695 | uint32_t mb = MB(ctx->opcode); | |
2696 | uint32_t me = ME(ctx->opcode); | |
2697 | target_ulong mask; | |
2698 | bool mask_in_32b = true; | |
2699 | ||
2700 | #if defined(TARGET_PPC64) | |
2701 | mb += 32; | |
2702 | me += 32; | |
2703 | #endif | |
2704 | mask = MASK(mb, me); | |
2705 | ||
2706 | #if defined(TARGET_PPC64) | |
2707 | if (mask > 0xffffffffu) { | |
2708 | mask_in_32b = false; | |
2709 | } | |
2710 | #endif | |
2711 | if (mask_in_32b) { | |
2712 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
2713 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
2714 | tcg_gen_trunc_tl_i32(t0, t_rb); | |
2715 | tcg_gen_trunc_tl_i32(t1, t_rs); | |
2716 | tcg_gen_andi_i32(t0, t0, 0x1f); | |
2717 | tcg_gen_rotl_i32(t1, t1, t0); | |
2718 | tcg_gen_extu_i32_tl(t_ra, t1); | |
2719 | } else { | |
2720 | #if defined(TARGET_PPC64) | |
2721 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
2722 | tcg_gen_andi_i64(t0, t_rb, 0x1f); | |
2723 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
2724 | tcg_gen_rotl_i64(t_ra, t_ra, t0); | |
2725 | #else | |
2726 | g_assert_not_reached(); | |
2727 | #endif | |
2728 | } | |
2729 | ||
2730 | tcg_gen_andi_tl(t_ra, t_ra, mask); | |
2731 | ||
2732 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2733 | gen_set_Rc0(ctx, t_ra); | |
2734 | } | |
2735 | } | |
2736 | ||
2737 | #if defined(TARGET_PPC64) | |
2738 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
2739 | static void glue(gen_, name##0)(DisasContext *ctx) \ | |
2740 | { \ | |
2741 | gen_##name(ctx, 0); \ | |
2742 | } \ | |
2743 | \ | |
2744 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
2745 | { \ | |
2746 | gen_##name(ctx, 1); \ | |
2747 | } | |
2748 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
2749 | static void glue(gen_, name##0)(DisasContext *ctx) \ | |
2750 | { \ | |
2751 | gen_##name(ctx, 0, 0); \ | |
2752 | } \ | |
2753 | \ | |
2754 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
2755 | { \ | |
2756 | gen_##name(ctx, 0, 1); \ | |
2757 | } \ | |
2758 | \ | |
2759 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
2760 | { \ | |
2761 | gen_##name(ctx, 1, 0); \ | |
2762 | } \ | |
2763 | \ | |
2764 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
2765 | { \ | |
2766 | gen_##name(ctx, 1, 1); \ | |
2767 | } | |
2768 | ||
2769 | static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) | |
2770 | { | |
2771 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; | |
2772 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2773 | int len = me - mb + 1; | |
2774 | int rsh = (64 - sh) & 63; | |
2775 | ||
2776 | if (sh != 0 && len > 0 && me == (63 - sh)) { | |
2777 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); | |
2778 | } else if (me == 63 && rsh + len <= 64) { | |
2779 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); | |
2780 | } else { | |
2781 | tcg_gen_rotli_tl(t_ra, t_rs, sh); | |
2782 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2783 | } | |
2784 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2785 | gen_set_Rc0(ctx, t_ra); | |
2786 | } | |
2787 | } | |
2788 | ||
2789 | /* rldicl - rldicl. */ | |
2790 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) | |
2791 | { | |
2792 | uint32_t sh, mb; | |
2793 | ||
2794 | sh = SH(ctx->opcode) | (shn << 5); | |
2795 | mb = MB(ctx->opcode) | (mbn << 5); | |
2796 | gen_rldinm(ctx, mb, 63, sh); | |
2797 | } | |
2798 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); | |
2799 | ||
2800 | /* rldicr - rldicr. */ | |
2801 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) | |
2802 | { | |
2803 | uint32_t sh, me; | |
2804 | ||
2805 | sh = SH(ctx->opcode) | (shn << 5); | |
2806 | me = MB(ctx->opcode) | (men << 5); | |
2807 | gen_rldinm(ctx, 0, me, sh); | |
2808 | } | |
2809 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); | |
2810 | ||
2811 | /* rldic - rldic. */ | |
2812 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) | |
2813 | { | |
2814 | uint32_t sh, mb; | |
2815 | ||
2816 | sh = SH(ctx->opcode) | (shn << 5); | |
2817 | mb = MB(ctx->opcode) | (mbn << 5); | |
2818 | gen_rldinm(ctx, mb, 63 - sh, sh); | |
2819 | } | |
2820 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
2821 | ||
2822 | static void gen_rldnm(DisasContext *ctx, int mb, int me) | |
2823 | { | |
2824 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; | |
2825 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2826 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
2827 | TCGv t0; | |
2828 | ||
2829 | t0 = tcg_temp_new(); | |
2830 | tcg_gen_andi_tl(t0, t_rb, 0x3f); | |
2831 | tcg_gen_rotl_tl(t_ra, t_rs, t0); | |
2832 | ||
2833 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2834 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2835 | gen_set_Rc0(ctx, t_ra); | |
2836 | } | |
2837 | } | |
2838 | ||
2839 | /* rldcl - rldcl. */ | |
2840 | static inline void gen_rldcl(DisasContext *ctx, int mbn) | |
2841 | { | |
2842 | uint32_t mb; | |
2843 | ||
2844 | mb = MB(ctx->opcode) | (mbn << 5); | |
2845 | gen_rldnm(ctx, mb, 63); | |
2846 | } | |
2847 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); | |
2848 | ||
2849 | /* rldcr - rldcr. */ | |
2850 | static inline void gen_rldcr(DisasContext *ctx, int men) | |
2851 | { | |
2852 | uint32_t me; | |
2853 | ||
2854 | me = MB(ctx->opcode) | (men << 5); | |
2855 | gen_rldnm(ctx, 0, me); | |
2856 | } | |
2857 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); | |
2858 | ||
2859 | /* rldimi - rldimi. */ | |
2860 | static void gen_rldimi(DisasContext *ctx, int mbn, int shn) | |
2861 | { | |
2862 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; | |
2863 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2864 | uint32_t sh = SH(ctx->opcode) | (shn << 5); | |
2865 | uint32_t mb = MB(ctx->opcode) | (mbn << 5); | |
2866 | uint32_t me = 63 - sh; | |
2867 | ||
2868 | if (mb <= me) { | |
2869 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
2870 | } else { | |
2871 | target_ulong mask = MASK(mb, me); | |
2872 | TCGv t1 = tcg_temp_new(); | |
2873 | ||
2874 | tcg_gen_rotli_tl(t1, t_rs, sh); | |
2875 | tcg_gen_andi_tl(t1, t1, mask); | |
2876 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2877 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
2878 | } | |
2879 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2880 | gen_set_Rc0(ctx, t_ra); | |
2881 | } | |
2882 | } | |
2883 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); | |
2884 | #endif | |
2885 | ||
2886 | /*** Integer shift ***/ | |
2887 | ||
2888 | /* slw & slw. */ | |
2889 | static void gen_slw(DisasContext *ctx) | |
2890 | { | |
2891 | TCGv t0, t1; | |
2892 | ||
2893 | t0 = tcg_temp_new(); | |
2894 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2895 | #if defined(TARGET_PPC64) | |
2896 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2897 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2898 | #else | |
2899 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2900 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2901 | #endif | |
2902 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2903 | t1 = tcg_temp_new(); | |
2904 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
2905 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2906 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
2907 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2908 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2909 | } | |
2910 | } | |
2911 | ||
2912 | /* sraw & sraw. */ | |
2913 | static void gen_sraw(DisasContext *ctx) | |
2914 | { | |
2915 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, | |
2916 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
2917 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2918 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2919 | } | |
2920 | } | |
2921 | ||
2922 | /* srawi & srawi. */ | |
2923 | static void gen_srawi(DisasContext *ctx) | |
2924 | { | |
2925 | int sh = SH(ctx->opcode); | |
2926 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
2927 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2928 | if (sh == 0) { | |
2929 | tcg_gen_ext32s_tl(dst, src); | |
2930 | tcg_gen_movi_tl(cpu_ca, 0); | |
2931 | if (is_isa300(ctx)) { | |
2932 | tcg_gen_movi_tl(cpu_ca32, 0); | |
2933 | } | |
2934 | } else { | |
2935 | TCGv t0; | |
2936 | tcg_gen_ext32s_tl(dst, src); | |
2937 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
2938 | t0 = tcg_temp_new(); | |
2939 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
2940 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2941 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
2942 | if (is_isa300(ctx)) { | |
2943 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
2944 | } | |
2945 | tcg_gen_sari_tl(dst, dst, sh); | |
2946 | } | |
2947 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2948 | gen_set_Rc0(ctx, dst); | |
2949 | } | |
2950 | } | |
2951 | ||
2952 | /* srw & srw. */ | |
2953 | static void gen_srw(DisasContext *ctx) | |
2954 | { | |
2955 | TCGv t0, t1; | |
2956 | ||
2957 | t0 = tcg_temp_new(); | |
2958 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2959 | #if defined(TARGET_PPC64) | |
2960 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2961 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2962 | #else | |
2963 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2964 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2965 | #endif | |
2966 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2967 | tcg_gen_ext32u_tl(t0, t0); | |
2968 | t1 = tcg_temp_new(); | |
2969 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
2970 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2971 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2972 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2973 | } | |
2974 | } | |
2975 | ||
2976 | #if defined(TARGET_PPC64) | |
2977 | /* sld & sld. */ | |
2978 | static void gen_sld(DisasContext *ctx) | |
2979 | { | |
2980 | TCGv t0, t1; | |
2981 | ||
2982 | t0 = tcg_temp_new(); | |
2983 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2984 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2985 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2986 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2987 | t1 = tcg_temp_new(); | |
2988 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2989 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2990 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2991 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2992 | } | |
2993 | } | |
2994 | ||
2995 | /* srad & srad. */ | |
2996 | static void gen_srad(DisasContext *ctx) | |
2997 | { | |
2998 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, | |
2999 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
3000 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
3001 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
3002 | } | |
3003 | } | |
3004 | /* sradi & sradi. */ | |
3005 | static inline void gen_sradi(DisasContext *ctx, int n) | |
3006 | { | |
3007 | int sh = SH(ctx->opcode) + (n << 5); | |
3008 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
3009 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
3010 | if (sh == 0) { | |
3011 | tcg_gen_mov_tl(dst, src); | |
3012 | tcg_gen_movi_tl(cpu_ca, 0); | |
3013 | if (is_isa300(ctx)) { | |
3014 | tcg_gen_movi_tl(cpu_ca32, 0); | |
3015 | } | |
3016 | } else { | |
3017 | TCGv t0; | |
3018 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
3019 | t0 = tcg_temp_new(); | |
3020 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
3021 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
3022 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
3023 | if (is_isa300(ctx)) { | |
3024 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); | |
3025 | } | |
3026 | tcg_gen_sari_tl(dst, src, sh); | |
3027 | } | |
3028 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
3029 | gen_set_Rc0(ctx, dst); | |
3030 | } | |
3031 | } | |
3032 | ||
3033 | static void gen_sradi0(DisasContext *ctx) | |
3034 | { | |
3035 | gen_sradi(ctx, 0); | |
3036 | } | |
3037 | ||
3038 | static void gen_sradi1(DisasContext *ctx) | |
3039 | { | |
3040 | gen_sradi(ctx, 1); | |
3041 | } | |
3042 | ||
3043 | /* extswsli & extswsli. */ | |
3044 | static inline void gen_extswsli(DisasContext *ctx, int n) | |
3045 | { | |
3046 | int sh = SH(ctx->opcode) + (n << 5); | |
3047 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
3048 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
3049 | ||
3050 | tcg_gen_ext32s_tl(dst, src); | |
3051 | tcg_gen_shli_tl(dst, dst, sh); | |
3052 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
3053 | gen_set_Rc0(ctx, dst); | |
3054 | } | |
3055 | } | |
3056 | ||
3057 | static void gen_extswsli0(DisasContext *ctx) | |
3058 | { | |
3059 | gen_extswsli(ctx, 0); | |
3060 | } | |
3061 | ||
3062 | static void gen_extswsli1(DisasContext *ctx) | |
3063 | { | |
3064 | gen_extswsli(ctx, 1); | |
3065 | } | |
3066 | ||
3067 | /* srd & srd. */ | |
3068 | static void gen_srd(DisasContext *ctx) | |
3069 | { | |
3070 | TCGv t0, t1; | |
3071 | ||
3072 | t0 = tcg_temp_new(); | |
3073 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
3074 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
3075 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
3076 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
3077 | t1 = tcg_temp_new(); | |
3078 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
3079 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
3080 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
3081 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
3082 | } | |
3083 | } | |
3084 | #endif | |
3085 | ||
3086 | /*** Addressing modes ***/ | |
3087 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
3088 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, | |
3089 | target_long maskl) | |
3090 | { | |
3091 | target_long simm = SIMM(ctx->opcode); | |
3092 | ||
3093 | simm &= ~maskl; | |
3094 | if (rA(ctx->opcode) == 0) { | |
3095 | if (NARROW_MODE(ctx)) { | |
3096 | simm = (uint32_t)simm; | |
3097 | } | |
3098 | tcg_gen_movi_tl(EA, simm); | |
3099 | } else if (likely(simm != 0)) { | |
3100 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); | |
3101 | if (NARROW_MODE(ctx)) { | |
3102 | tcg_gen_ext32u_tl(EA, EA); | |
3103 | } | |
3104 | } else { | |
3105 | if (NARROW_MODE(ctx)) { | |
3106 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
3107 | } else { | |
3108 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
3109 | } | |
3110 | } | |
3111 | } | |
3112 | ||
3113 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) | |
3114 | { | |
3115 | if (rA(ctx->opcode) == 0) { | |
3116 | if (NARROW_MODE(ctx)) { | |
3117 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
3118 | } else { | |
3119 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
3120 | } | |
3121 | } else { | |
3122 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
3123 | if (NARROW_MODE(ctx)) { | |
3124 | tcg_gen_ext32u_tl(EA, EA); | |
3125 | } | |
3126 | } | |
3127 | } | |
3128 | ||
3129 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) | |
3130 | { | |
3131 | if (rA(ctx->opcode) == 0) { | |
3132 | tcg_gen_movi_tl(EA, 0); | |
3133 | } else if (NARROW_MODE(ctx)) { | |
3134 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
3135 | } else { | |
3136 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
3137 | } | |
3138 | } | |
3139 | ||
3140 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, | |
3141 | target_long val) | |
3142 | { | |
3143 | tcg_gen_addi_tl(ret, arg1, val); | |
3144 | if (NARROW_MODE(ctx)) { | |
3145 | tcg_gen_ext32u_tl(ret, ret); | |
3146 | } | |
3147 | } | |
3148 | ||
3149 | static inline void gen_align_no_le(DisasContext *ctx) | |
3150 | { | |
3151 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, | |
3152 | (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); | |
3153 | } | |
3154 | ||
3155 | static TCGv do_ea_calc(DisasContext *ctx, int ra, TCGv displ) | |
3156 | { | |
3157 | TCGv ea = tcg_temp_new(); | |
3158 | if (ra) { | |
3159 | tcg_gen_add_tl(ea, cpu_gpr[ra], displ); | |
3160 | } else { | |
3161 | tcg_gen_mov_tl(ea, displ); | |
3162 | } | |
3163 | if (NARROW_MODE(ctx)) { | |
3164 | tcg_gen_ext32u_tl(ea, ea); | |
3165 | } | |
3166 | return ea; | |
3167 | } | |
3168 | ||
3169 | /*** Integer load ***/ | |
3170 | #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) | |
3171 | #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) | |
3172 | ||
3173 | #define GEN_QEMU_LOAD_TL(ldop, op) \ | |
3174 | static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ | |
3175 | TCGv val, \ | |
3176 | TCGv addr) \ | |
3177 | { \ | |
3178 | tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ | |
3179 | } | |
3180 | ||
3181 | GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) | |
3182 | GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) | |
3183 | GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) | |
3184 | GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) | |
3185 | GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) | |
3186 | ||
3187 | GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) | |
3188 | GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) | |
3189 | ||
3190 | #define GEN_QEMU_LOAD_64(ldop, op) \ | |
3191 | static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ | |
3192 | TCGv_i64 val, \ | |
3193 | TCGv addr) \ | |
3194 | { \ | |
3195 | tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ | |
3196 | } | |
3197 | ||
3198 | GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) | |
3199 | GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) | |
3200 | GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) | |
3201 | GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) | |
3202 | GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_UQ)) | |
3203 | ||
3204 | #if defined(TARGET_PPC64) | |
3205 | GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_UQ)) | |
3206 | #endif | |
3207 | ||
3208 | #define GEN_QEMU_STORE_TL(stop, op) \ | |
3209 | static void glue(gen_qemu_, stop)(DisasContext *ctx, \ | |
3210 | TCGv val, \ | |
3211 | TCGv addr) \ | |
3212 | { \ | |
3213 | tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ | |
3214 | } | |
3215 | ||
3216 | #if defined(TARGET_PPC64) || !defined(CONFIG_USER_ONLY) | |
3217 | GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) | |
3218 | #endif | |
3219 | GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) | |
3220 | GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) | |
3221 | ||
3222 | GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) | |
3223 | GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) | |
3224 | ||
3225 | #define GEN_QEMU_STORE_64(stop, op) \ | |
3226 | static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ | |
3227 | TCGv_i64 val, \ | |
3228 | TCGv addr) \ | |
3229 | { \ | |
3230 | tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ | |
3231 | } | |
3232 | ||
3233 | GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) | |
3234 | GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) | |
3235 | GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) | |
3236 | GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_UQ)) | |
3237 | ||
3238 | #if defined(TARGET_PPC64) | |
3239 | GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ)) | |
3240 | #endif | |
3241 | ||
3242 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ | |
3243 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
3244 | { \ | |
3245 | TCGv EA; \ | |
3246 | chk(ctx); \ | |
3247 | gen_set_access_type(ctx, ACCESS_INT); \ | |
3248 | EA = tcg_temp_new(); \ | |
3249 | gen_addr_reg_index(ctx, EA); \ | |
3250 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
3251 | } | |
3252 | ||
3253 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ | |
3254 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) | |
3255 | ||
3256 | #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ | |
3257 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
3258 | ||
3259 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ | |
3260 | static void glue(gen_, name##epx)(DisasContext *ctx) \ | |
3261 | { \ | |
3262 | TCGv EA; \ | |
3263 | CHK_SV(ctx); \ | |
3264 | gen_set_access_type(ctx, ACCESS_INT); \ | |
3265 | EA = tcg_temp_new(); \ | |
3266 | gen_addr_reg_index(ctx, EA); \ | |
3267 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ | |
3268 | } | |
3269 | ||
3270 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) | |
3271 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) | |
3272 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) | |
3273 | #if defined(TARGET_PPC64) | |
3274 | GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) | |
3275 | #endif | |
3276 | ||
3277 | #if defined(TARGET_PPC64) | |
3278 | /* CI load/store variants */ | |
3279 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) | |
3280 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) | |
3281 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
3282 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
3283 | #endif | |
3284 | ||
3285 | /*** Integer store ***/ | |
3286 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ | |
3287 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
3288 | { \ | |
3289 | TCGv EA; \ | |
3290 | chk(ctx); \ | |
3291 | gen_set_access_type(ctx, ACCESS_INT); \ | |
3292 | EA = tcg_temp_new(); \ | |
3293 | gen_addr_reg_index(ctx, EA); \ | |
3294 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
3295 | } | |
3296 | #define GEN_STX(name, stop, opc2, opc3, type) \ | |
3297 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) | |
3298 | ||
3299 | #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ | |
3300 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
3301 | ||
3302 | #define GEN_STEPX(name, stop, opc2, opc3) \ | |
3303 | static void glue(gen_, name##epx)(DisasContext *ctx) \ | |
3304 | { \ | |
3305 | TCGv EA; \ | |
3306 | CHK_SV(ctx); \ | |
3307 | gen_set_access_type(ctx, ACCESS_INT); \ | |
3308 | EA = tcg_temp_new(); \ | |
3309 | gen_addr_reg_index(ctx, EA); \ | |
3310 | tcg_gen_qemu_st_tl( \ | |
3311 | cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ | |
3312 | } | |
3313 | ||
3314 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) | |
3315 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) | |
3316 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) | |
3317 | #if defined(TARGET_PPC64) | |
3318 | GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1d, 0x04) | |
3319 | #endif | |
3320 | ||
3321 | #if defined(TARGET_PPC64) | |
3322 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) | |
3323 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) | |
3324 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
3325 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
3326 | #endif | |
3327 | /*** Integer load and store with byte reverse ***/ | |
3328 | ||
3329 | /* lhbrx */ | |
3330 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); | |
3331 | ||
3332 | /* lwbrx */ | |
3333 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); | |
3334 | ||
3335 | #if defined(TARGET_PPC64) | |
3336 | /* ldbrx */ | |
3337 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); | |
3338 | /* stdbrx */ | |
3339 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); | |
3340 | #endif /* TARGET_PPC64 */ | |
3341 | ||
3342 | /* sthbrx */ | |
3343 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); | |
3344 | /* stwbrx */ | |
3345 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); | |
3346 | ||
3347 | /*** Integer load and store multiple ***/ | |
3348 | ||
3349 | /* lmw */ | |
3350 | static void gen_lmw(DisasContext *ctx) | |
3351 | { | |
3352 | TCGv t0; | |
3353 | TCGv_i32 t1; | |
3354 | ||
3355 | if (ctx->le_mode) { | |
3356 | gen_align_no_le(ctx); | |
3357 | return; | |
3358 | } | |
3359 | gen_set_access_type(ctx, ACCESS_INT); | |
3360 | t0 = tcg_temp_new(); | |
3361 | t1 = tcg_constant_i32(rD(ctx->opcode)); | |
3362 | gen_addr_imm_index(ctx, t0, 0); | |
3363 | gen_helper_lmw(tcg_env, t0, t1); | |
3364 | } | |
3365 | ||
3366 | /* stmw */ | |
3367 | static void gen_stmw(DisasContext *ctx) | |
3368 | { | |
3369 | TCGv t0; | |
3370 | TCGv_i32 t1; | |
3371 | ||
3372 | if (ctx->le_mode) { | |
3373 | gen_align_no_le(ctx); | |
3374 | return; | |
3375 | } | |
3376 | gen_set_access_type(ctx, ACCESS_INT); | |
3377 | t0 = tcg_temp_new(); | |
3378 | t1 = tcg_constant_i32(rS(ctx->opcode)); | |
3379 | gen_addr_imm_index(ctx, t0, 0); | |
3380 | gen_helper_stmw(tcg_env, t0, t1); | |
3381 | } | |
3382 | ||
3383 | /*** Integer load and store strings ***/ | |
3384 | ||
3385 | /* lswi */ | |
3386 | /* | |
3387 | * PowerPC32 specification says we must generate an exception if rA is | |
3388 | * in the range of registers to be loaded. In an other hand, IBM says | |
3389 | * this is valid, but rA won't be loaded. For now, I'll follow the | |
3390 | * spec... | |
3391 | */ | |
3392 | static void gen_lswi(DisasContext *ctx) | |
3393 | { | |
3394 | TCGv t0; | |
3395 | TCGv_i32 t1, t2; | |
3396 | int nb = NB(ctx->opcode); | |
3397 | int start = rD(ctx->opcode); | |
3398 | int ra = rA(ctx->opcode); | |
3399 | int nr; | |
3400 | ||
3401 | if (ctx->le_mode) { | |
3402 | gen_align_no_le(ctx); | |
3403 | return; | |
3404 | } | |
3405 | if (nb == 0) { | |
3406 | nb = 32; | |
3407 | } | |
3408 | nr = DIV_ROUND_UP(nb, 4); | |
3409 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { | |
3410 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
3411 | return; | |
3412 | } | |
3413 | gen_set_access_type(ctx, ACCESS_INT); | |
3414 | t0 = tcg_temp_new(); | |
3415 | gen_addr_register(ctx, t0); | |
3416 | t1 = tcg_constant_i32(nb); | |
3417 | t2 = tcg_constant_i32(start); | |
3418 | gen_helper_lsw(tcg_env, t0, t1, t2); | |
3419 | } | |
3420 | ||
3421 | /* lswx */ | |
3422 | static void gen_lswx(DisasContext *ctx) | |
3423 | { | |
3424 | TCGv t0; | |
3425 | TCGv_i32 t1, t2, t3; | |
3426 | ||
3427 | if (ctx->le_mode) { | |
3428 | gen_align_no_le(ctx); | |
3429 | return; | |
3430 | } | |
3431 | gen_set_access_type(ctx, ACCESS_INT); | |
3432 | t0 = tcg_temp_new(); | |
3433 | gen_addr_reg_index(ctx, t0); | |
3434 | t1 = tcg_constant_i32(rD(ctx->opcode)); | |
3435 | t2 = tcg_constant_i32(rA(ctx->opcode)); | |
3436 | t3 = tcg_constant_i32(rB(ctx->opcode)); | |
3437 | gen_helper_lswx(tcg_env, t0, t1, t2, t3); | |
3438 | } | |
3439 | ||
3440 | /* stswi */ | |
3441 | static void gen_stswi(DisasContext *ctx) | |
3442 | { | |
3443 | TCGv t0; | |
3444 | TCGv_i32 t1, t2; | |
3445 | int nb = NB(ctx->opcode); | |
3446 | ||
3447 | if (ctx->le_mode) { | |
3448 | gen_align_no_le(ctx); | |
3449 | return; | |
3450 | } | |
3451 | gen_set_access_type(ctx, ACCESS_INT); | |
3452 | t0 = tcg_temp_new(); | |
3453 | gen_addr_register(ctx, t0); | |
3454 | if (nb == 0) { | |
3455 | nb = 32; | |
3456 | } | |
3457 | t1 = tcg_constant_i32(nb); | |
3458 | t2 = tcg_constant_i32(rS(ctx->opcode)); | |
3459 | gen_helper_stsw(tcg_env, t0, t1, t2); | |
3460 | } | |
3461 | ||
3462 | /* stswx */ | |
3463 | static void gen_stswx(DisasContext *ctx) | |
3464 | { | |
3465 | TCGv t0; | |
3466 | TCGv_i32 t1, t2; | |
3467 | ||
3468 | if (ctx->le_mode) { | |
3469 | gen_align_no_le(ctx); | |
3470 | return; | |
3471 | } | |
3472 | gen_set_access_type(ctx, ACCESS_INT); | |
3473 | t0 = tcg_temp_new(); | |
3474 | gen_addr_reg_index(ctx, t0); | |
3475 | t1 = tcg_temp_new_i32(); | |
3476 | tcg_gen_trunc_tl_i32(t1, cpu_xer); | |
3477 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
3478 | t2 = tcg_constant_i32(rS(ctx->opcode)); | |
3479 | gen_helper_stsw(tcg_env, t0, t1, t2); | |
3480 | } | |
3481 | ||
3482 | /*** Memory synchronisation ***/ | |
3483 | /* eieio */ | |
3484 | static void gen_eieio(DisasContext *ctx) | |
3485 | { | |
3486 | TCGBar bar = TCG_MO_ALL; | |
3487 | ||
3488 | /* | |
3489 | * eieio has complex semanitcs. It provides memory ordering between | |
3490 | * operations in the set: | |
3491 | * - loads from CI memory. | |
3492 | * - stores to CI memory. | |
3493 | * - stores to WT memory. | |
3494 | * | |
3495 | * It separately also orders memory for operations in the set: | |
3496 | * - stores to cacheble memory. | |
3497 | * | |
3498 | * It also serializes instructions: | |
3499 | * - dcbt and dcbst. | |
3500 | * | |
3501 | * It separately serializes: | |
3502 | * - tlbie and tlbsync. | |
3503 | * | |
3504 | * And separately serializes: | |
3505 | * - slbieg, slbiag, and slbsync. | |
3506 | * | |
3507 | * The end result is that CI memory ordering requires TCG_MO_ALL | |
3508 | * and it is not possible to special-case more relaxed ordering for | |
3509 | * cacheable accesses. TCG_BAR_SC is required to provide this | |
3510 | * serialization. | |
3511 | */ | |
3512 | ||
3513 | /* | |
3514 | * POWER9 has a eieio instruction variant using bit 6 as a hint to | |
3515 | * tell the CPU it is a store-forwarding barrier. | |
3516 | */ | |
3517 | if (ctx->opcode & 0x2000000) { | |
3518 | /* | |
3519 | * ISA says that "Reserved fields in instructions are ignored | |
3520 | * by the processor". So ignore the bit 6 on non-POWER9 CPU but | |
3521 | * as this is not an instruction software should be using, | |
3522 | * complain to the user. | |
3523 | */ | |
3524 | if (!(ctx->insns_flags2 & PPC2_ISA300)) { | |
3525 | qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" | |
3526 | TARGET_FMT_lx "\n", ctx->cia); | |
3527 | } else { | |
3528 | bar = TCG_MO_ST_LD; | |
3529 | } | |
3530 | } | |
3531 | ||
3532 | tcg_gen_mb(bar | TCG_BAR_SC); | |
3533 | } | |
3534 | ||
3535 | #if !defined(CONFIG_USER_ONLY) | |
3536 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) | |
3537 | { | |
3538 | TCGv_i32 t; | |
3539 | TCGLabel *l; | |
3540 | ||
3541 | if (!ctx->lazy_tlb_flush) { | |
3542 | return; | |
3543 | } | |
3544 | l = gen_new_label(); | |
3545 | t = tcg_temp_new_i32(); | |
3546 | tcg_gen_ld_i32(t, tcg_env, offsetof(CPUPPCState, tlb_need_flush)); | |
3547 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); | |
3548 | if (global) { | |
3549 | gen_helper_check_tlb_flush_global(tcg_env); | |
3550 | } else { | |
3551 | gen_helper_check_tlb_flush_local(tcg_env); | |
3552 | } | |
3553 | gen_set_label(l); | |
3554 | } | |
3555 | #else | |
3556 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } | |
3557 | #endif | |
3558 | ||
3559 | /* isync */ | |
3560 | static void gen_isync(DisasContext *ctx) | |
3561 | { | |
3562 | /* | |
3563 | * We need to check for a pending TLB flush. This can only happen in | |
3564 | * kernel mode however so check MSR_PR | |
3565 | */ | |
3566 | if (!ctx->pr) { | |
3567 | gen_check_tlb_flush(ctx, false); | |
3568 | } | |
3569 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | |
3570 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
3571 | } | |
3572 | ||
3573 | #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) | |
3574 | ||
3575 | static void gen_load_locked(DisasContext *ctx, MemOp memop) | |
3576 | { | |
3577 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; | |
3578 | TCGv t0 = tcg_temp_new(); | |
3579 | ||
3580 | gen_set_access_type(ctx, ACCESS_RES); | |
3581 | gen_addr_reg_index(ctx, t0); | |
3582 | tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); | |
3583 | tcg_gen_mov_tl(cpu_reserve, t0); | |
3584 | tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop)); | |
3585 | tcg_gen_mov_tl(cpu_reserve_val, gpr); | |
3586 | } | |
3587 | ||
3588 | #define LARX(name, memop) \ | |
3589 | static void gen_##name(DisasContext *ctx) \ | |
3590 | { \ | |
3591 | gen_load_locked(ctx, memop); \ | |
3592 | } | |
3593 | ||
3594 | /* lwarx */ | |
3595 | LARX(lbarx, DEF_MEMOP(MO_UB)) | |
3596 | LARX(lharx, DEF_MEMOP(MO_UW)) | |
3597 | LARX(lwarx, DEF_MEMOP(MO_UL)) | |
3598 | ||
3599 | static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, | |
3600 | TCGv EA, TCGCond cond, int addend) | |
3601 | { | |
3602 | TCGv t = tcg_temp_new(); | |
3603 | TCGv t2 = tcg_temp_new(); | |
3604 | TCGv u = tcg_temp_new(); | |
3605 | ||
3606 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); | |
3607 | tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); | |
3608 | tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); | |
3609 | tcg_gen_addi_tl(u, t, addend); | |
3610 | ||
3611 | /* E.g. for fetch and increment bounded... */ | |
3612 | /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ | |
3613 | tcg_gen_movcond_tl(cond, u, t, t2, u, t); | |
3614 | tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); | |
3615 | ||
3616 | /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ | |
3617 | tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); | |
3618 | tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); | |
3619 | } | |
3620 | ||
3621 | static void gen_ld_atomic(DisasContext *ctx, MemOp memop) | |
3622 | { | |
3623 | uint32_t gpr_FC = FC(ctx->opcode); | |
3624 | TCGv EA = tcg_temp_new(); | |
3625 | int rt = rD(ctx->opcode); | |
3626 | bool need_serial; | |
3627 | TCGv src, dst; | |
3628 | ||
3629 | gen_addr_register(ctx, EA); | |
3630 | dst = cpu_gpr[rt]; | |
3631 | src = cpu_gpr[(rt + 1) & 31]; | |
3632 | ||
3633 | need_serial = false; | |
3634 | memop |= MO_ALIGN; | |
3635 | switch (gpr_FC) { | |
3636 | case 0: /* Fetch and add */ | |
3637 | tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); | |
3638 | break; | |
3639 | case 1: /* Fetch and xor */ | |
3640 | tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); | |
3641 | break; | |
3642 | case 2: /* Fetch and or */ | |
3643 | tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); | |
3644 | break; | |
3645 | case 3: /* Fetch and 'and' */ | |
3646 | tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); | |
3647 | break; | |
3648 | case 4: /* Fetch and max unsigned */ | |
3649 | tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); | |
3650 | break; | |
3651 | case 5: /* Fetch and max signed */ | |
3652 | tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); | |
3653 | break; | |
3654 | case 6: /* Fetch and min unsigned */ | |
3655 | tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); | |
3656 | break; | |
3657 | case 7: /* Fetch and min signed */ | |
3658 | tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); | |
3659 | break; | |
3660 | case 8: /* Swap */ | |
3661 | tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); | |
3662 | break; | |
3663 | ||
3664 | case 16: /* Compare and swap not equal */ | |
3665 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3666 | need_serial = true; | |
3667 | } else { | |
3668 | TCGv t0 = tcg_temp_new(); | |
3669 | TCGv t1 = tcg_temp_new(); | |
3670 | ||
3671 | tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); | |
3672 | if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { | |
3673 | tcg_gen_mov_tl(t1, src); | |
3674 | } else { | |
3675 | tcg_gen_ext32u_tl(t1, src); | |
3676 | } | |
3677 | tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, | |
3678 | cpu_gpr[(rt + 2) & 31], t0); | |
3679 | tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); | |
3680 | tcg_gen_mov_tl(dst, t0); | |
3681 | } | |
3682 | break; | |
3683 | ||
3684 | case 24: /* Fetch and increment bounded */ | |
3685 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3686 | need_serial = true; | |
3687 | } else { | |
3688 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); | |
3689 | } | |
3690 | break; | |
3691 | case 25: /* Fetch and increment equal */ | |
3692 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3693 | need_serial = true; | |
3694 | } else { | |
3695 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); | |
3696 | } | |
3697 | break; | |
3698 | case 28: /* Fetch and decrement bounded */ | |
3699 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3700 | need_serial = true; | |
3701 | } else { | |
3702 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); | |
3703 | } | |
3704 | break; | |
3705 | ||
3706 | default: | |
3707 | /* invoke data storage error handler */ | |
3708 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3709 | } | |
3710 | ||
3711 | if (need_serial) { | |
3712 | /* Restart with exclusive lock. */ | |
3713 | gen_helper_exit_atomic(tcg_env); | |
3714 | ctx->base.is_jmp = DISAS_NORETURN; | |
3715 | } | |
3716 | } | |
3717 | ||
3718 | static void gen_lwat(DisasContext *ctx) | |
3719 | { | |
3720 | gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3721 | } | |
3722 | ||
3723 | #ifdef TARGET_PPC64 | |
3724 | static void gen_ldat(DisasContext *ctx) | |
3725 | { | |
3726 | gen_ld_atomic(ctx, DEF_MEMOP(MO_UQ)); | |
3727 | } | |
3728 | #endif | |
3729 | ||
3730 | static void gen_st_atomic(DisasContext *ctx, MemOp memop) | |
3731 | { | |
3732 | uint32_t gpr_FC = FC(ctx->opcode); | |
3733 | TCGv EA = tcg_temp_new(); | |
3734 | TCGv src, discard; | |
3735 | ||
3736 | gen_addr_register(ctx, EA); | |
3737 | src = cpu_gpr[rD(ctx->opcode)]; | |
3738 | discard = tcg_temp_new(); | |
3739 | ||
3740 | memop |= MO_ALIGN; | |
3741 | switch (gpr_FC) { | |
3742 | case 0: /* add and Store */ | |
3743 | tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3744 | break; | |
3745 | case 1: /* xor and Store */ | |
3746 | tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3747 | break; | |
3748 | case 2: /* Or and Store */ | |
3749 | tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3750 | break; | |
3751 | case 3: /* 'and' and Store */ | |
3752 | tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3753 | break; | |
3754 | case 4: /* Store max unsigned */ | |
3755 | tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3756 | break; | |
3757 | case 5: /* Store max signed */ | |
3758 | tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3759 | break; | |
3760 | case 6: /* Store min unsigned */ | |
3761 | tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3762 | break; | |
3763 | case 7: /* Store min signed */ | |
3764 | tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); | |
3765 | break; | |
3766 | case 24: /* Store twin */ | |
3767 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { | |
3768 | /* Restart with exclusive lock. */ | |
3769 | gen_helper_exit_atomic(tcg_env); | |
3770 | ctx->base.is_jmp = DISAS_NORETURN; | |
3771 | } else { | |
3772 | TCGv t = tcg_temp_new(); | |
3773 | TCGv t2 = tcg_temp_new(); | |
3774 | TCGv s = tcg_temp_new(); | |
3775 | TCGv s2 = tcg_temp_new(); | |
3776 | TCGv ea_plus_s = tcg_temp_new(); | |
3777 | ||
3778 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); | |
3779 | tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); | |
3780 | tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); | |
3781 | tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); | |
3782 | tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); | |
3783 | tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); | |
3784 | tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); | |
3785 | } | |
3786 | break; | |
3787 | default: | |
3788 | /* invoke data storage error handler */ | |
3789 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); | |
3790 | } | |
3791 | } | |
3792 | ||
3793 | static void gen_stwat(DisasContext *ctx) | |
3794 | { | |
3795 | gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); | |
3796 | } | |
3797 | ||
3798 | #ifdef TARGET_PPC64 | |
3799 | static void gen_stdat(DisasContext *ctx) | |
3800 | { | |
3801 | gen_st_atomic(ctx, DEF_MEMOP(MO_UQ)); | |
3802 | } | |
3803 | #endif | |
3804 | ||
3805 | static void gen_conditional_store(DisasContext *ctx, MemOp memop) | |
3806 | { | |
3807 | TCGLabel *lfail; | |
3808 | TCGv EA; | |
3809 | TCGv cr0; | |
3810 | TCGv t0; | |
3811 | int rs = rS(ctx->opcode); | |
3812 | ||
3813 | lfail = gen_new_label(); | |
3814 | EA = tcg_temp_new(); | |
3815 | cr0 = tcg_temp_new(); | |
3816 | t0 = tcg_temp_new(); | |
3817 | ||
3818 | tcg_gen_mov_tl(cr0, cpu_so); | |
3819 | gen_set_access_type(ctx, ACCESS_RES); | |
3820 | gen_addr_reg_index(ctx, EA); | |
3821 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); | |
3822 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, memop_size(memop), lfail); | |
3823 | ||
3824 | tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, | |
3825 | cpu_gpr[rs], ctx->mem_idx, | |
3826 | DEF_MEMOP(memop) | MO_ALIGN); | |
3827 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); | |
3828 | tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); | |
3829 | tcg_gen_or_tl(cr0, cr0, t0); | |
3830 | ||
3831 | gen_set_label(lfail); | |
3832 | tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); | |
3833 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3834 | } | |
3835 | ||
3836 | #define STCX(name, memop) \ | |
3837 | static void gen_##name(DisasContext *ctx) \ | |
3838 | { \ | |
3839 | gen_conditional_store(ctx, memop); \ | |
3840 | } | |
3841 | ||
3842 | STCX(stbcx_, DEF_MEMOP(MO_UB)) | |
3843 | STCX(sthcx_, DEF_MEMOP(MO_UW)) | |
3844 | STCX(stwcx_, DEF_MEMOP(MO_UL)) | |
3845 | ||
3846 | #if defined(TARGET_PPC64) | |
3847 | /* ldarx */ | |
3848 | LARX(ldarx, DEF_MEMOP(MO_UQ)) | |
3849 | /* stdcx. */ | |
3850 | STCX(stdcx_, DEF_MEMOP(MO_UQ)) | |
3851 | ||
3852 | /* lqarx */ | |
3853 | static void gen_lqarx(DisasContext *ctx) | |
3854 | { | |
3855 | int rd = rD(ctx->opcode); | |
3856 | TCGv EA, hi, lo; | |
3857 | TCGv_i128 t16; | |
3858 | ||
3859 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3860 | (rd == rB(ctx->opcode)))) { | |
3861 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3862 | return; | |
3863 | } | |
3864 | ||
3865 | gen_set_access_type(ctx, ACCESS_RES); | |
3866 | EA = tcg_temp_new(); | |
3867 | gen_addr_reg_index(ctx, EA); | |
3868 | ||
3869 | /* Note that the low part is always in RD+1, even in LE mode. */ | |
3870 | lo = cpu_gpr[rd + 1]; | |
3871 | hi = cpu_gpr[rd]; | |
3872 | ||
3873 | t16 = tcg_temp_new_i128(); | |
3874 | tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 | MO_ALIGN)); | |
3875 | tcg_gen_extr_i128_i64(lo, hi, t16); | |
3876 | ||
3877 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3878 | tcg_gen_movi_tl(cpu_reserve_length, 16); | |
3879 | tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); | |
3880 | tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); | |
3881 | } | |
3882 | ||
3883 | /* stqcx. */ | |
3884 | static void gen_stqcx_(DisasContext *ctx) | |
3885 | { | |
3886 | TCGLabel *lfail; | |
3887 | TCGv EA, t0, t1; | |
3888 | TCGv cr0; | |
3889 | TCGv_i128 cmp, val; | |
3890 | int rs = rS(ctx->opcode); | |
3891 | ||
3892 | if (unlikely(rs & 1)) { | |
3893 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3894 | return; | |
3895 | } | |
3896 | ||
3897 | lfail = gen_new_label(); | |
3898 | EA = tcg_temp_new(); | |
3899 | cr0 = tcg_temp_new(); | |
3900 | ||
3901 | tcg_gen_mov_tl(cr0, cpu_so); | |
3902 | gen_set_access_type(ctx, ACCESS_RES); | |
3903 | gen_addr_reg_index(ctx, EA); | |
3904 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail); | |
3905 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_length, 16, lfail); | |
3906 | ||
3907 | cmp = tcg_temp_new_i128(); | |
3908 | val = tcg_temp_new_i128(); | |
3909 | ||
3910 | tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); | |
3911 | ||
3912 | /* Note that the low part is always in RS+1, even in LE mode. */ | |
3913 | tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); | |
3914 | ||
3915 | tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, | |
3916 | DEF_MEMOP(MO_128 | MO_ALIGN)); | |
3917 | ||
3918 | t0 = tcg_temp_new(); | |
3919 | t1 = tcg_temp_new(); | |
3920 | tcg_gen_extr_i128_i64(t1, t0, val); | |
3921 | ||
3922 | tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); | |
3923 | tcg_gen_xor_tl(t0, t0, cpu_reserve_val); | |
3924 | tcg_gen_or_tl(t0, t0, t1); | |
3925 | ||
3926 | tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); | |
3927 | tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); | |
3928 | tcg_gen_or_tl(cr0, cr0, t0); | |
3929 | ||
3930 | gen_set_label(lfail); | |
3931 | tcg_gen_trunc_tl_i32(cpu_crf[0], cr0); | |
3932 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3933 | } | |
3934 | #endif /* defined(TARGET_PPC64) */ | |
3935 | ||
3936 | /* sync */ | |
3937 | static void gen_sync(DisasContext *ctx) | |
3938 | { | |
3939 | TCGBar bar = TCG_MO_ALL; | |
3940 | uint32_t l = (ctx->opcode >> 21) & 3; | |
3941 | ||
3942 | if ((l == 1) && (ctx->insns_flags2 & PPC2_MEM_LWSYNC)) { | |
3943 | bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST; | |
3944 | } | |
3945 | ||
3946 | /* | |
3947 | * We may need to check for a pending TLB flush. | |
3948 | * | |
3949 | * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. | |
3950 | * | |
3951 | * Additionally, this can only happen in kernel mode however so | |
3952 | * check MSR_PR as well. | |
3953 | */ | |
3954 | if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { | |
3955 | gen_check_tlb_flush(ctx, true); | |
3956 | } | |
3957 | ||
3958 | tcg_gen_mb(bar | TCG_BAR_SC); | |
3959 | } | |
3960 | ||
3961 | /* wait */ | |
3962 | static void gen_wait(DisasContext *ctx) | |
3963 | { | |
3964 | uint32_t wc; | |
3965 | ||
3966 | if (ctx->insns_flags & PPC_WAIT) { | |
3967 | /* v2.03-v2.07 define an older incompatible 'wait' encoding. */ | |
3968 | ||
3969 | if (ctx->insns_flags2 & PPC2_PM_ISA206) { | |
3970 | /* v2.06 introduced the WC field. WC > 0 may be treated as no-op. */ | |
3971 | wc = WC(ctx->opcode); | |
3972 | } else { | |
3973 | wc = 0; | |
3974 | } | |
3975 | ||
3976 | } else if (ctx->insns_flags2 & PPC2_ISA300) { | |
3977 | /* v3.0 defines a new 'wait' encoding. */ | |
3978 | wc = WC(ctx->opcode); | |
3979 | if (ctx->insns_flags2 & PPC2_ISA310) { | |
3980 | uint32_t pl = PL(ctx->opcode); | |
3981 | ||
3982 | /* WC 1,2 may be treated as no-op. WC 3 is reserved. */ | |
3983 | if (wc == 3) { | |
3984 | gen_invalid(ctx); | |
3985 | return; | |
3986 | } | |
3987 | ||
3988 | /* PL 1-3 are reserved. If WC=2 then the insn is treated as noop. */ | |
3989 | if (pl > 0 && wc != 2) { | |
3990 | gen_invalid(ctx); | |
3991 | return; | |
3992 | } | |
3993 | ||
3994 | } else { /* ISA300 */ | |
3995 | /* WC 1-3 are reserved */ | |
3996 | if (wc > 0) { | |
3997 | gen_invalid(ctx); | |
3998 | return; | |
3999 | } | |
4000 | } | |
4001 | ||
4002 | } else { | |
4003 | warn_report("wait instruction decoded with wrong ISA flags."); | |
4004 | gen_invalid(ctx); | |
4005 | return; | |
4006 | } | |
4007 | ||
4008 | /* | |
4009 | * wait without WC field or with WC=0 waits for an exception / interrupt | |
4010 | * to occur. | |
4011 | */ | |
4012 | if (wc == 0) { | |
4013 | TCGv_i32 t0 = tcg_constant_i32(1); | |
4014 | tcg_gen_st_i32(t0, tcg_env, | |
4015 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
4016 | /* Stop translation, as the CPU is supposed to sleep from now */ | |
4017 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
4018 | } | |
4019 | ||
4020 | /* | |
4021 | * Other wait types must not just wait until an exception occurs because | |
4022 | * ignoring their other wake-up conditions could cause a hang. | |
4023 | * | |
4024 | * For v2.06 and 2.07, wc=1,2,3 are architected but may be implemented as | |
4025 | * no-ops. | |
4026 | * | |
4027 | * wc=1 and wc=3 explicitly allow the instruction to be treated as a no-op. | |
4028 | * | |
4029 | * wc=2 waits for an implementation-specific condition, such could be | |
4030 | * always true, so it can be implemented as a no-op. | |
4031 | * | |
4032 | * For v3.1, wc=1,2 are architected but may be implemented as no-ops. | |
4033 | * | |
4034 | * wc=1 (waitrsv) waits for an exception or a reservation to be lost. | |
4035 | * Reservation-loss may have implementation-specific conditions, so it | |
4036 | * can be implemented as a no-op. | |
4037 | * | |
4038 | * wc=2 waits for an exception or an amount of time to pass. This | |
4039 | * amount is implementation-specific so it can be implemented as a | |
4040 | * no-op. | |
4041 | * | |
4042 | * ISA v3.1 allows for execution to resume "in the rare case of | |
4043 | * an implementation-dependent event", so in any case software must | |
4044 | * not depend on the architected resumption condition to become | |
4045 | * true, so no-op implementations should be architecturally correct | |
4046 | * (if suboptimal). | |
4047 | */ | |
4048 | } | |
4049 | ||
4050 | #if defined(TARGET_PPC64) | |
4051 | static void gen_doze(DisasContext *ctx) | |
4052 | { | |
4053 | #if defined(CONFIG_USER_ONLY) | |
4054 | GEN_PRIV(ctx); | |
4055 | #else | |
4056 | TCGv_i32 t; | |
4057 | ||
4058 | CHK_HV(ctx); | |
4059 | translator_io_start(&ctx->base); | |
4060 | t = tcg_constant_i32(PPC_PM_DOZE); | |
4061 | gen_helper_pminsn(tcg_env, t); | |
4062 | /* Stop translation, as the CPU is supposed to sleep from now */ | |
4063 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
4064 | #endif /* defined(CONFIG_USER_ONLY) */ | |
4065 | } | |
4066 | ||
4067 | static void gen_nap(DisasContext *ctx) | |
4068 | { | |
4069 | #if defined(CONFIG_USER_ONLY) | |
4070 | GEN_PRIV(ctx); | |
4071 | #else | |
4072 | TCGv_i32 t; | |
4073 | ||
4074 | CHK_HV(ctx); | |
4075 | translator_io_start(&ctx->base); | |
4076 | t = tcg_constant_i32(PPC_PM_NAP); | |
4077 | gen_helper_pminsn(tcg_env, t); | |
4078 | /* Stop translation, as the CPU is supposed to sleep from now */ | |
4079 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
4080 | #endif /* defined(CONFIG_USER_ONLY) */ | |
4081 | } | |
4082 | ||
4083 | static void gen_stop(DisasContext *ctx) | |
4084 | { | |
4085 | #if defined(CONFIG_USER_ONLY) | |
4086 | GEN_PRIV(ctx); | |
4087 | #else | |
4088 | TCGv_i32 t; | |
4089 | ||
4090 | CHK_HV(ctx); | |
4091 | translator_io_start(&ctx->base); | |
4092 | t = tcg_constant_i32(PPC_PM_STOP); | |
4093 | gen_helper_pminsn(tcg_env, t); | |
4094 | /* Stop translation, as the CPU is supposed to sleep from now */ | |
4095 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
4096 | #endif /* defined(CONFIG_USER_ONLY) */ | |
4097 | } | |
4098 | ||
4099 | static void gen_sleep(DisasContext *ctx) | |
4100 | { | |
4101 | #if defined(CONFIG_USER_ONLY) | |
4102 | GEN_PRIV(ctx); | |
4103 | #else | |
4104 | TCGv_i32 t; | |
4105 | ||
4106 | CHK_HV(ctx); | |
4107 | translator_io_start(&ctx->base); | |
4108 | t = tcg_constant_i32(PPC_PM_SLEEP); | |
4109 | gen_helper_pminsn(tcg_env, t); | |
4110 | /* Stop translation, as the CPU is supposed to sleep from now */ | |
4111 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
4112 | #endif /* defined(CONFIG_USER_ONLY) */ | |
4113 | } | |
4114 | ||
4115 | static void gen_rvwinkle(DisasContext *ctx) | |
4116 | { | |
4117 | #if defined(CONFIG_USER_ONLY) | |
4118 | GEN_PRIV(ctx); | |
4119 | #else | |
4120 | TCGv_i32 t; | |
4121 | ||
4122 | CHK_HV(ctx); | |
4123 | translator_io_start(&ctx->base); | |
4124 | t = tcg_constant_i32(PPC_PM_RVWINKLE); | |
4125 | gen_helper_pminsn(tcg_env, t); | |
4126 | /* Stop translation, as the CPU is supposed to sleep from now */ | |
4127 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); | |
4128 | #endif /* defined(CONFIG_USER_ONLY) */ | |
4129 | } | |
4130 | #endif /* #if defined(TARGET_PPC64) */ | |
4131 | ||
4132 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) | |
4133 | { | |
4134 | #if defined(TARGET_PPC64) | |
4135 | if (ctx->has_cfar) { | |
4136 | tcg_gen_movi_tl(cpu_cfar, nip); | |
4137 | } | |
4138 | #endif | |
4139 | } | |
4140 | ||
4141 | #if defined(TARGET_PPC64) | |
4142 | static void pmu_count_insns(DisasContext *ctx) | |
4143 | { | |
4144 | /* | |
4145 | * Do not bother calling the helper if the PMU isn't counting | |
4146 | * instructions. | |
4147 | */ | |
4148 | if (!ctx->pmu_insn_cnt) { | |
4149 | return; | |
4150 | } | |
4151 | ||
4152 | #if !defined(CONFIG_USER_ONLY) | |
4153 | TCGLabel *l; | |
4154 | TCGv t0; | |
4155 | ||
4156 | /* | |
4157 | * The PMU insns_inc() helper stops the internal PMU timer if a | |
4158 | * counter overflows happens. In that case, if the guest is | |
4159 | * running with icount and we do not handle it beforehand, | |
4160 | * the helper can trigger a 'bad icount read'. | |
4161 | */ | |
4162 | translator_io_start(&ctx->base); | |
4163 | ||
4164 | /* Avoid helper calls when only PMC5-6 are enabled. */ | |
4165 | if (!ctx->pmc_other) { | |
4166 | l = gen_new_label(); | |
4167 | t0 = tcg_temp_new(); | |
4168 | ||
4169 | gen_load_spr(t0, SPR_POWER_PMC5); | |
4170 | tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); | |
4171 | gen_store_spr(SPR_POWER_PMC5, t0); | |
4172 | /* Check for overflow, if it's enabled */ | |
4173 | if (ctx->mmcr0_pmcjce) { | |
4174 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, l); | |
4175 | gen_helper_handle_pmc5_overflow(tcg_env); | |
4176 | } | |
4177 | ||
4178 | gen_set_label(l); | |
4179 | } else { | |
4180 | gen_helper_insns_inc(tcg_env, tcg_constant_i32(ctx->base.num_insns)); | |
4181 | } | |
4182 | #else | |
4183 | /* | |
4184 | * User mode can read (but not write) PMC5 and start/stop | |
4185 | * the PMU via MMCR0_FC. In this case just increment | |
4186 | * PMC5 with base.num_insns. | |
4187 | */ | |
4188 | TCGv t0 = tcg_temp_new(); | |
4189 | ||
4190 | gen_load_spr(t0, SPR_POWER_PMC5); | |
4191 | tcg_gen_addi_tl(t0, t0, ctx->base.num_insns); | |
4192 | gen_store_spr(SPR_POWER_PMC5, t0); | |
4193 | #endif /* #if !defined(CONFIG_USER_ONLY) */ | |
4194 | } | |
4195 | #else | |
4196 | static void pmu_count_insns(DisasContext *ctx) | |
4197 | { | |
4198 | return; | |
4199 | } | |
4200 | #endif /* #if defined(TARGET_PPC64) */ | |
4201 | ||
4202 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) | |
4203 | { | |
4204 | if (unlikely(ctx->singlestep_enabled)) { | |
4205 | return false; | |
4206 | } | |
4207 | return translator_use_goto_tb(&ctx->base, dest); | |
4208 | } | |
4209 | ||
4210 | static void gen_lookup_and_goto_ptr(DisasContext *ctx) | |
4211 | { | |
4212 | if (unlikely(ctx->singlestep_enabled)) { | |
4213 | gen_debug_exception(ctx, false); | |
4214 | } else { | |
4215 | /* | |
4216 | * tcg_gen_lookup_and_goto_ptr will exit the TB if | |
4217 | * CF_NO_GOTO_PTR is set. Count insns now. | |
4218 | */ | |
4219 | if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { | |
4220 | pmu_count_insns(ctx); | |
4221 | } | |
4222 | ||
4223 | tcg_gen_lookup_and_goto_ptr(); | |
4224 | } | |
4225 | } | |
4226 | ||
4227 | /*** Branch ***/ | |
4228 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) | |
4229 | { | |
4230 | if (NARROW_MODE(ctx)) { | |
4231 | dest = (uint32_t) dest; | |
4232 | } | |
4233 | if (use_goto_tb(ctx, dest)) { | |
4234 | pmu_count_insns(ctx); | |
4235 | tcg_gen_goto_tb(n); | |
4236 | tcg_gen_movi_tl(cpu_nip, dest & ~3); | |
4237 | tcg_gen_exit_tb(ctx->base.tb, n); | |
4238 | } else { | |
4239 | tcg_gen_movi_tl(cpu_nip, dest & ~3); | |
4240 | gen_lookup_and_goto_ptr(ctx); | |
4241 | } | |
4242 | } | |
4243 | ||
4244 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) | |
4245 | { | |
4246 | if (NARROW_MODE(ctx)) { | |
4247 | nip = (uint32_t)nip; | |
4248 | } | |
4249 | tcg_gen_movi_tl(cpu_lr, nip); | |
4250 | } | |
4251 | ||
4252 | /* b ba bl bla */ | |
4253 | static void gen_b(DisasContext *ctx) | |
4254 | { | |
4255 | target_ulong li, target; | |
4256 | ||
4257 | /* sign extend LI */ | |
4258 | li = LI(ctx->opcode); | |
4259 | li = (li ^ 0x02000000) - 0x02000000; | |
4260 | if (likely(AA(ctx->opcode) == 0)) { | |
4261 | target = ctx->cia + li; | |
4262 | } else { | |
4263 | target = li; | |
4264 | } | |
4265 | if (LK(ctx->opcode)) { | |
4266 | gen_setlr(ctx, ctx->base.pc_next); | |
4267 | } | |
4268 | gen_update_cfar(ctx, ctx->cia); | |
4269 | gen_goto_tb(ctx, 0, target); | |
4270 | ctx->base.is_jmp = DISAS_NORETURN; | |
4271 | } | |
4272 | ||
4273 | #define BCOND_IM 0 | |
4274 | #define BCOND_LR 1 | |
4275 | #define BCOND_CTR 2 | |
4276 | #define BCOND_TAR 3 | |
4277 | ||
4278 | static void gen_bcond(DisasContext *ctx, int type) | |
4279 | { | |
4280 | uint32_t bo = BO(ctx->opcode); | |
4281 | TCGLabel *l1; | |
4282 | TCGv target; | |
4283 | ||
4284 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { | |
4285 | target = tcg_temp_new(); | |
4286 | if (type == BCOND_CTR) { | |
4287 | tcg_gen_mov_tl(target, cpu_ctr); | |
4288 | } else if (type == BCOND_TAR) { | |
4289 | gen_load_spr(target, SPR_TAR); | |
4290 | } else { | |
4291 | tcg_gen_mov_tl(target, cpu_lr); | |
4292 | } | |
4293 | } else { | |
4294 | target = NULL; | |
4295 | } | |
4296 | if (LK(ctx->opcode)) { | |
4297 | gen_setlr(ctx, ctx->base.pc_next); | |
4298 | } | |
4299 | l1 = gen_new_label(); | |
4300 | if ((bo & 0x4) == 0) { | |
4301 | /* Decrement and test CTR */ | |
4302 | TCGv temp = tcg_temp_new(); | |
4303 | ||
4304 | if (type == BCOND_CTR) { | |
4305 | /* | |
4306 | * All ISAs up to v3 describe this form of bcctr as invalid but | |
4307 | * some processors, ie. 64-bit server processors compliant with | |
4308 | * arch 2.x, do implement a "test and decrement" logic instead, | |
4309 | * as described in their respective UMs. This logic involves CTR | |
4310 | * to act as both the branch target and a counter, which makes | |
4311 | * it basically useless and thus never used in real code. | |
4312 | * | |
4313 | * This form was hence chosen to trigger extra micro-architectural | |
4314 | * side-effect on real HW needed for the Spectre v2 workaround. | |
4315 | * It is up to guests that implement such workaround, ie. linux, to | |
4316 | * use this form in a way it just triggers the side-effect without | |
4317 | * doing anything else harmful. | |
4318 | */ | |
4319 | if (unlikely(!is_book3s_arch2x(ctx))) { | |
4320 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
4321 | return; | |
4322 | } | |
4323 | ||
4324 | if (NARROW_MODE(ctx)) { | |
4325 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
4326 | } else { | |
4327 | tcg_gen_mov_tl(temp, cpu_ctr); | |
4328 | } | |
4329 | if (bo & 0x2) { | |
4330 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
4331 | } else { | |
4332 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
4333 | } | |
4334 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
4335 | } else { | |
4336 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
4337 | if (NARROW_MODE(ctx)) { | |
4338 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
4339 | } else { | |
4340 | tcg_gen_mov_tl(temp, cpu_ctr); | |
4341 | } | |
4342 | if (bo & 0x2) { | |
4343 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
4344 | } else { | |
4345 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
4346 | } | |
4347 | } | |
4348 | } | |
4349 | if ((bo & 0x10) == 0) { | |
4350 | /* Test CR */ | |
4351 | uint32_t bi = BI(ctx->opcode); | |
4352 | uint32_t mask = 0x08 >> (bi & 0x03); | |
4353 | TCGv_i32 temp = tcg_temp_new_i32(); | |
4354 | ||
4355 | if (bo & 0x8) { | |
4356 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); | |
4357 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
4358 | } else { | |
4359 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); | |
4360 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
4361 | } | |
4362 | } | |
4363 | gen_update_cfar(ctx, ctx->cia); | |
4364 | if (type == BCOND_IM) { | |
4365 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); | |
4366 | if (likely(AA(ctx->opcode) == 0)) { | |
4367 | gen_goto_tb(ctx, 0, ctx->cia + li); | |
4368 | } else { | |
4369 | gen_goto_tb(ctx, 0, li); | |
4370 | } | |
4371 | } else { | |
4372 | if (NARROW_MODE(ctx)) { | |
4373 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); | |
4374 | } else { | |
4375 | tcg_gen_andi_tl(cpu_nip, target, ~3); | |
4376 | } | |
4377 | gen_lookup_and_goto_ptr(ctx); | |
4378 | } | |
4379 | if ((bo & 0x14) != 0x14) { | |
4380 | /* fallthrough case */ | |
4381 | gen_set_label(l1); | |
4382 | gen_goto_tb(ctx, 1, ctx->base.pc_next); | |
4383 | } | |
4384 | ctx->base.is_jmp = DISAS_NORETURN; | |
4385 | } | |
4386 | ||
4387 | static void gen_bc(DisasContext *ctx) | |
4388 | { | |
4389 | gen_bcond(ctx, BCOND_IM); | |
4390 | } | |
4391 | ||
4392 | static void gen_bcctr(DisasContext *ctx) | |
4393 | { | |
4394 | gen_bcond(ctx, BCOND_CTR); | |
4395 | } | |
4396 | ||
4397 | static void gen_bclr(DisasContext *ctx) | |
4398 | { | |
4399 | gen_bcond(ctx, BCOND_LR); | |
4400 | } | |
4401 | ||
4402 | static void gen_bctar(DisasContext *ctx) | |
4403 | { | |
4404 | gen_bcond(ctx, BCOND_TAR); | |
4405 | } | |
4406 | ||
4407 | /*** Condition register logical ***/ | |
4408 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
4409 | static void glue(gen_, name)(DisasContext *ctx) \ | |
4410 | { \ | |
4411 | uint8_t bitmask; \ | |
4412 | int sh; \ | |
4413 | TCGv_i32 t0, t1; \ | |
4414 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ | |
4415 | t0 = tcg_temp_new_i32(); \ | |
4416 | if (sh > 0) \ | |
4417 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ | |
4418 | else if (sh < 0) \ | |
4419 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ | |
4420 | else \ | |
4421 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ | |
4422 | t1 = tcg_temp_new_i32(); \ | |
4423 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ | |
4424 | if (sh > 0) \ | |
4425 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ | |
4426 | else if (sh < 0) \ | |
4427 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ | |
4428 | else \ | |
4429 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ | |
4430 | tcg_op(t0, t0, t1); \ | |
4431 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ | |
4432 | tcg_gen_andi_i32(t0, t0, bitmask); \ | |
4433 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
4434 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
4435 | } | |
4436 | ||
4437 | /* crand */ | |
4438 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); | |
4439 | /* crandc */ | |
4440 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); | |
4441 | /* creqv */ | |
4442 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); | |
4443 | /* crnand */ | |
4444 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); | |
4445 | /* crnor */ | |
4446 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); | |
4447 | /* cror */ | |
4448 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); | |
4449 | /* crorc */ | |
4450 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); | |
4451 | /* crxor */ | |
4452 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); | |
4453 | ||
4454 | /* mcrf */ | |
4455 | static void gen_mcrf(DisasContext *ctx) | |
4456 | { | |
4457 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); | |
4458 | } | |
4459 | ||
4460 | /*** System linkage ***/ | |
4461 | ||
4462 | /* rfi (supervisor only) */ | |
4463 | static void gen_rfi(DisasContext *ctx) | |
4464 | { | |
4465 | #if defined(CONFIG_USER_ONLY) | |
4466 | GEN_PRIV(ctx); | |
4467 | #else | |
4468 | /* | |
4469 | * This instruction doesn't exist anymore on 64-bit server | |
4470 | * processors compliant with arch 2.x | |
4471 | */ | |
4472 | if (is_book3s_arch2x(ctx)) { | |
4473 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
4474 | return; | |
4475 | } | |
4476 | /* Restore CPU state */ | |
4477 | CHK_SV(ctx); | |
4478 | translator_io_start(&ctx->base); | |
4479 | gen_update_cfar(ctx, ctx->cia); | |
4480 | gen_helper_rfi(tcg_env); | |
4481 | ctx->base.is_jmp = DISAS_EXIT; | |
4482 | #endif | |
4483 | } | |
4484 | ||
4485 | #if defined(TARGET_PPC64) | |
4486 | static void gen_rfid(DisasContext *ctx) | |
4487 | { | |
4488 | #if defined(CONFIG_USER_ONLY) | |
4489 | GEN_PRIV(ctx); | |
4490 | #else | |
4491 | /* Restore CPU state */ | |
4492 | CHK_SV(ctx); | |
4493 | translator_io_start(&ctx->base); | |
4494 | gen_update_cfar(ctx, ctx->cia); | |
4495 | gen_helper_rfid(tcg_env); | |
4496 | ctx->base.is_jmp = DISAS_EXIT; | |
4497 | #endif | |
4498 | } | |
4499 | ||
4500 | #if !defined(CONFIG_USER_ONLY) | |
4501 | static void gen_rfscv(DisasContext *ctx) | |
4502 | { | |
4503 | #if defined(CONFIG_USER_ONLY) | |
4504 | GEN_PRIV(ctx); | |
4505 | #else | |
4506 | /* Restore CPU state */ | |
4507 | CHK_SV(ctx); | |
4508 | translator_io_start(&ctx->base); | |
4509 | gen_update_cfar(ctx, ctx->cia); | |
4510 | gen_helper_rfscv(tcg_env); | |
4511 | ctx->base.is_jmp = DISAS_EXIT; | |
4512 | #endif | |
4513 | } | |
4514 | #endif | |
4515 | ||
4516 | static void gen_hrfid(DisasContext *ctx) | |
4517 | { | |
4518 | #if defined(CONFIG_USER_ONLY) | |
4519 | GEN_PRIV(ctx); | |
4520 | #else | |
4521 | /* Restore CPU state */ | |
4522 | CHK_HV(ctx); | |
4523 | translator_io_start(&ctx->base); | |
4524 | gen_helper_hrfid(tcg_env); | |
4525 | ctx->base.is_jmp = DISAS_EXIT; | |
4526 | #endif | |
4527 | } | |
4528 | #endif | |
4529 | ||
4530 | /* sc */ | |
4531 | #if defined(CONFIG_USER_ONLY) | |
4532 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
4533 | #else | |
4534 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
4535 | #endif | |
4536 | static void gen_sc(DisasContext *ctx) | |
4537 | { | |
4538 | uint32_t lev; | |
4539 | ||
4540 | /* | |
4541 | * LEV is a 7-bit field, but the top 6 bits are treated as a reserved | |
4542 | * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is | |
4543 | * for Ultravisor which TCG does not support, so just ignore the top 6. | |
4544 | */ | |
4545 | lev = (ctx->opcode >> 5) & 0x1; | |
4546 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); | |
4547 | } | |
4548 | ||
4549 | #if defined(TARGET_PPC64) | |
4550 | #if !defined(CONFIG_USER_ONLY) | |
4551 | static void gen_scv(DisasContext *ctx) | |
4552 | { | |
4553 | uint32_t lev = (ctx->opcode >> 5) & 0x7F; | |
4554 | ||
4555 | /* Set the PC back to the faulting instruction. */ | |
4556 | gen_update_nip(ctx, ctx->cia); | |
4557 | gen_helper_scv(tcg_env, tcg_constant_i32(lev)); | |
4558 | ||
4559 | ctx->base.is_jmp = DISAS_NORETURN; | |
4560 | } | |
4561 | #endif | |
4562 | #endif | |
4563 | ||
4564 | /*** Trap ***/ | |
4565 | ||
4566 | /* Check for unconditional traps (always or never) */ | |
4567 | static bool check_unconditional_trap(DisasContext *ctx) | |
4568 | { | |
4569 | /* Trap never */ | |
4570 | if (TO(ctx->opcode) == 0) { | |
4571 | return true; | |
4572 | } | |
4573 | /* Trap always */ | |
4574 | if (TO(ctx->opcode) == 31) { | |
4575 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); | |
4576 | return true; | |
4577 | } | |
4578 | return false; | |
4579 | } | |
4580 | ||
4581 | /* tw */ | |
4582 | static void gen_tw(DisasContext *ctx) | |
4583 | { | |
4584 | TCGv_i32 t0; | |
4585 | ||
4586 | if (check_unconditional_trap(ctx)) { | |
4587 | return; | |
4588 | } | |
4589 | t0 = tcg_constant_i32(TO(ctx->opcode)); | |
4590 | gen_helper_tw(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
4591 | t0); | |
4592 | } | |
4593 | ||
4594 | /* twi */ | |
4595 | static void gen_twi(DisasContext *ctx) | |
4596 | { | |
4597 | TCGv t0; | |
4598 | TCGv_i32 t1; | |
4599 | ||
4600 | if (check_unconditional_trap(ctx)) { | |
4601 | return; | |
4602 | } | |
4603 | t0 = tcg_constant_tl(SIMM(ctx->opcode)); | |
4604 | t1 = tcg_constant_i32(TO(ctx->opcode)); | |
4605 | gen_helper_tw(tcg_env, cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4606 | } | |
4607 | ||
4608 | #if defined(TARGET_PPC64) | |
4609 | /* td */ | |
4610 | static void gen_td(DisasContext *ctx) | |
4611 | { | |
4612 | TCGv_i32 t0; | |
4613 | ||
4614 | if (check_unconditional_trap(ctx)) { | |
4615 | return; | |
4616 | } | |
4617 | t0 = tcg_constant_i32(TO(ctx->opcode)); | |
4618 | gen_helper_td(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
4619 | t0); | |
4620 | } | |
4621 | ||
4622 | /* tdi */ | |
4623 | static void gen_tdi(DisasContext *ctx) | |
4624 | { | |
4625 | TCGv t0; | |
4626 | TCGv_i32 t1; | |
4627 | ||
4628 | if (check_unconditional_trap(ctx)) { | |
4629 | return; | |
4630 | } | |
4631 | t0 = tcg_constant_tl(SIMM(ctx->opcode)); | |
4632 | t1 = tcg_constant_i32(TO(ctx->opcode)); | |
4633 | gen_helper_td(tcg_env, cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4634 | } | |
4635 | #endif | |
4636 | ||
4637 | /*** Processor control ***/ | |
4638 | ||
4639 | /* mcrxr */ | |
4640 | static void gen_mcrxr(DisasContext *ctx) | |
4641 | { | |
4642 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
4643 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4644 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4645 | ||
4646 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
4647 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
4648 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
4649 | tcg_gen_shli_i32(t0, t0, 3); | |
4650 | tcg_gen_shli_i32(t1, t1, 2); | |
4651 | tcg_gen_shli_i32(dst, dst, 1); | |
4652 | tcg_gen_or_i32(dst, dst, t0); | |
4653 | tcg_gen_or_i32(dst, dst, t1); | |
4654 | ||
4655 | tcg_gen_movi_tl(cpu_so, 0); | |
4656 | tcg_gen_movi_tl(cpu_ov, 0); | |
4657 | tcg_gen_movi_tl(cpu_ca, 0); | |
4658 | } | |
4659 | ||
4660 | #ifdef TARGET_PPC64 | |
4661 | /* mcrxrx */ | |
4662 | static void gen_mcrxrx(DisasContext *ctx) | |
4663 | { | |
4664 | TCGv t0 = tcg_temp_new(); | |
4665 | TCGv t1 = tcg_temp_new(); | |
4666 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4667 | ||
4668 | /* copy OV and OV32 */ | |
4669 | tcg_gen_shli_tl(t0, cpu_ov, 1); | |
4670 | tcg_gen_or_tl(t0, t0, cpu_ov32); | |
4671 | tcg_gen_shli_tl(t0, t0, 2); | |
4672 | /* copy CA and CA32 */ | |
4673 | tcg_gen_shli_tl(t1, cpu_ca, 1); | |
4674 | tcg_gen_or_tl(t1, t1, cpu_ca32); | |
4675 | tcg_gen_or_tl(t0, t0, t1); | |
4676 | tcg_gen_trunc_tl_i32(dst, t0); | |
4677 | } | |
4678 | #endif | |
4679 | ||
4680 | /* mfcr mfocrf */ | |
4681 | static void gen_mfcr(DisasContext *ctx) | |
4682 | { | |
4683 | uint32_t crm, crn; | |
4684 | ||
4685 | if (likely(ctx->opcode & 0x00100000)) { | |
4686 | crm = CRM(ctx->opcode); | |
4687 | if (likely(crm && ((crm & (crm - 1)) == 0))) { | |
4688 | crn = ctz32(crm); | |
4689 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); | |
4690 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], | |
4691 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
4692 | } | |
4693 | } else { | |
4694 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
4695 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
4696 | tcg_gen_shli_i32(t0, t0, 4); | |
4697 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
4698 | tcg_gen_shli_i32(t0, t0, 4); | |
4699 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
4700 | tcg_gen_shli_i32(t0, t0, 4); | |
4701 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
4702 | tcg_gen_shli_i32(t0, t0, 4); | |
4703 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
4704 | tcg_gen_shli_i32(t0, t0, 4); | |
4705 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
4706 | tcg_gen_shli_i32(t0, t0, 4); | |
4707 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
4708 | tcg_gen_shli_i32(t0, t0, 4); | |
4709 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
4710 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4711 | } | |
4712 | } | |
4713 | ||
4714 | /* mfmsr */ | |
4715 | static void gen_mfmsr(DisasContext *ctx) | |
4716 | { | |
4717 | CHK_SV(ctx); | |
4718 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); | |
4719 | } | |
4720 | ||
4721 | /* mfspr */ | |
4722 | static inline void gen_op_mfspr(DisasContext *ctx) | |
4723 | { | |
4724 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); | |
4725 | uint32_t sprn = SPR(ctx->opcode); | |
4726 | ||
4727 | #if defined(CONFIG_USER_ONLY) | |
4728 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4729 | #else | |
4730 | if (ctx->pr) { | |
4731 | read_cb = ctx->spr_cb[sprn].uea_read; | |
4732 | } else if (ctx->hv) { | |
4733 | read_cb = ctx->spr_cb[sprn].hea_read; | |
4734 | } else { | |
4735 | read_cb = ctx->spr_cb[sprn].oea_read; | |
4736 | } | |
4737 | #endif | |
4738 | if (likely(read_cb != NULL)) { | |
4739 | if (likely(read_cb != SPR_NOACCESS)) { | |
4740 | (*read_cb)(ctx, rD(ctx->opcode), sprn); | |
4741 | } else { | |
4742 | /* Privilege exception */ | |
4743 | /* | |
4744 | * This is a hack to avoid warnings when running Linux: | |
4745 | * this OS breaks the PowerPC virtualisation model, | |
4746 | * allowing userland application to read the PVR | |
4747 | */ | |
4748 | if (sprn != SPR_PVR) { | |
4749 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " | |
4750 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4751 | ctx->cia); | |
4752 | } | |
4753 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4754 | } | |
4755 | } else { | |
4756 | /* ISA 2.07 defines these as no-ops */ | |
4757 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4758 | (sprn >= 808 && sprn <= 811)) { | |
4759 | /* This is a nop */ | |
4760 | return; | |
4761 | } | |
4762 | /* Not defined */ | |
4763 | qemu_log_mask(LOG_GUEST_ERROR, | |
4764 | "Trying to read invalid spr %d (0x%03x) at " | |
4765 | TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); | |
4766 | ||
4767 | /* | |
4768 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can | |
4769 | * generate a priv, a hv emu or a no-op | |
4770 | */ | |
4771 | if (sprn & 0x10) { | |
4772 | if (ctx->pr) { | |
4773 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4774 | } | |
4775 | } else { | |
4776 | if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { | |
4777 | gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4778 | } | |
4779 | } | |
4780 | } | |
4781 | } | |
4782 | ||
4783 | static void gen_mfspr(DisasContext *ctx) | |
4784 | { | |
4785 | gen_op_mfspr(ctx); | |
4786 | } | |
4787 | ||
4788 | /* mftb */ | |
4789 | static void gen_mftb(DisasContext *ctx) | |
4790 | { | |
4791 | gen_op_mfspr(ctx); | |
4792 | } | |
4793 | ||
4794 | /* mtcrf mtocrf*/ | |
4795 | static void gen_mtcrf(DisasContext *ctx) | |
4796 | { | |
4797 | uint32_t crm, crn; | |
4798 | ||
4799 | crm = CRM(ctx->opcode); | |
4800 | if (likely((ctx->opcode & 0x00100000))) { | |
4801 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4802 | TCGv_i32 temp = tcg_temp_new_i32(); | |
4803 | crn = ctz32(crm); | |
4804 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4805 | tcg_gen_shri_i32(temp, temp, crn * 4); | |
4806 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
4807 | } | |
4808 | } else { | |
4809 | TCGv_i32 temp = tcg_temp_new_i32(); | |
4810 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4811 | for (crn = 0 ; crn < 8 ; crn++) { | |
4812 | if (crm & (1 << crn)) { | |
4813 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4814 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4815 | } | |
4816 | } | |
4817 | } | |
4818 | } | |
4819 | ||
4820 | /* mtmsr */ | |
4821 | #if defined(TARGET_PPC64) | |
4822 | static void gen_mtmsrd(DisasContext *ctx) | |
4823 | { | |
4824 | if (unlikely(!is_book3s_arch2x(ctx))) { | |
4825 | gen_invalid(ctx); | |
4826 | return; | |
4827 | } | |
4828 | ||
4829 | CHK_SV(ctx); | |
4830 | ||
4831 | #if !defined(CONFIG_USER_ONLY) | |
4832 | TCGv t0, t1; | |
4833 | target_ulong mask; | |
4834 | ||
4835 | t0 = tcg_temp_new(); | |
4836 | t1 = tcg_temp_new(); | |
4837 | ||
4838 | translator_io_start(&ctx->base); | |
4839 | ||
4840 | if (ctx->opcode & 0x00010000) { | |
4841 | /* L=1 form only updates EE and RI */ | |
4842 | mask = (1ULL << MSR_RI) | (1ULL << MSR_EE); | |
4843 | } else { | |
4844 | /* mtmsrd does not alter HV, S, ME, or LE */ | |
4845 | mask = ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S) | | |
4846 | (1ULL << MSR_HV)); | |
4847 | /* | |
4848 | * XXX: we need to update nip before the store if we enter | |
4849 | * power saving mode, we will exit the loop directly from | |
4850 | * ppc_store_msr | |
4851 | */ | |
4852 | gen_update_nip(ctx, ctx->base.pc_next); | |
4853 | } | |
4854 | ||
4855 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); | |
4856 | tcg_gen_andi_tl(t1, cpu_msr, ~mask); | |
4857 | tcg_gen_or_tl(t0, t0, t1); | |
4858 | ||
4859 | gen_helper_store_msr(tcg_env, t0); | |
4860 | ||
4861 | /* Must stop the translation as machine state (may have) changed */ | |
4862 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
4863 | #endif /* !defined(CONFIG_USER_ONLY) */ | |
4864 | } | |
4865 | #endif /* defined(TARGET_PPC64) */ | |
4866 | ||
4867 | static void gen_mtmsr(DisasContext *ctx) | |
4868 | { | |
4869 | CHK_SV(ctx); | |
4870 | ||
4871 | #if !defined(CONFIG_USER_ONLY) | |
4872 | TCGv t0, t1; | |
4873 | target_ulong mask = 0xFFFFFFFF; | |
4874 | ||
4875 | t0 = tcg_temp_new(); | |
4876 | t1 = tcg_temp_new(); | |
4877 | ||
4878 | translator_io_start(&ctx->base); | |
4879 | if (ctx->opcode & 0x00010000) { | |
4880 | /* L=1 form only updates EE and RI */ | |
4881 | mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); | |
4882 | } else { | |
4883 | /* mtmsr does not alter S, ME, or LE */ | |
4884 | mask &= ~((1ULL << MSR_LE) | (1ULL << MSR_ME) | (1ULL << MSR_S)); | |
4885 | ||
4886 | /* | |
4887 | * XXX: we need to update nip before the store if we enter | |
4888 | * power saving mode, we will exit the loop directly from | |
4889 | * ppc_store_msr | |
4890 | */ | |
4891 | gen_update_nip(ctx, ctx->base.pc_next); | |
4892 | } | |
4893 | ||
4894 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], mask); | |
4895 | tcg_gen_andi_tl(t1, cpu_msr, ~mask); | |
4896 | tcg_gen_or_tl(t0, t0, t1); | |
4897 | ||
4898 | gen_helper_store_msr(tcg_env, t0); | |
4899 | ||
4900 | /* Must stop the translation as machine state (may have) changed */ | |
4901 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
4902 | #endif | |
4903 | } | |
4904 | ||
4905 | /* mtspr */ | |
4906 | static void gen_mtspr(DisasContext *ctx) | |
4907 | { | |
4908 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); | |
4909 | uint32_t sprn = SPR(ctx->opcode); | |
4910 | ||
4911 | #if defined(CONFIG_USER_ONLY) | |
4912 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4913 | #else | |
4914 | if (ctx->pr) { | |
4915 | write_cb = ctx->spr_cb[sprn].uea_write; | |
4916 | } else if (ctx->hv) { | |
4917 | write_cb = ctx->spr_cb[sprn].hea_write; | |
4918 | } else { | |
4919 | write_cb = ctx->spr_cb[sprn].oea_write; | |
4920 | } | |
4921 | #endif | |
4922 | if (likely(write_cb != NULL)) { | |
4923 | if (likely(write_cb != SPR_NOACCESS)) { | |
4924 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); | |
4925 | } else { | |
4926 | /* Privilege exception */ | |
4927 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " | |
4928 | "%d (0x%03x) at " TARGET_FMT_lx "\n", sprn, sprn, | |
4929 | ctx->cia); | |
4930 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4931 | } | |
4932 | } else { | |
4933 | /* ISA 2.07 defines these as no-ops */ | |
4934 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4935 | (sprn >= 808 && sprn <= 811)) { | |
4936 | /* This is a nop */ | |
4937 | return; | |
4938 | } | |
4939 | ||
4940 | /* Not defined */ | |
4941 | qemu_log_mask(LOG_GUEST_ERROR, | |
4942 | "Trying to write invalid spr %d (0x%03x) at " | |
4943 | TARGET_FMT_lx "\n", sprn, sprn, ctx->cia); | |
4944 | ||
4945 | ||
4946 | /* | |
4947 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can | |
4948 | * generate a priv, a hv emu or a no-op | |
4949 | */ | |
4950 | if (sprn & 0x10) { | |
4951 | if (ctx->pr) { | |
4952 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4953 | } | |
4954 | } else { | |
4955 | if (ctx->pr || sprn == 0) { | |
4956 | gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4957 | } | |
4958 | } | |
4959 | } | |
4960 | } | |
4961 | ||
4962 | #if defined(TARGET_PPC64) | |
4963 | /* setb */ | |
4964 | static void gen_setb(DisasContext *ctx) | |
4965 | { | |
4966 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
4967 | TCGv_i32 t8 = tcg_constant_i32(8); | |
4968 | TCGv_i32 tm1 = tcg_constant_i32(-1); | |
4969 | int crf = crfS(ctx->opcode); | |
4970 | ||
4971 | tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); | |
4972 | tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); | |
4973 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4974 | } | |
4975 | #endif | |
4976 | ||
4977 | /*** Cache management ***/ | |
4978 | ||
4979 | /* dcbf */ | |
4980 | static void gen_dcbf(DisasContext *ctx) | |
4981 | { | |
4982 | /* XXX: specification says this is treated as a load by the MMU */ | |
4983 | TCGv t0; | |
4984 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4985 | t0 = tcg_temp_new(); | |
4986 | gen_addr_reg_index(ctx, t0); | |
4987 | gen_qemu_ld8u(ctx, t0, t0); | |
4988 | } | |
4989 | ||
4990 | /* dcbfep (external PID dcbf) */ | |
4991 | static void gen_dcbfep(DisasContext *ctx) | |
4992 | { | |
4993 | /* XXX: specification says this is treated as a load by the MMU */ | |
4994 | TCGv t0; | |
4995 | CHK_SV(ctx); | |
4996 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4997 | t0 = tcg_temp_new(); | |
4998 | gen_addr_reg_index(ctx, t0); | |
4999 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); | |
5000 | } | |
5001 | ||
5002 | /* dcbi (Supervisor only) */ | |
5003 | static void gen_dcbi(DisasContext *ctx) | |
5004 | { | |
5005 | #if defined(CONFIG_USER_ONLY) | |
5006 | GEN_PRIV(ctx); | |
5007 | #else | |
5008 | TCGv EA, val; | |
5009 | ||
5010 | CHK_SV(ctx); | |
5011 | EA = tcg_temp_new(); | |
5012 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5013 | gen_addr_reg_index(ctx, EA); | |
5014 | val = tcg_temp_new(); | |
5015 | /* XXX: specification says this should be treated as a store by the MMU */ | |
5016 | gen_qemu_ld8u(ctx, val, EA); | |
5017 | gen_qemu_st8(ctx, val, EA); | |
5018 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5019 | } | |
5020 | ||
5021 | /* dcdst */ | |
5022 | static void gen_dcbst(DisasContext *ctx) | |
5023 | { | |
5024 | /* XXX: specification say this is treated as a load by the MMU */ | |
5025 | TCGv t0; | |
5026 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5027 | t0 = tcg_temp_new(); | |
5028 | gen_addr_reg_index(ctx, t0); | |
5029 | gen_qemu_ld8u(ctx, t0, t0); | |
5030 | } | |
5031 | ||
5032 | /* dcbstep (dcbstep External PID version) */ | |
5033 | static void gen_dcbstep(DisasContext *ctx) | |
5034 | { | |
5035 | /* XXX: specification say this is treated as a load by the MMU */ | |
5036 | TCGv t0; | |
5037 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5038 | t0 = tcg_temp_new(); | |
5039 | gen_addr_reg_index(ctx, t0); | |
5040 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); | |
5041 | } | |
5042 | ||
5043 | /* dcbt */ | |
5044 | static void gen_dcbt(DisasContext *ctx) | |
5045 | { | |
5046 | /* | |
5047 | * interpreted as no-op | |
5048 | * XXX: specification say this is treated as a load by the MMU but | |
5049 | * does not generate any exception | |
5050 | */ | |
5051 | } | |
5052 | ||
5053 | /* dcbtep */ | |
5054 | static void gen_dcbtep(DisasContext *ctx) | |
5055 | { | |
5056 | /* | |
5057 | * interpreted as no-op | |
5058 | * XXX: specification say this is treated as a load by the MMU but | |
5059 | * does not generate any exception | |
5060 | */ | |
5061 | } | |
5062 | ||
5063 | /* dcbtst */ | |
5064 | static void gen_dcbtst(DisasContext *ctx) | |
5065 | { | |
5066 | /* | |
5067 | * interpreted as no-op | |
5068 | * XXX: specification say this is treated as a load by the MMU but | |
5069 | * does not generate any exception | |
5070 | */ | |
5071 | } | |
5072 | ||
5073 | /* dcbtstep */ | |
5074 | static void gen_dcbtstep(DisasContext *ctx) | |
5075 | { | |
5076 | /* | |
5077 | * interpreted as no-op | |
5078 | * XXX: specification say this is treated as a load by the MMU but | |
5079 | * does not generate any exception | |
5080 | */ | |
5081 | } | |
5082 | ||
5083 | /* dcbtls */ | |
5084 | static void gen_dcbtls(DisasContext *ctx) | |
5085 | { | |
5086 | /* Always fails locking the cache */ | |
5087 | TCGv t0 = tcg_temp_new(); | |
5088 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
5089 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
5090 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
5091 | } | |
5092 | ||
5093 | /* dcblc */ | |
5094 | static void gen_dcblc(DisasContext *ctx) | |
5095 | { | |
5096 | /* | |
5097 | * interpreted as no-op | |
5098 | */ | |
5099 | } | |
5100 | ||
5101 | /* dcbz */ | |
5102 | static void gen_dcbz(DisasContext *ctx) | |
5103 | { | |
5104 | TCGv tcgv_addr; | |
5105 | TCGv_i32 tcgv_op; | |
5106 | ||
5107 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5108 | tcgv_addr = tcg_temp_new(); | |
5109 | tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); | |
5110 | gen_addr_reg_index(ctx, tcgv_addr); | |
5111 | gen_helper_dcbz(tcg_env, tcgv_addr, tcgv_op); | |
5112 | } | |
5113 | ||
5114 | /* dcbzep */ | |
5115 | static void gen_dcbzep(DisasContext *ctx) | |
5116 | { | |
5117 | TCGv tcgv_addr; | |
5118 | TCGv_i32 tcgv_op; | |
5119 | ||
5120 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5121 | tcgv_addr = tcg_temp_new(); | |
5122 | tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000); | |
5123 | gen_addr_reg_index(ctx, tcgv_addr); | |
5124 | gen_helper_dcbzep(tcg_env, tcgv_addr, tcgv_op); | |
5125 | } | |
5126 | ||
5127 | /* dst / dstt */ | |
5128 | static void gen_dst(DisasContext *ctx) | |
5129 | { | |
5130 | if (rA(ctx->opcode) == 0) { | |
5131 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5132 | } else { | |
5133 | /* interpreted as no-op */ | |
5134 | } | |
5135 | } | |
5136 | ||
5137 | /* dstst /dststt */ | |
5138 | static void gen_dstst(DisasContext *ctx) | |
5139 | { | |
5140 | if (rA(ctx->opcode) == 0) { | |
5141 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5142 | } else { | |
5143 | /* interpreted as no-op */ | |
5144 | } | |
5145 | ||
5146 | } | |
5147 | ||
5148 | /* dss / dssall */ | |
5149 | static void gen_dss(DisasContext *ctx) | |
5150 | { | |
5151 | /* interpreted as no-op */ | |
5152 | } | |
5153 | ||
5154 | /* icbi */ | |
5155 | static void gen_icbi(DisasContext *ctx) | |
5156 | { | |
5157 | TCGv t0; | |
5158 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5159 | t0 = tcg_temp_new(); | |
5160 | gen_addr_reg_index(ctx, t0); | |
5161 | gen_helper_icbi(tcg_env, t0); | |
5162 | } | |
5163 | ||
5164 | /* icbiep */ | |
5165 | static void gen_icbiep(DisasContext *ctx) | |
5166 | { | |
5167 | TCGv t0; | |
5168 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5169 | t0 = tcg_temp_new(); | |
5170 | gen_addr_reg_index(ctx, t0); | |
5171 | gen_helper_icbiep(tcg_env, t0); | |
5172 | } | |
5173 | ||
5174 | /* Optional: */ | |
5175 | /* dcba */ | |
5176 | static void gen_dcba(DisasContext *ctx) | |
5177 | { | |
5178 | /* | |
5179 | * interpreted as no-op | |
5180 | * XXX: specification say this is treated as a store by the MMU | |
5181 | * but does not generate any exception | |
5182 | */ | |
5183 | } | |
5184 | ||
5185 | /*** Segment register manipulation ***/ | |
5186 | /* Supervisor only: */ | |
5187 | ||
5188 | /* mfsr */ | |
5189 | static void gen_mfsr(DisasContext *ctx) | |
5190 | { | |
5191 | #if defined(CONFIG_USER_ONLY) | |
5192 | GEN_PRIV(ctx); | |
5193 | #else | |
5194 | TCGv t0; | |
5195 | ||
5196 | CHK_SV(ctx); | |
5197 | t0 = tcg_constant_tl(SR(ctx->opcode)); | |
5198 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); | |
5199 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5200 | } | |
5201 | ||
5202 | /* mfsrin */ | |
5203 | static void gen_mfsrin(DisasContext *ctx) | |
5204 | { | |
5205 | #if defined(CONFIG_USER_ONLY) | |
5206 | GEN_PRIV(ctx); | |
5207 | #else | |
5208 | TCGv t0; | |
5209 | ||
5210 | CHK_SV(ctx); | |
5211 | t0 = tcg_temp_new(); | |
5212 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); | |
5213 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); | |
5214 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5215 | } | |
5216 | ||
5217 | /* mtsr */ | |
5218 | static void gen_mtsr(DisasContext *ctx) | |
5219 | { | |
5220 | #if defined(CONFIG_USER_ONLY) | |
5221 | GEN_PRIV(ctx); | |
5222 | #else | |
5223 | TCGv t0; | |
5224 | ||
5225 | CHK_SV(ctx); | |
5226 | t0 = tcg_constant_tl(SR(ctx->opcode)); | |
5227 | gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); | |
5228 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5229 | } | |
5230 | ||
5231 | /* mtsrin */ | |
5232 | static void gen_mtsrin(DisasContext *ctx) | |
5233 | { | |
5234 | #if defined(CONFIG_USER_ONLY) | |
5235 | GEN_PRIV(ctx); | |
5236 | #else | |
5237 | TCGv t0; | |
5238 | CHK_SV(ctx); | |
5239 | ||
5240 | t0 = tcg_temp_new(); | |
5241 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); | |
5242 | gen_helper_store_sr(tcg_env, t0, cpu_gpr[rD(ctx->opcode)]); | |
5243 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5244 | } | |
5245 | ||
5246 | #if defined(TARGET_PPC64) | |
5247 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
5248 | ||
5249 | /* mfsr */ | |
5250 | static void gen_mfsr_64b(DisasContext *ctx) | |
5251 | { | |
5252 | #if defined(CONFIG_USER_ONLY) | |
5253 | GEN_PRIV(ctx); | |
5254 | #else | |
5255 | TCGv t0; | |
5256 | ||
5257 | CHK_SV(ctx); | |
5258 | t0 = tcg_constant_tl(SR(ctx->opcode)); | |
5259 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); | |
5260 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5261 | } | |
5262 | ||
5263 | /* mfsrin */ | |
5264 | static void gen_mfsrin_64b(DisasContext *ctx) | |
5265 | { | |
5266 | #if defined(CONFIG_USER_ONLY) | |
5267 | GEN_PRIV(ctx); | |
5268 | #else | |
5269 | TCGv t0; | |
5270 | ||
5271 | CHK_SV(ctx); | |
5272 | t0 = tcg_temp_new(); | |
5273 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); | |
5274 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); | |
5275 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5276 | } | |
5277 | ||
5278 | /* mtsr */ | |
5279 | static void gen_mtsr_64b(DisasContext *ctx) | |
5280 | { | |
5281 | #if defined(CONFIG_USER_ONLY) | |
5282 | GEN_PRIV(ctx); | |
5283 | #else | |
5284 | TCGv t0; | |
5285 | ||
5286 | CHK_SV(ctx); | |
5287 | t0 = tcg_constant_tl(SR(ctx->opcode)); | |
5288 | gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); | |
5289 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5290 | } | |
5291 | ||
5292 | /* mtsrin */ | |
5293 | static void gen_mtsrin_64b(DisasContext *ctx) | |
5294 | { | |
5295 | #if defined(CONFIG_USER_ONLY) | |
5296 | GEN_PRIV(ctx); | |
5297 | #else | |
5298 | TCGv t0; | |
5299 | ||
5300 | CHK_SV(ctx); | |
5301 | t0 = tcg_temp_new(); | |
5302 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); | |
5303 | gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); | |
5304 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5305 | } | |
5306 | ||
5307 | #endif /* defined(TARGET_PPC64) */ | |
5308 | ||
5309 | /*** Lookaside buffer management ***/ | |
5310 | /* Optional & supervisor only: */ | |
5311 | ||
5312 | /* tlbia */ | |
5313 | static void gen_tlbia(DisasContext *ctx) | |
5314 | { | |
5315 | #if defined(CONFIG_USER_ONLY) | |
5316 | GEN_PRIV(ctx); | |
5317 | #else | |
5318 | CHK_HV(ctx); | |
5319 | ||
5320 | gen_helper_tlbia(tcg_env); | |
5321 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5322 | } | |
5323 | ||
5324 | /* tlbsync */ | |
5325 | static void gen_tlbsync(DisasContext *ctx) | |
5326 | { | |
5327 | #if defined(CONFIG_USER_ONLY) | |
5328 | GEN_PRIV(ctx); | |
5329 | #else | |
5330 | ||
5331 | if (ctx->gtse) { | |
5332 | CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */ | |
5333 | } else { | |
5334 | CHK_HV(ctx); /* Else hypervisor privileged */ | |
5335 | } | |
5336 | ||
5337 | /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ | |
5338 | if (ctx->insns_flags & PPC_BOOKE) { | |
5339 | gen_check_tlb_flush(ctx, true); | |
5340 | } | |
5341 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5342 | } | |
5343 | ||
5344 | /*** External control ***/ | |
5345 | /* Optional: */ | |
5346 | ||
5347 | /* eciwx */ | |
5348 | static void gen_eciwx(DisasContext *ctx) | |
5349 | { | |
5350 | TCGv t0; | |
5351 | /* Should check EAR[E] ! */ | |
5352 | gen_set_access_type(ctx, ACCESS_EXT); | |
5353 | t0 = tcg_temp_new(); | |
5354 | gen_addr_reg_index(ctx, t0); | |
5355 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, | |
5356 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
5357 | } | |
5358 | ||
5359 | /* ecowx */ | |
5360 | static void gen_ecowx(DisasContext *ctx) | |
5361 | { | |
5362 | TCGv t0; | |
5363 | /* Should check EAR[E] ! */ | |
5364 | gen_set_access_type(ctx, ACCESS_EXT); | |
5365 | t0 = tcg_temp_new(); | |
5366 | gen_addr_reg_index(ctx, t0); | |
5367 | tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, | |
5368 | DEF_MEMOP(MO_UL | MO_ALIGN)); | |
5369 | } | |
5370 | ||
5371 | /* 602 - 603 - G2 TLB management */ | |
5372 | ||
5373 | /* tlbld */ | |
5374 | static void gen_tlbld_6xx(DisasContext *ctx) | |
5375 | { | |
5376 | #if defined(CONFIG_USER_ONLY) | |
5377 | GEN_PRIV(ctx); | |
5378 | #else | |
5379 | CHK_SV(ctx); | |
5380 | gen_helper_6xx_tlbd(tcg_env, cpu_gpr[rB(ctx->opcode)]); | |
5381 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5382 | } | |
5383 | ||
5384 | /* tlbli */ | |
5385 | static void gen_tlbli_6xx(DisasContext *ctx) | |
5386 | { | |
5387 | #if defined(CONFIG_USER_ONLY) | |
5388 | GEN_PRIV(ctx); | |
5389 | #else | |
5390 | CHK_SV(ctx); | |
5391 | gen_helper_6xx_tlbi(tcg_env, cpu_gpr[rB(ctx->opcode)]); | |
5392 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5393 | } | |
5394 | ||
5395 | /* BookE specific instructions */ | |
5396 | ||
5397 | /* XXX: not implemented on 440 ? */ | |
5398 | static void gen_mfapidi(DisasContext *ctx) | |
5399 | { | |
5400 | /* XXX: TODO */ | |
5401 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5402 | } | |
5403 | ||
5404 | /* XXX: not implemented on 440 ? */ | |
5405 | static void gen_tlbiva(DisasContext *ctx) | |
5406 | { | |
5407 | #if defined(CONFIG_USER_ONLY) | |
5408 | GEN_PRIV(ctx); | |
5409 | #else | |
5410 | TCGv t0; | |
5411 | ||
5412 | CHK_SV(ctx); | |
5413 | t0 = tcg_temp_new(); | |
5414 | gen_addr_reg_index(ctx, t0); | |
5415 | gen_helper_tlbiva(tcg_env, cpu_gpr[rB(ctx->opcode)]); | |
5416 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5417 | } | |
5418 | ||
5419 | /* All 405 MAC instructions are translated here */ | |
5420 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, | |
5421 | int ra, int rb, int rt, int Rc) | |
5422 | { | |
5423 | TCGv t0, t1; | |
5424 | ||
5425 | t0 = tcg_temp_new(); | |
5426 | t1 = tcg_temp_new(); | |
5427 | ||
5428 | switch (opc3 & 0x0D) { | |
5429 | case 0x05: | |
5430 | /* macchw - macchw. - macchwo - macchwo. */ | |
5431 | /* macchws - macchws. - macchwso - macchwso. */ | |
5432 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5433 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5434 | /* mulchw - mulchw. */ | |
5435 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); | |
5436 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5437 | tcg_gen_ext16s_tl(t1, t1); | |
5438 | break; | |
5439 | case 0x04: | |
5440 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5441 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5442 | /* mulchwu - mulchwu. */ | |
5443 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); | |
5444 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5445 | tcg_gen_ext16u_tl(t1, t1); | |
5446 | break; | |
5447 | case 0x01: | |
5448 | /* machhw - machhw. - machhwo - machhwo. */ | |
5449 | /* machhws - machhws. - machhwso - machhwso. */ | |
5450 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5451 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5452 | /* mulhhw - mulhhw. */ | |
5453 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); | |
5454 | tcg_gen_ext16s_tl(t0, t0); | |
5455 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5456 | tcg_gen_ext16s_tl(t1, t1); | |
5457 | break; | |
5458 | case 0x00: | |
5459 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5460 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5461 | /* mulhhwu - mulhhwu. */ | |
5462 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); | |
5463 | tcg_gen_ext16u_tl(t0, t0); | |
5464 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5465 | tcg_gen_ext16u_tl(t1, t1); | |
5466 | break; | |
5467 | case 0x0D: | |
5468 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5469 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5470 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5471 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5472 | /* mullhw - mullhw. */ | |
5473 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); | |
5474 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
5475 | break; | |
5476 | case 0x0C: | |
5477 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5478 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5479 | /* mullhwu - mullhwu. */ | |
5480 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); | |
5481 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
5482 | break; | |
5483 | } | |
5484 | if (opc2 & 0x04) { | |
5485 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ | |
5486 | tcg_gen_mul_tl(t1, t0, t1); | |
5487 | if (opc2 & 0x02) { | |
5488 | /* nmultiply-and-accumulate (0x0E) */ | |
5489 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5490 | } else { | |
5491 | /* multiply-and-accumulate (0x0C) */ | |
5492 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5493 | } | |
5494 | ||
5495 | if (opc3 & 0x12) { | |
5496 | /* Check overflow and/or saturate */ | |
5497 | TCGLabel *l1 = gen_new_label(); | |
5498 | ||
5499 | if (opc3 & 0x10) { | |
5500 | /* Start with XER OV disabled, the most likely case */ | |
5501 | tcg_gen_movi_tl(cpu_ov, 0); | |
5502 | } | |
5503 | if (opc3 & 0x01) { | |
5504 | /* Signed */ | |
5505 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5506 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5507 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5508 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
5509 | if (opc3 & 0x02) { | |
5510 | /* Saturate */ | |
5511 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5512 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5513 | } | |
5514 | } else { | |
5515 | /* Unsigned */ | |
5516 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
5517 | if (opc3 & 0x02) { | |
5518 | /* Saturate */ | |
5519 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5520 | } | |
5521 | } | |
5522 | if (opc3 & 0x10) { | |
5523 | /* Check overflow */ | |
5524 | tcg_gen_movi_tl(cpu_ov, 1); | |
5525 | tcg_gen_movi_tl(cpu_so, 1); | |
5526 | } | |
5527 | gen_set_label(l1); | |
5528 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5529 | } | |
5530 | } else { | |
5531 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
5532 | } | |
5533 | if (unlikely(Rc) != 0) { | |
5534 | /* Update Rc0 */ | |
5535 | gen_set_Rc0(ctx, cpu_gpr[rt]); | |
5536 | } | |
5537 | } | |
5538 | ||
5539 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
5540 | static void glue(gen_, name)(DisasContext *ctx) \ | |
5541 | { \ | |
5542 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5543 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5544 | } | |
5545 | ||
5546 | /* macchw - macchw. */ | |
5547 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); | |
5548 | /* macchwo - macchwo. */ | |
5549 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); | |
5550 | /* macchws - macchws. */ | |
5551 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); | |
5552 | /* macchwso - macchwso. */ | |
5553 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); | |
5554 | /* macchwsu - macchwsu. */ | |
5555 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); | |
5556 | /* macchwsuo - macchwsuo. */ | |
5557 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); | |
5558 | /* macchwu - macchwu. */ | |
5559 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); | |
5560 | /* macchwuo - macchwuo. */ | |
5561 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); | |
5562 | /* machhw - machhw. */ | |
5563 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); | |
5564 | /* machhwo - machhwo. */ | |
5565 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); | |
5566 | /* machhws - machhws. */ | |
5567 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); | |
5568 | /* machhwso - machhwso. */ | |
5569 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); | |
5570 | /* machhwsu - machhwsu. */ | |
5571 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); | |
5572 | /* machhwsuo - machhwsuo. */ | |
5573 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); | |
5574 | /* machhwu - machhwu. */ | |
5575 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); | |
5576 | /* machhwuo - machhwuo. */ | |
5577 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); | |
5578 | /* maclhw - maclhw. */ | |
5579 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); | |
5580 | /* maclhwo - maclhwo. */ | |
5581 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); | |
5582 | /* maclhws - maclhws. */ | |
5583 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); | |
5584 | /* maclhwso - maclhwso. */ | |
5585 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); | |
5586 | /* maclhwu - maclhwu. */ | |
5587 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); | |
5588 | /* maclhwuo - maclhwuo. */ | |
5589 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); | |
5590 | /* maclhwsu - maclhwsu. */ | |
5591 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); | |
5592 | /* maclhwsuo - maclhwsuo. */ | |
5593 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); | |
5594 | /* nmacchw - nmacchw. */ | |
5595 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); | |
5596 | /* nmacchwo - nmacchwo. */ | |
5597 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); | |
5598 | /* nmacchws - nmacchws. */ | |
5599 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); | |
5600 | /* nmacchwso - nmacchwso. */ | |
5601 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); | |
5602 | /* nmachhw - nmachhw. */ | |
5603 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); | |
5604 | /* nmachhwo - nmachhwo. */ | |
5605 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); | |
5606 | /* nmachhws - nmachhws. */ | |
5607 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); | |
5608 | /* nmachhwso - nmachhwso. */ | |
5609 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); | |
5610 | /* nmaclhw - nmaclhw. */ | |
5611 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); | |
5612 | /* nmaclhwo - nmaclhwo. */ | |
5613 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); | |
5614 | /* nmaclhws - nmaclhws. */ | |
5615 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); | |
5616 | /* nmaclhwso - nmaclhwso. */ | |
5617 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); | |
5618 | ||
5619 | /* mulchw - mulchw. */ | |
5620 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); | |
5621 | /* mulchwu - mulchwu. */ | |
5622 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); | |
5623 | /* mulhhw - mulhhw. */ | |
5624 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); | |
5625 | /* mulhhwu - mulhhwu. */ | |
5626 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); | |
5627 | /* mullhw - mullhw. */ | |
5628 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); | |
5629 | /* mullhwu - mullhwu. */ | |
5630 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); | |
5631 | ||
5632 | /* mfdcr */ | |
5633 | static void gen_mfdcr(DisasContext *ctx) | |
5634 | { | |
5635 | #if defined(CONFIG_USER_ONLY) | |
5636 | GEN_PRIV(ctx); | |
5637 | #else | |
5638 | TCGv dcrn; | |
5639 | ||
5640 | CHK_SV(ctx); | |
5641 | dcrn = tcg_constant_tl(SPR(ctx->opcode)); | |
5642 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, dcrn); | |
5643 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5644 | } | |
5645 | ||
5646 | /* mtdcr */ | |
5647 | static void gen_mtdcr(DisasContext *ctx) | |
5648 | { | |
5649 | #if defined(CONFIG_USER_ONLY) | |
5650 | GEN_PRIV(ctx); | |
5651 | #else | |
5652 | TCGv dcrn; | |
5653 | ||
5654 | CHK_SV(ctx); | |
5655 | dcrn = tcg_constant_tl(SPR(ctx->opcode)); | |
5656 | gen_helper_store_dcr(tcg_env, dcrn, cpu_gpr[rS(ctx->opcode)]); | |
5657 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5658 | } | |
5659 | ||
5660 | /* mfdcrx */ | |
5661 | /* XXX: not implemented on 440 ? */ | |
5662 | static void gen_mfdcrx(DisasContext *ctx) | |
5663 | { | |
5664 | #if defined(CONFIG_USER_ONLY) | |
5665 | GEN_PRIV(ctx); | |
5666 | #else | |
5667 | CHK_SV(ctx); | |
5668 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, | |
5669 | cpu_gpr[rA(ctx->opcode)]); | |
5670 | /* Note: Rc update flag set leads to undefined state of Rc0 */ | |
5671 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5672 | } | |
5673 | ||
5674 | /* mtdcrx */ | |
5675 | /* XXX: not implemented on 440 ? */ | |
5676 | static void gen_mtdcrx(DisasContext *ctx) | |
5677 | { | |
5678 | #if defined(CONFIG_USER_ONLY) | |
5679 | GEN_PRIV(ctx); | |
5680 | #else | |
5681 | CHK_SV(ctx); | |
5682 | gen_helper_store_dcr(tcg_env, cpu_gpr[rA(ctx->opcode)], | |
5683 | cpu_gpr[rS(ctx->opcode)]); | |
5684 | /* Note: Rc update flag set leads to undefined state of Rc0 */ | |
5685 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5686 | } | |
5687 | ||
5688 | /* dccci */ | |
5689 | static void gen_dccci(DisasContext *ctx) | |
5690 | { | |
5691 | CHK_SV(ctx); | |
5692 | /* interpreted as no-op */ | |
5693 | } | |
5694 | ||
5695 | /* dcread */ | |
5696 | static void gen_dcread(DisasContext *ctx) | |
5697 | { | |
5698 | #if defined(CONFIG_USER_ONLY) | |
5699 | GEN_PRIV(ctx); | |
5700 | #else | |
5701 | TCGv EA, val; | |
5702 | ||
5703 | CHK_SV(ctx); | |
5704 | gen_set_access_type(ctx, ACCESS_CACHE); | |
5705 | EA = tcg_temp_new(); | |
5706 | gen_addr_reg_index(ctx, EA); | |
5707 | val = tcg_temp_new(); | |
5708 | gen_qemu_ld32u(ctx, val, EA); | |
5709 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5710 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5711 | } | |
5712 | ||
5713 | /* icbt */ | |
5714 | static void gen_icbt_40x(DisasContext *ctx) | |
5715 | { | |
5716 | /* | |
5717 | * interpreted as no-op | |
5718 | * XXX: specification say this is treated as a load by the MMU but | |
5719 | * does not generate any exception | |
5720 | */ | |
5721 | } | |
5722 | ||
5723 | /* iccci */ | |
5724 | static void gen_iccci(DisasContext *ctx) | |
5725 | { | |
5726 | CHK_SV(ctx); | |
5727 | /* interpreted as no-op */ | |
5728 | } | |
5729 | ||
5730 | /* icread */ | |
5731 | static void gen_icread(DisasContext *ctx) | |
5732 | { | |
5733 | CHK_SV(ctx); | |
5734 | /* interpreted as no-op */ | |
5735 | } | |
5736 | ||
5737 | /* rfci (supervisor only) */ | |
5738 | static void gen_rfci_40x(DisasContext *ctx) | |
5739 | { | |
5740 | #if defined(CONFIG_USER_ONLY) | |
5741 | GEN_PRIV(ctx); | |
5742 | #else | |
5743 | CHK_SV(ctx); | |
5744 | /* Restore CPU state */ | |
5745 | gen_helper_40x_rfci(tcg_env); | |
5746 | ctx->base.is_jmp = DISAS_EXIT; | |
5747 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5748 | } | |
5749 | ||
5750 | static void gen_rfci(DisasContext *ctx) | |
5751 | { | |
5752 | #if defined(CONFIG_USER_ONLY) | |
5753 | GEN_PRIV(ctx); | |
5754 | #else | |
5755 | CHK_SV(ctx); | |
5756 | /* Restore CPU state */ | |
5757 | gen_helper_rfci(tcg_env); | |
5758 | ctx->base.is_jmp = DISAS_EXIT; | |
5759 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5760 | } | |
5761 | ||
5762 | /* BookE specific */ | |
5763 | ||
5764 | /* XXX: not implemented on 440 ? */ | |
5765 | static void gen_rfdi(DisasContext *ctx) | |
5766 | { | |
5767 | #if defined(CONFIG_USER_ONLY) | |
5768 | GEN_PRIV(ctx); | |
5769 | #else | |
5770 | CHK_SV(ctx); | |
5771 | /* Restore CPU state */ | |
5772 | gen_helper_rfdi(tcg_env); | |
5773 | ctx->base.is_jmp = DISAS_EXIT; | |
5774 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5775 | } | |
5776 | ||
5777 | /* XXX: not implemented on 440 ? */ | |
5778 | static void gen_rfmci(DisasContext *ctx) | |
5779 | { | |
5780 | #if defined(CONFIG_USER_ONLY) | |
5781 | GEN_PRIV(ctx); | |
5782 | #else | |
5783 | CHK_SV(ctx); | |
5784 | /* Restore CPU state */ | |
5785 | gen_helper_rfmci(tcg_env); | |
5786 | ctx->base.is_jmp = DISAS_EXIT; | |
5787 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5788 | } | |
5789 | ||
5790 | /* TLB management - PowerPC 405 implementation */ | |
5791 | ||
5792 | /* tlbre */ | |
5793 | static void gen_tlbre_40x(DisasContext *ctx) | |
5794 | { | |
5795 | #if defined(CONFIG_USER_ONLY) | |
5796 | GEN_PRIV(ctx); | |
5797 | #else | |
5798 | CHK_SV(ctx); | |
5799 | switch (rB(ctx->opcode)) { | |
5800 | case 0: | |
5801 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env, | |
5802 | cpu_gpr[rA(ctx->opcode)]); | |
5803 | break; | |
5804 | case 1: | |
5805 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env, | |
5806 | cpu_gpr[rA(ctx->opcode)]); | |
5807 | break; | |
5808 | default: | |
5809 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5810 | break; | |
5811 | } | |
5812 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5813 | } | |
5814 | ||
5815 | /* tlbsx - tlbsx. */ | |
5816 | static void gen_tlbsx_40x(DisasContext *ctx) | |
5817 | { | |
5818 | #if defined(CONFIG_USER_ONLY) | |
5819 | GEN_PRIV(ctx); | |
5820 | #else | |
5821 | TCGv t0; | |
5822 | ||
5823 | CHK_SV(ctx); | |
5824 | t0 = tcg_temp_new(); | |
5825 | gen_addr_reg_index(ctx, t0); | |
5826 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); | |
5827 | if (Rc(ctx->opcode)) { | |
5828 | TCGLabel *l1 = gen_new_label(); | |
5829 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
5830 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); | |
5831 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5832 | gen_set_label(l1); | |
5833 | } | |
5834 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5835 | } | |
5836 | ||
5837 | /* tlbwe */ | |
5838 | static void gen_tlbwe_40x(DisasContext *ctx) | |
5839 | { | |
5840 | #if defined(CONFIG_USER_ONLY) | |
5841 | GEN_PRIV(ctx); | |
5842 | #else | |
5843 | CHK_SV(ctx); | |
5844 | ||
5845 | switch (rB(ctx->opcode)) { | |
5846 | case 0: | |
5847 | gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)], | |
5848 | cpu_gpr[rS(ctx->opcode)]); | |
5849 | break; | |
5850 | case 1: | |
5851 | gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)], | |
5852 | cpu_gpr[rS(ctx->opcode)]); | |
5853 | break; | |
5854 | default: | |
5855 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5856 | break; | |
5857 | } | |
5858 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5859 | } | |
5860 | ||
5861 | /* TLB management - PowerPC 440 implementation */ | |
5862 | ||
5863 | /* tlbre */ | |
5864 | static void gen_tlbre_440(DisasContext *ctx) | |
5865 | { | |
5866 | #if defined(CONFIG_USER_ONLY) | |
5867 | GEN_PRIV(ctx); | |
5868 | #else | |
5869 | CHK_SV(ctx); | |
5870 | ||
5871 | switch (rB(ctx->opcode)) { | |
5872 | case 0: | |
5873 | case 1: | |
5874 | case 2: | |
5875 | { | |
5876 | TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); | |
5877 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], tcg_env, | |
5878 | t0, cpu_gpr[rA(ctx->opcode)]); | |
5879 | } | |
5880 | break; | |
5881 | default: | |
5882 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5883 | break; | |
5884 | } | |
5885 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5886 | } | |
5887 | ||
5888 | /* tlbsx - tlbsx. */ | |
5889 | static void gen_tlbsx_440(DisasContext *ctx) | |
5890 | { | |
5891 | #if defined(CONFIG_USER_ONLY) | |
5892 | GEN_PRIV(ctx); | |
5893 | #else | |
5894 | TCGv t0; | |
5895 | ||
5896 | CHK_SV(ctx); | |
5897 | t0 = tcg_temp_new(); | |
5898 | gen_addr_reg_index(ctx, t0); | |
5899 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); | |
5900 | if (Rc(ctx->opcode)) { | |
5901 | TCGLabel *l1 = gen_new_label(); | |
5902 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
5903 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); | |
5904 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5905 | gen_set_label(l1); | |
5906 | } | |
5907 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5908 | } | |
5909 | ||
5910 | /* tlbwe */ | |
5911 | static void gen_tlbwe_440(DisasContext *ctx) | |
5912 | { | |
5913 | #if defined(CONFIG_USER_ONLY) | |
5914 | GEN_PRIV(ctx); | |
5915 | #else | |
5916 | CHK_SV(ctx); | |
5917 | switch (rB(ctx->opcode)) { | |
5918 | case 0: | |
5919 | case 1: | |
5920 | case 2: | |
5921 | { | |
5922 | TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode)); | |
5923 | gen_helper_440_tlbwe(tcg_env, t0, cpu_gpr[rA(ctx->opcode)], | |
5924 | cpu_gpr[rS(ctx->opcode)]); | |
5925 | } | |
5926 | break; | |
5927 | default: | |
5928 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5929 | break; | |
5930 | } | |
5931 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5932 | } | |
5933 | ||
5934 | /* TLB management - PowerPC BookE 2.06 implementation */ | |
5935 | ||
5936 | /* tlbre */ | |
5937 | static void gen_tlbre_booke206(DisasContext *ctx) | |
5938 | { | |
5939 | #if defined(CONFIG_USER_ONLY) | |
5940 | GEN_PRIV(ctx); | |
5941 | #else | |
5942 | CHK_SV(ctx); | |
5943 | gen_helper_booke206_tlbre(tcg_env); | |
5944 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5945 | } | |
5946 | ||
5947 | /* tlbsx - tlbsx. */ | |
5948 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
5949 | { | |
5950 | #if defined(CONFIG_USER_ONLY) | |
5951 | GEN_PRIV(ctx); | |
5952 | #else | |
5953 | TCGv t0; | |
5954 | ||
5955 | CHK_SV(ctx); | |
5956 | if (rA(ctx->opcode)) { | |
5957 | t0 = tcg_temp_new(); | |
5958 | tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5959 | } else { | |
5960 | t0 = cpu_gpr[rB(ctx->opcode)]; | |
5961 | } | |
5962 | gen_helper_booke206_tlbsx(tcg_env, t0); | |
5963 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5964 | } | |
5965 | ||
5966 | /* tlbwe */ | |
5967 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
5968 | { | |
5969 | #if defined(CONFIG_USER_ONLY) | |
5970 | GEN_PRIV(ctx); | |
5971 | #else | |
5972 | CHK_SV(ctx); | |
5973 | gen_helper_booke206_tlbwe(tcg_env); | |
5974 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5975 | } | |
5976 | ||
5977 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
5978 | { | |
5979 | #if defined(CONFIG_USER_ONLY) | |
5980 | GEN_PRIV(ctx); | |
5981 | #else | |
5982 | TCGv t0; | |
5983 | ||
5984 | CHK_SV(ctx); | |
5985 | t0 = tcg_temp_new(); | |
5986 | gen_addr_reg_index(ctx, t0); | |
5987 | gen_helper_booke206_tlbivax(tcg_env, t0); | |
5988 | #endif /* defined(CONFIG_USER_ONLY) */ | |
5989 | } | |
5990 | ||
5991 | static void gen_tlbilx_booke206(DisasContext *ctx) | |
5992 | { | |
5993 | #if defined(CONFIG_USER_ONLY) | |
5994 | GEN_PRIV(ctx); | |
5995 | #else | |
5996 | TCGv t0; | |
5997 | ||
5998 | CHK_SV(ctx); | |
5999 | t0 = tcg_temp_new(); | |
6000 | gen_addr_reg_index(ctx, t0); | |
6001 | ||
6002 | switch ((ctx->opcode >> 21) & 0x3) { | |
6003 | case 0: | |
6004 | gen_helper_booke206_tlbilx0(tcg_env, t0); | |
6005 | break; | |
6006 | case 1: | |
6007 | gen_helper_booke206_tlbilx1(tcg_env, t0); | |
6008 | break; | |
6009 | case 3: | |
6010 | gen_helper_booke206_tlbilx3(tcg_env, t0); | |
6011 | break; | |
6012 | default: | |
6013 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6014 | break; | |
6015 | } | |
6016 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6017 | } | |
6018 | ||
6019 | /* wrtee */ | |
6020 | static void gen_wrtee(DisasContext *ctx) | |
6021 | { | |
6022 | #if defined(CONFIG_USER_ONLY) | |
6023 | GEN_PRIV(ctx); | |
6024 | #else | |
6025 | TCGv t0; | |
6026 | ||
6027 | CHK_SV(ctx); | |
6028 | t0 = tcg_temp_new(); | |
6029 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6030 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6031 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6032 | gen_ppc_maybe_interrupt(ctx); | |
6033 | /* | |
6034 | * Stop translation to have a chance to raise an exception if we | |
6035 | * just set msr_ee to 1 | |
6036 | */ | |
6037 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
6038 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6039 | } | |
6040 | ||
6041 | /* wrteei */ | |
6042 | static void gen_wrteei(DisasContext *ctx) | |
6043 | { | |
6044 | #if defined(CONFIG_USER_ONLY) | |
6045 | GEN_PRIV(ctx); | |
6046 | #else | |
6047 | CHK_SV(ctx); | |
6048 | if (ctx->opcode & 0x00008000) { | |
6049 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); | |
6050 | gen_ppc_maybe_interrupt(ctx); | |
6051 | /* Stop translation to have a chance to raise an exception */ | |
6052 | ctx->base.is_jmp = DISAS_EXIT_UPDATE; | |
6053 | } else { | |
6054 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6055 | } | |
6056 | #endif /* defined(CONFIG_USER_ONLY) */ | |
6057 | } | |
6058 | ||
6059 | /* PowerPC 440 specific instructions */ | |
6060 | ||
6061 | /* dlmzb */ | |
6062 | static void gen_dlmzb(DisasContext *ctx) | |
6063 | { | |
6064 | TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode)); | |
6065 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], tcg_env, | |
6066 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
6067 | } | |
6068 | ||
6069 | /* mbar replaces eieio on 440 */ | |
6070 | static void gen_mbar(DisasContext *ctx) | |
6071 | { | |
6072 | /* interpreted as no-op */ | |
6073 | } | |
6074 | ||
6075 | /* msync replaces sync on 440 */ | |
6076 | static void gen_msync_4xx(DisasContext *ctx) | |
6077 | { | |
6078 | /* Only e500 seems to treat reserved bits as invalid */ | |
6079 | if ((ctx->insns_flags2 & PPC2_BOOKE206) && | |
6080 | (ctx->opcode & 0x03FFF801)) { | |
6081 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6082 | } | |
6083 | /* otherwise interpreted as no-op */ | |
6084 | } | |
6085 | ||
6086 | /* icbt */ | |
6087 | static void gen_icbt_440(DisasContext *ctx) | |
6088 | { | |
6089 | /* | |
6090 | * interpreted as no-op | |
6091 | * XXX: specification say this is treated as a load by the MMU but | |
6092 | * does not generate any exception | |
6093 | */ | |
6094 | } | |
6095 | ||
6096 | #if defined(TARGET_PPC64) | |
6097 | static void gen_maddld(DisasContext *ctx) | |
6098 | { | |
6099 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6100 | ||
6101 | tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6102 | tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); | |
6103 | } | |
6104 | ||
6105 | /* maddhd maddhdu */ | |
6106 | static void gen_maddhd_maddhdu(DisasContext *ctx) | |
6107 | { | |
6108 | TCGv_i64 lo = tcg_temp_new_i64(); | |
6109 | TCGv_i64 hi = tcg_temp_new_i64(); | |
6110 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6111 | ||
6112 | if (Rc(ctx->opcode)) { | |
6113 | tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6114 | cpu_gpr[rB(ctx->opcode)]); | |
6115 | tcg_gen_movi_i64(t1, 0); | |
6116 | } else { | |
6117 | tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6118 | cpu_gpr[rB(ctx->opcode)]); | |
6119 | tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); | |
6120 | } | |
6121 | tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, | |
6122 | cpu_gpr[rC(ctx->opcode)], t1); | |
6123 | } | |
6124 | #endif /* defined(TARGET_PPC64) */ | |
6125 | ||
6126 | static void gen_tbegin(DisasContext *ctx) | |
6127 | { | |
6128 | if (unlikely(!ctx->tm_enabled)) { | |
6129 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6130 | return; | |
6131 | } | |
6132 | gen_helper_tbegin(tcg_env); | |
6133 | } | |
6134 | ||
6135 | #define GEN_TM_NOOP(name) \ | |
6136 | static inline void gen_##name(DisasContext *ctx) \ | |
6137 | { \ | |
6138 | if (unlikely(!ctx->tm_enabled)) { \ | |
6139 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6140 | return; \ | |
6141 | } \ | |
6142 | /* \ | |
6143 | * Because tbegin always fails in QEMU, these user \ | |
6144 | * space instructions all have a simple implementation: \ | |
6145 | * \ | |
6146 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6147 | * = 0b0 || 0b00 || 0b0 \ | |
6148 | */ \ | |
6149 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6150 | } | |
6151 | ||
6152 | GEN_TM_NOOP(tend); | |
6153 | GEN_TM_NOOP(tabort); | |
6154 | GEN_TM_NOOP(tabortwc); | |
6155 | GEN_TM_NOOP(tabortwci); | |
6156 | GEN_TM_NOOP(tabortdc); | |
6157 | GEN_TM_NOOP(tabortdci); | |
6158 | GEN_TM_NOOP(tsr); | |
6159 | ||
6160 | static inline void gen_cp_abort(DisasContext *ctx) | |
6161 | { | |
6162 | /* Do Nothing */ | |
6163 | } | |
6164 | ||
6165 | #define GEN_CP_PASTE_NOOP(name) \ | |
6166 | static inline void gen_##name(DisasContext *ctx) \ | |
6167 | { \ | |
6168 | /* \ | |
6169 | * Generate invalid exception until we have an \ | |
6170 | * implementation of the copy paste facility \ | |
6171 | */ \ | |
6172 | gen_invalid(ctx); \ | |
6173 | } | |
6174 | ||
6175 | GEN_CP_PASTE_NOOP(copy) | |
6176 | GEN_CP_PASTE_NOOP(paste) | |
6177 | ||
6178 | static void gen_tcheck(DisasContext *ctx) | |
6179 | { | |
6180 | if (unlikely(!ctx->tm_enabled)) { | |
6181 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6182 | return; | |
6183 | } | |
6184 | /* | |
6185 | * Because tbegin always fails, the tcheck implementation is | |
6186 | * simple: | |
6187 | * | |
6188 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 | |
6189 | * = 0b1 || 0b00 || 0b0 | |
6190 | */ | |
6191 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); | |
6192 | } | |
6193 | ||
6194 | #if defined(CONFIG_USER_ONLY) | |
6195 | #define GEN_TM_PRIV_NOOP(name) \ | |
6196 | static inline void gen_##name(DisasContext *ctx) \ | |
6197 | { \ | |
6198 | gen_priv_opc(ctx); \ | |
6199 | } | |
6200 | ||
6201 | #else | |
6202 | ||
6203 | #define GEN_TM_PRIV_NOOP(name) \ | |
6204 | static inline void gen_##name(DisasContext *ctx) \ | |
6205 | { \ | |
6206 | CHK_SV(ctx); \ | |
6207 | if (unlikely(!ctx->tm_enabled)) { \ | |
6208 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6209 | return; \ | |
6210 | } \ | |
6211 | /* \ | |
6212 | * Because tbegin always fails, the implementation is \ | |
6213 | * simple: \ | |
6214 | * \ | |
6215 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6216 | * = 0b0 || 0b00 | 0b0 \ | |
6217 | */ \ | |
6218 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6219 | } | |
6220 | ||
6221 | #endif | |
6222 | ||
6223 | GEN_TM_PRIV_NOOP(treclaim); | |
6224 | GEN_TM_PRIV_NOOP(trechkpt); | |
6225 | ||
6226 | static inline void get_fpr(TCGv_i64 dst, int regno) | |
6227 | { | |
6228 | tcg_gen_ld_i64(dst, tcg_env, fpr_offset(regno)); | |
6229 | } | |
6230 | ||
6231 | static inline void set_fpr(int regno, TCGv_i64 src) | |
6232 | { | |
6233 | tcg_gen_st_i64(src, tcg_env, fpr_offset(regno)); | |
6234 | /* | |
6235 | * Before PowerISA v3.1 the result of doubleword 1 of the VSR | |
6236 | * corresponding to the target FPR was undefined. However, | |
6237 | * most (if not all) real hardware were setting the result to 0. | |
6238 | * Starting at ISA v3.1, the result for doubleword 1 is now defined | |
6239 | * to be 0. | |
6240 | */ | |
6241 | tcg_gen_st_i64(tcg_constant_i64(0), tcg_env, vsr64_offset(regno, false)); | |
6242 | } | |
6243 | ||
6244 | static inline void get_avr64(TCGv_i64 dst, int regno, bool high) | |
6245 | { | |
6246 | tcg_gen_ld_i64(dst, tcg_env, avr64_offset(regno, high)); | |
6247 | } | |
6248 | ||
6249 | static inline void set_avr64(int regno, TCGv_i64 src, bool high) | |
6250 | { | |
6251 | tcg_gen_st_i64(src, tcg_env, avr64_offset(regno, high)); | |
6252 | } | |
6253 | ||
6254 | /* | |
6255 | * Helpers for decodetree used by !function for decoding arguments. | |
6256 | */ | |
6257 | static int times_2(DisasContext *ctx, int x) | |
6258 | { | |
6259 | return x * 2; | |
6260 | } | |
6261 | ||
6262 | static int times_4(DisasContext *ctx, int x) | |
6263 | { | |
6264 | return x * 4; | |
6265 | } | |
6266 | ||
6267 | static int times_16(DisasContext *ctx, int x) | |
6268 | { | |
6269 | return x * 16; | |
6270 | } | |
6271 | ||
6272 | static int64_t dw_compose_ea(DisasContext *ctx, int x) | |
6273 | { | |
6274 | return deposit64(0xfffffffffffffe00, 3, 6, x); | |
6275 | } | |
6276 | ||
6277 | /* | |
6278 | * Helpers for trans_* functions to check for specific insns flags. | |
6279 | * Use token pasting to ensure that we use the proper flag with the | |
6280 | * proper variable. | |
6281 | */ | |
6282 | #define REQUIRE_INSNS_FLAGS(CTX, NAME) \ | |
6283 | do { \ | |
6284 | if (((CTX)->insns_flags & PPC_##NAME) == 0) { \ | |
6285 | return false; \ | |
6286 | } \ | |
6287 | } while (0) | |
6288 | ||
6289 | #define REQUIRE_INSNS_FLAGS2(CTX, NAME) \ | |
6290 | do { \ | |
6291 | if (((CTX)->insns_flags2 & PPC2_##NAME) == 0) { \ | |
6292 | return false; \ | |
6293 | } \ | |
6294 | } while (0) | |
6295 | ||
6296 | /* Then special-case the check for 64-bit so that we elide code for ppc32. */ | |
6297 | #if TARGET_LONG_BITS == 32 | |
6298 | # define REQUIRE_64BIT(CTX) return false | |
6299 | #else | |
6300 | # define REQUIRE_64BIT(CTX) REQUIRE_INSNS_FLAGS(CTX, 64B) | |
6301 | #endif | |
6302 | ||
6303 | #define REQUIRE_VECTOR(CTX) \ | |
6304 | do { \ | |
6305 | if (unlikely(!(CTX)->altivec_enabled)) { \ | |
6306 | gen_exception((CTX), POWERPC_EXCP_VPU); \ | |
6307 | return true; \ | |
6308 | } \ | |
6309 | } while (0) | |
6310 | ||
6311 | #define REQUIRE_VSX(CTX) \ | |
6312 | do { \ | |
6313 | if (unlikely(!(CTX)->vsx_enabled)) { \ | |
6314 | gen_exception((CTX), POWERPC_EXCP_VSXU); \ | |
6315 | return true; \ | |
6316 | } \ | |
6317 | } while (0) | |
6318 | ||
6319 | #define REQUIRE_FPU(ctx) \ | |
6320 | do { \ | |
6321 | if (unlikely(!(ctx)->fpu_enabled)) { \ | |
6322 | gen_exception((ctx), POWERPC_EXCP_FPU); \ | |
6323 | return true; \ | |
6324 | } \ | |
6325 | } while (0) | |
6326 | ||
6327 | #if !defined(CONFIG_USER_ONLY) | |
6328 | #define REQUIRE_SV(CTX) \ | |
6329 | do { \ | |
6330 | if (unlikely((CTX)->pr)) { \ | |
6331 | gen_priv_opc(CTX); \ | |
6332 | return true; \ | |
6333 | } \ | |
6334 | } while (0) | |
6335 | ||
6336 | #define REQUIRE_HV(CTX) \ | |
6337 | do { \ | |
6338 | if (unlikely((CTX)->pr || !(CTX)->hv)) { \ | |
6339 | gen_priv_opc(CTX); \ | |
6340 | return true; \ | |
6341 | } \ | |
6342 | } while (0) | |
6343 | #else | |
6344 | #define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0) | |
6345 | #define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0) | |
6346 | #endif | |
6347 | ||
6348 | /* | |
6349 | * Helpers for implementing sets of trans_* functions. | |
6350 | * Defer the implementation of NAME to FUNC, with optional extra arguments. | |
6351 | */ | |
6352 | #define TRANS(NAME, FUNC, ...) \ | |
6353 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6354 | { return FUNC(ctx, a, __VA_ARGS__); } | |
6355 | #define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \ | |
6356 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6357 | { \ | |
6358 | REQUIRE_INSNS_FLAGS(ctx, FLAGS); \ | |
6359 | return FUNC(ctx, a, __VA_ARGS__); \ | |
6360 | } | |
6361 | #define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \ | |
6362 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6363 | { \ | |
6364 | REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ | |
6365 | return FUNC(ctx, a, __VA_ARGS__); \ | |
6366 | } | |
6367 | ||
6368 | #define TRANS64(NAME, FUNC, ...) \ | |
6369 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6370 | { REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); } | |
6371 | #define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \ | |
6372 | static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ | |
6373 | { \ | |
6374 | REQUIRE_64BIT(ctx); \ | |
6375 | REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \ | |
6376 | return FUNC(ctx, a, __VA_ARGS__); \ | |
6377 | } | |
6378 | ||
6379 | /* TODO: More TRANS* helpers for extra insn_flags checks. */ | |
6380 | ||
6381 | ||
6382 | #include "decode-insn32.c.inc" | |
6383 | #include "decode-insn64.c.inc" | |
6384 | #include "power8-pmu-regs.c.inc" | |
6385 | ||
6386 | /* | |
6387 | * Incorporate CIA into the constant when R=1. | |
6388 | * Validate that when R=1, RA=0. | |
6389 | */ | |
6390 | static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) | |
6391 | { | |
6392 | d->rt = a->rt; | |
6393 | d->ra = a->ra; | |
6394 | d->si = a->si; | |
6395 | if (a->r) { | |
6396 | if (unlikely(a->ra != 0)) { | |
6397 | gen_invalid(ctx); | |
6398 | return false; | |
6399 | } | |
6400 | d->si += ctx->cia; | |
6401 | } | |
6402 | return true; | |
6403 | } | |
6404 | ||
6405 | #include "translate/fixedpoint-impl.c.inc" | |
6406 | ||
6407 | #include "translate/fp-impl.c.inc" | |
6408 | ||
6409 | #include "translate/vmx-impl.c.inc" | |
6410 | ||
6411 | #include "translate/vsx-impl.c.inc" | |
6412 | ||
6413 | #include "translate/dfp-impl.c.inc" | |
6414 | ||
6415 | #include "translate/spe-impl.c.inc" | |
6416 | ||
6417 | #include "translate/branch-impl.c.inc" | |
6418 | ||
6419 | #include "translate/processor-ctrl-impl.c.inc" | |
6420 | ||
6421 | #include "translate/storage-ctrl-impl.c.inc" | |
6422 | ||
6423 | /* Handles lfdp */ | |
6424 | static void gen_dform39(DisasContext *ctx) | |
6425 | { | |
6426 | if ((ctx->opcode & 0x3) == 0) { | |
6427 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6428 | return gen_lfdp(ctx); | |
6429 | } | |
6430 | } | |
6431 | return gen_invalid(ctx); | |
6432 | } | |
6433 | ||
6434 | /* Handles stfdp */ | |
6435 | static void gen_dform3D(DisasContext *ctx) | |
6436 | { | |
6437 | if ((ctx->opcode & 3) == 0) { /* DS-FORM */ | |
6438 | /* stfdp */ | |
6439 | if (ctx->insns_flags2 & PPC2_ISA205) { | |
6440 | return gen_stfdp(ctx); | |
6441 | } | |
6442 | } | |
6443 | return gen_invalid(ctx); | |
6444 | } | |
6445 | ||
6446 | #if defined(TARGET_PPC64) | |
6447 | /* brd */ | |
6448 | static void gen_brd(DisasContext *ctx) | |
6449 | { | |
6450 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
6451 | } | |
6452 | ||
6453 | /* brw */ | |
6454 | static void gen_brw(DisasContext *ctx) | |
6455 | { | |
6456 | tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
6457 | tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); | |
6458 | ||
6459 | } | |
6460 | ||
6461 | /* brh */ | |
6462 | static void gen_brh(DisasContext *ctx) | |
6463 | { | |
6464 | TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull); | |
6465 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6466 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
6467 | ||
6468 | tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); | |
6469 | tcg_gen_and_i64(t2, t1, mask); | |
6470 | tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], mask); | |
6471 | tcg_gen_shli_i64(t1, t1, 8); | |
6472 | tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); | |
6473 | } | |
6474 | #endif | |
6475 | ||
6476 | static opcode_t opcodes[] = { | |
6477 | #if defined(TARGET_PPC64) | |
6478 | GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), | |
6479 | GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), | |
6480 | GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), | |
6481 | #endif | |
6482 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), | |
6483 | #if defined(TARGET_PPC64) | |
6484 | GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), | |
6485 | #endif | |
6486 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), | |
6487 | GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), | |
6488 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), | |
6489 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6490 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6491 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
6492 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
6493 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
6494 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
6495 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6496 | #if defined(TARGET_PPC64) | |
6497 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
6498 | #endif | |
6499 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
6500 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
6501 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6502 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6503 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6504 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
6505 | GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), | |
6506 | GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), | |
6507 | GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), | |
6508 | GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), | |
6509 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
6510 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
6511 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6512 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6513 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6514 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6515 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), | |
6516 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), | |
6517 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), | |
6518 | #if defined(TARGET_PPC64) | |
6519 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), | |
6520 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), | |
6521 | GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), | |
6522 | GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), | |
6523 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), | |
6524 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), | |
6525 | #endif | |
6526 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6527 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6528 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6529 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
6530 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
6531 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
6532 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
6533 | #if defined(TARGET_PPC64) | |
6534 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
6535 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
6536 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
6537 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
6538 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
6539 | GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, | |
6540 | PPC_NONE, PPC2_ISA300), | |
6541 | GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, | |
6542 | PPC_NONE, PPC2_ISA300), | |
6543 | #endif | |
6544 | /* handles lfdp, lxsd, lxssp */ | |
6545 | GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), | |
6546 | /* handles stfdp, stxsd, stxssp */ | |
6547 | GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), | |
6548 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6549 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6550 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
6551 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
6552 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
6553 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
6554 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), | |
6555 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
6556 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
6557 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
6558 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), | |
6559 | GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), | |
6560 | GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), | |
6561 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
6562 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
6563 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), | |
6564 | #if defined(TARGET_PPC64) | |
6565 | GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), | |
6566 | GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), | |
6567 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), | |
6568 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), | |
6569 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), | |
6570 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), | |
6571 | #endif | |
6572 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
6573 | /* ISA v3.0 changed the extended opcode from 62 to 30 */ | |
6574 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x039FF801, PPC_WAIT), | |
6575 | GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039CF801, PPC_NONE, PPC2_ISA300), | |
6576 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6577 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6578 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
6579 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
6580 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), | |
6581 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), | |
6582 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
6583 | #if defined(TARGET_PPC64) | |
6584 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
6585 | #if !defined(CONFIG_USER_ONLY) | |
6586 | /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ | |
6587 | GEN_HANDLER_E(scv, 0x11, 0x10, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), | |
6588 | GEN_HANDLER_E(scv, 0x11, 0x00, 0xFF, 0x03FFF01E, PPC_NONE, PPC2_ISA300), | |
6589 | GEN_HANDLER_E(rfscv, 0x13, 0x12, 0x02, 0x03FF8001, PPC_NONE, PPC2_ISA300), | |
6590 | #endif | |
6591 | GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), | |
6592 | GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6593 | GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6594 | GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6595 | GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6596 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
6597 | #endif | |
6598 | /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ | |
6599 | GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), | |
6600 | GEN_HANDLER(sc, 0x11, 0x01, 0xFF, 0x03FFF01D, PPC_FLOW), | |
6601 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
6602 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6603 | #if defined(TARGET_PPC64) | |
6604 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
6605 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6606 | #endif | |
6607 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
6608 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
6609 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
6610 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
6611 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
6612 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
6613 | #if defined(TARGET_PPC64) | |
6614 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
6615 | GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), | |
6616 | GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), | |
6617 | #endif | |
6618 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), | |
6619 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), | |
6620 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
6621 | GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), | |
6622 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
6623 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
6624 | GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), | |
6625 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), | |
6626 | GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
6627 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), | |
6628 | GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
6629 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), | |
6630 | GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), | |
6631 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), | |
6632 | GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), | |
6633 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), | |
6634 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), | |
6635 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
6636 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
6637 | GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), | |
6638 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
6639 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
6640 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
6641 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
6642 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
6643 | #if defined(TARGET_PPC64) | |
6644 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
6645 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
6646 | PPC_SEGMENT_64B), | |
6647 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
6648 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
6649 | PPC_SEGMENT_64B), | |
6650 | #endif | |
6651 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
6652 | /* | |
6653 | * XXX Those instructions will need to be handled differently for | |
6654 | * different ISA versions | |
6655 | */ | |
6656 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
6657 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
6658 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
6659 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
6660 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
6661 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
6662 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
6663 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
6664 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
6665 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
6666 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
6667 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
6668 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
6669 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
6670 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
6671 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
6672 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
6673 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), | |
6674 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), | |
6675 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
6676 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
6677 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
6678 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
6679 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
6680 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
6681 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
6682 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, | |
6683 | PPC_NONE, PPC2_BOOKE206), | |
6684 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
6685 | PPC_NONE, PPC2_BOOKE206), | |
6686 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
6687 | PPC_NONE, PPC2_BOOKE206), | |
6688 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
6689 | PPC_NONE, PPC2_BOOKE206), | |
6690 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, | |
6691 | PPC_NONE, PPC2_BOOKE206), | |
6692 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), | |
6693 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), | |
6694 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), | |
6695 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, | |
6696 | PPC_BOOKE, PPC2_BOOKE206), | |
6697 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), | |
6698 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, | |
6699 | PPC_BOOKE, PPC2_BOOKE206), | |
6700 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, | |
6701 | PPC_440_SPEC), | |
6702 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), | |
6703 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
6704 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
6705 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
6706 | #if defined(TARGET_PPC64) | |
6707 | GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, | |
6708 | PPC2_ISA300), | |
6709 | GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), | |
6710 | #endif | |
6711 | ||
6712 | #undef GEN_INT_ARITH_ADD | |
6713 | #undef GEN_INT_ARITH_ADD_CONST | |
6714 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6715 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
6716 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
6717 | add_ca, compute_ca, compute_ov) \ | |
6718 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
6719 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
6720 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
6721 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
6722 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
6723 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
6724 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
6725 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
6726 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
6727 | GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), | |
6728 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
6729 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
6730 | ||
6731 | #undef GEN_INT_ARITH_DIVW | |
6732 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
6733 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
6734 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
6735 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
6736 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
6737 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
6738 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6739 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6740 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6741 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6742 | GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), | |
6743 | GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
6744 | ||
6745 | #if defined(TARGET_PPC64) | |
6746 | #undef GEN_INT_ARITH_DIVD | |
6747 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
6748 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6749 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
6750 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
6751 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
6752 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
6753 | ||
6754 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6755 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6756 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6757 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6758 | GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), | |
6759 | GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
6760 | ||
6761 | #undef GEN_INT_ARITH_MUL_HELPER | |
6762 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
6763 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6764 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
6765 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
6766 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
6767 | #endif | |
6768 | ||
6769 | #undef GEN_INT_ARITH_SUBF | |
6770 | #undef GEN_INT_ARITH_SUBF_CONST | |
6771 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6772 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
6773 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
6774 | add_ca, compute_ca, compute_ov) \ | |
6775 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
6776 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
6777 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
6778 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
6779 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
6780 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
6781 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
6782 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
6783 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
6784 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
6785 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
6786 | ||
6787 | #undef GEN_LOGICAL1 | |
6788 | #undef GEN_LOGICAL2 | |
6789 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
6790 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
6791 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
6792 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
6793 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
6794 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
6795 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
6796 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
6797 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
6798 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
6799 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
6800 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
6801 | #if defined(TARGET_PPC64) | |
6802 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
6803 | #endif | |
6804 | ||
6805 | #if defined(TARGET_PPC64) | |
6806 | #undef GEN_PPC64_R2 | |
6807 | #undef GEN_PPC64_R4 | |
6808 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
6809 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6810 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6811 | PPC_64B) | |
6812 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
6813 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6814 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
6815 | PPC_64B), \ | |
6816 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6817 | PPC_64B), \ | |
6818 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
6819 | PPC_64B) | |
6820 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
6821 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
6822 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
6823 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
6824 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
6825 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
6826 | #endif | |
6827 | ||
6828 | #undef GEN_LDX_E | |
6829 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ | |
6830 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
6831 | ||
6832 | #if defined(TARGET_PPC64) | |
6833 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) | |
6834 | ||
6835 | /* HV/P7 and later only */ | |
6836 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) | |
6837 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) | |
6838 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
6839 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
6840 | #endif | |
6841 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
6842 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
6843 | ||
6844 | /* External PID based load */ | |
6845 | #undef GEN_LDEPX | |
6846 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ | |
6847 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ | |
6848 | 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
6849 | ||
6850 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) | |
6851 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) | |
6852 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) | |
6853 | #if defined(TARGET_PPC64) | |
6854 | GEN_LDEPX(ld, DEF_MEMOP(MO_UQ), 0x1D, 0x00) | |
6855 | #endif | |
6856 | ||
6857 | #undef GEN_STX_E | |
6858 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ | |
6859 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), | |
6860 | ||
6861 | #if defined(TARGET_PPC64) | |
6862 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) | |
6863 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) | |
6864 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) | |
6865 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
6866 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
6867 | #endif | |
6868 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
6869 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
6870 | ||
6871 | #undef GEN_STEPX | |
6872 | #define GEN_STEPX(name, ldop, opc2, opc3) \ | |
6873 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ | |
6874 | 0x00000001, PPC_NONE, PPC2_BOOKE206), | |
6875 | ||
6876 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) | |
6877 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) | |
6878 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) | |
6879 | #if defined(TARGET_PPC64) | |
6880 | GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) | |
6881 | #endif | |
6882 | ||
6883 | #undef GEN_CRLOGIC | |
6884 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
6885 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
6886 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
6887 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
6888 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
6889 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
6890 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
6891 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
6892 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
6893 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
6894 | ||
6895 | #undef GEN_MAC_HANDLER | |
6896 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
6897 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
6898 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
6899 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
6900 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
6901 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
6902 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
6903 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
6904 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
6905 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
6906 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
6907 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
6908 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
6909 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
6910 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
6911 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
6912 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
6913 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
6914 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
6915 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
6916 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
6917 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
6918 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
6919 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
6920 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
6921 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
6922 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
6923 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
6924 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
6925 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
6926 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
6927 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
6928 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
6929 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
6930 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
6931 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
6932 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
6933 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
6934 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
6935 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
6936 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
6937 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
6938 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
6939 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
6940 | ||
6941 | GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ | |
6942 | PPC_NONE, PPC2_TM), | |
6943 | GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ | |
6944 | PPC_NONE, PPC2_TM), | |
6945 | GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ | |
6946 | PPC_NONE, PPC2_TM), | |
6947 | GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ | |
6948 | PPC_NONE, PPC2_TM), | |
6949 | GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ | |
6950 | PPC_NONE, PPC2_TM), | |
6951 | GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ | |
6952 | PPC_NONE, PPC2_TM), | |
6953 | GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ | |
6954 | PPC_NONE, PPC2_TM), | |
6955 | GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ | |
6956 | PPC_NONE, PPC2_TM), | |
6957 | GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ | |
6958 | PPC_NONE, PPC2_TM), | |
6959 | GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ | |
6960 | PPC_NONE, PPC2_TM), | |
6961 | GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ | |
6962 | PPC_NONE, PPC2_TM), | |
6963 | ||
6964 | #include "translate/fp-ops.c.inc" | |
6965 | ||
6966 | #include "translate/vmx-ops.c.inc" | |
6967 | ||
6968 | #include "translate/vsx-ops.c.inc" | |
6969 | ||
6970 | #include "translate/spe-ops.c.inc" | |
6971 | }; | |
6972 | ||
6973 | /*****************************************************************************/ | |
6974 | /* Opcode types */ | |
6975 | enum { | |
6976 | PPC_DIRECT = 0, /* Opcode routine */ | |
6977 | PPC_INDIRECT = 1, /* Indirect opcode table */ | |
6978 | }; | |
6979 | ||
6980 | #define PPC_OPCODE_MASK 0x3 | |
6981 | ||
6982 | static inline int is_indirect_opcode(void *handler) | |
6983 | { | |
6984 | return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; | |
6985 | } | |
6986 | ||
6987 | static inline opc_handler_t **ind_table(void *handler) | |
6988 | { | |
6989 | return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); | |
6990 | } | |
6991 | ||
6992 | /* Instruction table creation */ | |
6993 | /* Opcodes tables creation */ | |
6994 | static void fill_new_table(opc_handler_t **table, int len) | |
6995 | { | |
6996 | int i; | |
6997 | ||
6998 | for (i = 0; i < len; i++) { | |
6999 | table[i] = &invalid_handler; | |
7000 | } | |
7001 | } | |
7002 | ||
7003 | static int create_new_table(opc_handler_t **table, unsigned char idx) | |
7004 | { | |
7005 | opc_handler_t **tmp; | |
7006 | ||
7007 | tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); | |
7008 | fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); | |
7009 | table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); | |
7010 | ||
7011 | return 0; | |
7012 | } | |
7013 | ||
7014 | static int insert_in_table(opc_handler_t **table, unsigned char idx, | |
7015 | opc_handler_t *handler) | |
7016 | { | |
7017 | if (table[idx] != &invalid_handler) { | |
7018 | return -1; | |
7019 | } | |
7020 | table[idx] = handler; | |
7021 | ||
7022 | return 0; | |
7023 | } | |
7024 | ||
7025 | static int register_direct_insn(opc_handler_t **ppc_opcodes, | |
7026 | unsigned char idx, opc_handler_t *handler) | |
7027 | { | |
7028 | if (insert_in_table(ppc_opcodes, idx, handler) < 0) { | |
7029 | printf("*** ERROR: opcode %02x already assigned in main " | |
7030 | "opcode table\n", idx); | |
7031 | return -1; | |
7032 | } | |
7033 | ||
7034 | return 0; | |
7035 | } | |
7036 | ||
7037 | static int register_ind_in_table(opc_handler_t **table, | |
7038 | unsigned char idx1, unsigned char idx2, | |
7039 | opc_handler_t *handler) | |
7040 | { | |
7041 | if (table[idx1] == &invalid_handler) { | |
7042 | if (create_new_table(table, idx1) < 0) { | |
7043 | printf("*** ERROR: unable to create indirect table " | |
7044 | "idx=%02x\n", idx1); | |
7045 | return -1; | |
7046 | } | |
7047 | } else { | |
7048 | if (!is_indirect_opcode(table[idx1])) { | |
7049 | printf("*** ERROR: idx %02x already assigned to a direct " | |
7050 | "opcode\n", idx1); | |
7051 | return -1; | |
7052 | } | |
7053 | } | |
7054 | if (handler != NULL && | |
7055 | insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { | |
7056 | printf("*** ERROR: opcode %02x already assigned in " | |
7057 | "opcode table %02x\n", idx2, idx1); | |
7058 | return -1; | |
7059 | } | |
7060 | ||
7061 | return 0; | |
7062 | } | |
7063 | ||
7064 | static int register_ind_insn(opc_handler_t **ppc_opcodes, | |
7065 | unsigned char idx1, unsigned char idx2, | |
7066 | opc_handler_t *handler) | |
7067 | { | |
7068 | return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); | |
7069 | } | |
7070 | ||
7071 | static int register_dblind_insn(opc_handler_t **ppc_opcodes, | |
7072 | unsigned char idx1, unsigned char idx2, | |
7073 | unsigned char idx3, opc_handler_t *handler) | |
7074 | { | |
7075 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { | |
7076 | printf("*** ERROR: unable to join indirect table idx " | |
7077 | "[%02x-%02x]\n", idx1, idx2); | |
7078 | return -1; | |
7079 | } | |
7080 | if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, | |
7081 | handler) < 0) { | |
7082 | printf("*** ERROR: unable to insert opcode " | |
7083 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); | |
7084 | return -1; | |
7085 | } | |
7086 | ||
7087 | return 0; | |
7088 | } | |
7089 | ||
7090 | static int register_trplind_insn(opc_handler_t **ppc_opcodes, | |
7091 | unsigned char idx1, unsigned char idx2, | |
7092 | unsigned char idx3, unsigned char idx4, | |
7093 | opc_handler_t *handler) | |
7094 | { | |
7095 | opc_handler_t **table; | |
7096 | ||
7097 | if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { | |
7098 | printf("*** ERROR: unable to join indirect table idx " | |
7099 | "[%02x-%02x]\n", idx1, idx2); | |
7100 | return -1; | |
7101 | } | |
7102 | table = ind_table(ppc_opcodes[idx1]); | |
7103 | if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { | |
7104 | printf("*** ERROR: unable to join 2nd-level indirect table idx " | |
7105 | "[%02x-%02x-%02x]\n", idx1, idx2, idx3); | |
7106 | return -1; | |
7107 | } | |
7108 | table = ind_table(table[idx2]); | |
7109 | if (register_ind_in_table(table, idx3, idx4, handler) < 0) { | |
7110 | printf("*** ERROR: unable to insert opcode " | |
7111 | "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); | |
7112 | return -1; | |
7113 | } | |
7114 | return 0; | |
7115 | } | |
7116 | static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) | |
7117 | { | |
7118 | if (insn->opc2 != 0xFF) { | |
7119 | if (insn->opc3 != 0xFF) { | |
7120 | if (insn->opc4 != 0xFF) { | |
7121 | if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, | |
7122 | insn->opc3, insn->opc4, | |
7123 | &insn->handler) < 0) { | |
7124 | return -1; | |
7125 | } | |
7126 | } else { | |
7127 | if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, | |
7128 | insn->opc3, &insn->handler) < 0) { | |
7129 | return -1; | |
7130 | } | |
7131 | } | |
7132 | } else { | |
7133 | if (register_ind_insn(ppc_opcodes, insn->opc1, | |
7134 | insn->opc2, &insn->handler) < 0) { | |
7135 | return -1; | |
7136 | } | |
7137 | } | |
7138 | } else { | |
7139 | if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { | |
7140 | return -1; | |
7141 | } | |
7142 | } | |
7143 | ||
7144 | return 0; | |
7145 | } | |
7146 | ||
7147 | static int test_opcode_table(opc_handler_t **table, int len) | |
7148 | { | |
7149 | int i, count, tmp; | |
7150 | ||
7151 | for (i = 0, count = 0; i < len; i++) { | |
7152 | /* Consistency fixup */ | |
7153 | if (table[i] == NULL) { | |
7154 | table[i] = &invalid_handler; | |
7155 | } | |
7156 | if (table[i] != &invalid_handler) { | |
7157 | if (is_indirect_opcode(table[i])) { | |
7158 | tmp = test_opcode_table(ind_table(table[i]), | |
7159 | PPC_CPU_INDIRECT_OPCODES_LEN); | |
7160 | if (tmp == 0) { | |
7161 | g_free(table[i]); | |
7162 | table[i] = &invalid_handler; | |
7163 | } else { | |
7164 | count++; | |
7165 | } | |
7166 | } else { | |
7167 | count++; | |
7168 | } | |
7169 | } | |
7170 | } | |
7171 | ||
7172 | return count; | |
7173 | } | |
7174 | ||
7175 | static void fix_opcode_tables(opc_handler_t **ppc_opcodes) | |
7176 | { | |
7177 | if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { | |
7178 | printf("*** WARNING: no opcode defined !\n"); | |
7179 | } | |
7180 | } | |
7181 | ||
7182 | /*****************************************************************************/ | |
7183 | void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) | |
7184 | { | |
7185 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
7186 | opcode_t *opc; | |
7187 | ||
7188 | fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); | |
7189 | for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { | |
7190 | if (((opc->handler.type & pcc->insns_flags) != 0) || | |
7191 | ((opc->handler.type2 & pcc->insns_flags2) != 0)) { | |
7192 | if (register_insn(cpu->opcodes, opc) < 0) { | |
7193 | error_setg(errp, "ERROR initializing PowerPC instruction " | |
7194 | "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, | |
7195 | opc->opc3); | |
7196 | return; | |
7197 | } | |
7198 | } | |
7199 | } | |
7200 | fix_opcode_tables(cpu->opcodes); | |
7201 | fflush(stdout); | |
7202 | fflush(stderr); | |
7203 | } | |
7204 | ||
7205 | void destroy_ppc_opcodes(PowerPCCPU *cpu) | |
7206 | { | |
7207 | opc_handler_t **table, **table_2; | |
7208 | int i, j, k; | |
7209 | ||
7210 | for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { | |
7211 | if (cpu->opcodes[i] == &invalid_handler) { | |
7212 | continue; | |
7213 | } | |
7214 | if (is_indirect_opcode(cpu->opcodes[i])) { | |
7215 | table = ind_table(cpu->opcodes[i]); | |
7216 | for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { | |
7217 | if (table[j] == &invalid_handler) { | |
7218 | continue; | |
7219 | } | |
7220 | if (is_indirect_opcode(table[j])) { | |
7221 | table_2 = ind_table(table[j]); | |
7222 | for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { | |
7223 | if (table_2[k] != &invalid_handler && | |
7224 | is_indirect_opcode(table_2[k])) { | |
7225 | g_free((opc_handler_t *)((uintptr_t)table_2[k] & | |
7226 | ~PPC_INDIRECT)); | |
7227 | } | |
7228 | } | |
7229 | g_free((opc_handler_t *)((uintptr_t)table[j] & | |
7230 | ~PPC_INDIRECT)); | |
7231 | } | |
7232 | } | |
7233 | g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & | |
7234 | ~PPC_INDIRECT)); | |
7235 | } | |
7236 | } | |
7237 | } | |
7238 | ||
7239 | int ppc_fixup_cpu(PowerPCCPU *cpu) | |
7240 | { | |
7241 | CPUPPCState *env = &cpu->env; | |
7242 | ||
7243 | /* | |
7244 | * TCG doesn't (yet) emulate some groups of instructions that are | |
7245 | * implemented on some otherwise supported CPUs (e.g. VSX and | |
7246 | * decimal floating point instructions on POWER7). We remove | |
7247 | * unsupported instruction groups from the cpu state's instruction | |
7248 | * masks and hope the guest can cope. For at least the pseries | |
7249 | * machine, the unavailability of these instructions can be | |
7250 | * advertised to the guest via the device tree. | |
7251 | */ | |
7252 | if ((env->insns_flags & ~PPC_TCG_INSNS) | |
7253 | || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { | |
7254 | warn_report("Disabling some instructions which are not " | |
7255 | "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", | |
7256 | env->insns_flags & ~PPC_TCG_INSNS, | |
7257 | env->insns_flags2 & ~PPC_TCG_INSNS2); | |
7258 | } | |
7259 | env->insns_flags &= PPC_TCG_INSNS; | |
7260 | env->insns_flags2 &= PPC_TCG_INSNS2; | |
7261 | return 0; | |
7262 | } | |
7263 | ||
7264 | static bool decode_legacy(PowerPCCPU *cpu, DisasContext *ctx, uint32_t insn) | |
7265 | { | |
7266 | opc_handler_t **table, *handler; | |
7267 | uint32_t inval; | |
7268 | ||
7269 | ctx->opcode = insn; | |
7270 | ||
7271 | LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", | |
7272 | insn, opc1(insn), opc2(insn), opc3(insn), opc4(insn), | |
7273 | ctx->le_mode ? "little" : "big"); | |
7274 | ||
7275 | table = cpu->opcodes; | |
7276 | handler = table[opc1(insn)]; | |
7277 | if (is_indirect_opcode(handler)) { | |
7278 | table = ind_table(handler); | |
7279 | handler = table[opc2(insn)]; | |
7280 | if (is_indirect_opcode(handler)) { | |
7281 | table = ind_table(handler); | |
7282 | handler = table[opc3(insn)]; | |
7283 | if (is_indirect_opcode(handler)) { | |
7284 | table = ind_table(handler); | |
7285 | handler = table[opc4(insn)]; | |
7286 | } | |
7287 | } | |
7288 | } | |
7289 | ||
7290 | /* Is opcode *REALLY* valid ? */ | |
7291 | if (unlikely(handler->handler == &gen_invalid)) { | |
7292 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " | |
7293 | "%02x - %02x - %02x - %02x (%08x) " | |
7294 | TARGET_FMT_lx "\n", | |
7295 | opc1(insn), opc2(insn), opc3(insn), opc4(insn), | |
7296 | insn, ctx->cia); | |
7297 | return false; | |
7298 | } | |
7299 | ||
7300 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) | |
7301 | && Rc(insn))) { | |
7302 | inval = handler->inval2; | |
7303 | } else { | |
7304 | inval = handler->inval1; | |
7305 | } | |
7306 | ||
7307 | if (unlikely((insn & inval) != 0)) { | |
7308 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " | |
7309 | "%02x - %02x - %02x - %02x (%08x) " | |
7310 | TARGET_FMT_lx "\n", insn & inval, | |
7311 | opc1(insn), opc2(insn), opc3(insn), opc4(insn), | |
7312 | insn, ctx->cia); | |
7313 | return false; | |
7314 | } | |
7315 | ||
7316 | handler->handler(ctx); | |
7317 | return true; | |
7318 | } | |
7319 | ||
7320 | static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | |
7321 | { | |
7322 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7323 | CPUPPCState *env = cpu_env(cs); | |
7324 | uint32_t hflags = ctx->base.tb->flags; | |
7325 | ||
7326 | ctx->spr_cb = env->spr_cb; | |
7327 | ctx->pr = (hflags >> HFLAGS_PR) & 1; | |
7328 | ctx->mem_idx = (hflags >> HFLAGS_DMMU_IDX) & 7; | |
7329 | ctx->dr = (hflags >> HFLAGS_DR) & 1; | |
7330 | ctx->hv = (hflags >> HFLAGS_HV) & 1; | |
7331 | ctx->insns_flags = env->insns_flags; | |
7332 | ctx->insns_flags2 = env->insns_flags2; | |
7333 | ctx->access_type = -1; | |
7334 | ctx->need_access_type = !mmu_is_64bit(env->mmu_model); | |
7335 | ctx->le_mode = (hflags >> HFLAGS_LE) & 1; | |
7336 | ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; | |
7337 | ctx->flags = env->flags; | |
7338 | #if defined(TARGET_PPC64) | |
7339 | ctx->sf_mode = (hflags >> HFLAGS_64) & 1; | |
7340 | ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); | |
7341 | #endif | |
7342 | ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B | |
7343 | || env->mmu_model & POWERPC_MMU_64; | |
7344 | ||
7345 | ctx->fpu_enabled = (hflags >> HFLAGS_FP) & 1; | |
7346 | ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1; | |
7347 | ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1; | |
7348 | ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1; | |
7349 | ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1; | |
7350 | ctx->gtse = (hflags >> HFLAGS_GTSE) & 1; | |
7351 | ctx->hr = (hflags >> HFLAGS_HR) & 1; | |
7352 | ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; | |
7353 | ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; | |
7354 | ctx->mmcr0_pmcjce = (hflags >> HFLAGS_PMCJCE) & 1; | |
7355 | ctx->pmc_other = (hflags >> HFLAGS_PMC_OTHER) & 1; | |
7356 | ctx->pmu_insn_cnt = (hflags >> HFLAGS_INSN_CNT) & 1; | |
7357 | ||
7358 | ctx->singlestep_enabled = 0; | |
7359 | if ((hflags >> HFLAGS_SE) & 1) { | |
7360 | ctx->singlestep_enabled |= CPU_SINGLE_STEP; | |
7361 | ctx->base.max_insns = 1; | |
7362 | } | |
7363 | if ((hflags >> HFLAGS_BE) & 1) { | |
7364 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; | |
7365 | } | |
7366 | } | |
7367 | ||
7368 | static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) | |
7369 | { | |
7370 | } | |
7371 | ||
7372 | static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) | |
7373 | { | |
7374 | tcg_gen_insn_start(dcbase->pc_next); | |
7375 | } | |
7376 | ||
7377 | static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) | |
7378 | { | |
7379 | REQUIRE_INSNS_FLAGS2(ctx, ISA310); | |
7380 | return opc1(insn) == 1; | |
7381 | } | |
7382 | ||
7383 | static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) | |
7384 | { | |
7385 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7386 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
7387 | CPUPPCState *env = cpu_env(cs); | |
7388 | target_ulong pc; | |
7389 | uint32_t insn; | |
7390 | bool ok; | |
7391 | ||
7392 | LOG_DISAS("----------------\n"); | |
7393 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", | |
7394 | ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); | |
7395 | ||
7396 | ctx->cia = pc = ctx->base.pc_next; | |
7397 | insn = translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); | |
7398 | ctx->base.pc_next = pc += 4; | |
7399 | ||
7400 | if (!is_prefix_insn(ctx, insn)) { | |
7401 | ok = (decode_insn32(ctx, insn) || | |
7402 | decode_legacy(cpu, ctx, insn)); | |
7403 | } else if ((pc & 63) == 0) { | |
7404 | /* | |
7405 | * Power v3.1, section 1.9 Exceptions: | |
7406 | * attempt to execute a prefixed instruction that crosses a | |
7407 | * 64-byte address boundary (system alignment error). | |
7408 | */ | |
7409 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_INSN); | |
7410 | ok = true; | |
7411 | } else { | |
7412 | uint32_t insn2 = translator_ldl_swap(env, dcbase, pc, | |
7413 | need_byteswap(ctx)); | |
7414 | ctx->base.pc_next = pc += 4; | |
7415 | ok = decode_insn64(ctx, deposit64(insn2, 32, 32, insn)); | |
7416 | } | |
7417 | if (!ok) { | |
7418 | gen_invalid(ctx); | |
7419 | } | |
7420 | ||
7421 | /* End the TB when crossing a page boundary. */ | |
7422 | if (ctx->base.is_jmp == DISAS_NEXT && !(pc & ~TARGET_PAGE_MASK)) { | |
7423 | ctx->base.is_jmp = DISAS_TOO_MANY; | |
7424 | } | |
7425 | } | |
7426 | ||
7427 | static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
7428 | { | |
7429 | DisasContext *ctx = container_of(dcbase, DisasContext, base); | |
7430 | DisasJumpType is_jmp = ctx->base.is_jmp; | |
7431 | target_ulong nip = ctx->base.pc_next; | |
7432 | ||
7433 | if (is_jmp == DISAS_NORETURN) { | |
7434 | /* We have already exited the TB. */ | |
7435 | return; | |
7436 | } | |
7437 | ||
7438 | /* Honor single stepping. */ | |
7439 | if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { | |
7440 | bool rfi_type = false; | |
7441 | ||
7442 | switch (is_jmp) { | |
7443 | case DISAS_TOO_MANY: | |
7444 | case DISAS_EXIT_UPDATE: | |
7445 | case DISAS_CHAIN_UPDATE: | |
7446 | gen_update_nip(ctx, nip); | |
7447 | break; | |
7448 | case DISAS_EXIT: | |
7449 | case DISAS_CHAIN: | |
7450 | /* | |
7451 | * This is a heuristic, to put it kindly. The rfi class of | |
7452 | * instructions are among the few outside branches that change | |
7453 | * NIP without taking an interrupt. Single step trace interrupts | |
7454 | * do not fire on completion of these instructions. | |
7455 | */ | |
7456 | rfi_type = true; | |
7457 | break; | |
7458 | default: | |
7459 | g_assert_not_reached(); | |
7460 | } | |
7461 | ||
7462 | gen_debug_exception(ctx, rfi_type); | |
7463 | return; | |
7464 | } | |
7465 | ||
7466 | switch (is_jmp) { | |
7467 | case DISAS_TOO_MANY: | |
7468 | if (use_goto_tb(ctx, nip)) { | |
7469 | pmu_count_insns(ctx); | |
7470 | tcg_gen_goto_tb(0); | |
7471 | gen_update_nip(ctx, nip); | |
7472 | tcg_gen_exit_tb(ctx->base.tb, 0); | |
7473 | break; | |
7474 | } | |
7475 | /* fall through */ | |
7476 | case DISAS_CHAIN_UPDATE: | |
7477 | gen_update_nip(ctx, nip); | |
7478 | /* fall through */ | |
7479 | case DISAS_CHAIN: | |
7480 | /* | |
7481 | * tcg_gen_lookup_and_goto_ptr will exit the TB if | |
7482 | * CF_NO_GOTO_PTR is set. Count insns now. | |
7483 | */ | |
7484 | if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { | |
7485 | pmu_count_insns(ctx); | |
7486 | } | |
7487 | ||
7488 | tcg_gen_lookup_and_goto_ptr(); | |
7489 | break; | |
7490 | ||
7491 | case DISAS_EXIT_UPDATE: | |
7492 | gen_update_nip(ctx, nip); | |
7493 | /* fall through */ | |
7494 | case DISAS_EXIT: | |
7495 | pmu_count_insns(ctx); | |
7496 | tcg_gen_exit_tb(NULL, 0); | |
7497 | break; | |
7498 | ||
7499 | default: | |
7500 | g_assert_not_reached(); | |
7501 | } | |
7502 | } | |
7503 | ||
7504 | static void ppc_tr_disas_log(const DisasContextBase *dcbase, | |
7505 | CPUState *cs, FILE *logfile) | |
7506 | { | |
7507 | fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); | |
7508 | target_disas(logfile, cs, dcbase->pc_first, dcbase->tb->size); | |
7509 | } | |
7510 | ||
7511 | static const TranslatorOps ppc_tr_ops = { | |
7512 | .init_disas_context = ppc_tr_init_disas_context, | |
7513 | .tb_start = ppc_tr_tb_start, | |
7514 | .insn_start = ppc_tr_insn_start, | |
7515 | .translate_insn = ppc_tr_translate_insn, | |
7516 | .tb_stop = ppc_tr_tb_stop, | |
7517 | .disas_log = ppc_tr_disas_log, | |
7518 | }; | |
7519 | ||
7520 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, | |
7521 | vaddr pc, void *host_pc) | |
7522 | { | |
7523 | DisasContext ctx; | |
7524 | ||
7525 | translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base); | |
7526 | } |