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1 | /* | |
2 | * QEMU Alpha CPU | |
3 | * | |
4 | * Copyright (c) 2007 Jocelyn Mayer | |
5 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2.1 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see | |
19 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
20 | */ | |
21 | ||
22 | #include "cpu.h" | |
23 | #include "qemu-common.h" | |
24 | #include "migration/vmstate.h" | |
25 | ||
26 | ||
27 | static void alpha_cpu_set_pc(CPUState *cs, vaddr value) | |
28 | { | |
29 | AlphaCPU *cpu = ALPHA_CPU(cs); | |
30 | ||
31 | cpu->env.pc = value; | |
32 | } | |
33 | ||
34 | static bool alpha_cpu_has_work(CPUState *cs) | |
35 | { | |
36 | /* Here we are checking to see if the CPU should wake up from HALT. | |
37 | We will have gotten into this state only for WTINT from PALmode. */ | |
38 | /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU | |
39 | asleep even if (some) interrupts have been asserted. For now, | |
40 | assume that if a CPU really wants to stay asleep, it will mask | |
41 | interrupts at the chipset level, which will prevent these bits | |
42 | from being set in the first place. */ | |
43 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | |
44 | | CPU_INTERRUPT_TIMER | |
45 | | CPU_INTERRUPT_SMP | |
46 | | CPU_INTERRUPT_MCHK); | |
47 | } | |
48 | ||
49 | static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | |
50 | { | |
51 | info->mach = bfd_mach_alpha_ev6; | |
52 | info->print_insn = print_insn_alpha; | |
53 | } | |
54 | ||
55 | static void alpha_cpu_realizefn(DeviceState *dev, Error **errp) | |
56 | { | |
57 | CPUState *cs = CPU(dev); | |
58 | AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev); | |
59 | ||
60 | qemu_init_vcpu(cs); | |
61 | ||
62 | acc->parent_realize(dev, errp); | |
63 | } | |
64 | ||
65 | /* Sort alphabetically by type name. */ | |
66 | static gint alpha_cpu_list_compare(gconstpointer a, gconstpointer b) | |
67 | { | |
68 | ObjectClass *class_a = (ObjectClass *)a; | |
69 | ObjectClass *class_b = (ObjectClass *)b; | |
70 | const char *name_a, *name_b; | |
71 | ||
72 | name_a = object_class_get_name(class_a); | |
73 | name_b = object_class_get_name(class_b); | |
74 | return strcmp(name_a, name_b); | |
75 | } | |
76 | ||
77 | static void alpha_cpu_list_entry(gpointer data, gpointer user_data) | |
78 | { | |
79 | ObjectClass *oc = data; | |
80 | CPUListState *s = user_data; | |
81 | ||
82 | (*s->cpu_fprintf)(s->file, " %s\n", | |
83 | object_class_get_name(oc)); | |
84 | } | |
85 | ||
86 | void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
87 | { | |
88 | CPUListState s = { | |
89 | .file = f, | |
90 | .cpu_fprintf = cpu_fprintf, | |
91 | }; | |
92 | GSList *list; | |
93 | ||
94 | list = object_class_get_list(TYPE_ALPHA_CPU, false); | |
95 | list = g_slist_sort(list, alpha_cpu_list_compare); | |
96 | (*cpu_fprintf)(f, "Available CPUs:\n"); | |
97 | g_slist_foreach(list, alpha_cpu_list_entry, &s); | |
98 | g_slist_free(list); | |
99 | } | |
100 | ||
101 | /* Models */ | |
102 | ||
103 | #define TYPE(model) model "-" TYPE_ALPHA_CPU | |
104 | ||
105 | typedef struct AlphaCPUAlias { | |
106 | const char *alias; | |
107 | const char *typename; | |
108 | } AlphaCPUAlias; | |
109 | ||
110 | static const AlphaCPUAlias alpha_cpu_aliases[] = { | |
111 | { "21064", TYPE("ev4") }, | |
112 | { "21164", TYPE("ev5") }, | |
113 | { "21164a", TYPE("ev56") }, | |
114 | { "21164pc", TYPE("pca56") }, | |
115 | { "21264", TYPE("ev6") }, | |
116 | { "21264a", TYPE("ev67") }, | |
117 | }; | |
118 | ||
119 | static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model) | |
120 | { | |
121 | ObjectClass *oc = NULL; | |
122 | char *typename; | |
123 | int i; | |
124 | ||
125 | if (cpu_model == NULL) { | |
126 | return NULL; | |
127 | } | |
128 | ||
129 | oc = object_class_by_name(cpu_model); | |
130 | if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL && | |
131 | !object_class_is_abstract(oc)) { | |
132 | return oc; | |
133 | } | |
134 | ||
135 | for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) { | |
136 | if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) { | |
137 | oc = object_class_by_name(alpha_cpu_aliases[i].typename); | |
138 | assert(oc != NULL && !object_class_is_abstract(oc)); | |
139 | return oc; | |
140 | } | |
141 | } | |
142 | ||
143 | typename = g_strdup_printf("%s-" TYPE_ALPHA_CPU, cpu_model); | |
144 | oc = object_class_by_name(typename); | |
145 | g_free(typename); | |
146 | if (oc != NULL && object_class_is_abstract(oc)) { | |
147 | oc = NULL; | |
148 | } | |
149 | return oc; | |
150 | } | |
151 | ||
152 | AlphaCPU *cpu_alpha_init(const char *cpu_model) | |
153 | { | |
154 | AlphaCPU *cpu; | |
155 | ObjectClass *cpu_class; | |
156 | ||
157 | cpu_class = alpha_cpu_class_by_name(cpu_model); | |
158 | if (cpu_class == NULL) { | |
159 | /* Default to ev67; no reason not to emulate insns by default. */ | |
160 | cpu_class = object_class_by_name(TYPE("ev67")); | |
161 | } | |
162 | cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class))); | |
163 | ||
164 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); | |
165 | ||
166 | return cpu; | |
167 | } | |
168 | ||
169 | static void ev4_cpu_initfn(Object *obj) | |
170 | { | |
171 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
172 | CPUAlphaState *env = &cpu->env; | |
173 | ||
174 | env->implver = IMPLVER_2106x; | |
175 | } | |
176 | ||
177 | static const TypeInfo ev4_cpu_type_info = { | |
178 | .name = TYPE("ev4"), | |
179 | .parent = TYPE_ALPHA_CPU, | |
180 | .instance_init = ev4_cpu_initfn, | |
181 | }; | |
182 | ||
183 | static void ev5_cpu_initfn(Object *obj) | |
184 | { | |
185 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
186 | CPUAlphaState *env = &cpu->env; | |
187 | ||
188 | env->implver = IMPLVER_21164; | |
189 | } | |
190 | ||
191 | static const TypeInfo ev5_cpu_type_info = { | |
192 | .name = TYPE("ev5"), | |
193 | .parent = TYPE_ALPHA_CPU, | |
194 | .instance_init = ev5_cpu_initfn, | |
195 | }; | |
196 | ||
197 | static void ev56_cpu_initfn(Object *obj) | |
198 | { | |
199 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
200 | CPUAlphaState *env = &cpu->env; | |
201 | ||
202 | env->amask |= AMASK_BWX; | |
203 | } | |
204 | ||
205 | static const TypeInfo ev56_cpu_type_info = { | |
206 | .name = TYPE("ev56"), | |
207 | .parent = TYPE("ev5"), | |
208 | .instance_init = ev56_cpu_initfn, | |
209 | }; | |
210 | ||
211 | static void pca56_cpu_initfn(Object *obj) | |
212 | { | |
213 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
214 | CPUAlphaState *env = &cpu->env; | |
215 | ||
216 | env->amask |= AMASK_MVI; | |
217 | } | |
218 | ||
219 | static const TypeInfo pca56_cpu_type_info = { | |
220 | .name = TYPE("pca56"), | |
221 | .parent = TYPE("ev56"), | |
222 | .instance_init = pca56_cpu_initfn, | |
223 | }; | |
224 | ||
225 | static void ev6_cpu_initfn(Object *obj) | |
226 | { | |
227 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
228 | CPUAlphaState *env = &cpu->env; | |
229 | ||
230 | env->implver = IMPLVER_21264; | |
231 | env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP; | |
232 | } | |
233 | ||
234 | static const TypeInfo ev6_cpu_type_info = { | |
235 | .name = TYPE("ev6"), | |
236 | .parent = TYPE_ALPHA_CPU, | |
237 | .instance_init = ev6_cpu_initfn, | |
238 | }; | |
239 | ||
240 | static void ev67_cpu_initfn(Object *obj) | |
241 | { | |
242 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
243 | CPUAlphaState *env = &cpu->env; | |
244 | ||
245 | env->amask |= AMASK_CIX | AMASK_PREFETCH; | |
246 | } | |
247 | ||
248 | static const TypeInfo ev67_cpu_type_info = { | |
249 | .name = TYPE("ev67"), | |
250 | .parent = TYPE("ev6"), | |
251 | .instance_init = ev67_cpu_initfn, | |
252 | }; | |
253 | ||
254 | static const TypeInfo ev68_cpu_type_info = { | |
255 | .name = TYPE("ev68"), | |
256 | .parent = TYPE("ev67"), | |
257 | }; | |
258 | ||
259 | static void alpha_cpu_initfn(Object *obj) | |
260 | { | |
261 | CPUState *cs = CPU(obj); | |
262 | AlphaCPU *cpu = ALPHA_CPU(obj); | |
263 | CPUAlphaState *env = &cpu->env; | |
264 | ||
265 | cs->env_ptr = env; | |
266 | cpu_exec_init(cs, &error_abort); | |
267 | tlb_flush(cs, 1); | |
268 | ||
269 | alpha_translate_init(); | |
270 | ||
271 | #if defined(CONFIG_USER_ONLY) | |
272 | env->ps = PS_USER_MODE; | |
273 | cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD | |
274 | | FPCR_UNFD | FPCR_INED | FPCR_DNOD | |
275 | | FPCR_DYN_NORMAL)); | |
276 | #endif | |
277 | env->lock_addr = -1; | |
278 | env->fen = 1; | |
279 | } | |
280 | ||
281 | static void alpha_cpu_class_init(ObjectClass *oc, void *data) | |
282 | { | |
283 | DeviceClass *dc = DEVICE_CLASS(oc); | |
284 | CPUClass *cc = CPU_CLASS(oc); | |
285 | AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc); | |
286 | ||
287 | acc->parent_realize = dc->realize; | |
288 | dc->realize = alpha_cpu_realizefn; | |
289 | ||
290 | cc->class_by_name = alpha_cpu_class_by_name; | |
291 | cc->has_work = alpha_cpu_has_work; | |
292 | cc->do_interrupt = alpha_cpu_do_interrupt; | |
293 | cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt; | |
294 | cc->dump_state = alpha_cpu_dump_state; | |
295 | cc->set_pc = alpha_cpu_set_pc; | |
296 | cc->gdb_read_register = alpha_cpu_gdb_read_register; | |
297 | cc->gdb_write_register = alpha_cpu_gdb_write_register; | |
298 | #ifdef CONFIG_USER_ONLY | |
299 | cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault; | |
300 | #else | |
301 | cc->do_unassigned_access = alpha_cpu_unassigned_access; | |
302 | cc->do_unaligned_access = alpha_cpu_do_unaligned_access; | |
303 | cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; | |
304 | dc->vmsd = &vmstate_alpha_cpu; | |
305 | #endif | |
306 | cc->disas_set_info = alpha_cpu_disas_set_info; | |
307 | ||
308 | cc->gdb_num_core_regs = 67; | |
309 | ||
310 | /* | |
311 | * Reason: alpha_cpu_initfn() calls cpu_exec_init(), which saves | |
312 | * the object in cpus -> dangling pointer after final | |
313 | * object_unref(). | |
314 | */ | |
315 | dc->cannot_destroy_with_object_finalize_yet = true; | |
316 | } | |
317 | ||
318 | static const TypeInfo alpha_cpu_type_info = { | |
319 | .name = TYPE_ALPHA_CPU, | |
320 | .parent = TYPE_CPU, | |
321 | .instance_size = sizeof(AlphaCPU), | |
322 | .instance_init = alpha_cpu_initfn, | |
323 | .abstract = true, | |
324 | .class_size = sizeof(AlphaCPUClass), | |
325 | .class_init = alpha_cpu_class_init, | |
326 | }; | |
327 | ||
328 | static void alpha_cpu_register_types(void) | |
329 | { | |
330 | type_register_static(&alpha_cpu_type_info); | |
331 | type_register_static(&ev4_cpu_type_info); | |
332 | type_register_static(&ev5_cpu_type_info); | |
333 | type_register_static(&ev56_cpu_type_info); | |
334 | type_register_static(&pca56_cpu_type_info); | |
335 | type_register_static(&ev6_cpu_type_info); | |
336 | type_register_static(&ev67_cpu_type_info); | |
337 | type_register_static(&ev68_cpu_type_info); | |
338 | } | |
339 | ||
340 | type_init(alpha_cpu_register_types) |