]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * QEMU ARM CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
21 | #include "cpu.h" | |
22 | #include "internals.h" | |
23 | #include "qemu-common.h" | |
24 | #include "hw/qdev-properties.h" | |
25 | #include "qapi/qmp/qerror.h" | |
26 | #if !defined(CONFIG_USER_ONLY) | |
27 | #include "hw/loader.h" | |
28 | #endif | |
29 | #include "hw/arm/arm.h" | |
30 | #include "sysemu/sysemu.h" | |
31 | #include "sysemu/kvm.h" | |
32 | ||
33 | static void arm_cpu_set_pc(CPUState *cs, vaddr value) | |
34 | { | |
35 | ARMCPU *cpu = ARM_CPU(cs); | |
36 | ||
37 | cpu->env.regs[15] = value; | |
38 | } | |
39 | ||
40 | static bool arm_cpu_has_work(CPUState *cs) | |
41 | { | |
42 | return cs->interrupt_request & | |
43 | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); | |
44 | } | |
45 | ||
46 | static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) | |
47 | { | |
48 | /* Reset a single ARMCPRegInfo register */ | |
49 | ARMCPRegInfo *ri = value; | |
50 | ARMCPU *cpu = opaque; | |
51 | ||
52 | if (ri->type & ARM_CP_SPECIAL) { | |
53 | return; | |
54 | } | |
55 | ||
56 | if (ri->resetfn) { | |
57 | ri->resetfn(&cpu->env, ri); | |
58 | return; | |
59 | } | |
60 | ||
61 | /* A zero offset is never possible as it would be regs[0] | |
62 | * so we use it to indicate that reset is being handled elsewhere. | |
63 | * This is basically only used for fields in non-core coprocessors | |
64 | * (like the pxa2xx ones). | |
65 | */ | |
66 | if (!ri->fieldoffset) { | |
67 | return; | |
68 | } | |
69 | ||
70 | if (cpreg_field_is_64bit(ri)) { | |
71 | CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue; | |
72 | } else { | |
73 | CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue; | |
74 | } | |
75 | } | |
76 | ||
77 | /* CPUClass::reset() */ | |
78 | static void arm_cpu_reset(CPUState *s) | |
79 | { | |
80 | ARMCPU *cpu = ARM_CPU(s); | |
81 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); | |
82 | CPUARMState *env = &cpu->env; | |
83 | ||
84 | acc->parent_reset(s); | |
85 | ||
86 | memset(env, 0, offsetof(CPUARMState, features)); | |
87 | g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu); | |
88 | env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; | |
89 | env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; | |
90 | env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; | |
91 | env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2; | |
92 | ||
93 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
94 | env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; | |
95 | } | |
96 | ||
97 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | |
98 | /* 64 bit CPUs always start in 64 bit mode */ | |
99 | env->aarch64 = 1; | |
100 | #if defined(CONFIG_USER_ONLY) | |
101 | env->pstate = PSTATE_MODE_EL0t; | |
102 | /* Userspace expects access to CTL_EL0 and the cache ops */ | |
103 | env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; | |
104 | /* and to the FP/Neon instructions */ | |
105 | env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); | |
106 | #else | |
107 | env->pstate = PSTATE_MODE_EL1h; | |
108 | env->pc = cpu->rvbar; | |
109 | #endif | |
110 | } else { | |
111 | #if defined(CONFIG_USER_ONLY) | |
112 | /* Userspace expects access to cp10 and cp11 for FP/Neon */ | |
113 | env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf); | |
114 | #endif | |
115 | } | |
116 | ||
117 | #if defined(CONFIG_USER_ONLY) | |
118 | env->uncached_cpsr = ARM_CPU_MODE_USR; | |
119 | /* For user mode we must enable access to coprocessors */ | |
120 | env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30; | |
121 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { | |
122 | env->cp15.c15_cpar = 3; | |
123 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { | |
124 | env->cp15.c15_cpar = 1; | |
125 | } | |
126 | #else | |
127 | /* SVC mode with interrupts disabled. */ | |
128 | env->uncached_cpsr = ARM_CPU_MODE_SVC; | |
129 | env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; | |
130 | /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is | |
131 | clear at reset. Initial SP and PC are loaded from ROM. */ | |
132 | if (IS_M(env)) { | |
133 | uint32_t pc; | |
134 | uint8_t *rom; | |
135 | env->daif &= ~PSTATE_I; | |
136 | rom = rom_ptr(0); | |
137 | if (rom) { | |
138 | /* We should really use ldl_phys here, in case the guest | |
139 | modified flash and reset itself. However images | |
140 | loaded via -kernel have not been copied yet, so load the | |
141 | values directly from there. */ | |
142 | env->regs[13] = ldl_p(rom) & 0xFFFFFFFC; | |
143 | pc = ldl_p(rom + 4); | |
144 | env->thumb = pc & 1; | |
145 | env->regs[15] = pc & ~1; | |
146 | } | |
147 | } | |
148 | ||
149 | if (env->cp15.c1_sys & SCTLR_V) { | |
150 | env->regs[15] = 0xFFFF0000; | |
151 | } | |
152 | ||
153 | env->vfp.xregs[ARM_VFP_FPEXC] = 0; | |
154 | #endif | |
155 | set_flush_to_zero(1, &env->vfp.standard_fp_status); | |
156 | set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); | |
157 | set_default_nan_mode(1, &env->vfp.standard_fp_status); | |
158 | set_float_detect_tininess(float_tininess_before_rounding, | |
159 | &env->vfp.fp_status); | |
160 | set_float_detect_tininess(float_tininess_before_rounding, | |
161 | &env->vfp.standard_fp_status); | |
162 | tlb_flush(s, 1); | |
163 | /* Reset is a state change for some CPUARMState fields which we | |
164 | * bake assumptions about into translated code, so we need to | |
165 | * tb_flush(). | |
166 | */ | |
167 | tb_flush(env); | |
168 | } | |
169 | ||
170 | #ifndef CONFIG_USER_ONLY | |
171 | static void arm_cpu_set_irq(void *opaque, int irq, int level) | |
172 | { | |
173 | ARMCPU *cpu = opaque; | |
174 | CPUState *cs = CPU(cpu); | |
175 | ||
176 | switch (irq) { | |
177 | case ARM_CPU_IRQ: | |
178 | if (level) { | |
179 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
180 | } else { | |
181 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
182 | } | |
183 | break; | |
184 | case ARM_CPU_FIQ: | |
185 | if (level) { | |
186 | cpu_interrupt(cs, CPU_INTERRUPT_FIQ); | |
187 | } else { | |
188 | cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); | |
189 | } | |
190 | break; | |
191 | default: | |
192 | hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq); | |
193 | } | |
194 | } | |
195 | ||
196 | static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) | |
197 | { | |
198 | #ifdef CONFIG_KVM | |
199 | ARMCPU *cpu = opaque; | |
200 | CPUState *cs = CPU(cpu); | |
201 | int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; | |
202 | ||
203 | switch (irq) { | |
204 | case ARM_CPU_IRQ: | |
205 | kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; | |
206 | break; | |
207 | case ARM_CPU_FIQ: | |
208 | kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; | |
209 | break; | |
210 | default: | |
211 | hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq); | |
212 | } | |
213 | kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; | |
214 | kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); | |
215 | #endif | |
216 | } | |
217 | #endif | |
218 | ||
219 | static inline void set_feature(CPUARMState *env, int feature) | |
220 | { | |
221 | env->features |= 1ULL << feature; | |
222 | } | |
223 | ||
224 | static void arm_cpu_initfn(Object *obj) | |
225 | { | |
226 | CPUState *cs = CPU(obj); | |
227 | ARMCPU *cpu = ARM_CPU(obj); | |
228 | static bool inited; | |
229 | ||
230 | cs->env_ptr = &cpu->env; | |
231 | cpu_exec_init(&cpu->env); | |
232 | cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, | |
233 | g_free, g_free); | |
234 | ||
235 | #ifndef CONFIG_USER_ONLY | |
236 | /* Our inbound IRQ and FIQ lines */ | |
237 | if (kvm_enabled()) { | |
238 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); | |
239 | } else { | |
240 | qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); | |
241 | } | |
242 | ||
243 | cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
244 | arm_gt_ptimer_cb, cpu); | |
245 | cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE, | |
246 | arm_gt_vtimer_cb, cpu); | |
247 | qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, | |
248 | ARRAY_SIZE(cpu->gt_timer_outputs)); | |
249 | #endif | |
250 | ||
251 | /* DTB consumers generally don't in fact care what the 'compatible' | |
252 | * string is, so always provide some string and trust that a hypothetical | |
253 | * picky DTB consumer will also provide a helpful error message. | |
254 | */ | |
255 | cpu->dtb_compatible = "qemu,unknown"; | |
256 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; | |
257 | ||
258 | if (tcg_enabled() && !inited) { | |
259 | inited = true; | |
260 | arm_translate_init(); | |
261 | } | |
262 | } | |
263 | ||
264 | static Property arm_cpu_reset_cbar_property = | |
265 | DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0); | |
266 | ||
267 | static Property arm_cpu_reset_hivecs_property = | |
268 | DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false); | |
269 | ||
270 | static Property arm_cpu_rvbar_property = | |
271 | DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); | |
272 | ||
273 | static void arm_cpu_post_init(Object *obj) | |
274 | { | |
275 | ARMCPU *cpu = ARM_CPU(obj); | |
276 | ||
277 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || | |
278 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | |
279 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, | |
280 | &error_abort); | |
281 | } | |
282 | ||
283 | if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { | |
284 | qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, | |
285 | &error_abort); | |
286 | } | |
287 | ||
288 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | |
289 | qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, | |
290 | &error_abort); | |
291 | } | |
292 | } | |
293 | ||
294 | static void arm_cpu_finalizefn(Object *obj) | |
295 | { | |
296 | ARMCPU *cpu = ARM_CPU(obj); | |
297 | g_hash_table_destroy(cpu->cp_regs); | |
298 | } | |
299 | ||
300 | static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | |
301 | { | |
302 | CPUState *cs = CPU(dev); | |
303 | ARMCPU *cpu = ARM_CPU(dev); | |
304 | ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev); | |
305 | CPUARMState *env = &cpu->env; | |
306 | ||
307 | /* Some features automatically imply others: */ | |
308 | if (arm_feature(env, ARM_FEATURE_V8)) { | |
309 | set_feature(env, ARM_FEATURE_V7); | |
310 | set_feature(env, ARM_FEATURE_ARM_DIV); | |
311 | set_feature(env, ARM_FEATURE_LPAE); | |
312 | set_feature(env, ARM_FEATURE_V8_AES); | |
313 | } | |
314 | if (arm_feature(env, ARM_FEATURE_V7)) { | |
315 | set_feature(env, ARM_FEATURE_VAPA); | |
316 | set_feature(env, ARM_FEATURE_THUMB2); | |
317 | set_feature(env, ARM_FEATURE_MPIDR); | |
318 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
319 | set_feature(env, ARM_FEATURE_V6K); | |
320 | } else { | |
321 | set_feature(env, ARM_FEATURE_V6); | |
322 | } | |
323 | } | |
324 | if (arm_feature(env, ARM_FEATURE_V6K)) { | |
325 | set_feature(env, ARM_FEATURE_V6); | |
326 | set_feature(env, ARM_FEATURE_MVFR); | |
327 | } | |
328 | if (arm_feature(env, ARM_FEATURE_V6)) { | |
329 | set_feature(env, ARM_FEATURE_V5); | |
330 | if (!arm_feature(env, ARM_FEATURE_M)) { | |
331 | set_feature(env, ARM_FEATURE_AUXCR); | |
332 | } | |
333 | } | |
334 | if (arm_feature(env, ARM_FEATURE_V5)) { | |
335 | set_feature(env, ARM_FEATURE_V4T); | |
336 | } | |
337 | if (arm_feature(env, ARM_FEATURE_M)) { | |
338 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
339 | } | |
340 | if (arm_feature(env, ARM_FEATURE_ARM_DIV)) { | |
341 | set_feature(env, ARM_FEATURE_THUMB_DIV); | |
342 | } | |
343 | if (arm_feature(env, ARM_FEATURE_VFP4)) { | |
344 | set_feature(env, ARM_FEATURE_VFP3); | |
345 | } | |
346 | if (arm_feature(env, ARM_FEATURE_VFP3)) { | |
347 | set_feature(env, ARM_FEATURE_VFP); | |
348 | } | |
349 | if (arm_feature(env, ARM_FEATURE_LPAE)) { | |
350 | set_feature(env, ARM_FEATURE_V7MP); | |
351 | set_feature(env, ARM_FEATURE_PXN); | |
352 | } | |
353 | if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
354 | set_feature(env, ARM_FEATURE_CBAR); | |
355 | } | |
356 | ||
357 | if (cpu->reset_hivecs) { | |
358 | cpu->reset_sctlr |= (1 << 13); | |
359 | } | |
360 | ||
361 | register_cp_regs_for_features(cpu); | |
362 | arm_cpu_register_gdb_regs_for_features(cpu); | |
363 | ||
364 | init_cpreg_list(cpu); | |
365 | ||
366 | cpu_reset(cs); | |
367 | qemu_init_vcpu(cs); | |
368 | ||
369 | acc->parent_realize(dev, errp); | |
370 | } | |
371 | ||
372 | static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) | |
373 | { | |
374 | ObjectClass *oc; | |
375 | char *typename; | |
376 | ||
377 | if (!cpu_model) { | |
378 | return NULL; | |
379 | } | |
380 | ||
381 | typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model); | |
382 | oc = object_class_by_name(typename); | |
383 | g_free(typename); | |
384 | if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) || | |
385 | object_class_is_abstract(oc)) { | |
386 | return NULL; | |
387 | } | |
388 | return oc; | |
389 | } | |
390 | ||
391 | /* CPU models. These are not needed for the AArch64 linux-user build. */ | |
392 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
393 | ||
394 | static void arm926_initfn(Object *obj) | |
395 | { | |
396 | ARMCPU *cpu = ARM_CPU(obj); | |
397 | ||
398 | cpu->dtb_compatible = "arm,arm926"; | |
399 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
400 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
401 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
402 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
403 | cpu->midr = 0x41069265; | |
404 | cpu->reset_fpsid = 0x41011090; | |
405 | cpu->ctr = 0x1dd20d2; | |
406 | cpu->reset_sctlr = 0x00090078; | |
407 | } | |
408 | ||
409 | static void arm946_initfn(Object *obj) | |
410 | { | |
411 | ARMCPU *cpu = ARM_CPU(obj); | |
412 | ||
413 | cpu->dtb_compatible = "arm,arm946"; | |
414 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
415 | set_feature(&cpu->env, ARM_FEATURE_MPU); | |
416 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
417 | cpu->midr = 0x41059461; | |
418 | cpu->ctr = 0x0f004006; | |
419 | cpu->reset_sctlr = 0x00000078; | |
420 | } | |
421 | ||
422 | static void arm1026_initfn(Object *obj) | |
423 | { | |
424 | ARMCPU *cpu = ARM_CPU(obj); | |
425 | ||
426 | cpu->dtb_compatible = "arm,arm1026"; | |
427 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
428 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
429 | set_feature(&cpu->env, ARM_FEATURE_AUXCR); | |
430 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
431 | set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); | |
432 | cpu->midr = 0x4106a262; | |
433 | cpu->reset_fpsid = 0x410110a0; | |
434 | cpu->ctr = 0x1dd20d2; | |
435 | cpu->reset_sctlr = 0x00090078; | |
436 | cpu->reset_auxcr = 1; | |
437 | { | |
438 | /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ | |
439 | ARMCPRegInfo ifar = { | |
440 | .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, | |
441 | .access = PL1_RW, | |
442 | .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1), | |
443 | .resetvalue = 0 | |
444 | }; | |
445 | define_one_arm_cp_reg(cpu, &ifar); | |
446 | } | |
447 | } | |
448 | ||
449 | static void arm1136_r2_initfn(Object *obj) | |
450 | { | |
451 | ARMCPU *cpu = ARM_CPU(obj); | |
452 | /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an | |
453 | * older core than plain "arm1136". In particular this does not | |
454 | * have the v6K features. | |
455 | * These ID register values are correct for 1136 but may be wrong | |
456 | * for 1136_r2 (in particular r0p2 does not actually implement most | |
457 | * of the ID registers). | |
458 | */ | |
459 | ||
460 | cpu->dtb_compatible = "arm,arm1136"; | |
461 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
462 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
463 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
464 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
465 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
466 | cpu->midr = 0x4107b362; | |
467 | cpu->reset_fpsid = 0x410120b4; | |
468 | cpu->mvfr0 = 0x11111111; | |
469 | cpu->mvfr1 = 0x00000000; | |
470 | cpu->ctr = 0x1dd20d2; | |
471 | cpu->reset_sctlr = 0x00050078; | |
472 | cpu->id_pfr0 = 0x111; | |
473 | cpu->id_pfr1 = 0x1; | |
474 | cpu->id_dfr0 = 0x2; | |
475 | cpu->id_afr0 = 0x3; | |
476 | cpu->id_mmfr0 = 0x01130003; | |
477 | cpu->id_mmfr1 = 0x10030302; | |
478 | cpu->id_mmfr2 = 0x01222110; | |
479 | cpu->id_isar0 = 0x00140011; | |
480 | cpu->id_isar1 = 0x12002111; | |
481 | cpu->id_isar2 = 0x11231111; | |
482 | cpu->id_isar3 = 0x01102131; | |
483 | cpu->id_isar4 = 0x141; | |
484 | cpu->reset_auxcr = 7; | |
485 | } | |
486 | ||
487 | static void arm1136_initfn(Object *obj) | |
488 | { | |
489 | ARMCPU *cpu = ARM_CPU(obj); | |
490 | ||
491 | cpu->dtb_compatible = "arm,arm1136"; | |
492 | set_feature(&cpu->env, ARM_FEATURE_V6K); | |
493 | set_feature(&cpu->env, ARM_FEATURE_V6); | |
494 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
495 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
496 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
497 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
498 | cpu->midr = 0x4117b363; | |
499 | cpu->reset_fpsid = 0x410120b4; | |
500 | cpu->mvfr0 = 0x11111111; | |
501 | cpu->mvfr1 = 0x00000000; | |
502 | cpu->ctr = 0x1dd20d2; | |
503 | cpu->reset_sctlr = 0x00050078; | |
504 | cpu->id_pfr0 = 0x111; | |
505 | cpu->id_pfr1 = 0x1; | |
506 | cpu->id_dfr0 = 0x2; | |
507 | cpu->id_afr0 = 0x3; | |
508 | cpu->id_mmfr0 = 0x01130003; | |
509 | cpu->id_mmfr1 = 0x10030302; | |
510 | cpu->id_mmfr2 = 0x01222110; | |
511 | cpu->id_isar0 = 0x00140011; | |
512 | cpu->id_isar1 = 0x12002111; | |
513 | cpu->id_isar2 = 0x11231111; | |
514 | cpu->id_isar3 = 0x01102131; | |
515 | cpu->id_isar4 = 0x141; | |
516 | cpu->reset_auxcr = 7; | |
517 | } | |
518 | ||
519 | static void arm1176_initfn(Object *obj) | |
520 | { | |
521 | ARMCPU *cpu = ARM_CPU(obj); | |
522 | ||
523 | cpu->dtb_compatible = "arm,arm1176"; | |
524 | set_feature(&cpu->env, ARM_FEATURE_V6K); | |
525 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
526 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
527 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
528 | set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); | |
529 | set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); | |
530 | cpu->midr = 0x410fb767; | |
531 | cpu->reset_fpsid = 0x410120b5; | |
532 | cpu->mvfr0 = 0x11111111; | |
533 | cpu->mvfr1 = 0x00000000; | |
534 | cpu->ctr = 0x1dd20d2; | |
535 | cpu->reset_sctlr = 0x00050078; | |
536 | cpu->id_pfr0 = 0x111; | |
537 | cpu->id_pfr1 = 0x11; | |
538 | cpu->id_dfr0 = 0x33; | |
539 | cpu->id_afr0 = 0; | |
540 | cpu->id_mmfr0 = 0x01130003; | |
541 | cpu->id_mmfr1 = 0x10030302; | |
542 | cpu->id_mmfr2 = 0x01222100; | |
543 | cpu->id_isar0 = 0x0140011; | |
544 | cpu->id_isar1 = 0x12002111; | |
545 | cpu->id_isar2 = 0x11231121; | |
546 | cpu->id_isar3 = 0x01102131; | |
547 | cpu->id_isar4 = 0x01141; | |
548 | cpu->reset_auxcr = 7; | |
549 | } | |
550 | ||
551 | static void arm11mpcore_initfn(Object *obj) | |
552 | { | |
553 | ARMCPU *cpu = ARM_CPU(obj); | |
554 | ||
555 | cpu->dtb_compatible = "arm,arm11mpcore"; | |
556 | set_feature(&cpu->env, ARM_FEATURE_V6K); | |
557 | set_feature(&cpu->env, ARM_FEATURE_VFP); | |
558 | set_feature(&cpu->env, ARM_FEATURE_VAPA); | |
559 | set_feature(&cpu->env, ARM_FEATURE_MPIDR); | |
560 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
561 | cpu->midr = 0x410fb022; | |
562 | cpu->reset_fpsid = 0x410120b4; | |
563 | cpu->mvfr0 = 0x11111111; | |
564 | cpu->mvfr1 = 0x00000000; | |
565 | cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ | |
566 | cpu->id_pfr0 = 0x111; | |
567 | cpu->id_pfr1 = 0x1; | |
568 | cpu->id_dfr0 = 0; | |
569 | cpu->id_afr0 = 0x2; | |
570 | cpu->id_mmfr0 = 0x01100103; | |
571 | cpu->id_mmfr1 = 0x10020302; | |
572 | cpu->id_mmfr2 = 0x01222000; | |
573 | cpu->id_isar0 = 0x00100011; | |
574 | cpu->id_isar1 = 0x12002111; | |
575 | cpu->id_isar2 = 0x11221011; | |
576 | cpu->id_isar3 = 0x01102131; | |
577 | cpu->id_isar4 = 0x141; | |
578 | cpu->reset_auxcr = 1; | |
579 | } | |
580 | ||
581 | static void cortex_m3_initfn(Object *obj) | |
582 | { | |
583 | ARMCPU *cpu = ARM_CPU(obj); | |
584 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
585 | set_feature(&cpu->env, ARM_FEATURE_M); | |
586 | cpu->midr = 0x410fc231; | |
587 | } | |
588 | ||
589 | static void arm_v7m_class_init(ObjectClass *oc, void *data) | |
590 | { | |
591 | #ifndef CONFIG_USER_ONLY | |
592 | CPUClass *cc = CPU_CLASS(oc); | |
593 | ||
594 | cc->do_interrupt = arm_v7m_cpu_do_interrupt; | |
595 | #endif | |
596 | } | |
597 | ||
598 | static const ARMCPRegInfo cortexa8_cp_reginfo[] = { | |
599 | { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, | |
600 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
601 | { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
602 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
603 | REGINFO_SENTINEL | |
604 | }; | |
605 | ||
606 | static void cortex_a8_initfn(Object *obj) | |
607 | { | |
608 | ARMCPU *cpu = ARM_CPU(obj); | |
609 | ||
610 | cpu->dtb_compatible = "arm,cortex-a8"; | |
611 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
612 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
613 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
614 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
615 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
616 | cpu->midr = 0x410fc080; | |
617 | cpu->reset_fpsid = 0x410330c0; | |
618 | cpu->mvfr0 = 0x11110222; | |
619 | cpu->mvfr1 = 0x00011100; | |
620 | cpu->ctr = 0x82048004; | |
621 | cpu->reset_sctlr = 0x00c50078; | |
622 | cpu->id_pfr0 = 0x1031; | |
623 | cpu->id_pfr1 = 0x11; | |
624 | cpu->id_dfr0 = 0x400; | |
625 | cpu->id_afr0 = 0; | |
626 | cpu->id_mmfr0 = 0x31100003; | |
627 | cpu->id_mmfr1 = 0x20000000; | |
628 | cpu->id_mmfr2 = 0x01202000; | |
629 | cpu->id_mmfr3 = 0x11; | |
630 | cpu->id_isar0 = 0x00101111; | |
631 | cpu->id_isar1 = 0x12112111; | |
632 | cpu->id_isar2 = 0x21232031; | |
633 | cpu->id_isar3 = 0x11112131; | |
634 | cpu->id_isar4 = 0x00111142; | |
635 | cpu->clidr = (1 << 27) | (2 << 24) | 3; | |
636 | cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ | |
637 | cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ | |
638 | cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ | |
639 | cpu->reset_auxcr = 2; | |
640 | define_arm_cp_regs(cpu, cortexa8_cp_reginfo); | |
641 | } | |
642 | ||
643 | static const ARMCPRegInfo cortexa9_cp_reginfo[] = { | |
644 | /* power_control should be set to maximum latency. Again, | |
645 | * default to 0 and set by private hook | |
646 | */ | |
647 | { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, | |
648 | .access = PL1_RW, .resetvalue = 0, | |
649 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, | |
650 | { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, | |
651 | .access = PL1_RW, .resetvalue = 0, | |
652 | .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, | |
653 | { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, | |
654 | .access = PL1_RW, .resetvalue = 0, | |
655 | .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, | |
656 | { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, | |
657 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
658 | /* TLB lockdown control */ | |
659 | { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, | |
660 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
661 | { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, | |
662 | .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, | |
663 | { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, | |
664 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
665 | { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, | |
666 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
667 | { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, | |
668 | .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, | |
669 | REGINFO_SENTINEL | |
670 | }; | |
671 | ||
672 | static void cortex_a9_initfn(Object *obj) | |
673 | { | |
674 | ARMCPU *cpu = ARM_CPU(obj); | |
675 | ||
676 | cpu->dtb_compatible = "arm,cortex-a9"; | |
677 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
678 | set_feature(&cpu->env, ARM_FEATURE_VFP3); | |
679 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
680 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
681 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
682 | /* Note that A9 supports the MP extensions even for | |
683 | * A9UP and single-core A9MP (which are both different | |
684 | * and valid configurations; we don't model A9UP). | |
685 | */ | |
686 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
687 | set_feature(&cpu->env, ARM_FEATURE_CBAR); | |
688 | cpu->midr = 0x410fc090; | |
689 | cpu->reset_fpsid = 0x41033090; | |
690 | cpu->mvfr0 = 0x11110222; | |
691 | cpu->mvfr1 = 0x01111111; | |
692 | cpu->ctr = 0x80038003; | |
693 | cpu->reset_sctlr = 0x00c50078; | |
694 | cpu->id_pfr0 = 0x1031; | |
695 | cpu->id_pfr1 = 0x11; | |
696 | cpu->id_dfr0 = 0x000; | |
697 | cpu->id_afr0 = 0; | |
698 | cpu->id_mmfr0 = 0x00100103; | |
699 | cpu->id_mmfr1 = 0x20000000; | |
700 | cpu->id_mmfr2 = 0x01230000; | |
701 | cpu->id_mmfr3 = 0x00002111; | |
702 | cpu->id_isar0 = 0x00101111; | |
703 | cpu->id_isar1 = 0x13112111; | |
704 | cpu->id_isar2 = 0x21232041; | |
705 | cpu->id_isar3 = 0x11112131; | |
706 | cpu->id_isar4 = 0x00111142; | |
707 | cpu->clidr = (1 << 27) | (1 << 24) | 3; | |
708 | cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ | |
709 | cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ | |
710 | define_arm_cp_regs(cpu, cortexa9_cp_reginfo); | |
711 | } | |
712 | ||
713 | #ifndef CONFIG_USER_ONLY | |
714 | static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) | |
715 | { | |
716 | /* Linux wants the number of processors from here. | |
717 | * Might as well set the interrupt-controller bit too. | |
718 | */ | |
719 | return ((smp_cpus - 1) << 24) | (1 << 23); | |
720 | } | |
721 | #endif | |
722 | ||
723 | static const ARMCPRegInfo cortexa15_cp_reginfo[] = { | |
724 | #ifndef CONFIG_USER_ONLY | |
725 | { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, | |
726 | .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, | |
727 | .writefn = arm_cp_write_ignore, }, | |
728 | #endif | |
729 | { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, | |
730 | .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | |
731 | REGINFO_SENTINEL | |
732 | }; | |
733 | ||
734 | static void cortex_a15_initfn(Object *obj) | |
735 | { | |
736 | ARMCPU *cpu = ARM_CPU(obj); | |
737 | ||
738 | cpu->dtb_compatible = "arm,cortex-a15"; | |
739 | set_feature(&cpu->env, ARM_FEATURE_V7); | |
740 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
741 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
742 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
743 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
744 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
745 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | |
746 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
747 | set_feature(&cpu->env, ARM_FEATURE_CBAR); | |
748 | set_feature(&cpu->env, ARM_FEATURE_LPAE); | |
749 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; | |
750 | cpu->midr = 0x412fc0f1; | |
751 | cpu->reset_fpsid = 0x410430f0; | |
752 | cpu->mvfr0 = 0x10110222; | |
753 | cpu->mvfr1 = 0x11111111; | |
754 | cpu->ctr = 0x8444c004; | |
755 | cpu->reset_sctlr = 0x00c50078; | |
756 | cpu->id_pfr0 = 0x00001131; | |
757 | cpu->id_pfr1 = 0x00011011; | |
758 | cpu->id_dfr0 = 0x02010555; | |
759 | cpu->id_afr0 = 0x00000000; | |
760 | cpu->id_mmfr0 = 0x10201105; | |
761 | cpu->id_mmfr1 = 0x20000000; | |
762 | cpu->id_mmfr2 = 0x01240000; | |
763 | cpu->id_mmfr3 = 0x02102211; | |
764 | cpu->id_isar0 = 0x02101110; | |
765 | cpu->id_isar1 = 0x13112111; | |
766 | cpu->id_isar2 = 0x21232041; | |
767 | cpu->id_isar3 = 0x11112131; | |
768 | cpu->id_isar4 = 0x10011142; | |
769 | cpu->clidr = 0x0a200023; | |
770 | cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ | |
771 | cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ | |
772 | cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ | |
773 | define_arm_cp_regs(cpu, cortexa15_cp_reginfo); | |
774 | } | |
775 | ||
776 | static void ti925t_initfn(Object *obj) | |
777 | { | |
778 | ARMCPU *cpu = ARM_CPU(obj); | |
779 | set_feature(&cpu->env, ARM_FEATURE_V4T); | |
780 | set_feature(&cpu->env, ARM_FEATURE_OMAPCP); | |
781 | cpu->midr = ARM_CPUID_TI925T; | |
782 | cpu->ctr = 0x5109149; | |
783 | cpu->reset_sctlr = 0x00000070; | |
784 | } | |
785 | ||
786 | static void sa1100_initfn(Object *obj) | |
787 | { | |
788 | ARMCPU *cpu = ARM_CPU(obj); | |
789 | ||
790 | cpu->dtb_compatible = "intel,sa1100"; | |
791 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); | |
792 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
793 | cpu->midr = 0x4401A11B; | |
794 | cpu->reset_sctlr = 0x00000070; | |
795 | } | |
796 | ||
797 | static void sa1110_initfn(Object *obj) | |
798 | { | |
799 | ARMCPU *cpu = ARM_CPU(obj); | |
800 | set_feature(&cpu->env, ARM_FEATURE_STRONGARM); | |
801 | set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); | |
802 | cpu->midr = 0x6901B119; | |
803 | cpu->reset_sctlr = 0x00000070; | |
804 | } | |
805 | ||
806 | static void pxa250_initfn(Object *obj) | |
807 | { | |
808 | ARMCPU *cpu = ARM_CPU(obj); | |
809 | ||
810 | cpu->dtb_compatible = "marvell,xscale"; | |
811 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
812 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
813 | cpu->midr = 0x69052100; | |
814 | cpu->ctr = 0xd172172; | |
815 | cpu->reset_sctlr = 0x00000078; | |
816 | } | |
817 | ||
818 | static void pxa255_initfn(Object *obj) | |
819 | { | |
820 | ARMCPU *cpu = ARM_CPU(obj); | |
821 | ||
822 | cpu->dtb_compatible = "marvell,xscale"; | |
823 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
824 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
825 | cpu->midr = 0x69052d00; | |
826 | cpu->ctr = 0xd172172; | |
827 | cpu->reset_sctlr = 0x00000078; | |
828 | } | |
829 | ||
830 | static void pxa260_initfn(Object *obj) | |
831 | { | |
832 | ARMCPU *cpu = ARM_CPU(obj); | |
833 | ||
834 | cpu->dtb_compatible = "marvell,xscale"; | |
835 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
836 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
837 | cpu->midr = 0x69052903; | |
838 | cpu->ctr = 0xd172172; | |
839 | cpu->reset_sctlr = 0x00000078; | |
840 | } | |
841 | ||
842 | static void pxa261_initfn(Object *obj) | |
843 | { | |
844 | ARMCPU *cpu = ARM_CPU(obj); | |
845 | ||
846 | cpu->dtb_compatible = "marvell,xscale"; | |
847 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
848 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
849 | cpu->midr = 0x69052d05; | |
850 | cpu->ctr = 0xd172172; | |
851 | cpu->reset_sctlr = 0x00000078; | |
852 | } | |
853 | ||
854 | static void pxa262_initfn(Object *obj) | |
855 | { | |
856 | ARMCPU *cpu = ARM_CPU(obj); | |
857 | ||
858 | cpu->dtb_compatible = "marvell,xscale"; | |
859 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
860 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
861 | cpu->midr = 0x69052d06; | |
862 | cpu->ctr = 0xd172172; | |
863 | cpu->reset_sctlr = 0x00000078; | |
864 | } | |
865 | ||
866 | static void pxa270a0_initfn(Object *obj) | |
867 | { | |
868 | ARMCPU *cpu = ARM_CPU(obj); | |
869 | ||
870 | cpu->dtb_compatible = "marvell,xscale"; | |
871 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
872 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
873 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
874 | cpu->midr = 0x69054110; | |
875 | cpu->ctr = 0xd172172; | |
876 | cpu->reset_sctlr = 0x00000078; | |
877 | } | |
878 | ||
879 | static void pxa270a1_initfn(Object *obj) | |
880 | { | |
881 | ARMCPU *cpu = ARM_CPU(obj); | |
882 | ||
883 | cpu->dtb_compatible = "marvell,xscale"; | |
884 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
885 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
886 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
887 | cpu->midr = 0x69054111; | |
888 | cpu->ctr = 0xd172172; | |
889 | cpu->reset_sctlr = 0x00000078; | |
890 | } | |
891 | ||
892 | static void pxa270b0_initfn(Object *obj) | |
893 | { | |
894 | ARMCPU *cpu = ARM_CPU(obj); | |
895 | ||
896 | cpu->dtb_compatible = "marvell,xscale"; | |
897 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
898 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
899 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
900 | cpu->midr = 0x69054112; | |
901 | cpu->ctr = 0xd172172; | |
902 | cpu->reset_sctlr = 0x00000078; | |
903 | } | |
904 | ||
905 | static void pxa270b1_initfn(Object *obj) | |
906 | { | |
907 | ARMCPU *cpu = ARM_CPU(obj); | |
908 | ||
909 | cpu->dtb_compatible = "marvell,xscale"; | |
910 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
911 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
912 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
913 | cpu->midr = 0x69054113; | |
914 | cpu->ctr = 0xd172172; | |
915 | cpu->reset_sctlr = 0x00000078; | |
916 | } | |
917 | ||
918 | static void pxa270c0_initfn(Object *obj) | |
919 | { | |
920 | ARMCPU *cpu = ARM_CPU(obj); | |
921 | ||
922 | cpu->dtb_compatible = "marvell,xscale"; | |
923 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
924 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
925 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
926 | cpu->midr = 0x69054114; | |
927 | cpu->ctr = 0xd172172; | |
928 | cpu->reset_sctlr = 0x00000078; | |
929 | } | |
930 | ||
931 | static void pxa270c5_initfn(Object *obj) | |
932 | { | |
933 | ARMCPU *cpu = ARM_CPU(obj); | |
934 | ||
935 | cpu->dtb_compatible = "marvell,xscale"; | |
936 | set_feature(&cpu->env, ARM_FEATURE_V5); | |
937 | set_feature(&cpu->env, ARM_FEATURE_XSCALE); | |
938 | set_feature(&cpu->env, ARM_FEATURE_IWMMXT); | |
939 | cpu->midr = 0x69054117; | |
940 | cpu->ctr = 0xd172172; | |
941 | cpu->reset_sctlr = 0x00000078; | |
942 | } | |
943 | ||
944 | #ifdef CONFIG_USER_ONLY | |
945 | static void arm_any_initfn(Object *obj) | |
946 | { | |
947 | ARMCPU *cpu = ARM_CPU(obj); | |
948 | set_feature(&cpu->env, ARM_FEATURE_V8); | |
949 | set_feature(&cpu->env, ARM_FEATURE_VFP4); | |
950 | set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); | |
951 | set_feature(&cpu->env, ARM_FEATURE_NEON); | |
952 | set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); | |
953 | set_feature(&cpu->env, ARM_FEATURE_ARM_DIV); | |
954 | set_feature(&cpu->env, ARM_FEATURE_V7MP); | |
955 | set_feature(&cpu->env, ARM_FEATURE_CRC); | |
956 | #ifdef TARGET_AARCH64 | |
957 | set_feature(&cpu->env, ARM_FEATURE_AARCH64); | |
958 | #endif | |
959 | cpu->midr = 0xffffffff; | |
960 | } | |
961 | #endif | |
962 | ||
963 | #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ | |
964 | ||
965 | typedef struct ARMCPUInfo { | |
966 | const char *name; | |
967 | void (*initfn)(Object *obj); | |
968 | void (*class_init)(ObjectClass *oc, void *data); | |
969 | } ARMCPUInfo; | |
970 | ||
971 | static const ARMCPUInfo arm_cpus[] = { | |
972 | #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) | |
973 | { .name = "arm926", .initfn = arm926_initfn }, | |
974 | { .name = "arm946", .initfn = arm946_initfn }, | |
975 | { .name = "arm1026", .initfn = arm1026_initfn }, | |
976 | /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an | |
977 | * older core than plain "arm1136". In particular this does not | |
978 | * have the v6K features. | |
979 | */ | |
980 | { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, | |
981 | { .name = "arm1136", .initfn = arm1136_initfn }, | |
982 | { .name = "arm1176", .initfn = arm1176_initfn }, | |
983 | { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, | |
984 | { .name = "cortex-m3", .initfn = cortex_m3_initfn, | |
985 | .class_init = arm_v7m_class_init }, | |
986 | { .name = "cortex-a8", .initfn = cortex_a8_initfn }, | |
987 | { .name = "cortex-a9", .initfn = cortex_a9_initfn }, | |
988 | { .name = "cortex-a15", .initfn = cortex_a15_initfn }, | |
989 | { .name = "ti925t", .initfn = ti925t_initfn }, | |
990 | { .name = "sa1100", .initfn = sa1100_initfn }, | |
991 | { .name = "sa1110", .initfn = sa1110_initfn }, | |
992 | { .name = "pxa250", .initfn = pxa250_initfn }, | |
993 | { .name = "pxa255", .initfn = pxa255_initfn }, | |
994 | { .name = "pxa260", .initfn = pxa260_initfn }, | |
995 | { .name = "pxa261", .initfn = pxa261_initfn }, | |
996 | { .name = "pxa262", .initfn = pxa262_initfn }, | |
997 | /* "pxa270" is an alias for "pxa270-a0" */ | |
998 | { .name = "pxa270", .initfn = pxa270a0_initfn }, | |
999 | { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, | |
1000 | { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, | |
1001 | { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, | |
1002 | { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, | |
1003 | { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, | |
1004 | { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, | |
1005 | #ifdef CONFIG_USER_ONLY | |
1006 | { .name = "any", .initfn = arm_any_initfn }, | |
1007 | #endif | |
1008 | #endif | |
1009 | { .name = NULL } | |
1010 | }; | |
1011 | ||
1012 | static Property arm_cpu_properties[] = { | |
1013 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | |
1014 | DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), | |
1015 | DEFINE_PROP_END_OF_LIST() | |
1016 | }; | |
1017 | ||
1018 | static void arm_cpu_class_init(ObjectClass *oc, void *data) | |
1019 | { | |
1020 | ARMCPUClass *acc = ARM_CPU_CLASS(oc); | |
1021 | CPUClass *cc = CPU_CLASS(acc); | |
1022 | DeviceClass *dc = DEVICE_CLASS(oc); | |
1023 | ||
1024 | acc->parent_realize = dc->realize; | |
1025 | dc->realize = arm_cpu_realizefn; | |
1026 | dc->props = arm_cpu_properties; | |
1027 | ||
1028 | acc->parent_reset = cc->reset; | |
1029 | cc->reset = arm_cpu_reset; | |
1030 | ||
1031 | cc->class_by_name = arm_cpu_class_by_name; | |
1032 | cc->has_work = arm_cpu_has_work; | |
1033 | cc->do_interrupt = arm_cpu_do_interrupt; | |
1034 | cc->dump_state = arm_cpu_dump_state; | |
1035 | cc->set_pc = arm_cpu_set_pc; | |
1036 | cc->gdb_read_register = arm_cpu_gdb_read_register; | |
1037 | cc->gdb_write_register = arm_cpu_gdb_write_register; | |
1038 | #ifdef CONFIG_USER_ONLY | |
1039 | cc->handle_mmu_fault = arm_cpu_handle_mmu_fault; | |
1040 | #else | |
1041 | cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; | |
1042 | cc->vmsd = &vmstate_arm_cpu; | |
1043 | #endif | |
1044 | cc->gdb_num_core_regs = 26; | |
1045 | cc->gdb_core_xml_file = "arm-core.xml"; | |
1046 | } | |
1047 | ||
1048 | static void cpu_register(const ARMCPUInfo *info) | |
1049 | { | |
1050 | TypeInfo type_info = { | |
1051 | .parent = TYPE_ARM_CPU, | |
1052 | .instance_size = sizeof(ARMCPU), | |
1053 | .instance_init = info->initfn, | |
1054 | .class_size = sizeof(ARMCPUClass), | |
1055 | .class_init = info->class_init, | |
1056 | }; | |
1057 | ||
1058 | type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); | |
1059 | type_register(&type_info); | |
1060 | g_free((void *)type_info.name); | |
1061 | } | |
1062 | ||
1063 | static const TypeInfo arm_cpu_type_info = { | |
1064 | .name = TYPE_ARM_CPU, | |
1065 | .parent = TYPE_CPU, | |
1066 | .instance_size = sizeof(ARMCPU), | |
1067 | .instance_init = arm_cpu_initfn, | |
1068 | .instance_post_init = arm_cpu_post_init, | |
1069 | .instance_finalize = arm_cpu_finalizefn, | |
1070 | .abstract = true, | |
1071 | .class_size = sizeof(ARMCPUClass), | |
1072 | .class_init = arm_cpu_class_init, | |
1073 | }; | |
1074 | ||
1075 | static void arm_cpu_register_types(void) | |
1076 | { | |
1077 | const ARMCPUInfo *info = arm_cpus; | |
1078 | ||
1079 | type_register_static(&arm_cpu_type_info); | |
1080 | ||
1081 | while (info->name) { | |
1082 | cpu_register(info); | |
1083 | info++; | |
1084 | } | |
1085 | } | |
1086 | ||
1087 | type_init(arm_cpu_register_types) |