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1 | /* | |
2 | * i386 CPUID helper functions | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include <stdlib.h> | |
20 | #include <stdio.h> | |
21 | #include <string.h> | |
22 | #include <inttypes.h> | |
23 | ||
24 | #include "cpu.h" | |
25 | #include "sysemu/kvm.h" | |
26 | #include "sysemu/cpus.h" | |
27 | #include "topology.h" | |
28 | ||
29 | #include "qemu/option.h" | |
30 | #include "qemu/config-file.h" | |
31 | #include "qapi/qmp/qerror.h" | |
32 | ||
33 | #include "qapi-types.h" | |
34 | #include "qapi-visit.h" | |
35 | #include "qapi/visitor.h" | |
36 | #include "sysemu/arch_init.h" | |
37 | ||
38 | #include "hw/hw.h" | |
39 | #if defined(CONFIG_KVM) | |
40 | #include <linux/kvm_para.h> | |
41 | #endif | |
42 | ||
43 | #include "sysemu/sysemu.h" | |
44 | #include "hw/qdev-properties.h" | |
45 | #include "hw/cpu/icc_bus.h" | |
46 | #ifndef CONFIG_USER_ONLY | |
47 | #include "hw/xen/xen.h" | |
48 | #include "hw/i386/apic_internal.h" | |
49 | #endif | |
50 | ||
51 | ||
52 | /* Cache topology CPUID constants: */ | |
53 | ||
54 | /* CPUID Leaf 2 Descriptors */ | |
55 | ||
56 | #define CPUID_2_L1D_32KB_8WAY_64B 0x2c | |
57 | #define CPUID_2_L1I_32KB_8WAY_64B 0x30 | |
58 | #define CPUID_2_L2_2MB_8WAY_64B 0x7d | |
59 | ||
60 | ||
61 | /* CPUID Leaf 4 constants: */ | |
62 | ||
63 | /* EAX: */ | |
64 | #define CPUID_4_TYPE_DCACHE 1 | |
65 | #define CPUID_4_TYPE_ICACHE 2 | |
66 | #define CPUID_4_TYPE_UNIFIED 3 | |
67 | ||
68 | #define CPUID_4_LEVEL(l) ((l) << 5) | |
69 | ||
70 | #define CPUID_4_SELF_INIT_LEVEL (1 << 8) | |
71 | #define CPUID_4_FULLY_ASSOC (1 << 9) | |
72 | ||
73 | /* EDX: */ | |
74 | #define CPUID_4_NO_INVD_SHARING (1 << 0) | |
75 | #define CPUID_4_INCLUSIVE (1 << 1) | |
76 | #define CPUID_4_COMPLEX_IDX (1 << 2) | |
77 | ||
78 | #define ASSOC_FULL 0xFF | |
79 | ||
80 | /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ | |
81 | #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ | |
82 | a == 2 ? 0x2 : \ | |
83 | a == 4 ? 0x4 : \ | |
84 | a == 8 ? 0x6 : \ | |
85 | a == 16 ? 0x8 : \ | |
86 | a == 32 ? 0xA : \ | |
87 | a == 48 ? 0xB : \ | |
88 | a == 64 ? 0xC : \ | |
89 | a == 96 ? 0xD : \ | |
90 | a == 128 ? 0xE : \ | |
91 | a == ASSOC_FULL ? 0xF : \ | |
92 | 0 /* invalid value */) | |
93 | ||
94 | ||
95 | /* Definitions of the hardcoded cache entries we expose: */ | |
96 | ||
97 | /* L1 data cache: */ | |
98 | #define L1D_LINE_SIZE 64 | |
99 | #define L1D_ASSOCIATIVITY 8 | |
100 | #define L1D_SETS 64 | |
101 | #define L1D_PARTITIONS 1 | |
102 | /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */ | |
103 | #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B | |
104 | /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ | |
105 | #define L1D_LINES_PER_TAG 1 | |
106 | #define L1D_SIZE_KB_AMD 64 | |
107 | #define L1D_ASSOCIATIVITY_AMD 2 | |
108 | ||
109 | /* L1 instruction cache: */ | |
110 | #define L1I_LINE_SIZE 64 | |
111 | #define L1I_ASSOCIATIVITY 8 | |
112 | #define L1I_SETS 64 | |
113 | #define L1I_PARTITIONS 1 | |
114 | /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */ | |
115 | #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B | |
116 | /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ | |
117 | #define L1I_LINES_PER_TAG 1 | |
118 | #define L1I_SIZE_KB_AMD 64 | |
119 | #define L1I_ASSOCIATIVITY_AMD 2 | |
120 | ||
121 | /* Level 2 unified cache: */ | |
122 | #define L2_LINE_SIZE 64 | |
123 | #define L2_ASSOCIATIVITY 16 | |
124 | #define L2_SETS 4096 | |
125 | #define L2_PARTITIONS 1 | |
126 | /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */ | |
127 | /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ | |
128 | #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B | |
129 | /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ | |
130 | #define L2_LINES_PER_TAG 1 | |
131 | #define L2_SIZE_KB_AMD 512 | |
132 | ||
133 | /* No L3 cache: */ | |
134 | #define L3_SIZE_KB 0 /* disabled */ | |
135 | #define L3_ASSOCIATIVITY 0 /* disabled */ | |
136 | #define L3_LINES_PER_TAG 0 /* disabled */ | |
137 | #define L3_LINE_SIZE 0 /* disabled */ | |
138 | ||
139 | /* TLB definitions: */ | |
140 | ||
141 | #define L1_DTLB_2M_ASSOC 1 | |
142 | #define L1_DTLB_2M_ENTRIES 255 | |
143 | #define L1_DTLB_4K_ASSOC 1 | |
144 | #define L1_DTLB_4K_ENTRIES 255 | |
145 | ||
146 | #define L1_ITLB_2M_ASSOC 1 | |
147 | #define L1_ITLB_2M_ENTRIES 255 | |
148 | #define L1_ITLB_4K_ASSOC 1 | |
149 | #define L1_ITLB_4K_ENTRIES 255 | |
150 | ||
151 | #define L2_DTLB_2M_ASSOC 0 /* disabled */ | |
152 | #define L2_DTLB_2M_ENTRIES 0 /* disabled */ | |
153 | #define L2_DTLB_4K_ASSOC 4 | |
154 | #define L2_DTLB_4K_ENTRIES 512 | |
155 | ||
156 | #define L2_ITLB_2M_ASSOC 0 /* disabled */ | |
157 | #define L2_ITLB_2M_ENTRIES 0 /* disabled */ | |
158 | #define L2_ITLB_4K_ASSOC 4 | |
159 | #define L2_ITLB_4K_ENTRIES 512 | |
160 | ||
161 | ||
162 | ||
163 | static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, | |
164 | uint32_t vendor2, uint32_t vendor3) | |
165 | { | |
166 | int i; | |
167 | for (i = 0; i < 4; i++) { | |
168 | dst[i] = vendor1 >> (8 * i); | |
169 | dst[i + 4] = vendor2 >> (8 * i); | |
170 | dst[i + 8] = vendor3 >> (8 * i); | |
171 | } | |
172 | dst[CPUID_VENDOR_SZ] = '\0'; | |
173 | } | |
174 | ||
175 | /* feature flags taken from "Intel Processor Identification and the CPUID | |
176 | * Instruction" and AMD's "CPUID Specification". In cases of disagreement | |
177 | * between feature naming conventions, aliases may be added. | |
178 | */ | |
179 | static const char *feature_name[] = { | |
180 | "fpu", "vme", "de", "pse", | |
181 | "tsc", "msr", "pae", "mce", | |
182 | "cx8", "apic", NULL, "sep", | |
183 | "mtrr", "pge", "mca", "cmov", | |
184 | "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, | |
185 | NULL, "ds" /* Intel dts */, "acpi", "mmx", | |
186 | "fxsr", "sse", "sse2", "ss", | |
187 | "ht" /* Intel htt */, "tm", "ia64", "pbe", | |
188 | }; | |
189 | static const char *ext_feature_name[] = { | |
190 | "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor", | |
191 | "ds_cpl", "vmx", "smx", "est", | |
192 | "tm2", "ssse3", "cid", NULL, | |
193 | "fma", "cx16", "xtpr", "pdcm", | |
194 | NULL, "pcid", "dca", "sse4.1|sse4_1", | |
195 | "sse4.2|sse4_2", "x2apic", "movbe", "popcnt", | |
196 | "tsc-deadline", "aes", "xsave", "osxsave", | |
197 | "avx", "f16c", "rdrand", "hypervisor", | |
198 | }; | |
199 | /* Feature names that are already defined on feature_name[] but are set on | |
200 | * CPUID[8000_0001].EDX on AMD CPUs don't have their names on | |
201 | * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features | |
202 | * if and only if CPU vendor is AMD. | |
203 | */ | |
204 | static const char *ext2_feature_name[] = { | |
205 | NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, | |
206 | NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, | |
207 | NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall", | |
208 | NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, | |
209 | NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, | |
210 | "nx|xd", NULL, "mmxext", NULL /* mmx */, | |
211 | NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp", | |
212 | NULL, "lm|i64", "3dnowext", "3dnow", | |
213 | }; | |
214 | static const char *ext3_feature_name[] = { | |
215 | "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, | |
216 | "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse", | |
217 | "3dnowprefetch", "osvw", "ibs", "xop", | |
218 | "skinit", "wdt", NULL, "lwp", | |
219 | "fma4", "tce", NULL, "nodeid_msr", | |
220 | NULL, "tbm", "topoext", "perfctr_core", | |
221 | "perfctr_nb", NULL, NULL, NULL, | |
222 | NULL, NULL, NULL, NULL, | |
223 | }; | |
224 | ||
225 | static const char *ext4_feature_name[] = { | |
226 | NULL, NULL, "xstore", "xstore-en", | |
227 | NULL, NULL, "xcrypt", "xcrypt-en", | |
228 | "ace2", "ace2-en", "phe", "phe-en", | |
229 | "pmm", "pmm-en", NULL, NULL, | |
230 | NULL, NULL, NULL, NULL, | |
231 | NULL, NULL, NULL, NULL, | |
232 | NULL, NULL, NULL, NULL, | |
233 | NULL, NULL, NULL, NULL, | |
234 | }; | |
235 | ||
236 | static const char *kvm_feature_name[] = { | |
237 | "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", | |
238 | "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL, | |
239 | NULL, NULL, NULL, NULL, | |
240 | NULL, NULL, NULL, NULL, | |
241 | NULL, NULL, NULL, NULL, | |
242 | NULL, NULL, NULL, NULL, | |
243 | NULL, NULL, NULL, NULL, | |
244 | NULL, NULL, NULL, NULL, | |
245 | }; | |
246 | ||
247 | static const char *svm_feature_name[] = { | |
248 | "npt", "lbrv", "svm_lock", "nrip_save", | |
249 | "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists", | |
250 | NULL, NULL, "pause_filter", NULL, | |
251 | "pfthreshold", NULL, NULL, NULL, | |
252 | NULL, NULL, NULL, NULL, | |
253 | NULL, NULL, NULL, NULL, | |
254 | NULL, NULL, NULL, NULL, | |
255 | NULL, NULL, NULL, NULL, | |
256 | }; | |
257 | ||
258 | static const char *cpuid_7_0_ebx_feature_name[] = { | |
259 | "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep", | |
260 | "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL, | |
261 | NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL, | |
262 | NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, | |
263 | }; | |
264 | ||
265 | typedef struct FeatureWordInfo { | |
266 | const char **feat_names; | |
267 | uint32_t cpuid_eax; /* Input EAX for CPUID */ | |
268 | bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */ | |
269 | uint32_t cpuid_ecx; /* Input ECX value for CPUID */ | |
270 | int cpuid_reg; /* output register (R_* constant) */ | |
271 | } FeatureWordInfo; | |
272 | ||
273 | static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { | |
274 | [FEAT_1_EDX] = { | |
275 | .feat_names = feature_name, | |
276 | .cpuid_eax = 1, .cpuid_reg = R_EDX, | |
277 | }, | |
278 | [FEAT_1_ECX] = { | |
279 | .feat_names = ext_feature_name, | |
280 | .cpuid_eax = 1, .cpuid_reg = R_ECX, | |
281 | }, | |
282 | [FEAT_8000_0001_EDX] = { | |
283 | .feat_names = ext2_feature_name, | |
284 | .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX, | |
285 | }, | |
286 | [FEAT_8000_0001_ECX] = { | |
287 | .feat_names = ext3_feature_name, | |
288 | .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX, | |
289 | }, | |
290 | [FEAT_C000_0001_EDX] = { | |
291 | .feat_names = ext4_feature_name, | |
292 | .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX, | |
293 | }, | |
294 | [FEAT_KVM] = { | |
295 | .feat_names = kvm_feature_name, | |
296 | .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX, | |
297 | }, | |
298 | [FEAT_SVM] = { | |
299 | .feat_names = svm_feature_name, | |
300 | .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX, | |
301 | }, | |
302 | [FEAT_7_0_EBX] = { | |
303 | .feat_names = cpuid_7_0_ebx_feature_name, | |
304 | .cpuid_eax = 7, | |
305 | .cpuid_needs_ecx = true, .cpuid_ecx = 0, | |
306 | .cpuid_reg = R_EBX, | |
307 | }, | |
308 | }; | |
309 | ||
310 | typedef struct X86RegisterInfo32 { | |
311 | /* Name of register */ | |
312 | const char *name; | |
313 | /* QAPI enum value register */ | |
314 | X86CPURegister32 qapi_enum; | |
315 | } X86RegisterInfo32; | |
316 | ||
317 | #define REGISTER(reg) \ | |
318 | [R_##reg] = { .name = #reg, .qapi_enum = X86_C_P_U_REGISTER32_##reg } | |
319 | X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { | |
320 | REGISTER(EAX), | |
321 | REGISTER(ECX), | |
322 | REGISTER(EDX), | |
323 | REGISTER(EBX), | |
324 | REGISTER(ESP), | |
325 | REGISTER(EBP), | |
326 | REGISTER(ESI), | |
327 | REGISTER(EDI), | |
328 | }; | |
329 | #undef REGISTER | |
330 | ||
331 | ||
332 | const char *get_register_name_32(unsigned int reg) | |
333 | { | |
334 | if (reg >= CPU_NB_REGS32) { | |
335 | return NULL; | |
336 | } | |
337 | return x86_reg_info_32[reg].name; | |
338 | } | |
339 | ||
340 | /* collects per-function cpuid data | |
341 | */ | |
342 | typedef struct model_features_t { | |
343 | uint32_t *guest_feat; | |
344 | uint32_t *host_feat; | |
345 | FeatureWord feat_word; | |
346 | } model_features_t; | |
347 | ||
348 | int check_cpuid = 0; | |
349 | int enforce_cpuid = 0; | |
350 | ||
351 | static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) | | |
352 | (1 << KVM_FEATURE_NOP_IO_DELAY) | | |
353 | (1 << KVM_FEATURE_CLOCKSOURCE2) | | |
354 | (1 << KVM_FEATURE_ASYNC_PF) | | |
355 | (1 << KVM_FEATURE_STEAL_TIME) | | |
356 | (1 << KVM_FEATURE_PV_EOI) | | |
357 | (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT); | |
358 | ||
359 | void disable_kvm_pv_eoi(void) | |
360 | { | |
361 | kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI); | |
362 | } | |
363 | ||
364 | void host_cpuid(uint32_t function, uint32_t count, | |
365 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) | |
366 | { | |
367 | #if defined(CONFIG_KVM) | |
368 | uint32_t vec[4]; | |
369 | ||
370 | #ifdef __x86_64__ | |
371 | asm volatile("cpuid" | |
372 | : "=a"(vec[0]), "=b"(vec[1]), | |
373 | "=c"(vec[2]), "=d"(vec[3]) | |
374 | : "0"(function), "c"(count) : "cc"); | |
375 | #else | |
376 | asm volatile("pusha \n\t" | |
377 | "cpuid \n\t" | |
378 | "mov %%eax, 0(%2) \n\t" | |
379 | "mov %%ebx, 4(%2) \n\t" | |
380 | "mov %%ecx, 8(%2) \n\t" | |
381 | "mov %%edx, 12(%2) \n\t" | |
382 | "popa" | |
383 | : : "a"(function), "c"(count), "S"(vec) | |
384 | : "memory", "cc"); | |
385 | #endif | |
386 | ||
387 | if (eax) | |
388 | *eax = vec[0]; | |
389 | if (ebx) | |
390 | *ebx = vec[1]; | |
391 | if (ecx) | |
392 | *ecx = vec[2]; | |
393 | if (edx) | |
394 | *edx = vec[3]; | |
395 | #endif | |
396 | } | |
397 | ||
398 | #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c))) | |
399 | ||
400 | /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of | |
401 | * a substring. ex if !NULL points to the first char after a substring, | |
402 | * otherwise the string is assumed to sized by a terminating nul. | |
403 | * Return lexical ordering of *s1:*s2. | |
404 | */ | |
405 | static int sstrcmp(const char *s1, const char *e1, const char *s2, | |
406 | const char *e2) | |
407 | { | |
408 | for (;;) { | |
409 | if (!*s1 || !*s2 || *s1 != *s2) | |
410 | return (*s1 - *s2); | |
411 | ++s1, ++s2; | |
412 | if (s1 == e1 && s2 == e2) | |
413 | return (0); | |
414 | else if (s1 == e1) | |
415 | return (*s2); | |
416 | else if (s2 == e2) | |
417 | return (*s1); | |
418 | } | |
419 | } | |
420 | ||
421 | /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple | |
422 | * '|' delimited (possibly empty) strings in which case search for a match | |
423 | * within the alternatives proceeds left to right. Return 0 for success, | |
424 | * non-zero otherwise. | |
425 | */ | |
426 | static int altcmp(const char *s, const char *e, const char *altstr) | |
427 | { | |
428 | const char *p, *q; | |
429 | ||
430 | for (q = p = altstr; ; ) { | |
431 | while (*p && *p != '|') | |
432 | ++p; | |
433 | if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p))) | |
434 | return (0); | |
435 | if (!*p) | |
436 | return (1); | |
437 | else | |
438 | q = ++p; | |
439 | } | |
440 | } | |
441 | ||
442 | /* search featureset for flag *[s..e), if found set corresponding bit in | |
443 | * *pval and return true, otherwise return false | |
444 | */ | |
445 | static bool lookup_feature(uint32_t *pval, const char *s, const char *e, | |
446 | const char **featureset) | |
447 | { | |
448 | uint32_t mask; | |
449 | const char **ppc; | |
450 | bool found = false; | |
451 | ||
452 | for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) { | |
453 | if (*ppc && !altcmp(s, e, *ppc)) { | |
454 | *pval |= mask; | |
455 | found = true; | |
456 | } | |
457 | } | |
458 | return found; | |
459 | } | |
460 | ||
461 | static void add_flagname_to_bitmaps(const char *flagname, | |
462 | FeatureWordArray words) | |
463 | { | |
464 | FeatureWord w; | |
465 | for (w = 0; w < FEATURE_WORDS; w++) { | |
466 | FeatureWordInfo *wi = &feature_word_info[w]; | |
467 | if (wi->feat_names && | |
468 | lookup_feature(&words[w], flagname, NULL, wi->feat_names)) { | |
469 | break; | |
470 | } | |
471 | } | |
472 | if (w == FEATURE_WORDS) { | |
473 | fprintf(stderr, "CPU feature %s not found\n", flagname); | |
474 | } | |
475 | } | |
476 | ||
477 | typedef struct x86_def_t { | |
478 | const char *name; | |
479 | uint32_t level; | |
480 | uint32_t xlevel; | |
481 | uint32_t xlevel2; | |
482 | /* vendor is zero-terminated, 12 character ASCII string */ | |
483 | char vendor[CPUID_VENDOR_SZ + 1]; | |
484 | int family; | |
485 | int model; | |
486 | int stepping; | |
487 | FeatureWordArray features; | |
488 | char model_id[48]; | |
489 | bool cache_info_passthrough; | |
490 | } x86_def_t; | |
491 | ||
492 | #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) | |
493 | #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ | |
494 | CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) | |
495 | #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ | |
496 | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ | |
497 | CPUID_PSE36 | CPUID_FXSR) | |
498 | #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) | |
499 | #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ | |
500 | CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ | |
501 | CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ | |
502 | CPUID_PAE | CPUID_SEP | CPUID_APIC) | |
503 | ||
504 | #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ | |
505 | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ | |
506 | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ | |
507 | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ | |
508 | CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS) | |
509 | /* partly implemented: | |
510 | CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) | |
511 | CPUID_PSE36 (needed for Solaris) */ | |
512 | /* missing: | |
513 | CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ | |
514 | #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ | |
515 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ | |
516 | CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ | |
517 | CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR) | |
518 | /* missing: | |
519 | CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, | |
520 | CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA, | |
521 | CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, | |
522 | CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE, | |
523 | CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C, | |
524 | CPUID_EXT_RDRAND */ | |
525 | #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ | |
526 | CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ | |
527 | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT) | |
528 | /* missing: | |
529 | CPUID_EXT2_PDPE1GB */ | |
530 | #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ | |
531 | CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) | |
532 | #define TCG_SVM_FEATURES 0 | |
533 | #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \ | |
534 | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX) | |
535 | /* missing: | |
536 | CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2, | |
537 | CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, | |
538 | CPUID_7_0_EBX_RDSEED */ | |
539 | ||
540 | /* built-in CPU model definitions | |
541 | */ | |
542 | static x86_def_t builtin_x86_defs[] = { | |
543 | { | |
544 | .name = "qemu64", | |
545 | .level = 4, | |
546 | .vendor = CPUID_VENDOR_AMD, | |
547 | .family = 6, | |
548 | .model = 2, | |
549 | .stepping = 3, | |
550 | .features[FEAT_1_EDX] = | |
551 | PPRO_FEATURES | | |
552 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | | |
553 | CPUID_PSE36, | |
554 | .features[FEAT_1_ECX] = | |
555 | CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, | |
556 | .features[FEAT_8000_0001_EDX] = | |
557 | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | | |
558 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, | |
559 | .features[FEAT_8000_0001_ECX] = | |
560 | CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | | |
561 | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, | |
562 | .xlevel = 0x8000000A, | |
563 | }, | |
564 | { | |
565 | .name = "phenom", | |
566 | .level = 5, | |
567 | .vendor = CPUID_VENDOR_AMD, | |
568 | .family = 16, | |
569 | .model = 2, | |
570 | .stepping = 3, | |
571 | .features[FEAT_1_EDX] = | |
572 | PPRO_FEATURES | | |
573 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | | |
574 | CPUID_PSE36 | CPUID_VME | CPUID_HT, | |
575 | .features[FEAT_1_ECX] = | |
576 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | | |
577 | CPUID_EXT_POPCNT, | |
578 | .features[FEAT_8000_0001_EDX] = | |
579 | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | | |
580 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | | |
581 | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | | |
582 | CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, | |
583 | /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, | |
584 | CPUID_EXT3_CR8LEG, | |
585 | CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, | |
586 | CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ | |
587 | .features[FEAT_8000_0001_ECX] = | |
588 | CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | | |
589 | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, | |
590 | .features[FEAT_SVM] = | |
591 | CPUID_SVM_NPT | CPUID_SVM_LBRV, | |
592 | .xlevel = 0x8000001A, | |
593 | .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" | |
594 | }, | |
595 | { | |
596 | .name = "core2duo", | |
597 | .level = 10, | |
598 | .vendor = CPUID_VENDOR_INTEL, | |
599 | .family = 6, | |
600 | .model = 15, | |
601 | .stepping = 11, | |
602 | .features[FEAT_1_EDX] = | |
603 | PPRO_FEATURES | | |
604 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | | |
605 | CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS | | |
606 | CPUID_HT | CPUID_TM | CPUID_PBE, | |
607 | .features[FEAT_1_ECX] = | |
608 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | | |
609 | CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST | | |
610 | CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, | |
611 | .features[FEAT_8000_0001_EDX] = | |
612 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, | |
613 | .features[FEAT_8000_0001_ECX] = | |
614 | CPUID_EXT3_LAHF_LM, | |
615 | .xlevel = 0x80000008, | |
616 | .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", | |
617 | }, | |
618 | { | |
619 | .name = "kvm64", | |
620 | .level = 5, | |
621 | .vendor = CPUID_VENDOR_INTEL, | |
622 | .family = 15, | |
623 | .model = 6, | |
624 | .stepping = 1, | |
625 | /* Missing: CPUID_VME, CPUID_HT */ | |
626 | .features[FEAT_1_EDX] = | |
627 | PPRO_FEATURES | | |
628 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | | |
629 | CPUID_PSE36, | |
630 | /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ | |
631 | .features[FEAT_1_ECX] = | |
632 | CPUID_EXT_SSE3 | CPUID_EXT_CX16, | |
633 | /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ | |
634 | .features[FEAT_8000_0001_EDX] = | |
635 | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | | |
636 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, | |
637 | /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, | |
638 | CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, | |
639 | CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, | |
640 | CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ | |
641 | .features[FEAT_8000_0001_ECX] = | |
642 | 0, | |
643 | .xlevel = 0x80000008, | |
644 | .model_id = "Common KVM processor" | |
645 | }, | |
646 | { | |
647 | .name = "qemu32", | |
648 | .level = 4, | |
649 | .vendor = CPUID_VENDOR_INTEL, | |
650 | .family = 6, | |
651 | .model = 3, | |
652 | .stepping = 3, | |
653 | .features[FEAT_1_EDX] = | |
654 | PPRO_FEATURES, | |
655 | .features[FEAT_1_ECX] = | |
656 | CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, | |
657 | .xlevel = 0x80000004, | |
658 | }, | |
659 | { | |
660 | .name = "kvm32", | |
661 | .level = 5, | |
662 | .vendor = CPUID_VENDOR_INTEL, | |
663 | .family = 15, | |
664 | .model = 6, | |
665 | .stepping = 1, | |
666 | .features[FEAT_1_EDX] = | |
667 | PPRO_FEATURES | | |
668 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, | |
669 | .features[FEAT_1_ECX] = | |
670 | CPUID_EXT_SSE3, | |
671 | .features[FEAT_8000_0001_EDX] = | |
672 | PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES, | |
673 | .features[FEAT_8000_0001_ECX] = | |
674 | 0, | |
675 | .xlevel = 0x80000008, | |
676 | .model_id = "Common 32-bit KVM processor" | |
677 | }, | |
678 | { | |
679 | .name = "coreduo", | |
680 | .level = 10, | |
681 | .vendor = CPUID_VENDOR_INTEL, | |
682 | .family = 6, | |
683 | .model = 14, | |
684 | .stepping = 8, | |
685 | .features[FEAT_1_EDX] = | |
686 | PPRO_FEATURES | CPUID_VME | | |
687 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI | | |
688 | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, | |
689 | .features[FEAT_1_ECX] = | |
690 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX | | |
691 | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, | |
692 | .features[FEAT_8000_0001_EDX] = | |
693 | CPUID_EXT2_NX, | |
694 | .xlevel = 0x80000008, | |
695 | .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", | |
696 | }, | |
697 | { | |
698 | .name = "486", | |
699 | .level = 1, | |
700 | .vendor = CPUID_VENDOR_INTEL, | |
701 | .family = 4, | |
702 | .model = 8, | |
703 | .stepping = 0, | |
704 | .features[FEAT_1_EDX] = | |
705 | I486_FEATURES, | |
706 | .xlevel = 0, | |
707 | }, | |
708 | { | |
709 | .name = "pentium", | |
710 | .level = 1, | |
711 | .vendor = CPUID_VENDOR_INTEL, | |
712 | .family = 5, | |
713 | .model = 4, | |
714 | .stepping = 3, | |
715 | .features[FEAT_1_EDX] = | |
716 | PENTIUM_FEATURES, | |
717 | .xlevel = 0, | |
718 | }, | |
719 | { | |
720 | .name = "pentium2", | |
721 | .level = 2, | |
722 | .vendor = CPUID_VENDOR_INTEL, | |
723 | .family = 6, | |
724 | .model = 5, | |
725 | .stepping = 2, | |
726 | .features[FEAT_1_EDX] = | |
727 | PENTIUM2_FEATURES, | |
728 | .xlevel = 0, | |
729 | }, | |
730 | { | |
731 | .name = "pentium3", | |
732 | .level = 2, | |
733 | .vendor = CPUID_VENDOR_INTEL, | |
734 | .family = 6, | |
735 | .model = 7, | |
736 | .stepping = 3, | |
737 | .features[FEAT_1_EDX] = | |
738 | PENTIUM3_FEATURES, | |
739 | .xlevel = 0, | |
740 | }, | |
741 | { | |
742 | .name = "athlon", | |
743 | .level = 2, | |
744 | .vendor = CPUID_VENDOR_AMD, | |
745 | .family = 6, | |
746 | .model = 2, | |
747 | .stepping = 3, | |
748 | .features[FEAT_1_EDX] = | |
749 | PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | | |
750 | CPUID_MCA, | |
751 | .features[FEAT_8000_0001_EDX] = | |
752 | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | | |
753 | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, | |
754 | .xlevel = 0x80000008, | |
755 | }, | |
756 | { | |
757 | .name = "n270", | |
758 | /* original is on level 10 */ | |
759 | .level = 5, | |
760 | .vendor = CPUID_VENDOR_INTEL, | |
761 | .family = 6, | |
762 | .model = 28, | |
763 | .stepping = 2, | |
764 | .features[FEAT_1_EDX] = | |
765 | PPRO_FEATURES | | |
766 | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS | | |
767 | CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, | |
768 | /* Some CPUs got no CPUID_SEP */ | |
769 | .features[FEAT_1_ECX] = | |
770 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | | |
771 | CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | | |
772 | CPUID_EXT_MOVBE, | |
773 | .features[FEAT_8000_0001_EDX] = | |
774 | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | | |
775 | CPUID_EXT2_NX, | |
776 | .features[FEAT_8000_0001_ECX] = | |
777 | CPUID_EXT3_LAHF_LM, | |
778 | .xlevel = 0x8000000A, | |
779 | .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", | |
780 | }, | |
781 | { | |
782 | .name = "Conroe", | |
783 | .level = 4, | |
784 | .vendor = CPUID_VENDOR_INTEL, | |
785 | .family = 6, | |
786 | .model = 15, | |
787 | .stepping = 3, | |
788 | .features[FEAT_1_EDX] = | |
789 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
790 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
791 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
792 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
793 | CPUID_DE | CPUID_FP87, | |
794 | .features[FEAT_1_ECX] = | |
795 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, | |
796 | .features[FEAT_8000_0001_EDX] = | |
797 | CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, | |
798 | .features[FEAT_8000_0001_ECX] = | |
799 | CPUID_EXT3_LAHF_LM, | |
800 | .xlevel = 0x8000000A, | |
801 | .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", | |
802 | }, | |
803 | { | |
804 | .name = "Penryn", | |
805 | .level = 4, | |
806 | .vendor = CPUID_VENDOR_INTEL, | |
807 | .family = 6, | |
808 | .model = 23, | |
809 | .stepping = 3, | |
810 | .features[FEAT_1_EDX] = | |
811 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
812 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
813 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
814 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
815 | CPUID_DE | CPUID_FP87, | |
816 | .features[FEAT_1_ECX] = | |
817 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | | |
818 | CPUID_EXT_SSE3, | |
819 | .features[FEAT_8000_0001_EDX] = | |
820 | CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, | |
821 | .features[FEAT_8000_0001_ECX] = | |
822 | CPUID_EXT3_LAHF_LM, | |
823 | .xlevel = 0x8000000A, | |
824 | .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", | |
825 | }, | |
826 | { | |
827 | .name = "Nehalem", | |
828 | .level = 4, | |
829 | .vendor = CPUID_VENDOR_INTEL, | |
830 | .family = 6, | |
831 | .model = 26, | |
832 | .stepping = 3, | |
833 | .features[FEAT_1_EDX] = | |
834 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
835 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
836 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
837 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
838 | CPUID_DE | CPUID_FP87, | |
839 | .features[FEAT_1_ECX] = | |
840 | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | | |
841 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, | |
842 | .features[FEAT_8000_0001_EDX] = | |
843 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, | |
844 | .features[FEAT_8000_0001_ECX] = | |
845 | CPUID_EXT3_LAHF_LM, | |
846 | .xlevel = 0x8000000A, | |
847 | .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", | |
848 | }, | |
849 | { | |
850 | .name = "Westmere", | |
851 | .level = 11, | |
852 | .vendor = CPUID_VENDOR_INTEL, | |
853 | .family = 6, | |
854 | .model = 44, | |
855 | .stepping = 1, | |
856 | .features[FEAT_1_EDX] = | |
857 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
858 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
859 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
860 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
861 | CPUID_DE | CPUID_FP87, | |
862 | .features[FEAT_1_ECX] = | |
863 | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | | |
864 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | | |
865 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, | |
866 | .features[FEAT_8000_0001_EDX] = | |
867 | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, | |
868 | .features[FEAT_8000_0001_ECX] = | |
869 | CPUID_EXT3_LAHF_LM, | |
870 | .xlevel = 0x8000000A, | |
871 | .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", | |
872 | }, | |
873 | { | |
874 | .name = "SandyBridge", | |
875 | .level = 0xd, | |
876 | .vendor = CPUID_VENDOR_INTEL, | |
877 | .family = 6, | |
878 | .model = 42, | |
879 | .stepping = 1, | |
880 | .features[FEAT_1_EDX] = | |
881 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
882 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
883 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
884 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
885 | CPUID_DE | CPUID_FP87, | |
886 | .features[FEAT_1_ECX] = | |
887 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | | |
888 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | | |
889 | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | | |
890 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | | |
891 | CPUID_EXT_SSE3, | |
892 | .features[FEAT_8000_0001_EDX] = | |
893 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | | |
894 | CPUID_EXT2_SYSCALL, | |
895 | .features[FEAT_8000_0001_ECX] = | |
896 | CPUID_EXT3_LAHF_LM, | |
897 | .xlevel = 0x8000000A, | |
898 | .model_id = "Intel Xeon E312xx (Sandy Bridge)", | |
899 | }, | |
900 | { | |
901 | .name = "Haswell", | |
902 | .level = 0xd, | |
903 | .vendor = CPUID_VENDOR_INTEL, | |
904 | .family = 6, | |
905 | .model = 60, | |
906 | .stepping = 1, | |
907 | .features[FEAT_1_EDX] = | |
908 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
909 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
910 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
911 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
912 | CPUID_DE | CPUID_FP87, | |
913 | .features[FEAT_1_ECX] = | |
914 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | | |
915 | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | | |
916 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | | |
917 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | | |
918 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | | |
919 | CPUID_EXT_PCID, | |
920 | .features[FEAT_8000_0001_EDX] = | |
921 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | | |
922 | CPUID_EXT2_SYSCALL, | |
923 | .features[FEAT_8000_0001_ECX] = | |
924 | CPUID_EXT3_LAHF_LM, | |
925 | .features[FEAT_7_0_EBX] = | |
926 | CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | | |
927 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | | |
928 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | | |
929 | CPUID_7_0_EBX_RTM, | |
930 | .xlevel = 0x8000000A, | |
931 | .model_id = "Intel Core Processor (Haswell)", | |
932 | }, | |
933 | { | |
934 | .name = "Opteron_G1", | |
935 | .level = 5, | |
936 | .vendor = CPUID_VENDOR_AMD, | |
937 | .family = 15, | |
938 | .model = 6, | |
939 | .stepping = 1, | |
940 | .features[FEAT_1_EDX] = | |
941 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
942 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
943 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
944 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
945 | CPUID_DE | CPUID_FP87, | |
946 | .features[FEAT_1_ECX] = | |
947 | CPUID_EXT_SSE3, | |
948 | .features[FEAT_8000_0001_EDX] = | |
949 | CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | | |
950 | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | | |
951 | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | | |
952 | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | | |
953 | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | | |
954 | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
955 | .xlevel = 0x80000008, | |
956 | .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", | |
957 | }, | |
958 | { | |
959 | .name = "Opteron_G2", | |
960 | .level = 5, | |
961 | .vendor = CPUID_VENDOR_AMD, | |
962 | .family = 15, | |
963 | .model = 6, | |
964 | .stepping = 1, | |
965 | .features[FEAT_1_EDX] = | |
966 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
967 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
968 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
969 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
970 | CPUID_DE | CPUID_FP87, | |
971 | .features[FEAT_1_ECX] = | |
972 | CPUID_EXT_CX16 | CPUID_EXT_SSE3, | |
973 | .features[FEAT_8000_0001_EDX] = | |
974 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | | |
975 | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | | |
976 | CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | | |
977 | CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | | |
978 | CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | | |
979 | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | | |
980 | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
981 | .features[FEAT_8000_0001_ECX] = | |
982 | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, | |
983 | .xlevel = 0x80000008, | |
984 | .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", | |
985 | }, | |
986 | { | |
987 | .name = "Opteron_G3", | |
988 | .level = 5, | |
989 | .vendor = CPUID_VENDOR_AMD, | |
990 | .family = 15, | |
991 | .model = 6, | |
992 | .stepping = 1, | |
993 | .features[FEAT_1_EDX] = | |
994 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
995 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
996 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
997 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
998 | CPUID_DE | CPUID_FP87, | |
999 | .features[FEAT_1_ECX] = | |
1000 | CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | | |
1001 | CPUID_EXT_SSE3, | |
1002 | .features[FEAT_8000_0001_EDX] = | |
1003 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | | |
1004 | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | | |
1005 | CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | | |
1006 | CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | | |
1007 | CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | | |
1008 | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | | |
1009 | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
1010 | .features[FEAT_8000_0001_ECX] = | |
1011 | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | | |
1012 | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, | |
1013 | .xlevel = 0x80000008, | |
1014 | .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", | |
1015 | }, | |
1016 | { | |
1017 | .name = "Opteron_G4", | |
1018 | .level = 0xd, | |
1019 | .vendor = CPUID_VENDOR_AMD, | |
1020 | .family = 21, | |
1021 | .model = 1, | |
1022 | .stepping = 2, | |
1023 | .features[FEAT_1_EDX] = | |
1024 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
1025 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
1026 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1027 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1028 | CPUID_DE | CPUID_FP87, | |
1029 | .features[FEAT_1_ECX] = | |
1030 | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | | |
1031 | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | | |
1032 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | | |
1033 | CPUID_EXT_SSE3, | |
1034 | .features[FEAT_8000_0001_EDX] = | |
1035 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | | |
1036 | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | | |
1037 | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | | |
1038 | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | | |
1039 | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | | |
1040 | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | | |
1041 | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
1042 | .features[FEAT_8000_0001_ECX] = | |
1043 | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | | |
1044 | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | | |
1045 | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | | |
1046 | CPUID_EXT3_LAHF_LM, | |
1047 | .xlevel = 0x8000001A, | |
1048 | .model_id = "AMD Opteron 62xx class CPU", | |
1049 | }, | |
1050 | { | |
1051 | .name = "Opteron_G5", | |
1052 | .level = 0xd, | |
1053 | .vendor = CPUID_VENDOR_AMD, | |
1054 | .family = 21, | |
1055 | .model = 2, | |
1056 | .stepping = 0, | |
1057 | .features[FEAT_1_EDX] = | |
1058 | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | | |
1059 | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | | |
1060 | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | | |
1061 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | | |
1062 | CPUID_DE | CPUID_FP87, | |
1063 | .features[FEAT_1_ECX] = | |
1064 | CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | | |
1065 | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | | |
1066 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | | |
1067 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, | |
1068 | .features[FEAT_8000_0001_EDX] = | |
1069 | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | | |
1070 | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | | |
1071 | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | | |
1072 | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | | |
1073 | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | | |
1074 | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | | |
1075 | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, | |
1076 | .features[FEAT_8000_0001_ECX] = | |
1077 | CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | | |
1078 | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | | |
1079 | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | | |
1080 | CPUID_EXT3_LAHF_LM, | |
1081 | .xlevel = 0x8000001A, | |
1082 | .model_id = "AMD Opteron 63xx class CPU", | |
1083 | }, | |
1084 | }; | |
1085 | ||
1086 | /** | |
1087 | * x86_cpu_compat_set_features: | |
1088 | * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed | |
1089 | * @w: Identifies the feature word to be changed. | |
1090 | * @feat_add: Feature bits to be added to feature word | |
1091 | * @feat_remove: Feature bits to be removed from feature word | |
1092 | * | |
1093 | * Change CPU model feature bits for compatibility. | |
1094 | * | |
1095 | * This function may be used by machine-type compatibility functions | |
1096 | * to enable or disable feature bits on specific CPU models. | |
1097 | */ | |
1098 | void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w, | |
1099 | uint32_t feat_add, uint32_t feat_remove) | |
1100 | { | |
1101 | x86_def_t *def; | |
1102 | int i; | |
1103 | for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { | |
1104 | def = &builtin_x86_defs[i]; | |
1105 | if (!cpu_model || !strcmp(cpu_model, def->name)) { | |
1106 | def->features[w] |= feat_add; | |
1107 | def->features[w] &= ~feat_remove; | |
1108 | } | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | #ifdef CONFIG_KVM | |
1113 | static int cpu_x86_fill_model_id(char *str) | |
1114 | { | |
1115 | uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; | |
1116 | int i; | |
1117 | ||
1118 | for (i = 0; i < 3; i++) { | |
1119 | host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); | |
1120 | memcpy(str + i * 16 + 0, &eax, 4); | |
1121 | memcpy(str + i * 16 + 4, &ebx, 4); | |
1122 | memcpy(str + i * 16 + 8, &ecx, 4); | |
1123 | memcpy(str + i * 16 + 12, &edx, 4); | |
1124 | } | |
1125 | return 0; | |
1126 | } | |
1127 | #endif | |
1128 | ||
1129 | /* Fill a x86_def_t struct with information about the host CPU, and | |
1130 | * the CPU features supported by the host hardware + host kernel | |
1131 | * | |
1132 | * This function may be called only if KVM is enabled. | |
1133 | */ | |
1134 | static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def) | |
1135 | { | |
1136 | #ifdef CONFIG_KVM | |
1137 | KVMState *s = kvm_state; | |
1138 | uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; | |
1139 | ||
1140 | assert(kvm_enabled()); | |
1141 | ||
1142 | x86_cpu_def->name = "host"; | |
1143 | x86_cpu_def->cache_info_passthrough = true; | |
1144 | host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); | |
1145 | x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx); | |
1146 | ||
1147 | host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); | |
1148 | x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); | |
1149 | x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); | |
1150 | x86_cpu_def->stepping = eax & 0x0F; | |
1151 | ||
1152 | x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); | |
1153 | x86_cpu_def->features[FEAT_1_EDX] = | |
1154 | kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX); | |
1155 | x86_cpu_def->features[FEAT_1_ECX] = | |
1156 | kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX); | |
1157 | ||
1158 | if (x86_cpu_def->level >= 7) { | |
1159 | x86_cpu_def->features[FEAT_7_0_EBX] = | |
1160 | kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX); | |
1161 | } else { | |
1162 | x86_cpu_def->features[FEAT_7_0_EBX] = 0; | |
1163 | } | |
1164 | ||
1165 | x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); | |
1166 | x86_cpu_def->features[FEAT_8000_0001_EDX] = | |
1167 | kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX); | |
1168 | x86_cpu_def->features[FEAT_8000_0001_ECX] = | |
1169 | kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX); | |
1170 | ||
1171 | cpu_x86_fill_model_id(x86_cpu_def->model_id); | |
1172 | ||
1173 | /* Call Centaur's CPUID instruction. */ | |
1174 | if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) { | |
1175 | host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx); | |
1176 | eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); | |
1177 | if (eax >= 0xC0000001) { | |
1178 | /* Support VIA max extended level */ | |
1179 | x86_cpu_def->xlevel2 = eax; | |
1180 | host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx); | |
1181 | x86_cpu_def->features[FEAT_C000_0001_EDX] = | |
1182 | kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX); | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | /* Other KVM-specific feature fields: */ | |
1187 | x86_cpu_def->features[FEAT_SVM] = | |
1188 | kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX); | |
1189 | x86_cpu_def->features[FEAT_KVM] = | |
1190 | kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); | |
1191 | ||
1192 | #endif /* CONFIG_KVM */ | |
1193 | } | |
1194 | ||
1195 | static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask) | |
1196 | { | |
1197 | int i; | |
1198 | ||
1199 | for (i = 0; i < 32; ++i) | |
1200 | if (1 << i & mask) { | |
1201 | const char *reg = get_register_name_32(f->cpuid_reg); | |
1202 | assert(reg); | |
1203 | fprintf(stderr, "warning: host doesn't support requested feature: " | |
1204 | "CPUID.%02XH:%s%s%s [bit %d]\n", | |
1205 | f->cpuid_eax, reg, | |
1206 | f->feat_names[i] ? "." : "", | |
1207 | f->feat_names[i] ? f->feat_names[i] : "", i); | |
1208 | break; | |
1209 | } | |
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | /* Check if all requested cpu flags are making their way to the guest | |
1214 | * | |
1215 | * Returns 0 if all flags are supported by the host, non-zero otherwise. | |
1216 | * | |
1217 | * This function may be called only if KVM is enabled. | |
1218 | */ | |
1219 | static int kvm_check_features_against_host(X86CPU *cpu) | |
1220 | { | |
1221 | CPUX86State *env = &cpu->env; | |
1222 | x86_def_t host_def; | |
1223 | uint32_t mask; | |
1224 | int rv, i; | |
1225 | struct model_features_t ft[] = { | |
1226 | {&env->features[FEAT_1_EDX], | |
1227 | &host_def.features[FEAT_1_EDX], | |
1228 | FEAT_1_EDX }, | |
1229 | {&env->features[FEAT_1_ECX], | |
1230 | &host_def.features[FEAT_1_ECX], | |
1231 | FEAT_1_ECX }, | |
1232 | {&env->features[FEAT_8000_0001_EDX], | |
1233 | &host_def.features[FEAT_8000_0001_EDX], | |
1234 | FEAT_8000_0001_EDX }, | |
1235 | {&env->features[FEAT_8000_0001_ECX], | |
1236 | &host_def.features[FEAT_8000_0001_ECX], | |
1237 | FEAT_8000_0001_ECX }, | |
1238 | {&env->features[FEAT_C000_0001_EDX], | |
1239 | &host_def.features[FEAT_C000_0001_EDX], | |
1240 | FEAT_C000_0001_EDX }, | |
1241 | {&env->features[FEAT_7_0_EBX], | |
1242 | &host_def.features[FEAT_7_0_EBX], | |
1243 | FEAT_7_0_EBX }, | |
1244 | {&env->features[FEAT_SVM], | |
1245 | &host_def.features[FEAT_SVM], | |
1246 | FEAT_SVM }, | |
1247 | {&env->features[FEAT_KVM], | |
1248 | &host_def.features[FEAT_KVM], | |
1249 | FEAT_KVM }, | |
1250 | }; | |
1251 | ||
1252 | assert(kvm_enabled()); | |
1253 | ||
1254 | kvm_cpu_fill_host(&host_def); | |
1255 | for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) { | |
1256 | FeatureWord w = ft[i].feat_word; | |
1257 | FeatureWordInfo *wi = &feature_word_info[w]; | |
1258 | for (mask = 1; mask; mask <<= 1) { | |
1259 | if (*ft[i].guest_feat & mask && | |
1260 | !(*ft[i].host_feat & mask)) { | |
1261 | unavailable_host_feature(wi, mask); | |
1262 | rv = 1; | |
1263 | } | |
1264 | } | |
1265 | } | |
1266 | return rv; | |
1267 | } | |
1268 | ||
1269 | static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque, | |
1270 | const char *name, Error **errp) | |
1271 | { | |
1272 | X86CPU *cpu = X86_CPU(obj); | |
1273 | CPUX86State *env = &cpu->env; | |
1274 | int64_t value; | |
1275 | ||
1276 | value = (env->cpuid_version >> 8) & 0xf; | |
1277 | if (value == 0xf) { | |
1278 | value += (env->cpuid_version >> 20) & 0xff; | |
1279 | } | |
1280 | visit_type_int(v, &value, name, errp); | |
1281 | } | |
1282 | ||
1283 | static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque, | |
1284 | const char *name, Error **errp) | |
1285 | { | |
1286 | X86CPU *cpu = X86_CPU(obj); | |
1287 | CPUX86State *env = &cpu->env; | |
1288 | const int64_t min = 0; | |
1289 | const int64_t max = 0xff + 0xf; | |
1290 | int64_t value; | |
1291 | ||
1292 | visit_type_int(v, &value, name, errp); | |
1293 | if (error_is_set(errp)) { | |
1294 | return; | |
1295 | } | |
1296 | if (value < min || value > max) { | |
1297 | error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", | |
1298 | name ? name : "null", value, min, max); | |
1299 | return; | |
1300 | } | |
1301 | ||
1302 | env->cpuid_version &= ~0xff00f00; | |
1303 | if (value > 0x0f) { | |
1304 | env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); | |
1305 | } else { | |
1306 | env->cpuid_version |= value << 8; | |
1307 | } | |
1308 | } | |
1309 | ||
1310 | static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque, | |
1311 | const char *name, Error **errp) | |
1312 | { | |
1313 | X86CPU *cpu = X86_CPU(obj); | |
1314 | CPUX86State *env = &cpu->env; | |
1315 | int64_t value; | |
1316 | ||
1317 | value = (env->cpuid_version >> 4) & 0xf; | |
1318 | value |= ((env->cpuid_version >> 16) & 0xf) << 4; | |
1319 | visit_type_int(v, &value, name, errp); | |
1320 | } | |
1321 | ||
1322 | static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque, | |
1323 | const char *name, Error **errp) | |
1324 | { | |
1325 | X86CPU *cpu = X86_CPU(obj); | |
1326 | CPUX86State *env = &cpu->env; | |
1327 | const int64_t min = 0; | |
1328 | const int64_t max = 0xff; | |
1329 | int64_t value; | |
1330 | ||
1331 | visit_type_int(v, &value, name, errp); | |
1332 | if (error_is_set(errp)) { | |
1333 | return; | |
1334 | } | |
1335 | if (value < min || value > max) { | |
1336 | error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", | |
1337 | name ? name : "null", value, min, max); | |
1338 | return; | |
1339 | } | |
1340 | ||
1341 | env->cpuid_version &= ~0xf00f0; | |
1342 | env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); | |
1343 | } | |
1344 | ||
1345 | static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, | |
1346 | void *opaque, const char *name, | |
1347 | Error **errp) | |
1348 | { | |
1349 | X86CPU *cpu = X86_CPU(obj); | |
1350 | CPUX86State *env = &cpu->env; | |
1351 | int64_t value; | |
1352 | ||
1353 | value = env->cpuid_version & 0xf; | |
1354 | visit_type_int(v, &value, name, errp); | |
1355 | } | |
1356 | ||
1357 | static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, | |
1358 | void *opaque, const char *name, | |
1359 | Error **errp) | |
1360 | { | |
1361 | X86CPU *cpu = X86_CPU(obj); | |
1362 | CPUX86State *env = &cpu->env; | |
1363 | const int64_t min = 0; | |
1364 | const int64_t max = 0xf; | |
1365 | int64_t value; | |
1366 | ||
1367 | visit_type_int(v, &value, name, errp); | |
1368 | if (error_is_set(errp)) { | |
1369 | return; | |
1370 | } | |
1371 | if (value < min || value > max) { | |
1372 | error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", | |
1373 | name ? name : "null", value, min, max); | |
1374 | return; | |
1375 | } | |
1376 | ||
1377 | env->cpuid_version &= ~0xf; | |
1378 | env->cpuid_version |= value & 0xf; | |
1379 | } | |
1380 | ||
1381 | static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque, | |
1382 | const char *name, Error **errp) | |
1383 | { | |
1384 | X86CPU *cpu = X86_CPU(obj); | |
1385 | ||
1386 | visit_type_uint32(v, &cpu->env.cpuid_level, name, errp); | |
1387 | } | |
1388 | ||
1389 | static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque, | |
1390 | const char *name, Error **errp) | |
1391 | { | |
1392 | X86CPU *cpu = X86_CPU(obj); | |
1393 | ||
1394 | visit_type_uint32(v, &cpu->env.cpuid_level, name, errp); | |
1395 | } | |
1396 | ||
1397 | static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque, | |
1398 | const char *name, Error **errp) | |
1399 | { | |
1400 | X86CPU *cpu = X86_CPU(obj); | |
1401 | ||
1402 | visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp); | |
1403 | } | |
1404 | ||
1405 | static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque, | |
1406 | const char *name, Error **errp) | |
1407 | { | |
1408 | X86CPU *cpu = X86_CPU(obj); | |
1409 | ||
1410 | visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp); | |
1411 | } | |
1412 | ||
1413 | static char *x86_cpuid_get_vendor(Object *obj, Error **errp) | |
1414 | { | |
1415 | X86CPU *cpu = X86_CPU(obj); | |
1416 | CPUX86State *env = &cpu->env; | |
1417 | char *value; | |
1418 | ||
1419 | value = (char *)g_malloc(CPUID_VENDOR_SZ + 1); | |
1420 | x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, | |
1421 | env->cpuid_vendor3); | |
1422 | return value; | |
1423 | } | |
1424 | ||
1425 | static void x86_cpuid_set_vendor(Object *obj, const char *value, | |
1426 | Error **errp) | |
1427 | { | |
1428 | X86CPU *cpu = X86_CPU(obj); | |
1429 | CPUX86State *env = &cpu->env; | |
1430 | int i; | |
1431 | ||
1432 | if (strlen(value) != CPUID_VENDOR_SZ) { | |
1433 | error_set(errp, QERR_PROPERTY_VALUE_BAD, "", | |
1434 | "vendor", value); | |
1435 | return; | |
1436 | } | |
1437 | ||
1438 | env->cpuid_vendor1 = 0; | |
1439 | env->cpuid_vendor2 = 0; | |
1440 | env->cpuid_vendor3 = 0; | |
1441 | for (i = 0; i < 4; i++) { | |
1442 | env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); | |
1443 | env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); | |
1444 | env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); | |
1445 | } | |
1446 | } | |
1447 | ||
1448 | static char *x86_cpuid_get_model_id(Object *obj, Error **errp) | |
1449 | { | |
1450 | X86CPU *cpu = X86_CPU(obj); | |
1451 | CPUX86State *env = &cpu->env; | |
1452 | char *value; | |
1453 | int i; | |
1454 | ||
1455 | value = g_malloc(48 + 1); | |
1456 | for (i = 0; i < 48; i++) { | |
1457 | value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); | |
1458 | } | |
1459 | value[48] = '\0'; | |
1460 | return value; | |
1461 | } | |
1462 | ||
1463 | static void x86_cpuid_set_model_id(Object *obj, const char *model_id, | |
1464 | Error **errp) | |
1465 | { | |
1466 | X86CPU *cpu = X86_CPU(obj); | |
1467 | CPUX86State *env = &cpu->env; | |
1468 | int c, len, i; | |
1469 | ||
1470 | if (model_id == NULL) { | |
1471 | model_id = ""; | |
1472 | } | |
1473 | len = strlen(model_id); | |
1474 | memset(env->cpuid_model, 0, 48); | |
1475 | for (i = 0; i < 48; i++) { | |
1476 | if (i >= len) { | |
1477 | c = '\0'; | |
1478 | } else { | |
1479 | c = (uint8_t)model_id[i]; | |
1480 | } | |
1481 | env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque, | |
1486 | const char *name, Error **errp) | |
1487 | { | |
1488 | X86CPU *cpu = X86_CPU(obj); | |
1489 | int64_t value; | |
1490 | ||
1491 | value = cpu->env.tsc_khz * 1000; | |
1492 | visit_type_int(v, &value, name, errp); | |
1493 | } | |
1494 | ||
1495 | static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque, | |
1496 | const char *name, Error **errp) | |
1497 | { | |
1498 | X86CPU *cpu = X86_CPU(obj); | |
1499 | const int64_t min = 0; | |
1500 | const int64_t max = INT64_MAX; | |
1501 | int64_t value; | |
1502 | ||
1503 | visit_type_int(v, &value, name, errp); | |
1504 | if (error_is_set(errp)) { | |
1505 | return; | |
1506 | } | |
1507 | if (value < min || value > max) { | |
1508 | error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", | |
1509 | name ? name : "null", value, min, max); | |
1510 | return; | |
1511 | } | |
1512 | ||
1513 | cpu->env.tsc_khz = value / 1000; | |
1514 | } | |
1515 | ||
1516 | static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque, | |
1517 | const char *name, Error **errp) | |
1518 | { | |
1519 | X86CPU *cpu = X86_CPU(obj); | |
1520 | int64_t value = cpu->env.cpuid_apic_id; | |
1521 | ||
1522 | visit_type_int(v, &value, name, errp); | |
1523 | } | |
1524 | ||
1525 | static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque, | |
1526 | const char *name, Error **errp) | |
1527 | { | |
1528 | X86CPU *cpu = X86_CPU(obj); | |
1529 | DeviceState *dev = DEVICE(obj); | |
1530 | const int64_t min = 0; | |
1531 | const int64_t max = UINT32_MAX; | |
1532 | Error *error = NULL; | |
1533 | int64_t value; | |
1534 | ||
1535 | if (dev->realized) { | |
1536 | error_setg(errp, "Attempt to set property '%s' on '%s' after " | |
1537 | "it was realized", name, object_get_typename(obj)); | |
1538 | return; | |
1539 | } | |
1540 | ||
1541 | visit_type_int(v, &value, name, &error); | |
1542 | if (error) { | |
1543 | error_propagate(errp, error); | |
1544 | return; | |
1545 | } | |
1546 | if (value < min || value > max) { | |
1547 | error_setg(errp, "Property %s.%s doesn't take value %" PRId64 | |
1548 | " (minimum: %" PRId64 ", maximum: %" PRId64 ")" , | |
1549 | object_get_typename(obj), name, value, min, max); | |
1550 | return; | |
1551 | } | |
1552 | ||
1553 | if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) { | |
1554 | error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value); | |
1555 | return; | |
1556 | } | |
1557 | cpu->env.cpuid_apic_id = value; | |
1558 | } | |
1559 | ||
1560 | /* Generic getter for "feature-words" and "filtered-features" properties */ | |
1561 | static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque, | |
1562 | const char *name, Error **errp) | |
1563 | { | |
1564 | uint32_t *array = (uint32_t *)opaque; | |
1565 | FeatureWord w; | |
1566 | Error *err = NULL; | |
1567 | X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; | |
1568 | X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; | |
1569 | X86CPUFeatureWordInfoList *list = NULL; | |
1570 | ||
1571 | for (w = 0; w < FEATURE_WORDS; w++) { | |
1572 | FeatureWordInfo *wi = &feature_word_info[w]; | |
1573 | X86CPUFeatureWordInfo *qwi = &word_infos[w]; | |
1574 | qwi->cpuid_input_eax = wi->cpuid_eax; | |
1575 | qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx; | |
1576 | qwi->cpuid_input_ecx = wi->cpuid_ecx; | |
1577 | qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum; | |
1578 | qwi->features = array[w]; | |
1579 | ||
1580 | /* List will be in reverse order, but order shouldn't matter */ | |
1581 | list_entries[w].next = list; | |
1582 | list_entries[w].value = &word_infos[w]; | |
1583 | list = &list_entries[w]; | |
1584 | } | |
1585 | ||
1586 | visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err); | |
1587 | error_propagate(errp, err); | |
1588 | } | |
1589 | ||
1590 | static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def, | |
1591 | const char *name) | |
1592 | { | |
1593 | x86_def_t *def; | |
1594 | Error *err = NULL; | |
1595 | int i; | |
1596 | ||
1597 | if (name == NULL) { | |
1598 | return -1; | |
1599 | } | |
1600 | if (kvm_enabled() && strcmp(name, "host") == 0) { | |
1601 | kvm_cpu_fill_host(x86_cpu_def); | |
1602 | object_property_set_bool(OBJECT(cpu), true, "pmu", &err); | |
1603 | assert_no_error(err); | |
1604 | return 0; | |
1605 | } | |
1606 | ||
1607 | for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { | |
1608 | def = &builtin_x86_defs[i]; | |
1609 | if (strcmp(name, def->name) == 0) { | |
1610 | memcpy(x86_cpu_def, def, sizeof(*def)); | |
1611 | /* sysenter isn't supported in compatibility mode on AMD, | |
1612 | * syscall isn't supported in compatibility mode on Intel. | |
1613 | * Normally we advertise the actual CPU vendor, but you can | |
1614 | * override this using the 'vendor' property if you want to use | |
1615 | * KVM's sysenter/syscall emulation in compatibility mode and | |
1616 | * when doing cross vendor migration | |
1617 | */ | |
1618 | if (kvm_enabled()) { | |
1619 | uint32_t ebx = 0, ecx = 0, edx = 0; | |
1620 | host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); | |
1621 | x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx); | |
1622 | } | |
1623 | return 0; | |
1624 | } | |
1625 | } | |
1626 | ||
1627 | return -1; | |
1628 | } | |
1629 | ||
1630 | /* Convert all '_' in a feature string option name to '-', to make feature | |
1631 | * name conform to QOM property naming rule, which uses '-' instead of '_'. | |
1632 | */ | |
1633 | static inline void feat2prop(char *s) | |
1634 | { | |
1635 | while ((s = strchr(s, '_'))) { | |
1636 | *s = '-'; | |
1637 | } | |
1638 | } | |
1639 | ||
1640 | /* Parse "+feature,-feature,feature=foo" CPU feature string | |
1641 | */ | |
1642 | static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp) | |
1643 | { | |
1644 | char *featurestr; /* Single 'key=value" string being parsed */ | |
1645 | /* Features to be added */ | |
1646 | FeatureWordArray plus_features = { 0 }; | |
1647 | /* Features to be removed */ | |
1648 | FeatureWordArray minus_features = { 0 }; | |
1649 | uint32_t numvalue; | |
1650 | CPUX86State *env = &cpu->env; | |
1651 | ||
1652 | featurestr = features ? strtok(features, ",") : NULL; | |
1653 | ||
1654 | while (featurestr) { | |
1655 | char *val; | |
1656 | if (featurestr[0] == '+') { | |
1657 | add_flagname_to_bitmaps(featurestr + 1, plus_features); | |
1658 | } else if (featurestr[0] == '-') { | |
1659 | add_flagname_to_bitmaps(featurestr + 1, minus_features); | |
1660 | } else if ((val = strchr(featurestr, '='))) { | |
1661 | *val = 0; val++; | |
1662 | feat2prop(featurestr); | |
1663 | if (!strcmp(featurestr, "family")) { | |
1664 | object_property_parse(OBJECT(cpu), val, featurestr, errp); | |
1665 | } else if (!strcmp(featurestr, "model")) { | |
1666 | object_property_parse(OBJECT(cpu), val, featurestr, errp); | |
1667 | } else if (!strcmp(featurestr, "stepping")) { | |
1668 | object_property_parse(OBJECT(cpu), val, featurestr, errp); | |
1669 | } else if (!strcmp(featurestr, "level")) { | |
1670 | object_property_parse(OBJECT(cpu), val, featurestr, errp); | |
1671 | } else if (!strcmp(featurestr, "xlevel")) { | |
1672 | char *err; | |
1673 | char num[32]; | |
1674 | ||
1675 | numvalue = strtoul(val, &err, 0); | |
1676 | if (!*val || *err) { | |
1677 | error_setg(errp, "bad numerical value %s", val); | |
1678 | goto out; | |
1679 | } | |
1680 | if (numvalue < 0x80000000) { | |
1681 | fprintf(stderr, "xlevel value shall always be >= 0x80000000" | |
1682 | ", fixup will be removed in future versions\n"); | |
1683 | numvalue += 0x80000000; | |
1684 | } | |
1685 | snprintf(num, sizeof(num), "%" PRIu32, numvalue); | |
1686 | object_property_parse(OBJECT(cpu), num, featurestr, errp); | |
1687 | } else if (!strcmp(featurestr, "vendor")) { | |
1688 | object_property_parse(OBJECT(cpu), val, featurestr, errp); | |
1689 | } else if (!strcmp(featurestr, "model-id")) { | |
1690 | object_property_parse(OBJECT(cpu), val, featurestr, errp); | |
1691 | } else if (!strcmp(featurestr, "tsc-freq")) { | |
1692 | int64_t tsc_freq; | |
1693 | char *err; | |
1694 | char num[32]; | |
1695 | ||
1696 | tsc_freq = strtosz_suffix_unit(val, &err, | |
1697 | STRTOSZ_DEFSUFFIX_B, 1000); | |
1698 | if (tsc_freq < 0 || *err) { | |
1699 | error_setg(errp, "bad numerical value %s", val); | |
1700 | goto out; | |
1701 | } | |
1702 | snprintf(num, sizeof(num), "%" PRId64, tsc_freq); | |
1703 | object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp); | |
1704 | } else if (!strcmp(featurestr, "hv-spinlocks")) { | |
1705 | char *err; | |
1706 | const int min = 0xFFF; | |
1707 | numvalue = strtoul(val, &err, 0); | |
1708 | if (!*val || *err) { | |
1709 | error_setg(errp, "bad numerical value %s", val); | |
1710 | goto out; | |
1711 | } | |
1712 | if (numvalue < min) { | |
1713 | fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x" | |
1714 | ", fixup will be removed in future versions\n", | |
1715 | min); | |
1716 | numvalue = min; | |
1717 | } | |
1718 | cpu->hyperv_spinlock_attempts = numvalue; | |
1719 | } else { | |
1720 | error_setg(errp, "unrecognized feature %s", featurestr); | |
1721 | goto out; | |
1722 | } | |
1723 | } else if (!strcmp(featurestr, "check")) { | |
1724 | check_cpuid = 1; | |
1725 | } else if (!strcmp(featurestr, "enforce")) { | |
1726 | check_cpuid = enforce_cpuid = 1; | |
1727 | } else if (!strcmp(featurestr, "hv_relaxed")) { | |
1728 | cpu->hyperv_relaxed_timing = true; | |
1729 | } else if (!strcmp(featurestr, "hv_vapic")) { | |
1730 | cpu->hyperv_vapic = true; | |
1731 | } else { | |
1732 | error_setg(errp, "feature string `%s' not in format (+feature|" | |
1733 | "-feature|feature=xyz)", featurestr); | |
1734 | goto out; | |
1735 | } | |
1736 | if (error_is_set(errp)) { | |
1737 | goto out; | |
1738 | } | |
1739 | featurestr = strtok(NULL, ","); | |
1740 | } | |
1741 | env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX]; | |
1742 | env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX]; | |
1743 | env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX]; | |
1744 | env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX]; | |
1745 | env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX]; | |
1746 | env->features[FEAT_KVM] |= plus_features[FEAT_KVM]; | |
1747 | env->features[FEAT_SVM] |= plus_features[FEAT_SVM]; | |
1748 | env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX]; | |
1749 | env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX]; | |
1750 | env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX]; | |
1751 | env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX]; | |
1752 | env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX]; | |
1753 | env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX]; | |
1754 | env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM]; | |
1755 | env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM]; | |
1756 | env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX]; | |
1757 | ||
1758 | out: | |
1759 | return; | |
1760 | } | |
1761 | ||
1762 | /* generate a composite string into buf of all cpuid names in featureset | |
1763 | * selected by fbits. indicate truncation at bufsize in the event of overflow. | |
1764 | * if flags, suppress names undefined in featureset. | |
1765 | */ | |
1766 | static void listflags(char *buf, int bufsize, uint32_t fbits, | |
1767 | const char **featureset, uint32_t flags) | |
1768 | { | |
1769 | const char **p = &featureset[31]; | |
1770 | char *q, *b, bit; | |
1771 | int nc; | |
1772 | ||
1773 | b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL; | |
1774 | *buf = '\0'; | |
1775 | for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit) | |
1776 | if (fbits & 1 << bit && (*p || !flags)) { | |
1777 | if (*p) | |
1778 | nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p); | |
1779 | else | |
1780 | nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit); | |
1781 | if (bufsize <= nc) { | |
1782 | if (b) { | |
1783 | memcpy(b, "...", sizeof("...")); | |
1784 | } | |
1785 | return; | |
1786 | } | |
1787 | q += nc; | |
1788 | bufsize -= nc; | |
1789 | } | |
1790 | } | |
1791 | ||
1792 | /* generate CPU information. */ | |
1793 | void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf) | |
1794 | { | |
1795 | x86_def_t *def; | |
1796 | char buf[256]; | |
1797 | int i; | |
1798 | ||
1799 | for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { | |
1800 | def = &builtin_x86_defs[i]; | |
1801 | snprintf(buf, sizeof(buf), "%s", def->name); | |
1802 | (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id); | |
1803 | } | |
1804 | #ifdef CONFIG_KVM | |
1805 | (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host", | |
1806 | "KVM processor with all supported host features " | |
1807 | "(only available in KVM mode)"); | |
1808 | #endif | |
1809 | ||
1810 | (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n"); | |
1811 | for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { | |
1812 | FeatureWordInfo *fw = &feature_word_info[i]; | |
1813 | ||
1814 | listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1); | |
1815 | (*cpu_fprintf)(f, " %s\n", buf); | |
1816 | } | |
1817 | } | |
1818 | ||
1819 | CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) | |
1820 | { | |
1821 | CpuDefinitionInfoList *cpu_list = NULL; | |
1822 | x86_def_t *def; | |
1823 | int i; | |
1824 | ||
1825 | for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { | |
1826 | CpuDefinitionInfoList *entry; | |
1827 | CpuDefinitionInfo *info; | |
1828 | ||
1829 | def = &builtin_x86_defs[i]; | |
1830 | info = g_malloc0(sizeof(*info)); | |
1831 | info->name = g_strdup(def->name); | |
1832 | ||
1833 | entry = g_malloc0(sizeof(*entry)); | |
1834 | entry->value = info; | |
1835 | entry->next = cpu_list; | |
1836 | cpu_list = entry; | |
1837 | } | |
1838 | ||
1839 | return cpu_list; | |
1840 | } | |
1841 | ||
1842 | #ifdef CONFIG_KVM | |
1843 | static void filter_features_for_kvm(X86CPU *cpu) | |
1844 | { | |
1845 | CPUX86State *env = &cpu->env; | |
1846 | KVMState *s = kvm_state; | |
1847 | FeatureWord w; | |
1848 | ||
1849 | for (w = 0; w < FEATURE_WORDS; w++) { | |
1850 | FeatureWordInfo *wi = &feature_word_info[w]; | |
1851 | uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, | |
1852 | wi->cpuid_ecx, | |
1853 | wi->cpuid_reg); | |
1854 | uint32_t requested_features = env->features[w]; | |
1855 | env->features[w] &= host_feat; | |
1856 | cpu->filtered_features[w] = requested_features & ~env->features[w]; | |
1857 | } | |
1858 | } | |
1859 | #endif | |
1860 | ||
1861 | static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp) | |
1862 | { | |
1863 | CPUX86State *env = &cpu->env; | |
1864 | x86_def_t def1, *def = &def1; | |
1865 | ||
1866 | memset(def, 0, sizeof(*def)); | |
1867 | ||
1868 | if (cpu_x86_find_by_name(cpu, def, name) < 0) { | |
1869 | error_setg(errp, "Unable to find CPU definition: %s", name); | |
1870 | return; | |
1871 | } | |
1872 | ||
1873 | if (kvm_enabled()) { | |
1874 | def->features[FEAT_KVM] |= kvm_default_features; | |
1875 | } | |
1876 | def->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; | |
1877 | ||
1878 | object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp); | |
1879 | object_property_set_int(OBJECT(cpu), def->level, "level", errp); | |
1880 | object_property_set_int(OBJECT(cpu), def->family, "family", errp); | |
1881 | object_property_set_int(OBJECT(cpu), def->model, "model", errp); | |
1882 | object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp); | |
1883 | env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX]; | |
1884 | env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX]; | |
1885 | env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX]; | |
1886 | env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX]; | |
1887 | object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp); | |
1888 | env->features[FEAT_KVM] = def->features[FEAT_KVM]; | |
1889 | env->features[FEAT_SVM] = def->features[FEAT_SVM]; | |
1890 | env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX]; | |
1891 | env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX]; | |
1892 | env->cpuid_xlevel2 = def->xlevel2; | |
1893 | cpu->cache_info_passthrough = def->cache_info_passthrough; | |
1894 | ||
1895 | object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp); | |
1896 | } | |
1897 | ||
1898 | X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge, | |
1899 | Error **errp) | |
1900 | { | |
1901 | X86CPU *cpu = NULL; | |
1902 | CPUX86State *env; | |
1903 | gchar **model_pieces; | |
1904 | char *name, *features; | |
1905 | char *typename; | |
1906 | Error *error = NULL; | |
1907 | ||
1908 | model_pieces = g_strsplit(cpu_model, ",", 2); | |
1909 | if (!model_pieces[0]) { | |
1910 | error_setg(&error, "Invalid/empty CPU model name"); | |
1911 | goto out; | |
1912 | } | |
1913 | name = model_pieces[0]; | |
1914 | features = model_pieces[1]; | |
1915 | ||
1916 | cpu = X86_CPU(object_new(TYPE_X86_CPU)); | |
1917 | #ifndef CONFIG_USER_ONLY | |
1918 | if (icc_bridge == NULL) { | |
1919 | error_setg(&error, "Invalid icc-bridge value"); | |
1920 | goto out; | |
1921 | } | |
1922 | qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc")); | |
1923 | object_unref(OBJECT(cpu)); | |
1924 | #endif | |
1925 | env = &cpu->env; | |
1926 | env->cpu_model_str = cpu_model; | |
1927 | ||
1928 | cpu_x86_register(cpu, name, &error); | |
1929 | if (error) { | |
1930 | goto out; | |
1931 | } | |
1932 | ||
1933 | /* Emulate per-model subclasses for global properties */ | |
1934 | typename = g_strdup_printf("%s-" TYPE_X86_CPU, name); | |
1935 | qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error); | |
1936 | g_free(typename); | |
1937 | if (error) { | |
1938 | goto out; | |
1939 | } | |
1940 | ||
1941 | cpu_x86_parse_featurestr(cpu, features, &error); | |
1942 | if (error) { | |
1943 | goto out; | |
1944 | } | |
1945 | ||
1946 | out: | |
1947 | if (error != NULL) { | |
1948 | error_propagate(errp, error); | |
1949 | object_unref(OBJECT(cpu)); | |
1950 | cpu = NULL; | |
1951 | } | |
1952 | g_strfreev(model_pieces); | |
1953 | return cpu; | |
1954 | } | |
1955 | ||
1956 | X86CPU *cpu_x86_init(const char *cpu_model) | |
1957 | { | |
1958 | Error *error = NULL; | |
1959 | X86CPU *cpu; | |
1960 | ||
1961 | cpu = cpu_x86_create(cpu_model, NULL, &error); | |
1962 | if (error) { | |
1963 | goto out; | |
1964 | } | |
1965 | ||
1966 | object_property_set_bool(OBJECT(cpu), true, "realized", &error); | |
1967 | ||
1968 | out: | |
1969 | if (error) { | |
1970 | error_report("%s", error_get_pretty(error)); | |
1971 | error_free(error); | |
1972 | if (cpu != NULL) { | |
1973 | object_unref(OBJECT(cpu)); | |
1974 | cpu = NULL; | |
1975 | } | |
1976 | } | |
1977 | return cpu; | |
1978 | } | |
1979 | ||
1980 | #if !defined(CONFIG_USER_ONLY) | |
1981 | ||
1982 | void cpu_clear_apic_feature(CPUX86State *env) | |
1983 | { | |
1984 | env->features[FEAT_1_EDX] &= ~CPUID_APIC; | |
1985 | } | |
1986 | ||
1987 | #endif /* !CONFIG_USER_ONLY */ | |
1988 | ||
1989 | /* Initialize list of CPU models, filling some non-static fields if necessary | |
1990 | */ | |
1991 | void x86_cpudef_setup(void) | |
1992 | { | |
1993 | int i, j; | |
1994 | static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" }; | |
1995 | ||
1996 | for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) { | |
1997 | x86_def_t *def = &builtin_x86_defs[i]; | |
1998 | ||
1999 | /* Look for specific "cpudef" models that */ | |
2000 | /* have the QEMU version in .model_id */ | |
2001 | for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) { | |
2002 | if (strcmp(model_with_versions[j], def->name) == 0) { | |
2003 | pstrcpy(def->model_id, sizeof(def->model_id), | |
2004 | "QEMU Virtual CPU version "); | |
2005 | pstrcat(def->model_id, sizeof(def->model_id), | |
2006 | qemu_get_version()); | |
2007 | break; | |
2008 | } | |
2009 | } | |
2010 | } | |
2011 | } | |
2012 | ||
2013 | static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx, | |
2014 | uint32_t *ecx, uint32_t *edx) | |
2015 | { | |
2016 | *ebx = env->cpuid_vendor1; | |
2017 | *edx = env->cpuid_vendor2; | |
2018 | *ecx = env->cpuid_vendor3; | |
2019 | } | |
2020 | ||
2021 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, | |
2022 | uint32_t *eax, uint32_t *ebx, | |
2023 | uint32_t *ecx, uint32_t *edx) | |
2024 | { | |
2025 | X86CPU *cpu = x86_env_get_cpu(env); | |
2026 | CPUState *cs = CPU(cpu); | |
2027 | ||
2028 | /* test if maximum index reached */ | |
2029 | if (index & 0x80000000) { | |
2030 | if (index > env->cpuid_xlevel) { | |
2031 | if (env->cpuid_xlevel2 > 0) { | |
2032 | /* Handle the Centaur's CPUID instruction. */ | |
2033 | if (index > env->cpuid_xlevel2) { | |
2034 | index = env->cpuid_xlevel2; | |
2035 | } else if (index < 0xC0000000) { | |
2036 | index = env->cpuid_xlevel; | |
2037 | } | |
2038 | } else { | |
2039 | /* Intel documentation states that invalid EAX input will | |
2040 | * return the same information as EAX=cpuid_level | |
2041 | * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) | |
2042 | */ | |
2043 | index = env->cpuid_level; | |
2044 | } | |
2045 | } | |
2046 | } else { | |
2047 | if (index > env->cpuid_level) | |
2048 | index = env->cpuid_level; | |
2049 | } | |
2050 | ||
2051 | switch(index) { | |
2052 | case 0: | |
2053 | *eax = env->cpuid_level; | |
2054 | get_cpuid_vendor(env, ebx, ecx, edx); | |
2055 | break; | |
2056 | case 1: | |
2057 | *eax = env->cpuid_version; | |
2058 | *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ | |
2059 | *ecx = env->features[FEAT_1_ECX]; | |
2060 | *edx = env->features[FEAT_1_EDX]; | |
2061 | if (cs->nr_cores * cs->nr_threads > 1) { | |
2062 | *ebx |= (cs->nr_cores * cs->nr_threads) << 16; | |
2063 | *edx |= 1 << 28; /* HTT bit */ | |
2064 | } | |
2065 | break; | |
2066 | case 2: | |
2067 | /* cache info: needed for Pentium Pro compatibility */ | |
2068 | if (cpu->cache_info_passthrough) { | |
2069 | host_cpuid(index, 0, eax, ebx, ecx, edx); | |
2070 | break; | |
2071 | } | |
2072 | *eax = 1; /* Number of CPUID[EAX=2] calls required */ | |
2073 | *ebx = 0; | |
2074 | *ecx = 0; | |
2075 | *edx = (L1D_DESCRIPTOR << 16) | \ | |
2076 | (L1I_DESCRIPTOR << 8) | \ | |
2077 | (L2_DESCRIPTOR); | |
2078 | break; | |
2079 | case 4: | |
2080 | /* cache info: needed for Core compatibility */ | |
2081 | if (cpu->cache_info_passthrough) { | |
2082 | host_cpuid(index, count, eax, ebx, ecx, edx); | |
2083 | break; | |
2084 | } | |
2085 | if (cs->nr_cores > 1) { | |
2086 | *eax = (cs->nr_cores - 1) << 26; | |
2087 | } else { | |
2088 | *eax = 0; | |
2089 | } | |
2090 | switch (count) { | |
2091 | case 0: /* L1 dcache info */ | |
2092 | *eax |= CPUID_4_TYPE_DCACHE | \ | |
2093 | CPUID_4_LEVEL(1) | \ | |
2094 | CPUID_4_SELF_INIT_LEVEL; | |
2095 | *ebx = (L1D_LINE_SIZE - 1) | \ | |
2096 | ((L1D_PARTITIONS - 1) << 12) | \ | |
2097 | ((L1D_ASSOCIATIVITY - 1) << 22); | |
2098 | *ecx = L1D_SETS - 1; | |
2099 | *edx = CPUID_4_NO_INVD_SHARING; | |
2100 | break; | |
2101 | case 1: /* L1 icache info */ | |
2102 | *eax |= CPUID_4_TYPE_ICACHE | \ | |
2103 | CPUID_4_LEVEL(1) | \ | |
2104 | CPUID_4_SELF_INIT_LEVEL; | |
2105 | *ebx = (L1I_LINE_SIZE - 1) | \ | |
2106 | ((L1I_PARTITIONS - 1) << 12) | \ | |
2107 | ((L1I_ASSOCIATIVITY - 1) << 22); | |
2108 | *ecx = L1I_SETS - 1; | |
2109 | *edx = CPUID_4_NO_INVD_SHARING; | |
2110 | break; | |
2111 | case 2: /* L2 cache info */ | |
2112 | *eax |= CPUID_4_TYPE_UNIFIED | \ | |
2113 | CPUID_4_LEVEL(2) | \ | |
2114 | CPUID_4_SELF_INIT_LEVEL; | |
2115 | if (cs->nr_threads > 1) { | |
2116 | *eax |= (cs->nr_threads - 1) << 14; | |
2117 | } | |
2118 | *ebx = (L2_LINE_SIZE - 1) | \ | |
2119 | ((L2_PARTITIONS - 1) << 12) | \ | |
2120 | ((L2_ASSOCIATIVITY - 1) << 22); | |
2121 | *ecx = L2_SETS - 1; | |
2122 | *edx = CPUID_4_NO_INVD_SHARING; | |
2123 | break; | |
2124 | default: /* end of info */ | |
2125 | *eax = 0; | |
2126 | *ebx = 0; | |
2127 | *ecx = 0; | |
2128 | *edx = 0; | |
2129 | break; | |
2130 | } | |
2131 | break; | |
2132 | case 5: | |
2133 | /* mwait info: needed for Core compatibility */ | |
2134 | *eax = 0; /* Smallest monitor-line size in bytes */ | |
2135 | *ebx = 0; /* Largest monitor-line size in bytes */ | |
2136 | *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; | |
2137 | *edx = 0; | |
2138 | break; | |
2139 | case 6: | |
2140 | /* Thermal and Power Leaf */ | |
2141 | *eax = 0; | |
2142 | *ebx = 0; | |
2143 | *ecx = 0; | |
2144 | *edx = 0; | |
2145 | break; | |
2146 | case 7: | |
2147 | /* Structured Extended Feature Flags Enumeration Leaf */ | |
2148 | if (count == 0) { | |
2149 | *eax = 0; /* Maximum ECX value for sub-leaves */ | |
2150 | *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ | |
2151 | *ecx = 0; /* Reserved */ | |
2152 | *edx = 0; /* Reserved */ | |
2153 | } else { | |
2154 | *eax = 0; | |
2155 | *ebx = 0; | |
2156 | *ecx = 0; | |
2157 | *edx = 0; | |
2158 | } | |
2159 | break; | |
2160 | case 9: | |
2161 | /* Direct Cache Access Information Leaf */ | |
2162 | *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ | |
2163 | *ebx = 0; | |
2164 | *ecx = 0; | |
2165 | *edx = 0; | |
2166 | break; | |
2167 | case 0xA: | |
2168 | /* Architectural Performance Monitoring Leaf */ | |
2169 | if (kvm_enabled() && cpu->enable_pmu) { | |
2170 | KVMState *s = cs->kvm_state; | |
2171 | ||
2172 | *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); | |
2173 | *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); | |
2174 | *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); | |
2175 | *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); | |
2176 | } else { | |
2177 | *eax = 0; | |
2178 | *ebx = 0; | |
2179 | *ecx = 0; | |
2180 | *edx = 0; | |
2181 | } | |
2182 | break; | |
2183 | case 0xD: | |
2184 | /* Processor Extended State */ | |
2185 | if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { | |
2186 | *eax = 0; | |
2187 | *ebx = 0; | |
2188 | *ecx = 0; | |
2189 | *edx = 0; | |
2190 | break; | |
2191 | } | |
2192 | if (kvm_enabled()) { | |
2193 | KVMState *s = cs->kvm_state; | |
2194 | ||
2195 | *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX); | |
2196 | *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX); | |
2197 | *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX); | |
2198 | *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX); | |
2199 | } else { | |
2200 | *eax = 0; | |
2201 | *ebx = 0; | |
2202 | *ecx = 0; | |
2203 | *edx = 0; | |
2204 | } | |
2205 | break; | |
2206 | case 0x80000000: | |
2207 | *eax = env->cpuid_xlevel; | |
2208 | *ebx = env->cpuid_vendor1; | |
2209 | *edx = env->cpuid_vendor2; | |
2210 | *ecx = env->cpuid_vendor3; | |
2211 | break; | |
2212 | case 0x80000001: | |
2213 | *eax = env->cpuid_version; | |
2214 | *ebx = 0; | |
2215 | *ecx = env->features[FEAT_8000_0001_ECX]; | |
2216 | *edx = env->features[FEAT_8000_0001_EDX]; | |
2217 | ||
2218 | /* The Linux kernel checks for the CMPLegacy bit and | |
2219 | * discards multiple thread information if it is set. | |
2220 | * So dont set it here for Intel to make Linux guests happy. | |
2221 | */ | |
2222 | if (cs->nr_cores * cs->nr_threads > 1) { | |
2223 | uint32_t tebx, tecx, tedx; | |
2224 | get_cpuid_vendor(env, &tebx, &tecx, &tedx); | |
2225 | if (tebx != CPUID_VENDOR_INTEL_1 || | |
2226 | tedx != CPUID_VENDOR_INTEL_2 || | |
2227 | tecx != CPUID_VENDOR_INTEL_3) { | |
2228 | *ecx |= 1 << 1; /* CmpLegacy bit */ | |
2229 | } | |
2230 | } | |
2231 | break; | |
2232 | case 0x80000002: | |
2233 | case 0x80000003: | |
2234 | case 0x80000004: | |
2235 | *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; | |
2236 | *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; | |
2237 | *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; | |
2238 | *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; | |
2239 | break; | |
2240 | case 0x80000005: | |
2241 | /* cache info (L1 cache) */ | |
2242 | if (cpu->cache_info_passthrough) { | |
2243 | host_cpuid(index, 0, eax, ebx, ecx, edx); | |
2244 | break; | |
2245 | } | |
2246 | *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \ | |
2247 | (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); | |
2248 | *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \ | |
2249 | (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); | |
2250 | *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \ | |
2251 | (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE); | |
2252 | *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \ | |
2253 | (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE); | |
2254 | break; | |
2255 | case 0x80000006: | |
2256 | /* cache info (L2 cache) */ | |
2257 | if (cpu->cache_info_passthrough) { | |
2258 | host_cpuid(index, 0, eax, ebx, ecx, edx); | |
2259 | break; | |
2260 | } | |
2261 | *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \ | |
2262 | (L2_DTLB_2M_ENTRIES << 16) | \ | |
2263 | (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \ | |
2264 | (L2_ITLB_2M_ENTRIES); | |
2265 | *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \ | |
2266 | (L2_DTLB_4K_ENTRIES << 16) | \ | |
2267 | (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ | |
2268 | (L2_ITLB_4K_ENTRIES); | |
2269 | *ecx = (L2_SIZE_KB_AMD << 16) | \ | |
2270 | (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \ | |
2271 | (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE); | |
2272 | *edx = ((L3_SIZE_KB/512) << 18) | \ | |
2273 | (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \ | |
2274 | (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE); | |
2275 | break; | |
2276 | case 0x80000008: | |
2277 | /* virtual & phys address size in low 2 bytes. */ | |
2278 | /* XXX: This value must match the one used in the MMU code. */ | |
2279 | if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { | |
2280 | /* 64 bit processor */ | |
2281 | /* XXX: The physical address space is limited to 42 bits in exec.c. */ | |
2282 | *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */ | |
2283 | } else { | |
2284 | if (env->features[FEAT_1_EDX] & CPUID_PSE36) { | |
2285 | *eax = 0x00000024; /* 36 bits physical */ | |
2286 | } else { | |
2287 | *eax = 0x00000020; /* 32 bits physical */ | |
2288 | } | |
2289 | } | |
2290 | *ebx = 0; | |
2291 | *ecx = 0; | |
2292 | *edx = 0; | |
2293 | if (cs->nr_cores * cs->nr_threads > 1) { | |
2294 | *ecx |= (cs->nr_cores * cs->nr_threads) - 1; | |
2295 | } | |
2296 | break; | |
2297 | case 0x8000000A: | |
2298 | if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { | |
2299 | *eax = 0x00000001; /* SVM Revision */ | |
2300 | *ebx = 0x00000010; /* nr of ASIDs */ | |
2301 | *ecx = 0; | |
2302 | *edx = env->features[FEAT_SVM]; /* optional features */ | |
2303 | } else { | |
2304 | *eax = 0; | |
2305 | *ebx = 0; | |
2306 | *ecx = 0; | |
2307 | *edx = 0; | |
2308 | } | |
2309 | break; | |
2310 | case 0xC0000000: | |
2311 | *eax = env->cpuid_xlevel2; | |
2312 | *ebx = 0; | |
2313 | *ecx = 0; | |
2314 | *edx = 0; | |
2315 | break; | |
2316 | case 0xC0000001: | |
2317 | /* Support for VIA CPU's CPUID instruction */ | |
2318 | *eax = env->cpuid_version; | |
2319 | *ebx = 0; | |
2320 | *ecx = 0; | |
2321 | *edx = env->features[FEAT_C000_0001_EDX]; | |
2322 | break; | |
2323 | case 0xC0000002: | |
2324 | case 0xC0000003: | |
2325 | case 0xC0000004: | |
2326 | /* Reserved for the future, and now filled with zero */ | |
2327 | *eax = 0; | |
2328 | *ebx = 0; | |
2329 | *ecx = 0; | |
2330 | *edx = 0; | |
2331 | break; | |
2332 | default: | |
2333 | /* reserved values: zero */ | |
2334 | *eax = 0; | |
2335 | *ebx = 0; | |
2336 | *ecx = 0; | |
2337 | *edx = 0; | |
2338 | break; | |
2339 | } | |
2340 | } | |
2341 | ||
2342 | /* CPUClass::reset() */ | |
2343 | static void x86_cpu_reset(CPUState *s) | |
2344 | { | |
2345 | X86CPU *cpu = X86_CPU(s); | |
2346 | X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); | |
2347 | CPUX86State *env = &cpu->env; | |
2348 | int i; | |
2349 | ||
2350 | xcc->parent_reset(s); | |
2351 | ||
2352 | ||
2353 | memset(env, 0, offsetof(CPUX86State, breakpoints)); | |
2354 | ||
2355 | tlb_flush(env, 1); | |
2356 | ||
2357 | env->old_exception = -1; | |
2358 | ||
2359 | /* init to reset state */ | |
2360 | ||
2361 | #ifdef CONFIG_SOFTMMU | |
2362 | env->hflags |= HF_SOFTMMU_MASK; | |
2363 | #endif | |
2364 | env->hflags2 |= HF2_GIF_MASK; | |
2365 | ||
2366 | cpu_x86_update_cr0(env, 0x60000010); | |
2367 | env->a20_mask = ~0x0; | |
2368 | env->smbase = 0x30000; | |
2369 | ||
2370 | env->idt.limit = 0xffff; | |
2371 | env->gdt.limit = 0xffff; | |
2372 | env->ldt.limit = 0xffff; | |
2373 | env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); | |
2374 | env->tr.limit = 0xffff; | |
2375 | env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); | |
2376 | ||
2377 | cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, | |
2378 | DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | | |
2379 | DESC_R_MASK | DESC_A_MASK); | |
2380 | cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, | |
2381 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2382 | DESC_A_MASK); | |
2383 | cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, | |
2384 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2385 | DESC_A_MASK); | |
2386 | cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, | |
2387 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2388 | DESC_A_MASK); | |
2389 | cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, | |
2390 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2391 | DESC_A_MASK); | |
2392 | cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, | |
2393 | DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | | |
2394 | DESC_A_MASK); | |
2395 | ||
2396 | env->eip = 0xfff0; | |
2397 | env->regs[R_EDX] = env->cpuid_version; | |
2398 | ||
2399 | env->eflags = 0x2; | |
2400 | ||
2401 | /* FPU init */ | |
2402 | for (i = 0; i < 8; i++) { | |
2403 | env->fptags[i] = 1; | |
2404 | } | |
2405 | env->fpuc = 0x37f; | |
2406 | ||
2407 | env->mxcsr = 0x1f80; | |
2408 | ||
2409 | env->pat = 0x0007040600070406ULL; | |
2410 | env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; | |
2411 | ||
2412 | memset(env->dr, 0, sizeof(env->dr)); | |
2413 | env->dr[6] = DR6_FIXED_1; | |
2414 | env->dr[7] = DR7_FIXED_1; | |
2415 | cpu_breakpoint_remove_all(env, BP_CPU); | |
2416 | cpu_watchpoint_remove_all(env, BP_CPU); | |
2417 | ||
2418 | #if !defined(CONFIG_USER_ONLY) | |
2419 | /* We hard-wire the BSP to the first CPU. */ | |
2420 | if (s->cpu_index == 0) { | |
2421 | apic_designate_bsp(env->apic_state); | |
2422 | } | |
2423 | ||
2424 | s->halted = !cpu_is_bsp(cpu); | |
2425 | #endif | |
2426 | } | |
2427 | ||
2428 | #ifndef CONFIG_USER_ONLY | |
2429 | bool cpu_is_bsp(X86CPU *cpu) | |
2430 | { | |
2431 | return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP; | |
2432 | } | |
2433 | ||
2434 | /* TODO: remove me, when reset over QOM tree is implemented */ | |
2435 | static void x86_cpu_machine_reset_cb(void *opaque) | |
2436 | { | |
2437 | X86CPU *cpu = opaque; | |
2438 | cpu_reset(CPU(cpu)); | |
2439 | } | |
2440 | #endif | |
2441 | ||
2442 | static void mce_init(X86CPU *cpu) | |
2443 | { | |
2444 | CPUX86State *cenv = &cpu->env; | |
2445 | unsigned int bank; | |
2446 | ||
2447 | if (((cenv->cpuid_version >> 8) & 0xf) >= 6 | |
2448 | && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == | |
2449 | (CPUID_MCE | CPUID_MCA)) { | |
2450 | cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF; | |
2451 | cenv->mcg_ctl = ~(uint64_t)0; | |
2452 | for (bank = 0; bank < MCE_BANKS_DEF; bank++) { | |
2453 | cenv->mce_banks[bank * 4] = ~(uint64_t)0; | |
2454 | } | |
2455 | } | |
2456 | } | |
2457 | ||
2458 | #ifndef CONFIG_USER_ONLY | |
2459 | static void x86_cpu_apic_create(X86CPU *cpu, Error **errp) | |
2460 | { | |
2461 | CPUX86State *env = &cpu->env; | |
2462 | DeviceState *dev = DEVICE(cpu); | |
2463 | APICCommonState *apic; | |
2464 | const char *apic_type = "apic"; | |
2465 | ||
2466 | if (kvm_irqchip_in_kernel()) { | |
2467 | apic_type = "kvm-apic"; | |
2468 | } else if (xen_enabled()) { | |
2469 | apic_type = "xen-apic"; | |
2470 | } | |
2471 | ||
2472 | env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type); | |
2473 | if (env->apic_state == NULL) { | |
2474 | error_setg(errp, "APIC device '%s' could not be created", apic_type); | |
2475 | return; | |
2476 | } | |
2477 | ||
2478 | object_property_add_child(OBJECT(cpu), "apic", | |
2479 | OBJECT(env->apic_state), NULL); | |
2480 | qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id); | |
2481 | /* TODO: convert to link<> */ | |
2482 | apic = APIC_COMMON(env->apic_state); | |
2483 | apic->cpu = cpu; | |
2484 | } | |
2485 | ||
2486 | static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) | |
2487 | { | |
2488 | CPUX86State *env = &cpu->env; | |
2489 | ||
2490 | if (env->apic_state == NULL) { | |
2491 | return; | |
2492 | } | |
2493 | ||
2494 | if (qdev_init(env->apic_state)) { | |
2495 | error_setg(errp, "APIC device '%s' could not be initialized", | |
2496 | object_get_typename(OBJECT(env->apic_state))); | |
2497 | return; | |
2498 | } | |
2499 | } | |
2500 | #else | |
2501 | static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) | |
2502 | { | |
2503 | } | |
2504 | #endif | |
2505 | ||
2506 | static void x86_cpu_realizefn(DeviceState *dev, Error **errp) | |
2507 | { | |
2508 | CPUState *cs = CPU(dev); | |
2509 | X86CPU *cpu = X86_CPU(dev); | |
2510 | X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); | |
2511 | CPUX86State *env = &cpu->env; | |
2512 | Error *local_err = NULL; | |
2513 | ||
2514 | if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) { | |
2515 | env->cpuid_level = 7; | |
2516 | } | |
2517 | ||
2518 | /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on | |
2519 | * CPUID[1].EDX. | |
2520 | */ | |
2521 | if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && | |
2522 | env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && | |
2523 | env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) { | |
2524 | env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; | |
2525 | env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] | |
2526 | & CPUID_EXT2_AMD_ALIASES); | |
2527 | } | |
2528 | ||
2529 | if (!kvm_enabled()) { | |
2530 | env->features[FEAT_1_EDX] &= TCG_FEATURES; | |
2531 | env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES; | |
2532 | env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES | |
2533 | #ifdef TARGET_X86_64 | |
2534 | | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM | |
2535 | #endif | |
2536 | ); | |
2537 | env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES; | |
2538 | env->features[FEAT_SVM] &= TCG_SVM_FEATURES; | |
2539 | } else { | |
2540 | if (check_cpuid && kvm_check_features_against_host(cpu) | |
2541 | && enforce_cpuid) { | |
2542 | error_setg(&local_err, | |
2543 | "Host's CPU doesn't support requested features"); | |
2544 | goto out; | |
2545 | } | |
2546 | #ifdef CONFIG_KVM | |
2547 | filter_features_for_kvm(cpu); | |
2548 | #endif | |
2549 | } | |
2550 | ||
2551 | #ifndef CONFIG_USER_ONLY | |
2552 | qemu_register_reset(x86_cpu_machine_reset_cb, cpu); | |
2553 | ||
2554 | if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) { | |
2555 | x86_cpu_apic_create(cpu, &local_err); | |
2556 | if (local_err != NULL) { | |
2557 | goto out; | |
2558 | } | |
2559 | } | |
2560 | #endif | |
2561 | ||
2562 | mce_init(cpu); | |
2563 | qemu_init_vcpu(cs); | |
2564 | ||
2565 | x86_cpu_apic_realize(cpu, &local_err); | |
2566 | if (local_err != NULL) { | |
2567 | goto out; | |
2568 | } | |
2569 | cpu_reset(cs); | |
2570 | ||
2571 | xcc->parent_realize(dev, &local_err); | |
2572 | out: | |
2573 | if (local_err != NULL) { | |
2574 | error_propagate(errp, local_err); | |
2575 | return; | |
2576 | } | |
2577 | } | |
2578 | ||
2579 | /* Enables contiguous-apic-ID mode, for compatibility */ | |
2580 | static bool compat_apic_id_mode; | |
2581 | ||
2582 | void enable_compat_apic_id_mode(void) | |
2583 | { | |
2584 | compat_apic_id_mode = true; | |
2585 | } | |
2586 | ||
2587 | /* Calculates initial APIC ID for a specific CPU index | |
2588 | * | |
2589 | * Currently we need to be able to calculate the APIC ID from the CPU index | |
2590 | * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have | |
2591 | * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of | |
2592 | * all CPUs up to max_cpus. | |
2593 | */ | |
2594 | uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) | |
2595 | { | |
2596 | uint32_t correct_id; | |
2597 | static bool warned; | |
2598 | ||
2599 | correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index); | |
2600 | if (compat_apic_id_mode) { | |
2601 | if (cpu_index != correct_id && !warned) { | |
2602 | error_report("APIC IDs set in compatibility mode, " | |
2603 | "CPU topology won't match the configuration"); | |
2604 | warned = true; | |
2605 | } | |
2606 | return cpu_index; | |
2607 | } else { | |
2608 | return correct_id; | |
2609 | } | |
2610 | } | |
2611 | ||
2612 | static void x86_cpu_initfn(Object *obj) | |
2613 | { | |
2614 | CPUState *cs = CPU(obj); | |
2615 | X86CPU *cpu = X86_CPU(obj); | |
2616 | CPUX86State *env = &cpu->env; | |
2617 | static int inited; | |
2618 | ||
2619 | cs->env_ptr = env; | |
2620 | cpu_exec_init(env); | |
2621 | ||
2622 | object_property_add(obj, "family", "int", | |
2623 | x86_cpuid_version_get_family, | |
2624 | x86_cpuid_version_set_family, NULL, NULL, NULL); | |
2625 | object_property_add(obj, "model", "int", | |
2626 | x86_cpuid_version_get_model, | |
2627 | x86_cpuid_version_set_model, NULL, NULL, NULL); | |
2628 | object_property_add(obj, "stepping", "int", | |
2629 | x86_cpuid_version_get_stepping, | |
2630 | x86_cpuid_version_set_stepping, NULL, NULL, NULL); | |
2631 | object_property_add(obj, "level", "int", | |
2632 | x86_cpuid_get_level, | |
2633 | x86_cpuid_set_level, NULL, NULL, NULL); | |
2634 | object_property_add(obj, "xlevel", "int", | |
2635 | x86_cpuid_get_xlevel, | |
2636 | x86_cpuid_set_xlevel, NULL, NULL, NULL); | |
2637 | object_property_add_str(obj, "vendor", | |
2638 | x86_cpuid_get_vendor, | |
2639 | x86_cpuid_set_vendor, NULL); | |
2640 | object_property_add_str(obj, "model-id", | |
2641 | x86_cpuid_get_model_id, | |
2642 | x86_cpuid_set_model_id, NULL); | |
2643 | object_property_add(obj, "tsc-frequency", "int", | |
2644 | x86_cpuid_get_tsc_freq, | |
2645 | x86_cpuid_set_tsc_freq, NULL, NULL, NULL); | |
2646 | object_property_add(obj, "apic-id", "int", | |
2647 | x86_cpuid_get_apic_id, | |
2648 | x86_cpuid_set_apic_id, NULL, NULL, NULL); | |
2649 | object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", | |
2650 | x86_cpu_get_feature_words, | |
2651 | NULL, NULL, (void *)env->features, NULL); | |
2652 | object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", | |
2653 | x86_cpu_get_feature_words, | |
2654 | NULL, NULL, (void *)cpu->filtered_features, NULL); | |
2655 | ||
2656 | cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY; | |
2657 | env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index); | |
2658 | ||
2659 | /* init various static tables used in TCG mode */ | |
2660 | if (tcg_enabled() && !inited) { | |
2661 | inited = 1; | |
2662 | optimize_flags_init(); | |
2663 | #ifndef CONFIG_USER_ONLY | |
2664 | cpu_set_debug_excp_handler(breakpoint_handler); | |
2665 | #endif | |
2666 | } | |
2667 | } | |
2668 | ||
2669 | static int64_t x86_cpu_get_arch_id(CPUState *cs) | |
2670 | { | |
2671 | X86CPU *cpu = X86_CPU(cs); | |
2672 | CPUX86State *env = &cpu->env; | |
2673 | ||
2674 | return env->cpuid_apic_id; | |
2675 | } | |
2676 | ||
2677 | static bool x86_cpu_get_paging_enabled(const CPUState *cs) | |
2678 | { | |
2679 | X86CPU *cpu = X86_CPU(cs); | |
2680 | ||
2681 | return cpu->env.cr[0] & CR0_PG_MASK; | |
2682 | } | |
2683 | ||
2684 | static void x86_cpu_set_pc(CPUState *cs, vaddr value) | |
2685 | { | |
2686 | X86CPU *cpu = X86_CPU(cs); | |
2687 | ||
2688 | cpu->env.eip = value; | |
2689 | } | |
2690 | ||
2691 | static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) | |
2692 | { | |
2693 | X86CPU *cpu = X86_CPU(cs); | |
2694 | ||
2695 | cpu->env.eip = tb->pc - tb->cs_base; | |
2696 | } | |
2697 | ||
2698 | static Property x86_cpu_properties[] = { | |
2699 | DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), | |
2700 | DEFINE_PROP_END_OF_LIST() | |
2701 | }; | |
2702 | ||
2703 | static void x86_cpu_common_class_init(ObjectClass *oc, void *data) | |
2704 | { | |
2705 | X86CPUClass *xcc = X86_CPU_CLASS(oc); | |
2706 | CPUClass *cc = CPU_CLASS(oc); | |
2707 | DeviceClass *dc = DEVICE_CLASS(oc); | |
2708 | ||
2709 | xcc->parent_realize = dc->realize; | |
2710 | dc->realize = x86_cpu_realizefn; | |
2711 | dc->bus_type = TYPE_ICC_BUS; | |
2712 | dc->props = x86_cpu_properties; | |
2713 | ||
2714 | xcc->parent_reset = cc->reset; | |
2715 | cc->reset = x86_cpu_reset; | |
2716 | cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; | |
2717 | ||
2718 | cc->do_interrupt = x86_cpu_do_interrupt; | |
2719 | cc->dump_state = x86_cpu_dump_state; | |
2720 | cc->set_pc = x86_cpu_set_pc; | |
2721 | cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; | |
2722 | cc->gdb_read_register = x86_cpu_gdb_read_register; | |
2723 | cc->gdb_write_register = x86_cpu_gdb_write_register; | |
2724 | cc->get_arch_id = x86_cpu_get_arch_id; | |
2725 | cc->get_paging_enabled = x86_cpu_get_paging_enabled; | |
2726 | #ifndef CONFIG_USER_ONLY | |
2727 | cc->get_memory_mapping = x86_cpu_get_memory_mapping; | |
2728 | cc->get_phys_page_debug = x86_cpu_get_phys_page_debug; | |
2729 | cc->write_elf64_note = x86_cpu_write_elf64_note; | |
2730 | cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote; | |
2731 | cc->write_elf32_note = x86_cpu_write_elf32_note; | |
2732 | cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; | |
2733 | cc->vmsd = &vmstate_x86_cpu; | |
2734 | #endif | |
2735 | cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25; | |
2736 | } | |
2737 | ||
2738 | static const TypeInfo x86_cpu_type_info = { | |
2739 | .name = TYPE_X86_CPU, | |
2740 | .parent = TYPE_CPU, | |
2741 | .instance_size = sizeof(X86CPU), | |
2742 | .instance_init = x86_cpu_initfn, | |
2743 | .abstract = false, | |
2744 | .class_size = sizeof(X86CPUClass), | |
2745 | .class_init = x86_cpu_common_class_init, | |
2746 | }; | |
2747 | ||
2748 | static void x86_cpu_register_types(void) | |
2749 | { | |
2750 | type_register_static(&x86_cpu_type_info); | |
2751 | } | |
2752 | ||
2753 | type_init(x86_cpu_register_types) |