]> git.proxmox.com Git - mirror_qemu.git/blame_incremental - target-i386/cpu.c
projects / mirror_qemu.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
target-i386: Merge feature filtering/checking functions
[mirror_qemu.git] / target-i386 / cpu.c
... / ...
CommitLineData
1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "sysemu/kvm.h"
26#include "sysemu/cpus.h"
27#include "kvm_i386.h"
28#include "topology.h"
29
30#include "qemu/option.h"
31#include "qemu/config-file.h"
32#include "qapi/qmp/qerror.h"
33
34#include "qapi-types.h"
35#include "qapi-visit.h"
36#include "qapi/visitor.h"
37#include "sysemu/arch_init.h"
38
39#include "hw/hw.h"
40#if defined(CONFIG_KVM)
41#include <linux/kvm_para.h>
42#endif
43
44#include "sysemu/sysemu.h"
45#include "hw/qdev-properties.h"
46#include "hw/cpu/icc_bus.h"
47#ifndef CONFIG_USER_ONLY
48#include "hw/xen/xen.h"
49#include "hw/i386/apic_internal.h"
50#endif
51
52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
192 "ds_cpl", "vmx", "smx", "est",
193 "tm2", "ssse3", "cid", NULL,
194 "fma", "cx16", "xtpr", "pdcm",
195 NULL, "pcid", "dca", "sse4.1|sse4_1",
196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
197 "tsc-deadline", "aes", "xsave", "osxsave",
198 "avx", "f16c", "rdrand", "hypervisor",
199};
200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
205static const char *ext2_feature_name[] = {
206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
213 NULL, "lm|i64", "3dnowext", "3dnow",
214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
218 "3dnowprefetch", "osvw", "ibs", "xop",
219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
223 NULL, NULL, NULL, NULL,
224};
225
226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
237static const char *kvm_feature_name[] = {
238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
246};
247
248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
259static const char *cpuid_7_0_ebx_feature_name[] = {
260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
266typedef struct FeatureWordInfo {
267 const char **feat_names;
268 uint32_t cpuid_eax; /* Input EAX for CPUID */
269 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
270 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
271 int cpuid_reg; /* output register (R_* constant) */
272} FeatureWordInfo;
273
274static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
275 [FEAT_1_EDX] = {
276 .feat_names = feature_name,
277 .cpuid_eax = 1, .cpuid_reg = R_EDX,
278 },
279 [FEAT_1_ECX] = {
280 .feat_names = ext_feature_name,
281 .cpuid_eax = 1, .cpuid_reg = R_ECX,
282 },
283 [FEAT_8000_0001_EDX] = {
284 .feat_names = ext2_feature_name,
285 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
286 },
287 [FEAT_8000_0001_ECX] = {
288 .feat_names = ext3_feature_name,
289 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
290 },
291 [FEAT_C000_0001_EDX] = {
292 .feat_names = ext4_feature_name,
293 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
294 },
295 [FEAT_KVM] = {
296 .feat_names = kvm_feature_name,
297 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
298 },
299 [FEAT_SVM] = {
300 .feat_names = svm_feature_name,
301 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
302 },
303 [FEAT_7_0_EBX] = {
304 .feat_names = cpuid_7_0_ebx_feature_name,
305 .cpuid_eax = 7,
306 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
307 .cpuid_reg = R_EBX,
308 },
309};
310
311typedef struct X86RegisterInfo32 {
312 /* Name of register */
313 const char *name;
314 /* QAPI enum value register */
315 X86CPURegister32 qapi_enum;
316} X86RegisterInfo32;
317
318#define REGISTER(reg) \
319 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
320static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
321 REGISTER(EAX),
322 REGISTER(ECX),
323 REGISTER(EDX),
324 REGISTER(EBX),
325 REGISTER(ESP),
326 REGISTER(EBP),
327 REGISTER(ESI),
328 REGISTER(EDI),
329};
330#undef REGISTER
331
332typedef struct ExtSaveArea {
333 uint32_t feature, bits;
334 uint32_t offset, size;
335} ExtSaveArea;
336
337static const ExtSaveArea ext_save_areas[] = {
338 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
339 .offset = 0x240, .size = 0x100 },
340 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
341 .offset = 0x3c0, .size = 0x40 },
342 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
343 .offset = 0x400, .size = 0x40 },
344};
345
346const char *get_register_name_32(unsigned int reg)
347{
348 if (reg >= CPU_NB_REGS32) {
349 return NULL;
350 }
351 return x86_reg_info_32[reg].name;
352}
353
354/* collects per-function cpuid data
355 */
356typedef struct model_features_t {
357 uint32_t *guest_feat;
358 uint32_t *host_feat;
359 FeatureWord feat_word;
360} model_features_t;
361
362/* KVM-specific features that are automatically added to all CPU models
363 * when KVM is enabled.
364 */
365static uint32_t kvm_default_features[FEATURE_WORDS] = {
366 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
367 (1 << KVM_FEATURE_NOP_IO_DELAY) |
368 (1 << KVM_FEATURE_CLOCKSOURCE2) |
369 (1 << KVM_FEATURE_ASYNC_PF) |
370 (1 << KVM_FEATURE_STEAL_TIME) |
371 (1 << KVM_FEATURE_PV_EOI) |
372 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
373 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
374};
375
376/* Features that are not added by default to any CPU model when KVM is enabled.
377 */
378static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
379 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
380};
381
382void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
383{
384 kvm_default_features[w] &= ~features;
385}
386
387void host_cpuid(uint32_t function, uint32_t count,
388 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
389{
390 uint32_t vec[4];
391
392#ifdef __x86_64__
393 asm volatile("cpuid"
394 : "=a"(vec[0]), "=b"(vec[1]),
395 "=c"(vec[2]), "=d"(vec[3])
396 : "0"(function), "c"(count) : "cc");
397#elif defined(__i386__)
398 asm volatile("pusha \n\t"
399 "cpuid \n\t"
400 "mov %%eax, 0(%2) \n\t"
401 "mov %%ebx, 4(%2) \n\t"
402 "mov %%ecx, 8(%2) \n\t"
403 "mov %%edx, 12(%2) \n\t"
404 "popa"
405 : : "a"(function), "c"(count), "S"(vec)
406 : "memory", "cc");
407#else
408 abort();
409#endif
410
411 if (eax)
412 *eax = vec[0];
413 if (ebx)
414 *ebx = vec[1];
415 if (ecx)
416 *ecx = vec[2];
417 if (edx)
418 *edx = vec[3];
419}
420
421#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
422
423/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
424 * a substring. ex if !NULL points to the first char after a substring,
425 * otherwise the string is assumed to sized by a terminating nul.
426 * Return lexical ordering of *s1:*s2.
427 */
428static int sstrcmp(const char *s1, const char *e1, const char *s2,
429 const char *e2)
430{
431 for (;;) {
432 if (!*s1 || !*s2 || *s1 != *s2)
433 return (*s1 - *s2);
434 ++s1, ++s2;
435 if (s1 == e1 && s2 == e2)
436 return (0);
437 else if (s1 == e1)
438 return (*s2);
439 else if (s2 == e2)
440 return (*s1);
441 }
442}
443
444/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
445 * '|' delimited (possibly empty) strings in which case search for a match
446 * within the alternatives proceeds left to right. Return 0 for success,
447 * non-zero otherwise.
448 */
449static int altcmp(const char *s, const char *e, const char *altstr)
450{
451 const char *p, *q;
452
453 for (q = p = altstr; ; ) {
454 while (*p && *p != '|')
455 ++p;
456 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
457 return (0);
458 if (!*p)
459 return (1);
460 else
461 q = ++p;
462 }
463}
464
465/* search featureset for flag *[s..e), if found set corresponding bit in
466 * *pval and return true, otherwise return false
467 */
468static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
469 const char **featureset)
470{
471 uint32_t mask;
472 const char **ppc;
473 bool found = false;
474
475 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
476 if (*ppc && !altcmp(s, e, *ppc)) {
477 *pval |= mask;
478 found = true;
479 }
480 }
481 return found;
482}
483
484static void add_flagname_to_bitmaps(const char *flagname,
485 FeatureWordArray words)
486{
487 FeatureWord w;
488 for (w = 0; w < FEATURE_WORDS; w++) {
489 FeatureWordInfo *wi = &feature_word_info[w];
490 if (wi->feat_names &&
491 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
492 break;
493 }
494 }
495 if (w == FEATURE_WORDS) {
496 fprintf(stderr, "CPU feature %s not found\n", flagname);
497 }
498}
499
500/* CPU class name definitions: */
501
502#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
503#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
504
505/* Return type name for a given CPU model name
506 * Caller is responsible for freeing the returned string.
507 */
508static char *x86_cpu_type_name(const char *model_name)
509{
510 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
511}
512
513static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
514{
515 ObjectClass *oc;
516 char *typename;
517
518 if (cpu_model == NULL) {
519 return NULL;
520 }
521
522 typename = x86_cpu_type_name(cpu_model);
523 oc = object_class_by_name(typename);
524 g_free(typename);
525 return oc;
526}
527
528struct X86CPUDefinition {
529 const char *name;
530 uint32_t level;
531 uint32_t xlevel;
532 uint32_t xlevel2;
533 /* vendor is zero-terminated, 12 character ASCII string */
534 char vendor[CPUID_VENDOR_SZ + 1];
535 int family;
536 int model;
537 int stepping;
538 FeatureWordArray features;
539 char model_id[48];
540 bool cache_info_passthrough;
541};
542
543#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
544#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
545 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
546#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
547 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
548 CPUID_PSE36 | CPUID_FXSR)
549#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
550#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
551 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
552 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
553 CPUID_PAE | CPUID_SEP | CPUID_APIC)
554
555#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
556 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
557 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
558 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
559 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
560 /* partly implemented:
561 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
562 /* missing:
563 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
564#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
565 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
566 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
567 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
568 /* missing:
569 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
570 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
571 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
572 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
573 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
574 CPUID_EXT_RDRAND */
575#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
576 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
577 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB)
578#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
579 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
580#define TCG_SVM_FEATURES 0
581#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
582 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
583 /* missing:
584 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
585 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
586 CPUID_7_0_EBX_RDSEED */
587
588static X86CPUDefinition builtin_x86_defs[] = {
589 {
590 .name = "qemu64",
591 .level = 4,
592 .vendor = CPUID_VENDOR_AMD,
593 .family = 6,
594 .model = 6,
595 .stepping = 3,
596 .features[FEAT_1_EDX] =
597 PPRO_FEATURES |
598 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
599 CPUID_PSE36,
600 .features[FEAT_1_ECX] =
601 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
602 .features[FEAT_8000_0001_EDX] =
603 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
604 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
605 .features[FEAT_8000_0001_ECX] =
606 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
607 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
608 .xlevel = 0x8000000A,
609 },
610 {
611 .name = "phenom",
612 .level = 5,
613 .vendor = CPUID_VENDOR_AMD,
614 .family = 16,
615 .model = 2,
616 .stepping = 3,
617 .features[FEAT_1_EDX] =
618 PPRO_FEATURES |
619 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
620 CPUID_PSE36 | CPUID_VME | CPUID_HT,
621 .features[FEAT_1_ECX] =
622 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
623 CPUID_EXT_POPCNT,
624 .features[FEAT_8000_0001_EDX] =
625 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
626 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
627 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
628 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
629 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
630 CPUID_EXT3_CR8LEG,
631 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
632 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
633 .features[FEAT_8000_0001_ECX] =
634 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
635 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
636 .features[FEAT_SVM] =
637 CPUID_SVM_NPT | CPUID_SVM_LBRV,
638 .xlevel = 0x8000001A,
639 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
640 },
641 {
642 .name = "core2duo",
643 .level = 10,
644 .vendor = CPUID_VENDOR_INTEL,
645 .family = 6,
646 .model = 15,
647 .stepping = 11,
648 .features[FEAT_1_EDX] =
649 PPRO_FEATURES |
650 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
651 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
652 CPUID_HT | CPUID_TM | CPUID_PBE,
653 .features[FEAT_1_ECX] =
654 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
655 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
656 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
657 .features[FEAT_8000_0001_EDX] =
658 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
659 .features[FEAT_8000_0001_ECX] =
660 CPUID_EXT3_LAHF_LM,
661 .xlevel = 0x80000008,
662 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
663 },
664 {
665 .name = "kvm64",
666 .level = 5,
667 .vendor = CPUID_VENDOR_INTEL,
668 .family = 15,
669 .model = 6,
670 .stepping = 1,
671 /* Missing: CPUID_VME, CPUID_HT */
672 .features[FEAT_1_EDX] =
673 PPRO_FEATURES |
674 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
675 CPUID_PSE36,
676 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
677 .features[FEAT_1_ECX] =
678 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
679 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
680 .features[FEAT_8000_0001_EDX] =
681 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
682 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
683 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
684 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
685 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
686 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
687 .features[FEAT_8000_0001_ECX] =
688 0,
689 .xlevel = 0x80000008,
690 .model_id = "Common KVM processor"
691 },
692 {
693 .name = "qemu32",
694 .level = 4,
695 .vendor = CPUID_VENDOR_INTEL,
696 .family = 6,
697 .model = 6,
698 .stepping = 3,
699 .features[FEAT_1_EDX] =
700 PPRO_FEATURES,
701 .features[FEAT_1_ECX] =
702 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
703 .xlevel = 0x80000004,
704 },
705 {
706 .name = "kvm32",
707 .level = 5,
708 .vendor = CPUID_VENDOR_INTEL,
709 .family = 15,
710 .model = 6,
711 .stepping = 1,
712 .features[FEAT_1_EDX] =
713 PPRO_FEATURES |
714 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
715 .features[FEAT_1_ECX] =
716 CPUID_EXT_SSE3,
717 .features[FEAT_8000_0001_EDX] =
718 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
719 .features[FEAT_8000_0001_ECX] =
720 0,
721 .xlevel = 0x80000008,
722 .model_id = "Common 32-bit KVM processor"
723 },
724 {
725 .name = "coreduo",
726 .level = 10,
727 .vendor = CPUID_VENDOR_INTEL,
728 .family = 6,
729 .model = 14,
730 .stepping = 8,
731 .features[FEAT_1_EDX] =
732 PPRO_FEATURES | CPUID_VME |
733 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
734 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
735 .features[FEAT_1_ECX] =
736 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
737 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
738 .features[FEAT_8000_0001_EDX] =
739 CPUID_EXT2_NX,
740 .xlevel = 0x80000008,
741 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
742 },
743 {
744 .name = "486",
745 .level = 1,
746 .vendor = CPUID_VENDOR_INTEL,
747 .family = 4,
748 .model = 8,
749 .stepping = 0,
750 .features[FEAT_1_EDX] =
751 I486_FEATURES,
752 .xlevel = 0,
753 },
754 {
755 .name = "pentium",
756 .level = 1,
757 .vendor = CPUID_VENDOR_INTEL,
758 .family = 5,
759 .model = 4,
760 .stepping = 3,
761 .features[FEAT_1_EDX] =
762 PENTIUM_FEATURES,
763 .xlevel = 0,
764 },
765 {
766 .name = "pentium2",
767 .level = 2,
768 .vendor = CPUID_VENDOR_INTEL,
769 .family = 6,
770 .model = 5,
771 .stepping = 2,
772 .features[FEAT_1_EDX] =
773 PENTIUM2_FEATURES,
774 .xlevel = 0,
775 },
776 {
777 .name = "pentium3",
778 .level = 2,
779 .vendor = CPUID_VENDOR_INTEL,
780 .family = 6,
781 .model = 7,
782 .stepping = 3,
783 .features[FEAT_1_EDX] =
784 PENTIUM3_FEATURES,
785 .xlevel = 0,
786 },
787 {
788 .name = "athlon",
789 .level = 2,
790 .vendor = CPUID_VENDOR_AMD,
791 .family = 6,
792 .model = 2,
793 .stepping = 3,
794 .features[FEAT_1_EDX] =
795 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
796 CPUID_MCA,
797 .features[FEAT_8000_0001_EDX] =
798 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
799 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
800 .xlevel = 0x80000008,
801 },
802 {
803 .name = "n270",
804 /* original is on level 10 */
805 .level = 5,
806 .vendor = CPUID_VENDOR_INTEL,
807 .family = 6,
808 .model = 28,
809 .stepping = 2,
810 .features[FEAT_1_EDX] =
811 PPRO_FEATURES |
812 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
813 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
814 /* Some CPUs got no CPUID_SEP */
815 .features[FEAT_1_ECX] =
816 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
817 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
818 CPUID_EXT_MOVBE,
819 .features[FEAT_8000_0001_EDX] =
820 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
821 CPUID_EXT2_NX,
822 .features[FEAT_8000_0001_ECX] =
823 CPUID_EXT3_LAHF_LM,
824 .xlevel = 0x8000000A,
825 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
826 },
827 {
828 .name = "Conroe",
829 .level = 4,
830 .vendor = CPUID_VENDOR_INTEL,
831 .family = 6,
832 .model = 15,
833 .stepping = 3,
834 .features[FEAT_1_EDX] =
835 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
836 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
837 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
838 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
839 CPUID_DE | CPUID_FP87,
840 .features[FEAT_1_ECX] =
841 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
842 .features[FEAT_8000_0001_EDX] =
843 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
844 .features[FEAT_8000_0001_ECX] =
845 CPUID_EXT3_LAHF_LM,
846 .xlevel = 0x8000000A,
847 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
848 },
849 {
850 .name = "Penryn",
851 .level = 4,
852 .vendor = CPUID_VENDOR_INTEL,
853 .family = 6,
854 .model = 23,
855 .stepping = 3,
856 .features[FEAT_1_EDX] =
857 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
858 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
859 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
860 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
861 CPUID_DE | CPUID_FP87,
862 .features[FEAT_1_ECX] =
863 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
864 CPUID_EXT_SSE3,
865 .features[FEAT_8000_0001_EDX] =
866 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
867 .features[FEAT_8000_0001_ECX] =
868 CPUID_EXT3_LAHF_LM,
869 .xlevel = 0x8000000A,
870 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
871 },
872 {
873 .name = "Nehalem",
874 .level = 4,
875 .vendor = CPUID_VENDOR_INTEL,
876 .family = 6,
877 .model = 26,
878 .stepping = 3,
879 .features[FEAT_1_EDX] =
880 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
881 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
882 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
883 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
884 CPUID_DE | CPUID_FP87,
885 .features[FEAT_1_ECX] =
886 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
887 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
888 .features[FEAT_8000_0001_EDX] =
889 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
890 .features[FEAT_8000_0001_ECX] =
891 CPUID_EXT3_LAHF_LM,
892 .xlevel = 0x8000000A,
893 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
894 },
895 {
896 .name = "Westmere",
897 .level = 11,
898 .vendor = CPUID_VENDOR_INTEL,
899 .family = 6,
900 .model = 44,
901 .stepping = 1,
902 .features[FEAT_1_EDX] =
903 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
904 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
905 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
906 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
907 CPUID_DE | CPUID_FP87,
908 .features[FEAT_1_ECX] =
909 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
910 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
911 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
912 .features[FEAT_8000_0001_EDX] =
913 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
914 .features[FEAT_8000_0001_ECX] =
915 CPUID_EXT3_LAHF_LM,
916 .xlevel = 0x8000000A,
917 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
918 },
919 {
920 .name = "SandyBridge",
921 .level = 0xd,
922 .vendor = CPUID_VENDOR_INTEL,
923 .family = 6,
924 .model = 42,
925 .stepping = 1,
926 .features[FEAT_1_EDX] =
927 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
928 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
929 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
930 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
931 CPUID_DE | CPUID_FP87,
932 .features[FEAT_1_ECX] =
933 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
934 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
935 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
936 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
937 CPUID_EXT_SSE3,
938 .features[FEAT_8000_0001_EDX] =
939 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
940 CPUID_EXT2_SYSCALL,
941 .features[FEAT_8000_0001_ECX] =
942 CPUID_EXT3_LAHF_LM,
943 .xlevel = 0x8000000A,
944 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
945 },
946 {
947 .name = "Haswell",
948 .level = 0xd,
949 .vendor = CPUID_VENDOR_INTEL,
950 .family = 6,
951 .model = 60,
952 .stepping = 1,
953 .features[FEAT_1_EDX] =
954 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
955 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
956 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
957 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
958 CPUID_DE | CPUID_FP87,
959 .features[FEAT_1_ECX] =
960 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
961 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
962 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
963 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
964 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
965 CPUID_EXT_PCID,
966 .features[FEAT_8000_0001_EDX] =
967 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
968 CPUID_EXT2_SYSCALL,
969 .features[FEAT_8000_0001_ECX] =
970 CPUID_EXT3_LAHF_LM,
971 .features[FEAT_7_0_EBX] =
972 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
973 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
974 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
975 CPUID_7_0_EBX_RTM,
976 .xlevel = 0x8000000A,
977 .model_id = "Intel Core Processor (Haswell)",
978 },
979 {
980 .name = "Opteron_G1",
981 .level = 5,
982 .vendor = CPUID_VENDOR_AMD,
983 .family = 15,
984 .model = 6,
985 .stepping = 1,
986 .features[FEAT_1_EDX] =
987 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
988 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
989 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
990 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
991 CPUID_DE | CPUID_FP87,
992 .features[FEAT_1_ECX] =
993 CPUID_EXT_SSE3,
994 .features[FEAT_8000_0001_EDX] =
995 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
996 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
997 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
998 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
999 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1000 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1001 .xlevel = 0x80000008,
1002 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1003 },
1004 {
1005 .name = "Opteron_G2",
1006 .level = 5,
1007 .vendor = CPUID_VENDOR_AMD,
1008 .family = 15,
1009 .model = 6,
1010 .stepping = 1,
1011 .features[FEAT_1_EDX] =
1012 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1013 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1014 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1015 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1016 CPUID_DE | CPUID_FP87,
1017 .features[FEAT_1_ECX] =
1018 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1019 .features[FEAT_8000_0001_EDX] =
1020 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1021 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1022 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1023 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1024 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1025 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1026 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1027 .features[FEAT_8000_0001_ECX] =
1028 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1029 .xlevel = 0x80000008,
1030 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1031 },
1032 {
1033 .name = "Opteron_G3",
1034 .level = 5,
1035 .vendor = CPUID_VENDOR_AMD,
1036 .family = 15,
1037 .model = 6,
1038 .stepping = 1,
1039 .features[FEAT_1_EDX] =
1040 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1041 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1042 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1043 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1044 CPUID_DE | CPUID_FP87,
1045 .features[FEAT_1_ECX] =
1046 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1047 CPUID_EXT_SSE3,
1048 .features[FEAT_8000_0001_EDX] =
1049 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1050 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1051 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1052 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1053 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1054 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1055 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1056 .features[FEAT_8000_0001_ECX] =
1057 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1058 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1059 .xlevel = 0x80000008,
1060 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1061 },
1062 {
1063 .name = "Opteron_G4",
1064 .level = 0xd,
1065 .vendor = CPUID_VENDOR_AMD,
1066 .family = 21,
1067 .model = 1,
1068 .stepping = 2,
1069 .features[FEAT_1_EDX] =
1070 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1071 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1072 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1073 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1074 CPUID_DE | CPUID_FP87,
1075 .features[FEAT_1_ECX] =
1076 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1077 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1078 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1079 CPUID_EXT_SSE3,
1080 .features[FEAT_8000_0001_EDX] =
1081 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1082 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1083 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1084 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1085 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1086 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1087 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1088 .features[FEAT_8000_0001_ECX] =
1089 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1090 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1091 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1092 CPUID_EXT3_LAHF_LM,
1093 .xlevel = 0x8000001A,
1094 .model_id = "AMD Opteron 62xx class CPU",
1095 },
1096 {
1097 .name = "Opteron_G5",
1098 .level = 0xd,
1099 .vendor = CPUID_VENDOR_AMD,
1100 .family = 21,
1101 .model = 2,
1102 .stepping = 0,
1103 .features[FEAT_1_EDX] =
1104 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1105 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1106 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1107 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1108 CPUID_DE | CPUID_FP87,
1109 .features[FEAT_1_ECX] =
1110 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1111 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1112 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1113 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1114 .features[FEAT_8000_0001_EDX] =
1115 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1116 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1117 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1118 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1119 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1120 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1121 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1122 .features[FEAT_8000_0001_ECX] =
1123 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1124 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1125 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1126 CPUID_EXT3_LAHF_LM,
1127 .xlevel = 0x8000001A,
1128 .model_id = "AMD Opteron 63xx class CPU",
1129 },
1130};
1131
1132/**
1133 * x86_cpu_compat_set_features:
1134 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1135 * @w: Identifies the feature word to be changed.
1136 * @feat_add: Feature bits to be added to feature word
1137 * @feat_remove: Feature bits to be removed from feature word
1138 *
1139 * Change CPU model feature bits for compatibility.
1140 *
1141 * This function may be used by machine-type compatibility functions
1142 * to enable or disable feature bits on specific CPU models.
1143 */
1144void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1145 uint32_t feat_add, uint32_t feat_remove)
1146{
1147 X86CPUDefinition *def;
1148 int i;
1149 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1150 def = &builtin_x86_defs[i];
1151 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1152 def->features[w] |= feat_add;
1153 def->features[w] &= ~feat_remove;
1154 }
1155 }
1156}
1157
1158#ifdef CONFIG_KVM
1159
1160static int cpu_x86_fill_model_id(char *str)
1161{
1162 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1163 int i;
1164
1165 for (i = 0; i < 3; i++) {
1166 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1167 memcpy(str + i * 16 + 0, &eax, 4);
1168 memcpy(str + i * 16 + 4, &ebx, 4);
1169 memcpy(str + i * 16 + 8, &ecx, 4);
1170 memcpy(str + i * 16 + 12, &edx, 4);
1171 }
1172 return 0;
1173}
1174
1175static X86CPUDefinition host_cpudef;
1176
1177/* class_init for the "host" CPU model
1178 *
1179 * This function may be called before KVM is initialized.
1180 */
1181static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1182{
1183 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1184 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1185
1186 xcc->kvm_required = true;
1187
1188 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1189 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1190
1191 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1192 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1193 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1194 host_cpudef.stepping = eax & 0x0F;
1195
1196 cpu_x86_fill_model_id(host_cpudef.model_id);
1197
1198 xcc->cpu_def = &host_cpudef;
1199 host_cpudef.cache_info_passthrough = true;
1200
1201 /* level, xlevel, xlevel2, and the feature words are initialized on
1202 * instance_init, because they require KVM to be initialized.
1203 */
1204}
1205
1206static void host_x86_cpu_initfn(Object *obj)
1207{
1208 X86CPU *cpu = X86_CPU(obj);
1209 CPUX86State *env = &cpu->env;
1210 KVMState *s = kvm_state;
1211 FeatureWord w;
1212
1213 assert(kvm_enabled());
1214
1215 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1216 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1217 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1218
1219 for (w = 0; w < FEATURE_WORDS; w++) {
1220 FeatureWordInfo *wi = &feature_word_info[w];
1221 env->features[w] =
1222 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1223 wi->cpuid_reg);
1224 }
1225 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1226}
1227
1228static const TypeInfo host_x86_cpu_type_info = {
1229 .name = X86_CPU_TYPE_NAME("host"),
1230 .parent = TYPE_X86_CPU,
1231 .instance_init = host_x86_cpu_initfn,
1232 .class_init = host_x86_cpu_class_init,
1233};
1234
1235#endif
1236
1237static void report_unavailable_features(FeatureWordInfo *f, uint32_t mask)
1238{
1239 int i;
1240
1241 for (i = 0; i < 32; ++i) {
1242 if (1 << i & mask) {
1243 const char *reg = get_register_name_32(f->cpuid_reg);
1244 assert(reg);
1245 fprintf(stderr, "warning: host doesn't support requested feature: "
1246 "CPUID.%02XH:%s%s%s [bit %d]\n",
1247 f->cpuid_eax, reg,
1248 f->feat_names[i] ? "." : "",
1249 f->feat_names[i] ? f->feat_names[i] : "", i);
1250 }
1251 }
1252}
1253
1254static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1255 const char *name, Error **errp)
1256{
1257 X86CPU *cpu = X86_CPU(obj);
1258 CPUX86State *env = &cpu->env;
1259 int64_t value;
1260
1261 value = (env->cpuid_version >> 8) & 0xf;
1262 if (value == 0xf) {
1263 value += (env->cpuid_version >> 20) & 0xff;
1264 }
1265 visit_type_int(v, &value, name, errp);
1266}
1267
1268static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1269 const char *name, Error **errp)
1270{
1271 X86CPU *cpu = X86_CPU(obj);
1272 CPUX86State *env = &cpu->env;
1273 const int64_t min = 0;
1274 const int64_t max = 0xff + 0xf;
1275 Error *local_err = NULL;
1276 int64_t value;
1277
1278 visit_type_int(v, &value, name, &local_err);
1279 if (local_err) {
1280 error_propagate(errp, local_err);
1281 return;
1282 }
1283 if (value < min || value > max) {
1284 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1285 name ? name : "null", value, min, max);
1286 return;
1287 }
1288
1289 env->cpuid_version &= ~0xff00f00;
1290 if (value > 0x0f) {
1291 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1292 } else {
1293 env->cpuid_version |= value << 8;
1294 }
1295}
1296
1297static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1298 const char *name, Error **errp)
1299{
1300 X86CPU *cpu = X86_CPU(obj);
1301 CPUX86State *env = &cpu->env;
1302 int64_t value;
1303
1304 value = (env->cpuid_version >> 4) & 0xf;
1305 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1306 visit_type_int(v, &value, name, errp);
1307}
1308
1309static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1310 const char *name, Error **errp)
1311{
1312 X86CPU *cpu = X86_CPU(obj);
1313 CPUX86State *env = &cpu->env;
1314 const int64_t min = 0;
1315 const int64_t max = 0xff;
1316 Error *local_err = NULL;
1317 int64_t value;
1318
1319 visit_type_int(v, &value, name, &local_err);
1320 if (local_err) {
1321 error_propagate(errp, local_err);
1322 return;
1323 }
1324 if (value < min || value > max) {
1325 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1326 name ? name : "null", value, min, max);
1327 return;
1328 }
1329
1330 env->cpuid_version &= ~0xf00f0;
1331 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1332}
1333
1334static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1335 void *opaque, const char *name,
1336 Error **errp)
1337{
1338 X86CPU *cpu = X86_CPU(obj);
1339 CPUX86State *env = &cpu->env;
1340 int64_t value;
1341
1342 value = env->cpuid_version & 0xf;
1343 visit_type_int(v, &value, name, errp);
1344}
1345
1346static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1347 void *opaque, const char *name,
1348 Error **errp)
1349{
1350 X86CPU *cpu = X86_CPU(obj);
1351 CPUX86State *env = &cpu->env;
1352 const int64_t min = 0;
1353 const int64_t max = 0xf;
1354 Error *local_err = NULL;
1355 int64_t value;
1356
1357 visit_type_int(v, &value, name, &local_err);
1358 if (local_err) {
1359 error_propagate(errp, local_err);
1360 return;
1361 }
1362 if (value < min || value > max) {
1363 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1364 name ? name : "null", value, min, max);
1365 return;
1366 }
1367
1368 env->cpuid_version &= ~0xf;
1369 env->cpuid_version |= value & 0xf;
1370}
1371
1372static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1373 const char *name, Error **errp)
1374{
1375 X86CPU *cpu = X86_CPU(obj);
1376
1377 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1378}
1379
1380static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1381 const char *name, Error **errp)
1382{
1383 X86CPU *cpu = X86_CPU(obj);
1384
1385 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1386}
1387
1388static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1389 const char *name, Error **errp)
1390{
1391 X86CPU *cpu = X86_CPU(obj);
1392
1393 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1394}
1395
1396static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1397 const char *name, Error **errp)
1398{
1399 X86CPU *cpu = X86_CPU(obj);
1400
1401 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1402}
1403
1404static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1405{
1406 X86CPU *cpu = X86_CPU(obj);
1407 CPUX86State *env = &cpu->env;
1408 char *value;
1409
1410 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1411 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1412 env->cpuid_vendor3);
1413 return value;
1414}
1415
1416static void x86_cpuid_set_vendor(Object *obj, const char *value,
1417 Error **errp)
1418{
1419 X86CPU *cpu = X86_CPU(obj);
1420 CPUX86State *env = &cpu->env;
1421 int i;
1422
1423 if (strlen(value) != CPUID_VENDOR_SZ) {
1424 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1425 "vendor", value);
1426 return;
1427 }
1428
1429 env->cpuid_vendor1 = 0;
1430 env->cpuid_vendor2 = 0;
1431 env->cpuid_vendor3 = 0;
1432 for (i = 0; i < 4; i++) {
1433 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1434 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1435 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1436 }
1437}
1438
1439static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1440{
1441 X86CPU *cpu = X86_CPU(obj);
1442 CPUX86State *env = &cpu->env;
1443 char *value;
1444 int i;
1445
1446 value = g_malloc(48 + 1);
1447 for (i = 0; i < 48; i++) {
1448 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1449 }
1450 value[48] = '\0';
1451 return value;
1452}
1453
1454static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1455 Error **errp)
1456{
1457 X86CPU *cpu = X86_CPU(obj);
1458 CPUX86State *env = &cpu->env;
1459 int c, len, i;
1460
1461 if (model_id == NULL) {
1462 model_id = "";
1463 }
1464 len = strlen(model_id);
1465 memset(env->cpuid_model, 0, 48);
1466 for (i = 0; i < 48; i++) {
1467 if (i >= len) {
1468 c = '\0';
1469 } else {
1470 c = (uint8_t)model_id[i];
1471 }
1472 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1473 }
1474}
1475
1476static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1477 const char *name, Error **errp)
1478{
1479 X86CPU *cpu = X86_CPU(obj);
1480 int64_t value;
1481
1482 value = cpu->env.tsc_khz * 1000;
1483 visit_type_int(v, &value, name, errp);
1484}
1485
1486static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1487 const char *name, Error **errp)
1488{
1489 X86CPU *cpu = X86_CPU(obj);
1490 const int64_t min = 0;
1491 const int64_t max = INT64_MAX;
1492 Error *local_err = NULL;
1493 int64_t value;
1494
1495 visit_type_int(v, &value, name, &local_err);
1496 if (local_err) {
1497 error_propagate(errp, local_err);
1498 return;
1499 }
1500 if (value < min || value > max) {
1501 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1502 name ? name : "null", value, min, max);
1503 return;
1504 }
1505
1506 cpu->env.tsc_khz = value / 1000;
1507}
1508
1509static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1510 const char *name, Error **errp)
1511{
1512 X86CPU *cpu = X86_CPU(obj);
1513 int64_t value = cpu->env.cpuid_apic_id;
1514
1515 visit_type_int(v, &value, name, errp);
1516}
1517
1518static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1519 const char *name, Error **errp)
1520{
1521 X86CPU *cpu = X86_CPU(obj);
1522 DeviceState *dev = DEVICE(obj);
1523 const int64_t min = 0;
1524 const int64_t max = UINT32_MAX;
1525 Error *error = NULL;
1526 int64_t value;
1527
1528 if (dev->realized) {
1529 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1530 "it was realized", name, object_get_typename(obj));
1531 return;
1532 }
1533
1534 visit_type_int(v, &value, name, &error);
1535 if (error) {
1536 error_propagate(errp, error);
1537 return;
1538 }
1539 if (value < min || value > max) {
1540 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1541 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1542 object_get_typename(obj), name, value, min, max);
1543 return;
1544 }
1545
1546 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1547 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1548 return;
1549 }
1550 cpu->env.cpuid_apic_id = value;
1551}
1552
1553/* Generic getter for "feature-words" and "filtered-features" properties */
1554static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1555 const char *name, Error **errp)
1556{
1557 uint32_t *array = (uint32_t *)opaque;
1558 FeatureWord w;
1559 Error *err = NULL;
1560 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1561 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1562 X86CPUFeatureWordInfoList *list = NULL;
1563
1564 for (w = 0; w < FEATURE_WORDS; w++) {
1565 FeatureWordInfo *wi = &feature_word_info[w];
1566 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1567 qwi->cpuid_input_eax = wi->cpuid_eax;
1568 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1569 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1570 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1571 qwi->features = array[w];
1572
1573 /* List will be in reverse order, but order shouldn't matter */
1574 list_entries[w].next = list;
1575 list_entries[w].value = &word_infos[w];
1576 list = &list_entries[w];
1577 }
1578
1579 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1580 error_propagate(errp, err);
1581}
1582
1583static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1584 const char *name, Error **errp)
1585{
1586 X86CPU *cpu = X86_CPU(obj);
1587 int64_t value = cpu->hyperv_spinlock_attempts;
1588
1589 visit_type_int(v, &value, name, errp);
1590}
1591
1592static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1593 const char *name, Error **errp)
1594{
1595 const int64_t min = 0xFFF;
1596 const int64_t max = UINT_MAX;
1597 X86CPU *cpu = X86_CPU(obj);
1598 Error *err = NULL;
1599 int64_t value;
1600
1601 visit_type_int(v, &value, name, &err);
1602 if (err) {
1603 error_propagate(errp, err);
1604 return;
1605 }
1606
1607 if (value < min || value > max) {
1608 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1609 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1610 object_get_typename(obj), name ? name : "null",
1611 value, min, max);
1612 return;
1613 }
1614 cpu->hyperv_spinlock_attempts = value;
1615}
1616
1617static PropertyInfo qdev_prop_spinlocks = {
1618 .name = "int",
1619 .get = x86_get_hv_spinlocks,
1620 .set = x86_set_hv_spinlocks,
1621};
1622
1623/* Convert all '_' in a feature string option name to '-', to make feature
1624 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1625 */
1626static inline void feat2prop(char *s)
1627{
1628 while ((s = strchr(s, '_'))) {
1629 *s = '-';
1630 }
1631}
1632
1633/* Parse "+feature,-feature,feature=foo" CPU feature string
1634 */
1635static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1636 Error **errp)
1637{
1638 X86CPU *cpu = X86_CPU(cs);
1639 char *featurestr; /* Single 'key=value" string being parsed */
1640 /* Features to be added */
1641 FeatureWordArray plus_features = { 0 };
1642 /* Features to be removed */
1643 FeatureWordArray minus_features = { 0 };
1644 uint32_t numvalue;
1645 CPUX86State *env = &cpu->env;
1646 Error *local_err = NULL;
1647
1648 featurestr = features ? strtok(features, ",") : NULL;
1649
1650 while (featurestr) {
1651 char *val;
1652 if (featurestr[0] == '+') {
1653 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1654 } else if (featurestr[0] == '-') {
1655 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1656 } else if ((val = strchr(featurestr, '='))) {
1657 *val = 0; val++;
1658 feat2prop(featurestr);
1659 if (!strcmp(featurestr, "xlevel")) {
1660 char *err;
1661 char num[32];
1662
1663 numvalue = strtoul(val, &err, 0);
1664 if (!*val || *err) {
1665 error_setg(errp, "bad numerical value %s", val);
1666 return;
1667 }
1668 if (numvalue < 0x80000000) {
1669 error_report("xlevel value shall always be >= 0x80000000"
1670 ", fixup will be removed in future versions");
1671 numvalue += 0x80000000;
1672 }
1673 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1674 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1675 } else if (!strcmp(featurestr, "tsc-freq")) {
1676 int64_t tsc_freq;
1677 char *err;
1678 char num[32];
1679
1680 tsc_freq = strtosz_suffix_unit(val, &err,
1681 STRTOSZ_DEFSUFFIX_B, 1000);
1682 if (tsc_freq < 0 || *err) {
1683 error_setg(errp, "bad numerical value %s", val);
1684 return;
1685 }
1686 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1687 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1688 &local_err);
1689 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1690 char *err;
1691 const int min = 0xFFF;
1692 char num[32];
1693 numvalue = strtoul(val, &err, 0);
1694 if (!*val || *err) {
1695 error_setg(errp, "bad numerical value %s", val);
1696 return;
1697 }
1698 if (numvalue < min) {
1699 error_report("hv-spinlocks value shall always be >= 0x%x"
1700 ", fixup will be removed in future versions",
1701 min);
1702 numvalue = min;
1703 }
1704 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1705 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1706 } else {
1707 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1708 }
1709 } else {
1710 feat2prop(featurestr);
1711 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1712 }
1713 if (local_err) {
1714 error_propagate(errp, local_err);
1715 return;
1716 }
1717 featurestr = strtok(NULL, ",");
1718 }
1719 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1720 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1721 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1722 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1723 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1724 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1725 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1726 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1727 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1728 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1729 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1730 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1731 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1732 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1733 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1734 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1735}
1736
1737/* generate a composite string into buf of all cpuid names in featureset
1738 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1739 * if flags, suppress names undefined in featureset.
1740 */
1741static void listflags(char *buf, int bufsize, uint32_t fbits,
1742 const char **featureset, uint32_t flags)
1743{
1744 const char **p = &featureset[31];
1745 char *q, *b, bit;
1746 int nc;
1747
1748 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1749 *buf = '\0';
1750 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1751 if (fbits & 1 << bit && (*p || !flags)) {
1752 if (*p)
1753 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1754 else
1755 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1756 if (bufsize <= nc) {
1757 if (b) {
1758 memcpy(b, "...", sizeof("..."));
1759 }
1760 return;
1761 }
1762 q += nc;
1763 bufsize -= nc;
1764 }
1765}
1766
1767/* generate CPU information. */
1768void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1769{
1770 X86CPUDefinition *def;
1771 char buf[256];
1772 int i;
1773
1774 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1775 def = &builtin_x86_defs[i];
1776 snprintf(buf, sizeof(buf), "%s", def->name);
1777 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1778 }
1779#ifdef CONFIG_KVM
1780 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1781 "KVM processor with all supported host features "
1782 "(only available in KVM mode)");
1783#endif
1784
1785 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1786 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1787 FeatureWordInfo *fw = &feature_word_info[i];
1788
1789 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1790 (*cpu_fprintf)(f, " %s\n", buf);
1791 }
1792}
1793
1794CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1795{
1796 CpuDefinitionInfoList *cpu_list = NULL;
1797 X86CPUDefinition *def;
1798 int i;
1799
1800 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1801 CpuDefinitionInfoList *entry;
1802 CpuDefinitionInfo *info;
1803
1804 def = &builtin_x86_defs[i];
1805 info = g_malloc0(sizeof(*info));
1806 info->name = g_strdup(def->name);
1807
1808 entry = g_malloc0(sizeof(*entry));
1809 entry->value = info;
1810 entry->next = cpu_list;
1811 cpu_list = entry;
1812 }
1813
1814 return cpu_list;
1815}
1816
1817/*
1818 * Filters CPU feature words based on host availability of each feature.
1819 *
1820 * This function may be called only if KVM is enabled.
1821 *
1822 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1823 */
1824static int filter_features_for_kvm(X86CPU *cpu)
1825{
1826 CPUX86State *env = &cpu->env;
1827 KVMState *s = kvm_state;
1828 FeatureWord w;
1829 int rv = 0;
1830
1831 assert(kvm_enabled());
1832
1833 for (w = 0; w < FEATURE_WORDS; w++) {
1834 FeatureWordInfo *wi = &feature_word_info[w];
1835 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1836 wi->cpuid_ecx,
1837 wi->cpuid_reg);
1838 uint32_t requested_features = env->features[w];
1839 env->features[w] &= host_feat;
1840 cpu->filtered_features[w] = requested_features & ~env->features[w];
1841 if (cpu->filtered_features[w]) {
1842 if (cpu->check_cpuid || cpu->enforce_cpuid) {
1843 report_unavailable_features(wi, cpu->filtered_features[w]);
1844 }
1845 rv = 1;
1846 }
1847 }
1848
1849 return rv;
1850}
1851
1852/* Load data from X86CPUDefinition
1853 */
1854static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1855{
1856 CPUX86State *env = &cpu->env;
1857 const char *vendor;
1858 char host_vendor[CPUID_VENDOR_SZ + 1];
1859
1860 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1861 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1862 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1863 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1864 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1865 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1866 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1867 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1868 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1869 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1870 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1871 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1872 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1873 env->cpuid_xlevel2 = def->xlevel2;
1874 cpu->cache_info_passthrough = def->cache_info_passthrough;
1875
1876 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1877
1878 /* Special cases not set in the X86CPUDefinition structs: */
1879 if (kvm_enabled()) {
1880 FeatureWord w;
1881 for (w = 0; w < FEATURE_WORDS; w++) {
1882 env->features[w] |= kvm_default_features[w];
1883 env->features[w] &= ~kvm_default_unset_features[w];
1884 }
1885 }
1886
1887 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1888
1889 /* sysenter isn't supported in compatibility mode on AMD,
1890 * syscall isn't supported in compatibility mode on Intel.
1891 * Normally we advertise the actual CPU vendor, but you can
1892 * override this using the 'vendor' property if you want to use
1893 * KVM's sysenter/syscall emulation in compatibility mode and
1894 * when doing cross vendor migration
1895 */
1896 vendor = def->vendor;
1897 if (kvm_enabled()) {
1898 uint32_t ebx = 0, ecx = 0, edx = 0;
1899 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1900 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1901 vendor = host_vendor;
1902 }
1903
1904 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1905
1906}
1907
1908X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1909 Error **errp)
1910{
1911 X86CPU *cpu = NULL;
1912 X86CPUClass *xcc;
1913 ObjectClass *oc;
1914 gchar **model_pieces;
1915 char *name, *features;
1916 Error *error = NULL;
1917
1918 model_pieces = g_strsplit(cpu_model, ",", 2);
1919 if (!model_pieces[0]) {
1920 error_setg(&error, "Invalid/empty CPU model name");
1921 goto out;
1922 }
1923 name = model_pieces[0];
1924 features = model_pieces[1];
1925
1926 oc = x86_cpu_class_by_name(name);
1927 if (oc == NULL) {
1928 error_setg(&error, "Unable to find CPU definition: %s", name);
1929 goto out;
1930 }
1931 xcc = X86_CPU_CLASS(oc);
1932
1933 if (xcc->kvm_required && !kvm_enabled()) {
1934 error_setg(&error, "CPU model '%s' requires KVM", name);
1935 goto out;
1936 }
1937
1938 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1939
1940#ifndef CONFIG_USER_ONLY
1941 if (icc_bridge == NULL) {
1942 error_setg(&error, "Invalid icc-bridge value");
1943 goto out;
1944 }
1945 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1946 object_unref(OBJECT(cpu));
1947#endif
1948
1949 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
1950 if (error) {
1951 goto out;
1952 }
1953
1954out:
1955 if (error != NULL) {
1956 error_propagate(errp, error);
1957 if (cpu) {
1958 object_unref(OBJECT(cpu));
1959 cpu = NULL;
1960 }
1961 }
1962 g_strfreev(model_pieces);
1963 return cpu;
1964}
1965
1966X86CPU *cpu_x86_init(const char *cpu_model)
1967{
1968 Error *error = NULL;
1969 X86CPU *cpu;
1970
1971 cpu = cpu_x86_create(cpu_model, NULL, &error);
1972 if (error) {
1973 goto out;
1974 }
1975
1976 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1977
1978out:
1979 if (error) {
1980 error_report("%s", error_get_pretty(error));
1981 error_free(error);
1982 if (cpu != NULL) {
1983 object_unref(OBJECT(cpu));
1984 cpu = NULL;
1985 }
1986 }
1987 return cpu;
1988}
1989
1990static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
1991{
1992 X86CPUDefinition *cpudef = data;
1993 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1994
1995 xcc->cpu_def = cpudef;
1996}
1997
1998static void x86_register_cpudef_type(X86CPUDefinition *def)
1999{
2000 char *typename = x86_cpu_type_name(def->name);
2001 TypeInfo ti = {
2002 .name = typename,
2003 .parent = TYPE_X86_CPU,
2004 .class_init = x86_cpu_cpudef_class_init,
2005 .class_data = def,
2006 };
2007
2008 type_register(&ti);
2009 g_free(typename);
2010}
2011
2012#if !defined(CONFIG_USER_ONLY)
2013
2014void cpu_clear_apic_feature(CPUX86State *env)
2015{
2016 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2017}
2018
2019#endif /* !CONFIG_USER_ONLY */
2020
2021/* Initialize list of CPU models, filling some non-static fields if necessary
2022 */
2023void x86_cpudef_setup(void)
2024{
2025 int i, j;
2026 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2027
2028 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2029 X86CPUDefinition *def = &builtin_x86_defs[i];
2030
2031 /* Look for specific "cpudef" models that */
2032 /* have the QEMU version in .model_id */
2033 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2034 if (strcmp(model_with_versions[j], def->name) == 0) {
2035 pstrcpy(def->model_id, sizeof(def->model_id),
2036 "QEMU Virtual CPU version ");
2037 pstrcat(def->model_id, sizeof(def->model_id),
2038 qemu_get_version());
2039 break;
2040 }
2041 }
2042 }
2043}
2044
2045static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2046 uint32_t *ecx, uint32_t *edx)
2047{
2048 *ebx = env->cpuid_vendor1;
2049 *edx = env->cpuid_vendor2;
2050 *ecx = env->cpuid_vendor3;
2051}
2052
2053void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2054 uint32_t *eax, uint32_t *ebx,
2055 uint32_t *ecx, uint32_t *edx)
2056{
2057 X86CPU *cpu = x86_env_get_cpu(env);
2058 CPUState *cs = CPU(cpu);
2059
2060 /* test if maximum index reached */
2061 if (index & 0x80000000) {
2062 if (index > env->cpuid_xlevel) {
2063 if (env->cpuid_xlevel2 > 0) {
2064 /* Handle the Centaur's CPUID instruction. */
2065 if (index > env->cpuid_xlevel2) {
2066 index = env->cpuid_xlevel2;
2067 } else if (index < 0xC0000000) {
2068 index = env->cpuid_xlevel;
2069 }
2070 } else {
2071 /* Intel documentation states that invalid EAX input will
2072 * return the same information as EAX=cpuid_level
2073 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2074 */
2075 index = env->cpuid_level;
2076 }
2077 }
2078 } else {
2079 if (index > env->cpuid_level)
2080 index = env->cpuid_level;
2081 }
2082
2083 switch(index) {
2084 case 0:
2085 *eax = env->cpuid_level;
2086 get_cpuid_vendor(env, ebx, ecx, edx);
2087 break;
2088 case 1:
2089 *eax = env->cpuid_version;
2090 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2091 *ecx = env->features[FEAT_1_ECX];
2092 *edx = env->features[FEAT_1_EDX];
2093 if (cs->nr_cores * cs->nr_threads > 1) {
2094 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2095 *edx |= 1 << 28; /* HTT bit */
2096 }
2097 break;
2098 case 2:
2099 /* cache info: needed for Pentium Pro compatibility */
2100 if (cpu->cache_info_passthrough) {
2101 host_cpuid(index, 0, eax, ebx, ecx, edx);
2102 break;
2103 }
2104 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2105 *ebx = 0;
2106 *ecx = 0;
2107 *edx = (L1D_DESCRIPTOR << 16) | \
2108 (L1I_DESCRIPTOR << 8) | \
2109 (L2_DESCRIPTOR);
2110 break;
2111 case 4:
2112 /* cache info: needed for Core compatibility */
2113 if (cpu->cache_info_passthrough) {
2114 host_cpuid(index, count, eax, ebx, ecx, edx);
2115 *eax &= ~0xFC000000;
2116 } else {
2117 *eax = 0;
2118 switch (count) {
2119 case 0: /* L1 dcache info */
2120 *eax |= CPUID_4_TYPE_DCACHE | \
2121 CPUID_4_LEVEL(1) | \
2122 CPUID_4_SELF_INIT_LEVEL;
2123 *ebx = (L1D_LINE_SIZE - 1) | \
2124 ((L1D_PARTITIONS - 1) << 12) | \
2125 ((L1D_ASSOCIATIVITY - 1) << 22);
2126 *ecx = L1D_SETS - 1;
2127 *edx = CPUID_4_NO_INVD_SHARING;
2128 break;
2129 case 1: /* L1 icache info */
2130 *eax |= CPUID_4_TYPE_ICACHE | \
2131 CPUID_4_LEVEL(1) | \
2132 CPUID_4_SELF_INIT_LEVEL;
2133 *ebx = (L1I_LINE_SIZE - 1) | \
2134 ((L1I_PARTITIONS - 1) << 12) | \
2135 ((L1I_ASSOCIATIVITY - 1) << 22);
2136 *ecx = L1I_SETS - 1;
2137 *edx = CPUID_4_NO_INVD_SHARING;
2138 break;
2139 case 2: /* L2 cache info */
2140 *eax |= CPUID_4_TYPE_UNIFIED | \
2141 CPUID_4_LEVEL(2) | \
2142 CPUID_4_SELF_INIT_LEVEL;
2143 if (cs->nr_threads > 1) {
2144 *eax |= (cs->nr_threads - 1) << 14;
2145 }
2146 *ebx = (L2_LINE_SIZE - 1) | \
2147 ((L2_PARTITIONS - 1) << 12) | \
2148 ((L2_ASSOCIATIVITY - 1) << 22);
2149 *ecx = L2_SETS - 1;
2150 *edx = CPUID_4_NO_INVD_SHARING;
2151 break;
2152 default: /* end of info */
2153 *eax = 0;
2154 *ebx = 0;
2155 *ecx = 0;
2156 *edx = 0;
2157 break;
2158 }
2159 }
2160
2161 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2162 if ((*eax & 31) && cs->nr_cores > 1) {
2163 *eax |= (cs->nr_cores - 1) << 26;
2164 }
2165 break;
2166 case 5:
2167 /* mwait info: needed for Core compatibility */
2168 *eax = 0; /* Smallest monitor-line size in bytes */
2169 *ebx = 0; /* Largest monitor-line size in bytes */
2170 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2171 *edx = 0;
2172 break;
2173 case 6:
2174 /* Thermal and Power Leaf */
2175 *eax = 0;
2176 *ebx = 0;
2177 *ecx = 0;
2178 *edx = 0;
2179 break;
2180 case 7:
2181 /* Structured Extended Feature Flags Enumeration Leaf */
2182 if (count == 0) {
2183 *eax = 0; /* Maximum ECX value for sub-leaves */
2184 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2185 *ecx = 0; /* Reserved */
2186 *edx = 0; /* Reserved */
2187 } else {
2188 *eax = 0;
2189 *ebx = 0;
2190 *ecx = 0;
2191 *edx = 0;
2192 }
2193 break;
2194 case 9:
2195 /* Direct Cache Access Information Leaf */
2196 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2197 *ebx = 0;
2198 *ecx = 0;
2199 *edx = 0;
2200 break;
2201 case 0xA:
2202 /* Architectural Performance Monitoring Leaf */
2203 if (kvm_enabled() && cpu->enable_pmu) {
2204 KVMState *s = cs->kvm_state;
2205
2206 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2207 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2208 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2209 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2210 } else {
2211 *eax = 0;
2212 *ebx = 0;
2213 *ecx = 0;
2214 *edx = 0;
2215 }
2216 break;
2217 case 0xD: {
2218 KVMState *s = cs->kvm_state;
2219 uint64_t kvm_mask;
2220 int i;
2221
2222 /* Processor Extended State */
2223 *eax = 0;
2224 *ebx = 0;
2225 *ecx = 0;
2226 *edx = 0;
2227 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2228 break;
2229 }
2230 kvm_mask =
2231 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2232 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2233
2234 if (count == 0) {
2235 *ecx = 0x240;
2236 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2237 const ExtSaveArea *esa = &ext_save_areas[i];
2238 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2239 (kvm_mask & (1 << i)) != 0) {
2240 if (i < 32) {
2241 *eax |= 1 << i;
2242 } else {
2243 *edx |= 1 << (i - 32);
2244 }
2245 *ecx = MAX(*ecx, esa->offset + esa->size);
2246 }
2247 }
2248 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2249 *ebx = *ecx;
2250 } else if (count == 1) {
2251 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2252 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2253 const ExtSaveArea *esa = &ext_save_areas[count];
2254 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2255 (kvm_mask & (1 << count)) != 0) {
2256 *eax = esa->size;
2257 *ebx = esa->offset;
2258 }
2259 }
2260 break;
2261 }
2262 case 0x80000000:
2263 *eax = env->cpuid_xlevel;
2264 *ebx = env->cpuid_vendor1;
2265 *edx = env->cpuid_vendor2;
2266 *ecx = env->cpuid_vendor3;
2267 break;
2268 case 0x80000001:
2269 *eax = env->cpuid_version;
2270 *ebx = 0;
2271 *ecx = env->features[FEAT_8000_0001_ECX];
2272 *edx = env->features[FEAT_8000_0001_EDX];
2273
2274 /* The Linux kernel checks for the CMPLegacy bit and
2275 * discards multiple thread information if it is set.
2276 * So dont set it here for Intel to make Linux guests happy.
2277 */
2278 if (cs->nr_cores * cs->nr_threads > 1) {
2279 uint32_t tebx, tecx, tedx;
2280 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2281 if (tebx != CPUID_VENDOR_INTEL_1 ||
2282 tedx != CPUID_VENDOR_INTEL_2 ||
2283 tecx != CPUID_VENDOR_INTEL_3) {
2284 *ecx |= 1 << 1; /* CmpLegacy bit */
2285 }
2286 }
2287 break;
2288 case 0x80000002:
2289 case 0x80000003:
2290 case 0x80000004:
2291 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2292 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2293 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2294 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2295 break;
2296 case 0x80000005:
2297 /* cache info (L1 cache) */
2298 if (cpu->cache_info_passthrough) {
2299 host_cpuid(index, 0, eax, ebx, ecx, edx);
2300 break;
2301 }
2302 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2303 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2304 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2305 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2306 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2307 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2308 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2309 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2310 break;
2311 case 0x80000006:
2312 /* cache info (L2 cache) */
2313 if (cpu->cache_info_passthrough) {
2314 host_cpuid(index, 0, eax, ebx, ecx, edx);
2315 break;
2316 }
2317 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2318 (L2_DTLB_2M_ENTRIES << 16) | \
2319 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2320 (L2_ITLB_2M_ENTRIES);
2321 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2322 (L2_DTLB_4K_ENTRIES << 16) | \
2323 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2324 (L2_ITLB_4K_ENTRIES);
2325 *ecx = (L2_SIZE_KB_AMD << 16) | \
2326 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2327 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2328 *edx = ((L3_SIZE_KB/512) << 18) | \
2329 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2330 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2331 break;
2332 case 0x80000008:
2333 /* virtual & phys address size in low 2 bytes. */
2334/* XXX: This value must match the one used in the MMU code. */
2335 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2336 /* 64 bit processor */
2337/* XXX: The physical address space is limited to 42 bits in exec.c. */
2338 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2339 } else {
2340 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2341 *eax = 0x00000024; /* 36 bits physical */
2342 } else {
2343 *eax = 0x00000020; /* 32 bits physical */
2344 }
2345 }
2346 *ebx = 0;
2347 *ecx = 0;
2348 *edx = 0;
2349 if (cs->nr_cores * cs->nr_threads > 1) {
2350 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2351 }
2352 break;
2353 case 0x8000000A:
2354 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2355 *eax = 0x00000001; /* SVM Revision */
2356 *ebx = 0x00000010; /* nr of ASIDs */
2357 *ecx = 0;
2358 *edx = env->features[FEAT_SVM]; /* optional features */
2359 } else {
2360 *eax = 0;
2361 *ebx = 0;
2362 *ecx = 0;
2363 *edx = 0;
2364 }
2365 break;
2366 case 0xC0000000:
2367 *eax = env->cpuid_xlevel2;
2368 *ebx = 0;
2369 *ecx = 0;
2370 *edx = 0;
2371 break;
2372 case 0xC0000001:
2373 /* Support for VIA CPU's CPUID instruction */
2374 *eax = env->cpuid_version;
2375 *ebx = 0;
2376 *ecx = 0;
2377 *edx = env->features[FEAT_C000_0001_EDX];
2378 break;
2379 case 0xC0000002:
2380 case 0xC0000003:
2381 case 0xC0000004:
2382 /* Reserved for the future, and now filled with zero */
2383 *eax = 0;
2384 *ebx = 0;
2385 *ecx = 0;
2386 *edx = 0;
2387 break;
2388 default:
2389 /* reserved values: zero */
2390 *eax = 0;
2391 *ebx = 0;
2392 *ecx = 0;
2393 *edx = 0;
2394 break;
2395 }
2396}
2397
2398/* CPUClass::reset() */
2399static void x86_cpu_reset(CPUState *s)
2400{
2401 X86CPU *cpu = X86_CPU(s);
2402 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2403 CPUX86State *env = &cpu->env;
2404 int i;
2405
2406 xcc->parent_reset(s);
2407
2408 memset(env, 0, offsetof(CPUX86State, cpuid_level));
2409
2410 tlb_flush(s, 1);
2411
2412 env->old_exception = -1;
2413
2414 /* init to reset state */
2415
2416#ifdef CONFIG_SOFTMMU
2417 env->hflags |= HF_SOFTMMU_MASK;
2418#endif
2419 env->hflags2 |= HF2_GIF_MASK;
2420
2421 cpu_x86_update_cr0(env, 0x60000010);
2422 env->a20_mask = ~0x0;
2423 env->smbase = 0x30000;
2424
2425 env->idt.limit = 0xffff;
2426 env->gdt.limit = 0xffff;
2427 env->ldt.limit = 0xffff;
2428 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2429 env->tr.limit = 0xffff;
2430 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2431
2432 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2433 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2434 DESC_R_MASK | DESC_A_MASK);
2435 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2436 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2437 DESC_A_MASK);
2438 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2439 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2440 DESC_A_MASK);
2441 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2442 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2443 DESC_A_MASK);
2444 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2445 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2446 DESC_A_MASK);
2447 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2448 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2449 DESC_A_MASK);
2450
2451 env->eip = 0xfff0;
2452 env->regs[R_EDX] = env->cpuid_version;
2453
2454 env->eflags = 0x2;
2455
2456 /* FPU init */
2457 for (i = 0; i < 8; i++) {
2458 env->fptags[i] = 1;
2459 }
2460 env->fpuc = 0x37f;
2461
2462 env->mxcsr = 0x1f80;
2463 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2464
2465 env->pat = 0x0007040600070406ULL;
2466 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2467
2468 memset(env->dr, 0, sizeof(env->dr));
2469 env->dr[6] = DR6_FIXED_1;
2470 env->dr[7] = DR7_FIXED_1;
2471 cpu_breakpoint_remove_all(s, BP_CPU);
2472 cpu_watchpoint_remove_all(s, BP_CPU);
2473
2474 env->xcr0 = 1;
2475
2476#if !defined(CONFIG_USER_ONLY)
2477 /* We hard-wire the BSP to the first CPU. */
2478 if (s->cpu_index == 0) {
2479 apic_designate_bsp(cpu->apic_state);
2480 }
2481
2482 s->halted = !cpu_is_bsp(cpu);
2483
2484 if (kvm_enabled()) {
2485 kvm_arch_reset_vcpu(cpu);
2486 }
2487#endif
2488}
2489
2490#ifndef CONFIG_USER_ONLY
2491bool cpu_is_bsp(X86CPU *cpu)
2492{
2493 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2494}
2495
2496/* TODO: remove me, when reset over QOM tree is implemented */
2497static void x86_cpu_machine_reset_cb(void *opaque)
2498{
2499 X86CPU *cpu = opaque;
2500 cpu_reset(CPU(cpu));
2501}
2502#endif
2503
2504static void mce_init(X86CPU *cpu)
2505{
2506 CPUX86State *cenv = &cpu->env;
2507 unsigned int bank;
2508
2509 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2510 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2511 (CPUID_MCE | CPUID_MCA)) {
2512 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2513 cenv->mcg_ctl = ~(uint64_t)0;
2514 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2515 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2516 }
2517 }
2518}
2519
2520#ifndef CONFIG_USER_ONLY
2521static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2522{
2523 CPUX86State *env = &cpu->env;
2524 DeviceState *dev = DEVICE(cpu);
2525 APICCommonState *apic;
2526 const char *apic_type = "apic";
2527
2528 if (kvm_irqchip_in_kernel()) {
2529 apic_type = "kvm-apic";
2530 } else if (xen_enabled()) {
2531 apic_type = "xen-apic";
2532 }
2533
2534 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2535 if (cpu->apic_state == NULL) {
2536 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2537 return;
2538 }
2539
2540 object_property_add_child(OBJECT(cpu), "apic",
2541 OBJECT(cpu->apic_state), NULL);
2542 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2543 /* TODO: convert to link<> */
2544 apic = APIC_COMMON(cpu->apic_state);
2545 apic->cpu = cpu;
2546}
2547
2548static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2549{
2550 if (cpu->apic_state == NULL) {
2551 return;
2552 }
2553
2554 if (qdev_init(cpu->apic_state)) {
2555 error_setg(errp, "APIC device '%s' could not be initialized",
2556 object_get_typename(OBJECT(cpu->apic_state)));
2557 return;
2558 }
2559}
2560#else
2561static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2562{
2563}
2564#endif
2565
2566static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2567{
2568 CPUState *cs = CPU(dev);
2569 X86CPU *cpu = X86_CPU(dev);
2570 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2571 CPUX86State *env = &cpu->env;
2572 Error *local_err = NULL;
2573
2574 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2575 env->cpuid_level = 7;
2576 }
2577
2578 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2579 * CPUID[1].EDX.
2580 */
2581 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2582 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2583 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2584 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2585 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2586 & CPUID_EXT2_AMD_ALIASES);
2587 }
2588
2589 if (!kvm_enabled()) {
2590 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2591 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2592 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2593#ifdef TARGET_X86_64
2594 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2595#endif
2596 );
2597 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2598 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2599 } else {
2600 if (filter_features_for_kvm(cpu) && cpu->enforce_cpuid) {
2601 error_setg(&local_err,
2602 "Host's CPU doesn't support requested features");
2603 goto out;
2604 }
2605 }
2606
2607#ifndef CONFIG_USER_ONLY
2608 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2609
2610 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2611 x86_cpu_apic_create(cpu, &local_err);
2612 if (local_err != NULL) {
2613 goto out;
2614 }
2615 }
2616#endif
2617
2618 mce_init(cpu);
2619 qemu_init_vcpu(cs);
2620
2621 x86_cpu_apic_realize(cpu, &local_err);
2622 if (local_err != NULL) {
2623 goto out;
2624 }
2625 cpu_reset(cs);
2626
2627 xcc->parent_realize(dev, &local_err);
2628out:
2629 if (local_err != NULL) {
2630 error_propagate(errp, local_err);
2631 return;
2632 }
2633}
2634
2635/* Enables contiguous-apic-ID mode, for compatibility */
2636static bool compat_apic_id_mode;
2637
2638void enable_compat_apic_id_mode(void)
2639{
2640 compat_apic_id_mode = true;
2641}
2642
2643/* Calculates initial APIC ID for a specific CPU index
2644 *
2645 * Currently we need to be able to calculate the APIC ID from the CPU index
2646 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2647 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2648 * all CPUs up to max_cpus.
2649 */
2650uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2651{
2652 uint32_t correct_id;
2653 static bool warned;
2654
2655 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2656 if (compat_apic_id_mode) {
2657 if (cpu_index != correct_id && !warned) {
2658 error_report("APIC IDs set in compatibility mode, "
2659 "CPU topology won't match the configuration");
2660 warned = true;
2661 }
2662 return cpu_index;
2663 } else {
2664 return correct_id;
2665 }
2666}
2667
2668static void x86_cpu_initfn(Object *obj)
2669{
2670 CPUState *cs = CPU(obj);
2671 X86CPU *cpu = X86_CPU(obj);
2672 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2673 CPUX86State *env = &cpu->env;
2674 static int inited;
2675
2676 cs->env_ptr = env;
2677 cpu_exec_init(env);
2678
2679 object_property_add(obj, "family", "int",
2680 x86_cpuid_version_get_family,
2681 x86_cpuid_version_set_family, NULL, NULL, NULL);
2682 object_property_add(obj, "model", "int",
2683 x86_cpuid_version_get_model,
2684 x86_cpuid_version_set_model, NULL, NULL, NULL);
2685 object_property_add(obj, "stepping", "int",
2686 x86_cpuid_version_get_stepping,
2687 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2688 object_property_add(obj, "level", "int",
2689 x86_cpuid_get_level,
2690 x86_cpuid_set_level, NULL, NULL, NULL);
2691 object_property_add(obj, "xlevel", "int",
2692 x86_cpuid_get_xlevel,
2693 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2694 object_property_add_str(obj, "vendor",
2695 x86_cpuid_get_vendor,
2696 x86_cpuid_set_vendor, NULL);
2697 object_property_add_str(obj, "model-id",
2698 x86_cpuid_get_model_id,
2699 x86_cpuid_set_model_id, NULL);
2700 object_property_add(obj, "tsc-frequency", "int",
2701 x86_cpuid_get_tsc_freq,
2702 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2703 object_property_add(obj, "apic-id", "int",
2704 x86_cpuid_get_apic_id,
2705 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2706 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2707 x86_cpu_get_feature_words,
2708 NULL, NULL, (void *)env->features, NULL);
2709 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2710 x86_cpu_get_feature_words,
2711 NULL, NULL, (void *)cpu->filtered_features, NULL);
2712
2713 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2714 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2715
2716 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2717
2718 /* init various static tables used in TCG mode */
2719 if (tcg_enabled() && !inited) {
2720 inited = 1;
2721 optimize_flags_init();
2722#ifndef CONFIG_USER_ONLY
2723 cpu_set_debug_excp_handler(breakpoint_handler);
2724#endif
2725 }
2726}
2727
2728static int64_t x86_cpu_get_arch_id(CPUState *cs)
2729{
2730 X86CPU *cpu = X86_CPU(cs);
2731 CPUX86State *env = &cpu->env;
2732
2733 return env->cpuid_apic_id;
2734}
2735
2736static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2737{
2738 X86CPU *cpu = X86_CPU(cs);
2739
2740 return cpu->env.cr[0] & CR0_PG_MASK;
2741}
2742
2743static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2744{
2745 X86CPU *cpu = X86_CPU(cs);
2746
2747 cpu->env.eip = value;
2748}
2749
2750static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2751{
2752 X86CPU *cpu = X86_CPU(cs);
2753
2754 cpu->env.eip = tb->pc - tb->cs_base;
2755}
2756
2757static bool x86_cpu_has_work(CPUState *cs)
2758{
2759 X86CPU *cpu = X86_CPU(cs);
2760 CPUX86State *env = &cpu->env;
2761
2762 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2763 CPU_INTERRUPT_POLL)) &&
2764 (env->eflags & IF_MASK)) ||
2765 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2766 CPU_INTERRUPT_INIT |
2767 CPU_INTERRUPT_SIPI |
2768 CPU_INTERRUPT_MCE));
2769}
2770
2771static Property x86_cpu_properties[] = {
2772 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2773 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2774 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2775 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2776 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2777 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2778 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2779 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
2780 DEFINE_PROP_END_OF_LIST()
2781};
2782
2783static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2784{
2785 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2786 CPUClass *cc = CPU_CLASS(oc);
2787 DeviceClass *dc = DEVICE_CLASS(oc);
2788
2789 xcc->parent_realize = dc->realize;
2790 dc->realize = x86_cpu_realizefn;
2791 dc->bus_type = TYPE_ICC_BUS;
2792 dc->props = x86_cpu_properties;
2793
2794 xcc->parent_reset = cc->reset;
2795 cc->reset = x86_cpu_reset;
2796 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2797
2798 cc->class_by_name = x86_cpu_class_by_name;
2799 cc->parse_features = x86_cpu_parse_featurestr;
2800 cc->has_work = x86_cpu_has_work;
2801 cc->do_interrupt = x86_cpu_do_interrupt;
2802 cc->dump_state = x86_cpu_dump_state;
2803 cc->set_pc = x86_cpu_set_pc;
2804 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2805 cc->gdb_read_register = x86_cpu_gdb_read_register;
2806 cc->gdb_write_register = x86_cpu_gdb_write_register;
2807 cc->get_arch_id = x86_cpu_get_arch_id;
2808 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2809#ifdef CONFIG_USER_ONLY
2810 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2811#else
2812 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2813 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2814 cc->write_elf64_note = x86_cpu_write_elf64_note;
2815 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2816 cc->write_elf32_note = x86_cpu_write_elf32_note;
2817 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2818 cc->vmsd = &vmstate_x86_cpu;
2819#endif
2820 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2821}
2822
2823static const TypeInfo x86_cpu_type_info = {
2824 .name = TYPE_X86_CPU,
2825 .parent = TYPE_CPU,
2826 .instance_size = sizeof(X86CPU),
2827 .instance_init = x86_cpu_initfn,
2828 .abstract = true,
2829 .class_size = sizeof(X86CPUClass),
2830 .class_init = x86_cpu_common_class_init,
2831};
2832
2833static void x86_cpu_register_types(void)
2834{
2835 int i;
2836
2837 type_register_static(&x86_cpu_type_info);
2838 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2839 x86_register_cpudef_type(&builtin_x86_defs[i]);
2840 }
2841#ifdef CONFIG_KVM
2842 type_register_static(&host_x86_cpu_type_info);
2843#endif
2844}
2845
2846type_init(x86_cpu_register_types)
QEMU mirror