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target-i386: Define TCG_*_FEATURES earlier in cpu.c
[mirror_qemu.git] / target-i386 / cpu.c
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1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "sysemu/kvm.h"
26#include "sysemu/cpus.h"
27#include "kvm_i386.h"
28#include "topology.h"
29
30#include "qemu/option.h"
31#include "qemu/config-file.h"
32#include "qapi/qmp/qerror.h"
33
34#include "qapi-types.h"
35#include "qapi-visit.h"
36#include "qapi/visitor.h"
37#include "sysemu/arch_init.h"
38
39#include "hw/hw.h"
40#if defined(CONFIG_KVM)
41#include <linux/kvm_para.h>
42#endif
43
44#include "sysemu/sysemu.h"
45#include "hw/qdev-properties.h"
46#include "hw/cpu/icc_bus.h"
47#ifndef CONFIG_USER_ONLY
48#include "hw/xen/xen.h"
49#include "hw/i386/apic_internal.h"
50#endif
51
52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
192 "ds_cpl", "vmx", "smx", "est",
193 "tm2", "ssse3", "cid", NULL,
194 "fma", "cx16", "xtpr", "pdcm",
195 NULL, "pcid", "dca", "sse4.1|sse4_1",
196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
197 "tsc-deadline", "aes", "xsave", "osxsave",
198 "avx", "f16c", "rdrand", "hypervisor",
199};
200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
205static const char *ext2_feature_name[] = {
206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
213 NULL, "lm|i64", "3dnowext", "3dnow",
214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
218 "3dnowprefetch", "osvw", "ibs", "xop",
219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
223 NULL, NULL, NULL, NULL,
224};
225
226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
237static const char *kvm_feature_name[] = {
238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
246};
247
248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
259static const char *cpuid_7_0_ebx_feature_name[] = {
260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
266#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
267#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
268 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
269#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
270 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
271 CPUID_PSE36 | CPUID_FXSR)
272#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
273#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
274 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
275 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
276 CPUID_PAE | CPUID_SEP | CPUID_APIC)
277
278#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
279 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
280 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
281 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
282 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
283 /* partly implemented:
284 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
285 /* missing:
286 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
287#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
288 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
289 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
290 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
291 /* missing:
292 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
293 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
294 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
295 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
296 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
297 CPUID_EXT_RDRAND */
298
299#ifdef TARGET_X86_64
300#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
301#else
302#define TCG_EXT2_X86_64_FEATURES 0
303#endif
304
305#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
306 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
307 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
308 TCG_EXT2_X86_64_FEATURES)
309#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
310 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
311#define TCG_EXT4_FEATURES 0
312#define TCG_SVM_FEATURES 0
313#define TCG_KVM_FEATURES 0
314#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
315 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
316 /* missing:
317 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
318 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
319 CPUID_7_0_EBX_RDSEED */
320
321
322typedef struct FeatureWordInfo {
323 const char **feat_names;
324 uint32_t cpuid_eax; /* Input EAX for CPUID */
325 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
326 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
327 int cpuid_reg; /* output register (R_* constant) */
328} FeatureWordInfo;
329
330static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
331 [FEAT_1_EDX] = {
332 .feat_names = feature_name,
333 .cpuid_eax = 1, .cpuid_reg = R_EDX,
334 },
335 [FEAT_1_ECX] = {
336 .feat_names = ext_feature_name,
337 .cpuid_eax = 1, .cpuid_reg = R_ECX,
338 },
339 [FEAT_8000_0001_EDX] = {
340 .feat_names = ext2_feature_name,
341 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
342 },
343 [FEAT_8000_0001_ECX] = {
344 .feat_names = ext3_feature_name,
345 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
346 },
347 [FEAT_C000_0001_EDX] = {
348 .feat_names = ext4_feature_name,
349 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
350 },
351 [FEAT_KVM] = {
352 .feat_names = kvm_feature_name,
353 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
354 },
355 [FEAT_SVM] = {
356 .feat_names = svm_feature_name,
357 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
358 },
359 [FEAT_7_0_EBX] = {
360 .feat_names = cpuid_7_0_ebx_feature_name,
361 .cpuid_eax = 7,
362 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
363 .cpuid_reg = R_EBX,
364 },
365};
366
367typedef struct X86RegisterInfo32 {
368 /* Name of register */
369 const char *name;
370 /* QAPI enum value register */
371 X86CPURegister32 qapi_enum;
372} X86RegisterInfo32;
373
374#define REGISTER(reg) \
375 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
376static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
377 REGISTER(EAX),
378 REGISTER(ECX),
379 REGISTER(EDX),
380 REGISTER(EBX),
381 REGISTER(ESP),
382 REGISTER(EBP),
383 REGISTER(ESI),
384 REGISTER(EDI),
385};
386#undef REGISTER
387
388typedef struct ExtSaveArea {
389 uint32_t feature, bits;
390 uint32_t offset, size;
391} ExtSaveArea;
392
393static const ExtSaveArea ext_save_areas[] = {
394 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
395 .offset = 0x240, .size = 0x100 },
396 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
397 .offset = 0x3c0, .size = 0x40 },
398 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
399 .offset = 0x400, .size = 0x40 },
400};
401
402const char *get_register_name_32(unsigned int reg)
403{
404 if (reg >= CPU_NB_REGS32) {
405 return NULL;
406 }
407 return x86_reg_info_32[reg].name;
408}
409
410/* collects per-function cpuid data
411 */
412typedef struct model_features_t {
413 uint32_t *guest_feat;
414 uint32_t *host_feat;
415 FeatureWord feat_word;
416} model_features_t;
417
418/* KVM-specific features that are automatically added to all CPU models
419 * when KVM is enabled.
420 */
421static uint32_t kvm_default_features[FEATURE_WORDS] = {
422 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
423 (1 << KVM_FEATURE_NOP_IO_DELAY) |
424 (1 << KVM_FEATURE_CLOCKSOURCE2) |
425 (1 << KVM_FEATURE_ASYNC_PF) |
426 (1 << KVM_FEATURE_STEAL_TIME) |
427 (1 << KVM_FEATURE_PV_EOI) |
428 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
429 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
430};
431
432/* Features that are not added by default to any CPU model when KVM is enabled.
433 */
434static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
435 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
436};
437
438void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
439{
440 kvm_default_features[w] &= ~features;
441}
442
443void host_cpuid(uint32_t function, uint32_t count,
444 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
445{
446 uint32_t vec[4];
447
448#ifdef __x86_64__
449 asm volatile("cpuid"
450 : "=a"(vec[0]), "=b"(vec[1]),
451 "=c"(vec[2]), "=d"(vec[3])
452 : "0"(function), "c"(count) : "cc");
453#elif defined(__i386__)
454 asm volatile("pusha \n\t"
455 "cpuid \n\t"
456 "mov %%eax, 0(%2) \n\t"
457 "mov %%ebx, 4(%2) \n\t"
458 "mov %%ecx, 8(%2) \n\t"
459 "mov %%edx, 12(%2) \n\t"
460 "popa"
461 : : "a"(function), "c"(count), "S"(vec)
462 : "memory", "cc");
463#else
464 abort();
465#endif
466
467 if (eax)
468 *eax = vec[0];
469 if (ebx)
470 *ebx = vec[1];
471 if (ecx)
472 *ecx = vec[2];
473 if (edx)
474 *edx = vec[3];
475}
476
477#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
478
479/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
480 * a substring. ex if !NULL points to the first char after a substring,
481 * otherwise the string is assumed to sized by a terminating nul.
482 * Return lexical ordering of *s1:*s2.
483 */
484static int sstrcmp(const char *s1, const char *e1, const char *s2,
485 const char *e2)
486{
487 for (;;) {
488 if (!*s1 || !*s2 || *s1 != *s2)
489 return (*s1 - *s2);
490 ++s1, ++s2;
491 if (s1 == e1 && s2 == e2)
492 return (0);
493 else if (s1 == e1)
494 return (*s2);
495 else if (s2 == e2)
496 return (*s1);
497 }
498}
499
500/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
501 * '|' delimited (possibly empty) strings in which case search for a match
502 * within the alternatives proceeds left to right. Return 0 for success,
503 * non-zero otherwise.
504 */
505static int altcmp(const char *s, const char *e, const char *altstr)
506{
507 const char *p, *q;
508
509 for (q = p = altstr; ; ) {
510 while (*p && *p != '|')
511 ++p;
512 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
513 return (0);
514 if (!*p)
515 return (1);
516 else
517 q = ++p;
518 }
519}
520
521/* search featureset for flag *[s..e), if found set corresponding bit in
522 * *pval and return true, otherwise return false
523 */
524static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
525 const char **featureset)
526{
527 uint32_t mask;
528 const char **ppc;
529 bool found = false;
530
531 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
532 if (*ppc && !altcmp(s, e, *ppc)) {
533 *pval |= mask;
534 found = true;
535 }
536 }
537 return found;
538}
539
540static void add_flagname_to_bitmaps(const char *flagname,
541 FeatureWordArray words)
542{
543 FeatureWord w;
544 for (w = 0; w < FEATURE_WORDS; w++) {
545 FeatureWordInfo *wi = &feature_word_info[w];
546 if (wi->feat_names &&
547 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
548 break;
549 }
550 }
551 if (w == FEATURE_WORDS) {
552 fprintf(stderr, "CPU feature %s not found\n", flagname);
553 }
554}
555
556/* CPU class name definitions: */
557
558#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
559#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
560
561/* Return type name for a given CPU model name
562 * Caller is responsible for freeing the returned string.
563 */
564static char *x86_cpu_type_name(const char *model_name)
565{
566 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
567}
568
569static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
570{
571 ObjectClass *oc;
572 char *typename;
573
574 if (cpu_model == NULL) {
575 return NULL;
576 }
577
578 typename = x86_cpu_type_name(cpu_model);
579 oc = object_class_by_name(typename);
580 g_free(typename);
581 return oc;
582}
583
584struct X86CPUDefinition {
585 const char *name;
586 uint32_t level;
587 uint32_t xlevel;
588 uint32_t xlevel2;
589 /* vendor is zero-terminated, 12 character ASCII string */
590 char vendor[CPUID_VENDOR_SZ + 1];
591 int family;
592 int model;
593 int stepping;
594 FeatureWordArray features;
595 char model_id[48];
596 bool cache_info_passthrough;
597};
598
599static X86CPUDefinition builtin_x86_defs[] = {
600 {
601 .name = "qemu64",
602 .level = 4,
603 .vendor = CPUID_VENDOR_AMD,
604 .family = 6,
605 .model = 6,
606 .stepping = 3,
607 .features[FEAT_1_EDX] =
608 PPRO_FEATURES |
609 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
610 CPUID_PSE36,
611 .features[FEAT_1_ECX] =
612 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
613 .features[FEAT_8000_0001_EDX] =
614 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
615 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
616 .features[FEAT_8000_0001_ECX] =
617 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
618 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
619 .xlevel = 0x8000000A,
620 },
621 {
622 .name = "phenom",
623 .level = 5,
624 .vendor = CPUID_VENDOR_AMD,
625 .family = 16,
626 .model = 2,
627 .stepping = 3,
628 .features[FEAT_1_EDX] =
629 PPRO_FEATURES |
630 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
631 CPUID_PSE36 | CPUID_VME | CPUID_HT,
632 .features[FEAT_1_ECX] =
633 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
634 CPUID_EXT_POPCNT,
635 .features[FEAT_8000_0001_EDX] =
636 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
637 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
638 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
639 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
640 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
641 CPUID_EXT3_CR8LEG,
642 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
643 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
644 .features[FEAT_8000_0001_ECX] =
645 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
646 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
647 .features[FEAT_SVM] =
648 CPUID_SVM_NPT | CPUID_SVM_LBRV,
649 .xlevel = 0x8000001A,
650 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
651 },
652 {
653 .name = "core2duo",
654 .level = 10,
655 .vendor = CPUID_VENDOR_INTEL,
656 .family = 6,
657 .model = 15,
658 .stepping = 11,
659 .features[FEAT_1_EDX] =
660 PPRO_FEATURES |
661 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
662 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
663 CPUID_HT | CPUID_TM | CPUID_PBE,
664 .features[FEAT_1_ECX] =
665 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
666 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
667 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
668 .features[FEAT_8000_0001_EDX] =
669 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
670 .features[FEAT_8000_0001_ECX] =
671 CPUID_EXT3_LAHF_LM,
672 .xlevel = 0x80000008,
673 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
674 },
675 {
676 .name = "kvm64",
677 .level = 5,
678 .vendor = CPUID_VENDOR_INTEL,
679 .family = 15,
680 .model = 6,
681 .stepping = 1,
682 /* Missing: CPUID_VME, CPUID_HT */
683 .features[FEAT_1_EDX] =
684 PPRO_FEATURES |
685 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
686 CPUID_PSE36,
687 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
688 .features[FEAT_1_ECX] =
689 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
690 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
691 .features[FEAT_8000_0001_EDX] =
692 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
693 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
694 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
695 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
696 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
697 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
698 .features[FEAT_8000_0001_ECX] =
699 0,
700 .xlevel = 0x80000008,
701 .model_id = "Common KVM processor"
702 },
703 {
704 .name = "qemu32",
705 .level = 4,
706 .vendor = CPUID_VENDOR_INTEL,
707 .family = 6,
708 .model = 6,
709 .stepping = 3,
710 .features[FEAT_1_EDX] =
711 PPRO_FEATURES,
712 .features[FEAT_1_ECX] =
713 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
714 .xlevel = 0x80000004,
715 },
716 {
717 .name = "kvm32",
718 .level = 5,
719 .vendor = CPUID_VENDOR_INTEL,
720 .family = 15,
721 .model = 6,
722 .stepping = 1,
723 .features[FEAT_1_EDX] =
724 PPRO_FEATURES |
725 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
726 .features[FEAT_1_ECX] =
727 CPUID_EXT_SSE3,
728 .features[FEAT_8000_0001_EDX] =
729 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
730 .features[FEAT_8000_0001_ECX] =
731 0,
732 .xlevel = 0x80000008,
733 .model_id = "Common 32-bit KVM processor"
734 },
735 {
736 .name = "coreduo",
737 .level = 10,
738 .vendor = CPUID_VENDOR_INTEL,
739 .family = 6,
740 .model = 14,
741 .stepping = 8,
742 .features[FEAT_1_EDX] =
743 PPRO_FEATURES | CPUID_VME |
744 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
745 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
746 .features[FEAT_1_ECX] =
747 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
748 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
749 .features[FEAT_8000_0001_EDX] =
750 CPUID_EXT2_NX,
751 .xlevel = 0x80000008,
752 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
753 },
754 {
755 .name = "486",
756 .level = 1,
757 .vendor = CPUID_VENDOR_INTEL,
758 .family = 4,
759 .model = 8,
760 .stepping = 0,
761 .features[FEAT_1_EDX] =
762 I486_FEATURES,
763 .xlevel = 0,
764 },
765 {
766 .name = "pentium",
767 .level = 1,
768 .vendor = CPUID_VENDOR_INTEL,
769 .family = 5,
770 .model = 4,
771 .stepping = 3,
772 .features[FEAT_1_EDX] =
773 PENTIUM_FEATURES,
774 .xlevel = 0,
775 },
776 {
777 .name = "pentium2",
778 .level = 2,
779 .vendor = CPUID_VENDOR_INTEL,
780 .family = 6,
781 .model = 5,
782 .stepping = 2,
783 .features[FEAT_1_EDX] =
784 PENTIUM2_FEATURES,
785 .xlevel = 0,
786 },
787 {
788 .name = "pentium3",
789 .level = 2,
790 .vendor = CPUID_VENDOR_INTEL,
791 .family = 6,
792 .model = 7,
793 .stepping = 3,
794 .features[FEAT_1_EDX] =
795 PENTIUM3_FEATURES,
796 .xlevel = 0,
797 },
798 {
799 .name = "athlon",
800 .level = 2,
801 .vendor = CPUID_VENDOR_AMD,
802 .family = 6,
803 .model = 2,
804 .stepping = 3,
805 .features[FEAT_1_EDX] =
806 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
807 CPUID_MCA,
808 .features[FEAT_8000_0001_EDX] =
809 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
810 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
811 .xlevel = 0x80000008,
812 },
813 {
814 .name = "n270",
815 /* original is on level 10 */
816 .level = 5,
817 .vendor = CPUID_VENDOR_INTEL,
818 .family = 6,
819 .model = 28,
820 .stepping = 2,
821 .features[FEAT_1_EDX] =
822 PPRO_FEATURES |
823 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
824 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
825 /* Some CPUs got no CPUID_SEP */
826 .features[FEAT_1_ECX] =
827 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
828 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
829 CPUID_EXT_MOVBE,
830 .features[FEAT_8000_0001_EDX] =
831 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
832 CPUID_EXT2_NX,
833 .features[FEAT_8000_0001_ECX] =
834 CPUID_EXT3_LAHF_LM,
835 .xlevel = 0x8000000A,
836 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
837 },
838 {
839 .name = "Conroe",
840 .level = 4,
841 .vendor = CPUID_VENDOR_INTEL,
842 .family = 6,
843 .model = 15,
844 .stepping = 3,
845 .features[FEAT_1_EDX] =
846 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
847 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
848 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
849 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
850 CPUID_DE | CPUID_FP87,
851 .features[FEAT_1_ECX] =
852 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
853 .features[FEAT_8000_0001_EDX] =
854 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
855 .features[FEAT_8000_0001_ECX] =
856 CPUID_EXT3_LAHF_LM,
857 .xlevel = 0x8000000A,
858 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
859 },
860 {
861 .name = "Penryn",
862 .level = 4,
863 .vendor = CPUID_VENDOR_INTEL,
864 .family = 6,
865 .model = 23,
866 .stepping = 3,
867 .features[FEAT_1_EDX] =
868 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
869 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
870 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
871 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
872 CPUID_DE | CPUID_FP87,
873 .features[FEAT_1_ECX] =
874 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
875 CPUID_EXT_SSE3,
876 .features[FEAT_8000_0001_EDX] =
877 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
878 .features[FEAT_8000_0001_ECX] =
879 CPUID_EXT3_LAHF_LM,
880 .xlevel = 0x8000000A,
881 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
882 },
883 {
884 .name = "Nehalem",
885 .level = 4,
886 .vendor = CPUID_VENDOR_INTEL,
887 .family = 6,
888 .model = 26,
889 .stepping = 3,
890 .features[FEAT_1_EDX] =
891 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
892 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
893 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
894 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
895 CPUID_DE | CPUID_FP87,
896 .features[FEAT_1_ECX] =
897 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
898 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
899 .features[FEAT_8000_0001_EDX] =
900 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
901 .features[FEAT_8000_0001_ECX] =
902 CPUID_EXT3_LAHF_LM,
903 .xlevel = 0x8000000A,
904 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
905 },
906 {
907 .name = "Westmere",
908 .level = 11,
909 .vendor = CPUID_VENDOR_INTEL,
910 .family = 6,
911 .model = 44,
912 .stepping = 1,
913 .features[FEAT_1_EDX] =
914 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
915 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
916 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
917 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
918 CPUID_DE | CPUID_FP87,
919 .features[FEAT_1_ECX] =
920 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
921 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
922 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
923 .features[FEAT_8000_0001_EDX] =
924 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
925 .features[FEAT_8000_0001_ECX] =
926 CPUID_EXT3_LAHF_LM,
927 .xlevel = 0x8000000A,
928 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
929 },
930 {
931 .name = "SandyBridge",
932 .level = 0xd,
933 .vendor = CPUID_VENDOR_INTEL,
934 .family = 6,
935 .model = 42,
936 .stepping = 1,
937 .features[FEAT_1_EDX] =
938 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
939 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
940 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
941 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
942 CPUID_DE | CPUID_FP87,
943 .features[FEAT_1_ECX] =
944 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
945 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
946 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
947 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
948 CPUID_EXT_SSE3,
949 .features[FEAT_8000_0001_EDX] =
950 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
951 CPUID_EXT2_SYSCALL,
952 .features[FEAT_8000_0001_ECX] =
953 CPUID_EXT3_LAHF_LM,
954 .xlevel = 0x8000000A,
955 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
956 },
957 {
958 .name = "Haswell",
959 .level = 0xd,
960 .vendor = CPUID_VENDOR_INTEL,
961 .family = 6,
962 .model = 60,
963 .stepping = 1,
964 .features[FEAT_1_EDX] =
965 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
966 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
967 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
968 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
969 CPUID_DE | CPUID_FP87,
970 .features[FEAT_1_ECX] =
971 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
972 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
973 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
974 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
975 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
976 CPUID_EXT_PCID,
977 .features[FEAT_8000_0001_EDX] =
978 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
979 CPUID_EXT2_SYSCALL,
980 .features[FEAT_8000_0001_ECX] =
981 CPUID_EXT3_LAHF_LM,
982 .features[FEAT_7_0_EBX] =
983 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
984 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
985 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
986 CPUID_7_0_EBX_RTM,
987 .xlevel = 0x8000000A,
988 .model_id = "Intel Core Processor (Haswell)",
989 },
990 {
991 .name = "Opteron_G1",
992 .level = 5,
993 .vendor = CPUID_VENDOR_AMD,
994 .family = 15,
995 .model = 6,
996 .stepping = 1,
997 .features[FEAT_1_EDX] =
998 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
999 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1000 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1001 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1002 CPUID_DE | CPUID_FP87,
1003 .features[FEAT_1_ECX] =
1004 CPUID_EXT_SSE3,
1005 .features[FEAT_8000_0001_EDX] =
1006 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1007 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1008 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1009 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1010 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1011 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1012 .xlevel = 0x80000008,
1013 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1014 },
1015 {
1016 .name = "Opteron_G2",
1017 .level = 5,
1018 .vendor = CPUID_VENDOR_AMD,
1019 .family = 15,
1020 .model = 6,
1021 .stepping = 1,
1022 .features[FEAT_1_EDX] =
1023 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1024 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1025 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1026 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1027 CPUID_DE | CPUID_FP87,
1028 .features[FEAT_1_ECX] =
1029 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1030 .features[FEAT_8000_0001_EDX] =
1031 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1032 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1033 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1034 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1035 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1036 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1037 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1038 .features[FEAT_8000_0001_ECX] =
1039 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1040 .xlevel = 0x80000008,
1041 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1042 },
1043 {
1044 .name = "Opteron_G3",
1045 .level = 5,
1046 .vendor = CPUID_VENDOR_AMD,
1047 .family = 15,
1048 .model = 6,
1049 .stepping = 1,
1050 .features[FEAT_1_EDX] =
1051 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1052 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1053 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1054 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1055 CPUID_DE | CPUID_FP87,
1056 .features[FEAT_1_ECX] =
1057 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1058 CPUID_EXT_SSE3,
1059 .features[FEAT_8000_0001_EDX] =
1060 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1061 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1062 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1063 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1064 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1065 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1066 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1067 .features[FEAT_8000_0001_ECX] =
1068 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1069 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1070 .xlevel = 0x80000008,
1071 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1072 },
1073 {
1074 .name = "Opteron_G4",
1075 .level = 0xd,
1076 .vendor = CPUID_VENDOR_AMD,
1077 .family = 21,
1078 .model = 1,
1079 .stepping = 2,
1080 .features[FEAT_1_EDX] =
1081 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1082 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1083 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1084 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1085 CPUID_DE | CPUID_FP87,
1086 .features[FEAT_1_ECX] =
1087 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1088 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1089 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1090 CPUID_EXT_SSE3,
1091 .features[FEAT_8000_0001_EDX] =
1092 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1093 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1094 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1095 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1096 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1097 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1098 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1099 .features[FEAT_8000_0001_ECX] =
1100 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1101 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1102 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1103 CPUID_EXT3_LAHF_LM,
1104 .xlevel = 0x8000001A,
1105 .model_id = "AMD Opteron 62xx class CPU",
1106 },
1107 {
1108 .name = "Opteron_G5",
1109 .level = 0xd,
1110 .vendor = CPUID_VENDOR_AMD,
1111 .family = 21,
1112 .model = 2,
1113 .stepping = 0,
1114 .features[FEAT_1_EDX] =
1115 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1116 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1117 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1118 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1119 CPUID_DE | CPUID_FP87,
1120 .features[FEAT_1_ECX] =
1121 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1122 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1123 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1124 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1125 .features[FEAT_8000_0001_EDX] =
1126 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1127 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1128 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1129 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1130 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1131 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1132 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1133 .features[FEAT_8000_0001_ECX] =
1134 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1135 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1136 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1137 CPUID_EXT3_LAHF_LM,
1138 .xlevel = 0x8000001A,
1139 .model_id = "AMD Opteron 63xx class CPU",
1140 },
1141};
1142
1143/**
1144 * x86_cpu_compat_set_features:
1145 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1146 * @w: Identifies the feature word to be changed.
1147 * @feat_add: Feature bits to be added to feature word
1148 * @feat_remove: Feature bits to be removed from feature word
1149 *
1150 * Change CPU model feature bits for compatibility.
1151 *
1152 * This function may be used by machine-type compatibility functions
1153 * to enable or disable feature bits on specific CPU models.
1154 */
1155void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1156 uint32_t feat_add, uint32_t feat_remove)
1157{
1158 X86CPUDefinition *def;
1159 int i;
1160 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1161 def = &builtin_x86_defs[i];
1162 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1163 def->features[w] |= feat_add;
1164 def->features[w] &= ~feat_remove;
1165 }
1166 }
1167}
1168
1169#ifdef CONFIG_KVM
1170
1171static int cpu_x86_fill_model_id(char *str)
1172{
1173 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1174 int i;
1175
1176 for (i = 0; i < 3; i++) {
1177 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1178 memcpy(str + i * 16 + 0, &eax, 4);
1179 memcpy(str + i * 16 + 4, &ebx, 4);
1180 memcpy(str + i * 16 + 8, &ecx, 4);
1181 memcpy(str + i * 16 + 12, &edx, 4);
1182 }
1183 return 0;
1184}
1185
1186static X86CPUDefinition host_cpudef;
1187
1188/* class_init for the "host" CPU model
1189 *
1190 * This function may be called before KVM is initialized.
1191 */
1192static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1193{
1194 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1195 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1196
1197 xcc->kvm_required = true;
1198
1199 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1200 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1201
1202 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1203 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1204 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1205 host_cpudef.stepping = eax & 0x0F;
1206
1207 cpu_x86_fill_model_id(host_cpudef.model_id);
1208
1209 xcc->cpu_def = &host_cpudef;
1210 host_cpudef.cache_info_passthrough = true;
1211
1212 /* level, xlevel, xlevel2, and the feature words are initialized on
1213 * instance_init, because they require KVM to be initialized.
1214 */
1215}
1216
1217static void host_x86_cpu_initfn(Object *obj)
1218{
1219 X86CPU *cpu = X86_CPU(obj);
1220 CPUX86State *env = &cpu->env;
1221 KVMState *s = kvm_state;
1222 FeatureWord w;
1223
1224 assert(kvm_enabled());
1225
1226 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1227 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1228 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1229
1230 for (w = 0; w < FEATURE_WORDS; w++) {
1231 FeatureWordInfo *wi = &feature_word_info[w];
1232 env->features[w] =
1233 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1234 wi->cpuid_reg);
1235 }
1236 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1237}
1238
1239static const TypeInfo host_x86_cpu_type_info = {
1240 .name = X86_CPU_TYPE_NAME("host"),
1241 .parent = TYPE_X86_CPU,
1242 .instance_init = host_x86_cpu_initfn,
1243 .class_init = host_x86_cpu_class_init,
1244};
1245
1246#endif
1247
1248static void report_unavailable_features(FeatureWord w, uint32_t mask)
1249{
1250 FeatureWordInfo *f = &feature_word_info[w];
1251 int i;
1252
1253 for (i = 0; i < 32; ++i) {
1254 if (1 << i & mask) {
1255 const char *reg = get_register_name_32(f->cpuid_reg);
1256 assert(reg);
1257 fprintf(stderr, "warning: host doesn't support requested feature: "
1258 "CPUID.%02XH:%s%s%s [bit %d]\n",
1259 f->cpuid_eax, reg,
1260 f->feat_names[i] ? "." : "",
1261 f->feat_names[i] ? f->feat_names[i] : "", i);
1262 }
1263 }
1264}
1265
1266static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1267 const char *name, Error **errp)
1268{
1269 X86CPU *cpu = X86_CPU(obj);
1270 CPUX86State *env = &cpu->env;
1271 int64_t value;
1272
1273 value = (env->cpuid_version >> 8) & 0xf;
1274 if (value == 0xf) {
1275 value += (env->cpuid_version >> 20) & 0xff;
1276 }
1277 visit_type_int(v, &value, name, errp);
1278}
1279
1280static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1281 const char *name, Error **errp)
1282{
1283 X86CPU *cpu = X86_CPU(obj);
1284 CPUX86State *env = &cpu->env;
1285 const int64_t min = 0;
1286 const int64_t max = 0xff + 0xf;
1287 Error *local_err = NULL;
1288 int64_t value;
1289
1290 visit_type_int(v, &value, name, &local_err);
1291 if (local_err) {
1292 error_propagate(errp, local_err);
1293 return;
1294 }
1295 if (value < min || value > max) {
1296 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1297 name ? name : "null", value, min, max);
1298 return;
1299 }
1300
1301 env->cpuid_version &= ~0xff00f00;
1302 if (value > 0x0f) {
1303 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1304 } else {
1305 env->cpuid_version |= value << 8;
1306 }
1307}
1308
1309static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1310 const char *name, Error **errp)
1311{
1312 X86CPU *cpu = X86_CPU(obj);
1313 CPUX86State *env = &cpu->env;
1314 int64_t value;
1315
1316 value = (env->cpuid_version >> 4) & 0xf;
1317 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1318 visit_type_int(v, &value, name, errp);
1319}
1320
1321static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1322 const char *name, Error **errp)
1323{
1324 X86CPU *cpu = X86_CPU(obj);
1325 CPUX86State *env = &cpu->env;
1326 const int64_t min = 0;
1327 const int64_t max = 0xff;
1328 Error *local_err = NULL;
1329 int64_t value;
1330
1331 visit_type_int(v, &value, name, &local_err);
1332 if (local_err) {
1333 error_propagate(errp, local_err);
1334 return;
1335 }
1336 if (value < min || value > max) {
1337 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1338 name ? name : "null", value, min, max);
1339 return;
1340 }
1341
1342 env->cpuid_version &= ~0xf00f0;
1343 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1344}
1345
1346static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1347 void *opaque, const char *name,
1348 Error **errp)
1349{
1350 X86CPU *cpu = X86_CPU(obj);
1351 CPUX86State *env = &cpu->env;
1352 int64_t value;
1353
1354 value = env->cpuid_version & 0xf;
1355 visit_type_int(v, &value, name, errp);
1356}
1357
1358static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1359 void *opaque, const char *name,
1360 Error **errp)
1361{
1362 X86CPU *cpu = X86_CPU(obj);
1363 CPUX86State *env = &cpu->env;
1364 const int64_t min = 0;
1365 const int64_t max = 0xf;
1366 Error *local_err = NULL;
1367 int64_t value;
1368
1369 visit_type_int(v, &value, name, &local_err);
1370 if (local_err) {
1371 error_propagate(errp, local_err);
1372 return;
1373 }
1374 if (value < min || value > max) {
1375 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1376 name ? name : "null", value, min, max);
1377 return;
1378 }
1379
1380 env->cpuid_version &= ~0xf;
1381 env->cpuid_version |= value & 0xf;
1382}
1383
1384static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1385 const char *name, Error **errp)
1386{
1387 X86CPU *cpu = X86_CPU(obj);
1388
1389 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1390}
1391
1392static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1393 const char *name, Error **errp)
1394{
1395 X86CPU *cpu = X86_CPU(obj);
1396
1397 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1398}
1399
1400static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1401 const char *name, Error **errp)
1402{
1403 X86CPU *cpu = X86_CPU(obj);
1404
1405 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1406}
1407
1408static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1409 const char *name, Error **errp)
1410{
1411 X86CPU *cpu = X86_CPU(obj);
1412
1413 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1414}
1415
1416static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1417{
1418 X86CPU *cpu = X86_CPU(obj);
1419 CPUX86State *env = &cpu->env;
1420 char *value;
1421
1422 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1423 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1424 env->cpuid_vendor3);
1425 return value;
1426}
1427
1428static void x86_cpuid_set_vendor(Object *obj, const char *value,
1429 Error **errp)
1430{
1431 X86CPU *cpu = X86_CPU(obj);
1432 CPUX86State *env = &cpu->env;
1433 int i;
1434
1435 if (strlen(value) != CPUID_VENDOR_SZ) {
1436 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1437 "vendor", value);
1438 return;
1439 }
1440
1441 env->cpuid_vendor1 = 0;
1442 env->cpuid_vendor2 = 0;
1443 env->cpuid_vendor3 = 0;
1444 for (i = 0; i < 4; i++) {
1445 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1446 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1447 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1448 }
1449}
1450
1451static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1452{
1453 X86CPU *cpu = X86_CPU(obj);
1454 CPUX86State *env = &cpu->env;
1455 char *value;
1456 int i;
1457
1458 value = g_malloc(48 + 1);
1459 for (i = 0; i < 48; i++) {
1460 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1461 }
1462 value[48] = '\0';
1463 return value;
1464}
1465
1466static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1467 Error **errp)
1468{
1469 X86CPU *cpu = X86_CPU(obj);
1470 CPUX86State *env = &cpu->env;
1471 int c, len, i;
1472
1473 if (model_id == NULL) {
1474 model_id = "";
1475 }
1476 len = strlen(model_id);
1477 memset(env->cpuid_model, 0, 48);
1478 for (i = 0; i < 48; i++) {
1479 if (i >= len) {
1480 c = '\0';
1481 } else {
1482 c = (uint8_t)model_id[i];
1483 }
1484 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1485 }
1486}
1487
1488static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1489 const char *name, Error **errp)
1490{
1491 X86CPU *cpu = X86_CPU(obj);
1492 int64_t value;
1493
1494 value = cpu->env.tsc_khz * 1000;
1495 visit_type_int(v, &value, name, errp);
1496}
1497
1498static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1499 const char *name, Error **errp)
1500{
1501 X86CPU *cpu = X86_CPU(obj);
1502 const int64_t min = 0;
1503 const int64_t max = INT64_MAX;
1504 Error *local_err = NULL;
1505 int64_t value;
1506
1507 visit_type_int(v, &value, name, &local_err);
1508 if (local_err) {
1509 error_propagate(errp, local_err);
1510 return;
1511 }
1512 if (value < min || value > max) {
1513 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1514 name ? name : "null", value, min, max);
1515 return;
1516 }
1517
1518 cpu->env.tsc_khz = value / 1000;
1519}
1520
1521static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1522 const char *name, Error **errp)
1523{
1524 X86CPU *cpu = X86_CPU(obj);
1525 int64_t value = cpu->env.cpuid_apic_id;
1526
1527 visit_type_int(v, &value, name, errp);
1528}
1529
1530static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1531 const char *name, Error **errp)
1532{
1533 X86CPU *cpu = X86_CPU(obj);
1534 DeviceState *dev = DEVICE(obj);
1535 const int64_t min = 0;
1536 const int64_t max = UINT32_MAX;
1537 Error *error = NULL;
1538 int64_t value;
1539
1540 if (dev->realized) {
1541 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1542 "it was realized", name, object_get_typename(obj));
1543 return;
1544 }
1545
1546 visit_type_int(v, &value, name, &error);
1547 if (error) {
1548 error_propagate(errp, error);
1549 return;
1550 }
1551 if (value < min || value > max) {
1552 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1553 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1554 object_get_typename(obj), name, value, min, max);
1555 return;
1556 }
1557
1558 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1559 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1560 return;
1561 }
1562 cpu->env.cpuid_apic_id = value;
1563}
1564
1565/* Generic getter for "feature-words" and "filtered-features" properties */
1566static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1567 const char *name, Error **errp)
1568{
1569 uint32_t *array = (uint32_t *)opaque;
1570 FeatureWord w;
1571 Error *err = NULL;
1572 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1573 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1574 X86CPUFeatureWordInfoList *list = NULL;
1575
1576 for (w = 0; w < FEATURE_WORDS; w++) {
1577 FeatureWordInfo *wi = &feature_word_info[w];
1578 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1579 qwi->cpuid_input_eax = wi->cpuid_eax;
1580 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1581 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1582 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1583 qwi->features = array[w];
1584
1585 /* List will be in reverse order, but order shouldn't matter */
1586 list_entries[w].next = list;
1587 list_entries[w].value = &word_infos[w];
1588 list = &list_entries[w];
1589 }
1590
1591 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1592 error_propagate(errp, err);
1593}
1594
1595static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1596 const char *name, Error **errp)
1597{
1598 X86CPU *cpu = X86_CPU(obj);
1599 int64_t value = cpu->hyperv_spinlock_attempts;
1600
1601 visit_type_int(v, &value, name, errp);
1602}
1603
1604static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1605 const char *name, Error **errp)
1606{
1607 const int64_t min = 0xFFF;
1608 const int64_t max = UINT_MAX;
1609 X86CPU *cpu = X86_CPU(obj);
1610 Error *err = NULL;
1611 int64_t value;
1612
1613 visit_type_int(v, &value, name, &err);
1614 if (err) {
1615 error_propagate(errp, err);
1616 return;
1617 }
1618
1619 if (value < min || value > max) {
1620 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1621 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1622 object_get_typename(obj), name ? name : "null",
1623 value, min, max);
1624 return;
1625 }
1626 cpu->hyperv_spinlock_attempts = value;
1627}
1628
1629static PropertyInfo qdev_prop_spinlocks = {
1630 .name = "int",
1631 .get = x86_get_hv_spinlocks,
1632 .set = x86_set_hv_spinlocks,
1633};
1634
1635/* Convert all '_' in a feature string option name to '-', to make feature
1636 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1637 */
1638static inline void feat2prop(char *s)
1639{
1640 while ((s = strchr(s, '_'))) {
1641 *s = '-';
1642 }
1643}
1644
1645/* Parse "+feature,-feature,feature=foo" CPU feature string
1646 */
1647static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1648 Error **errp)
1649{
1650 X86CPU *cpu = X86_CPU(cs);
1651 char *featurestr; /* Single 'key=value" string being parsed */
1652 /* Features to be added */
1653 FeatureWordArray plus_features = { 0 };
1654 /* Features to be removed */
1655 FeatureWordArray minus_features = { 0 };
1656 uint32_t numvalue;
1657 CPUX86State *env = &cpu->env;
1658 Error *local_err = NULL;
1659
1660 featurestr = features ? strtok(features, ",") : NULL;
1661
1662 while (featurestr) {
1663 char *val;
1664 if (featurestr[0] == '+') {
1665 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1666 } else if (featurestr[0] == '-') {
1667 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1668 } else if ((val = strchr(featurestr, '='))) {
1669 *val = 0; val++;
1670 feat2prop(featurestr);
1671 if (!strcmp(featurestr, "xlevel")) {
1672 char *err;
1673 char num[32];
1674
1675 numvalue = strtoul(val, &err, 0);
1676 if (!*val || *err) {
1677 error_setg(errp, "bad numerical value %s", val);
1678 return;
1679 }
1680 if (numvalue < 0x80000000) {
1681 error_report("xlevel value shall always be >= 0x80000000"
1682 ", fixup will be removed in future versions");
1683 numvalue += 0x80000000;
1684 }
1685 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1686 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1687 } else if (!strcmp(featurestr, "tsc-freq")) {
1688 int64_t tsc_freq;
1689 char *err;
1690 char num[32];
1691
1692 tsc_freq = strtosz_suffix_unit(val, &err,
1693 STRTOSZ_DEFSUFFIX_B, 1000);
1694 if (tsc_freq < 0 || *err) {
1695 error_setg(errp, "bad numerical value %s", val);
1696 return;
1697 }
1698 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1699 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1700 &local_err);
1701 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1702 char *err;
1703 const int min = 0xFFF;
1704 char num[32];
1705 numvalue = strtoul(val, &err, 0);
1706 if (!*val || *err) {
1707 error_setg(errp, "bad numerical value %s", val);
1708 return;
1709 }
1710 if (numvalue < min) {
1711 error_report("hv-spinlocks value shall always be >= 0x%x"
1712 ", fixup will be removed in future versions",
1713 min);
1714 numvalue = min;
1715 }
1716 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1717 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1718 } else {
1719 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1720 }
1721 } else {
1722 feat2prop(featurestr);
1723 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1724 }
1725 if (local_err) {
1726 error_propagate(errp, local_err);
1727 return;
1728 }
1729 featurestr = strtok(NULL, ",");
1730 }
1731 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1732 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1733 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1734 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1735 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1736 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1737 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1738 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1739 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1740 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1741 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1742 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1743 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1744 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1745 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1746 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1747}
1748
1749/* generate a composite string into buf of all cpuid names in featureset
1750 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1751 * if flags, suppress names undefined in featureset.
1752 */
1753static void listflags(char *buf, int bufsize, uint32_t fbits,
1754 const char **featureset, uint32_t flags)
1755{
1756 const char **p = &featureset[31];
1757 char *q, *b, bit;
1758 int nc;
1759
1760 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1761 *buf = '\0';
1762 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1763 if (fbits & 1 << bit && (*p || !flags)) {
1764 if (*p)
1765 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1766 else
1767 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1768 if (bufsize <= nc) {
1769 if (b) {
1770 memcpy(b, "...", sizeof("..."));
1771 }
1772 return;
1773 }
1774 q += nc;
1775 bufsize -= nc;
1776 }
1777}
1778
1779/* generate CPU information. */
1780void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1781{
1782 X86CPUDefinition *def;
1783 char buf[256];
1784 int i;
1785
1786 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1787 def = &builtin_x86_defs[i];
1788 snprintf(buf, sizeof(buf), "%s", def->name);
1789 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1790 }
1791#ifdef CONFIG_KVM
1792 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1793 "KVM processor with all supported host features "
1794 "(only available in KVM mode)");
1795#endif
1796
1797 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1798 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1799 FeatureWordInfo *fw = &feature_word_info[i];
1800
1801 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1802 (*cpu_fprintf)(f, " %s\n", buf);
1803 }
1804}
1805
1806CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1807{
1808 CpuDefinitionInfoList *cpu_list = NULL;
1809 X86CPUDefinition *def;
1810 int i;
1811
1812 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1813 CpuDefinitionInfoList *entry;
1814 CpuDefinitionInfo *info;
1815
1816 def = &builtin_x86_defs[i];
1817 info = g_malloc0(sizeof(*info));
1818 info->name = g_strdup(def->name);
1819
1820 entry = g_malloc0(sizeof(*entry));
1821 entry->value = info;
1822 entry->next = cpu_list;
1823 cpu_list = entry;
1824 }
1825
1826 return cpu_list;
1827}
1828
1829static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w)
1830{
1831 FeatureWordInfo *wi = &feature_word_info[w];
1832
1833 assert(kvm_enabled());
1834 return kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1835 wi->cpuid_ecx,
1836 wi->cpuid_reg);
1837}
1838
1839/*
1840 * Filters CPU feature words based on host availability of each feature.
1841 *
1842 * This function may be called only if KVM is enabled.
1843 *
1844 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1845 */
1846static int x86_cpu_filter_features(X86CPU *cpu)
1847{
1848 CPUX86State *env = &cpu->env;
1849 FeatureWord w;
1850 int rv = 0;
1851
1852 for (w = 0; w < FEATURE_WORDS; w++) {
1853 uint32_t host_feat = x86_cpu_get_supported_feature_word(w);
1854 uint32_t requested_features = env->features[w];
1855 env->features[w] &= host_feat;
1856 cpu->filtered_features[w] = requested_features & ~env->features[w];
1857 if (cpu->filtered_features[w]) {
1858 if (cpu->check_cpuid || cpu->enforce_cpuid) {
1859 report_unavailable_features(w, cpu->filtered_features[w]);
1860 }
1861 rv = 1;
1862 }
1863 }
1864
1865 return rv;
1866}
1867
1868/* Load data from X86CPUDefinition
1869 */
1870static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1871{
1872 CPUX86State *env = &cpu->env;
1873 const char *vendor;
1874 char host_vendor[CPUID_VENDOR_SZ + 1];
1875
1876 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1877 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1878 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1879 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1880 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1881 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1882 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1883 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1884 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1885 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1886 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1887 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1888 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1889 env->cpuid_xlevel2 = def->xlevel2;
1890 cpu->cache_info_passthrough = def->cache_info_passthrough;
1891
1892 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1893
1894 /* Special cases not set in the X86CPUDefinition structs: */
1895 if (kvm_enabled()) {
1896 FeatureWord w;
1897 for (w = 0; w < FEATURE_WORDS; w++) {
1898 env->features[w] |= kvm_default_features[w];
1899 env->features[w] &= ~kvm_default_unset_features[w];
1900 }
1901 }
1902
1903 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1904
1905 /* sysenter isn't supported in compatibility mode on AMD,
1906 * syscall isn't supported in compatibility mode on Intel.
1907 * Normally we advertise the actual CPU vendor, but you can
1908 * override this using the 'vendor' property if you want to use
1909 * KVM's sysenter/syscall emulation in compatibility mode and
1910 * when doing cross vendor migration
1911 */
1912 vendor = def->vendor;
1913 if (kvm_enabled()) {
1914 uint32_t ebx = 0, ecx = 0, edx = 0;
1915 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1916 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1917 vendor = host_vendor;
1918 }
1919
1920 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1921
1922}
1923
1924X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1925 Error **errp)
1926{
1927 X86CPU *cpu = NULL;
1928 X86CPUClass *xcc;
1929 ObjectClass *oc;
1930 gchar **model_pieces;
1931 char *name, *features;
1932 Error *error = NULL;
1933
1934 model_pieces = g_strsplit(cpu_model, ",", 2);
1935 if (!model_pieces[0]) {
1936 error_setg(&error, "Invalid/empty CPU model name");
1937 goto out;
1938 }
1939 name = model_pieces[0];
1940 features = model_pieces[1];
1941
1942 oc = x86_cpu_class_by_name(name);
1943 if (oc == NULL) {
1944 error_setg(&error, "Unable to find CPU definition: %s", name);
1945 goto out;
1946 }
1947 xcc = X86_CPU_CLASS(oc);
1948
1949 if (xcc->kvm_required && !kvm_enabled()) {
1950 error_setg(&error, "CPU model '%s' requires KVM", name);
1951 goto out;
1952 }
1953
1954 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1955
1956#ifndef CONFIG_USER_ONLY
1957 if (icc_bridge == NULL) {
1958 error_setg(&error, "Invalid icc-bridge value");
1959 goto out;
1960 }
1961 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1962 object_unref(OBJECT(cpu));
1963#endif
1964
1965 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
1966 if (error) {
1967 goto out;
1968 }
1969
1970out:
1971 if (error != NULL) {
1972 error_propagate(errp, error);
1973 if (cpu) {
1974 object_unref(OBJECT(cpu));
1975 cpu = NULL;
1976 }
1977 }
1978 g_strfreev(model_pieces);
1979 return cpu;
1980}
1981
1982X86CPU *cpu_x86_init(const char *cpu_model)
1983{
1984 Error *error = NULL;
1985 X86CPU *cpu;
1986
1987 cpu = cpu_x86_create(cpu_model, NULL, &error);
1988 if (error) {
1989 goto out;
1990 }
1991
1992 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1993
1994out:
1995 if (error) {
1996 error_report("%s", error_get_pretty(error));
1997 error_free(error);
1998 if (cpu != NULL) {
1999 object_unref(OBJECT(cpu));
2000 cpu = NULL;
2001 }
2002 }
2003 return cpu;
2004}
2005
2006static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2007{
2008 X86CPUDefinition *cpudef = data;
2009 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2010
2011 xcc->cpu_def = cpudef;
2012}
2013
2014static void x86_register_cpudef_type(X86CPUDefinition *def)
2015{
2016 char *typename = x86_cpu_type_name(def->name);
2017 TypeInfo ti = {
2018 .name = typename,
2019 .parent = TYPE_X86_CPU,
2020 .class_init = x86_cpu_cpudef_class_init,
2021 .class_data = def,
2022 };
2023
2024 type_register(&ti);
2025 g_free(typename);
2026}
2027
2028#if !defined(CONFIG_USER_ONLY)
2029
2030void cpu_clear_apic_feature(CPUX86State *env)
2031{
2032 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2033}
2034
2035#endif /* !CONFIG_USER_ONLY */
2036
2037/* Initialize list of CPU models, filling some non-static fields if necessary
2038 */
2039void x86_cpudef_setup(void)
2040{
2041 int i, j;
2042 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2043
2044 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2045 X86CPUDefinition *def = &builtin_x86_defs[i];
2046
2047 /* Look for specific "cpudef" models that */
2048 /* have the QEMU version in .model_id */
2049 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2050 if (strcmp(model_with_versions[j], def->name) == 0) {
2051 pstrcpy(def->model_id, sizeof(def->model_id),
2052 "QEMU Virtual CPU version ");
2053 pstrcat(def->model_id, sizeof(def->model_id),
2054 qemu_get_version());
2055 break;
2056 }
2057 }
2058 }
2059}
2060
2061static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2062 uint32_t *ecx, uint32_t *edx)
2063{
2064 *ebx = env->cpuid_vendor1;
2065 *edx = env->cpuid_vendor2;
2066 *ecx = env->cpuid_vendor3;
2067}
2068
2069void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2070 uint32_t *eax, uint32_t *ebx,
2071 uint32_t *ecx, uint32_t *edx)
2072{
2073 X86CPU *cpu = x86_env_get_cpu(env);
2074 CPUState *cs = CPU(cpu);
2075
2076 /* test if maximum index reached */
2077 if (index & 0x80000000) {
2078 if (index > env->cpuid_xlevel) {
2079 if (env->cpuid_xlevel2 > 0) {
2080 /* Handle the Centaur's CPUID instruction. */
2081 if (index > env->cpuid_xlevel2) {
2082 index = env->cpuid_xlevel2;
2083 } else if (index < 0xC0000000) {
2084 index = env->cpuid_xlevel;
2085 }
2086 } else {
2087 /* Intel documentation states that invalid EAX input will
2088 * return the same information as EAX=cpuid_level
2089 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2090 */
2091 index = env->cpuid_level;
2092 }
2093 }
2094 } else {
2095 if (index > env->cpuid_level)
2096 index = env->cpuid_level;
2097 }
2098
2099 switch(index) {
2100 case 0:
2101 *eax = env->cpuid_level;
2102 get_cpuid_vendor(env, ebx, ecx, edx);
2103 break;
2104 case 1:
2105 *eax = env->cpuid_version;
2106 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2107 *ecx = env->features[FEAT_1_ECX];
2108 *edx = env->features[FEAT_1_EDX];
2109 if (cs->nr_cores * cs->nr_threads > 1) {
2110 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2111 *edx |= 1 << 28; /* HTT bit */
2112 }
2113 break;
2114 case 2:
2115 /* cache info: needed for Pentium Pro compatibility */
2116 if (cpu->cache_info_passthrough) {
2117 host_cpuid(index, 0, eax, ebx, ecx, edx);
2118 break;
2119 }
2120 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2121 *ebx = 0;
2122 *ecx = 0;
2123 *edx = (L1D_DESCRIPTOR << 16) | \
2124 (L1I_DESCRIPTOR << 8) | \
2125 (L2_DESCRIPTOR);
2126 break;
2127 case 4:
2128 /* cache info: needed for Core compatibility */
2129 if (cpu->cache_info_passthrough) {
2130 host_cpuid(index, count, eax, ebx, ecx, edx);
2131 *eax &= ~0xFC000000;
2132 } else {
2133 *eax = 0;
2134 switch (count) {
2135 case 0: /* L1 dcache info */
2136 *eax |= CPUID_4_TYPE_DCACHE | \
2137 CPUID_4_LEVEL(1) | \
2138 CPUID_4_SELF_INIT_LEVEL;
2139 *ebx = (L1D_LINE_SIZE - 1) | \
2140 ((L1D_PARTITIONS - 1) << 12) | \
2141 ((L1D_ASSOCIATIVITY - 1) << 22);
2142 *ecx = L1D_SETS - 1;
2143 *edx = CPUID_4_NO_INVD_SHARING;
2144 break;
2145 case 1: /* L1 icache info */
2146 *eax |= CPUID_4_TYPE_ICACHE | \
2147 CPUID_4_LEVEL(1) | \
2148 CPUID_4_SELF_INIT_LEVEL;
2149 *ebx = (L1I_LINE_SIZE - 1) | \
2150 ((L1I_PARTITIONS - 1) << 12) | \
2151 ((L1I_ASSOCIATIVITY - 1) << 22);
2152 *ecx = L1I_SETS - 1;
2153 *edx = CPUID_4_NO_INVD_SHARING;
2154 break;
2155 case 2: /* L2 cache info */
2156 *eax |= CPUID_4_TYPE_UNIFIED | \
2157 CPUID_4_LEVEL(2) | \
2158 CPUID_4_SELF_INIT_LEVEL;
2159 if (cs->nr_threads > 1) {
2160 *eax |= (cs->nr_threads - 1) << 14;
2161 }
2162 *ebx = (L2_LINE_SIZE - 1) | \
2163 ((L2_PARTITIONS - 1) << 12) | \
2164 ((L2_ASSOCIATIVITY - 1) << 22);
2165 *ecx = L2_SETS - 1;
2166 *edx = CPUID_4_NO_INVD_SHARING;
2167 break;
2168 default: /* end of info */
2169 *eax = 0;
2170 *ebx = 0;
2171 *ecx = 0;
2172 *edx = 0;
2173 break;
2174 }
2175 }
2176
2177 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2178 if ((*eax & 31) && cs->nr_cores > 1) {
2179 *eax |= (cs->nr_cores - 1) << 26;
2180 }
2181 break;
2182 case 5:
2183 /* mwait info: needed for Core compatibility */
2184 *eax = 0; /* Smallest monitor-line size in bytes */
2185 *ebx = 0; /* Largest monitor-line size in bytes */
2186 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2187 *edx = 0;
2188 break;
2189 case 6:
2190 /* Thermal and Power Leaf */
2191 *eax = 0;
2192 *ebx = 0;
2193 *ecx = 0;
2194 *edx = 0;
2195 break;
2196 case 7:
2197 /* Structured Extended Feature Flags Enumeration Leaf */
2198 if (count == 0) {
2199 *eax = 0; /* Maximum ECX value for sub-leaves */
2200 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2201 *ecx = 0; /* Reserved */
2202 *edx = 0; /* Reserved */
2203 } else {
2204 *eax = 0;
2205 *ebx = 0;
2206 *ecx = 0;
2207 *edx = 0;
2208 }
2209 break;
2210 case 9:
2211 /* Direct Cache Access Information Leaf */
2212 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2213 *ebx = 0;
2214 *ecx = 0;
2215 *edx = 0;
2216 break;
2217 case 0xA:
2218 /* Architectural Performance Monitoring Leaf */
2219 if (kvm_enabled() && cpu->enable_pmu) {
2220 KVMState *s = cs->kvm_state;
2221
2222 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2223 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2224 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2225 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2226 } else {
2227 *eax = 0;
2228 *ebx = 0;
2229 *ecx = 0;
2230 *edx = 0;
2231 }
2232 break;
2233 case 0xD: {
2234 KVMState *s = cs->kvm_state;
2235 uint64_t kvm_mask;
2236 int i;
2237
2238 /* Processor Extended State */
2239 *eax = 0;
2240 *ebx = 0;
2241 *ecx = 0;
2242 *edx = 0;
2243 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2244 break;
2245 }
2246 kvm_mask =
2247 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2248 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2249
2250 if (count == 0) {
2251 *ecx = 0x240;
2252 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2253 const ExtSaveArea *esa = &ext_save_areas[i];
2254 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2255 (kvm_mask & (1 << i)) != 0) {
2256 if (i < 32) {
2257 *eax |= 1 << i;
2258 } else {
2259 *edx |= 1 << (i - 32);
2260 }
2261 *ecx = MAX(*ecx, esa->offset + esa->size);
2262 }
2263 }
2264 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2265 *ebx = *ecx;
2266 } else if (count == 1) {
2267 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2268 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2269 const ExtSaveArea *esa = &ext_save_areas[count];
2270 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2271 (kvm_mask & (1 << count)) != 0) {
2272 *eax = esa->size;
2273 *ebx = esa->offset;
2274 }
2275 }
2276 break;
2277 }
2278 case 0x80000000:
2279 *eax = env->cpuid_xlevel;
2280 *ebx = env->cpuid_vendor1;
2281 *edx = env->cpuid_vendor2;
2282 *ecx = env->cpuid_vendor3;
2283 break;
2284 case 0x80000001:
2285 *eax = env->cpuid_version;
2286 *ebx = 0;
2287 *ecx = env->features[FEAT_8000_0001_ECX];
2288 *edx = env->features[FEAT_8000_0001_EDX];
2289
2290 /* The Linux kernel checks for the CMPLegacy bit and
2291 * discards multiple thread information if it is set.
2292 * So dont set it here for Intel to make Linux guests happy.
2293 */
2294 if (cs->nr_cores * cs->nr_threads > 1) {
2295 uint32_t tebx, tecx, tedx;
2296 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2297 if (tebx != CPUID_VENDOR_INTEL_1 ||
2298 tedx != CPUID_VENDOR_INTEL_2 ||
2299 tecx != CPUID_VENDOR_INTEL_3) {
2300 *ecx |= 1 << 1; /* CmpLegacy bit */
2301 }
2302 }
2303 break;
2304 case 0x80000002:
2305 case 0x80000003:
2306 case 0x80000004:
2307 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2308 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2309 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2310 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2311 break;
2312 case 0x80000005:
2313 /* cache info (L1 cache) */
2314 if (cpu->cache_info_passthrough) {
2315 host_cpuid(index, 0, eax, ebx, ecx, edx);
2316 break;
2317 }
2318 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2319 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2320 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2321 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2322 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2323 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2324 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2325 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2326 break;
2327 case 0x80000006:
2328 /* cache info (L2 cache) */
2329 if (cpu->cache_info_passthrough) {
2330 host_cpuid(index, 0, eax, ebx, ecx, edx);
2331 break;
2332 }
2333 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2334 (L2_DTLB_2M_ENTRIES << 16) | \
2335 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2336 (L2_ITLB_2M_ENTRIES);
2337 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2338 (L2_DTLB_4K_ENTRIES << 16) | \
2339 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2340 (L2_ITLB_4K_ENTRIES);
2341 *ecx = (L2_SIZE_KB_AMD << 16) | \
2342 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2343 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2344 *edx = ((L3_SIZE_KB/512) << 18) | \
2345 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2346 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2347 break;
2348 case 0x80000008:
2349 /* virtual & phys address size in low 2 bytes. */
2350/* XXX: This value must match the one used in the MMU code. */
2351 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2352 /* 64 bit processor */
2353/* XXX: The physical address space is limited to 42 bits in exec.c. */
2354 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2355 } else {
2356 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2357 *eax = 0x00000024; /* 36 bits physical */
2358 } else {
2359 *eax = 0x00000020; /* 32 bits physical */
2360 }
2361 }
2362 *ebx = 0;
2363 *ecx = 0;
2364 *edx = 0;
2365 if (cs->nr_cores * cs->nr_threads > 1) {
2366 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2367 }
2368 break;
2369 case 0x8000000A:
2370 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2371 *eax = 0x00000001; /* SVM Revision */
2372 *ebx = 0x00000010; /* nr of ASIDs */
2373 *ecx = 0;
2374 *edx = env->features[FEAT_SVM]; /* optional features */
2375 } else {
2376 *eax = 0;
2377 *ebx = 0;
2378 *ecx = 0;
2379 *edx = 0;
2380 }
2381 break;
2382 case 0xC0000000:
2383 *eax = env->cpuid_xlevel2;
2384 *ebx = 0;
2385 *ecx = 0;
2386 *edx = 0;
2387 break;
2388 case 0xC0000001:
2389 /* Support for VIA CPU's CPUID instruction */
2390 *eax = env->cpuid_version;
2391 *ebx = 0;
2392 *ecx = 0;
2393 *edx = env->features[FEAT_C000_0001_EDX];
2394 break;
2395 case 0xC0000002:
2396 case 0xC0000003:
2397 case 0xC0000004:
2398 /* Reserved for the future, and now filled with zero */
2399 *eax = 0;
2400 *ebx = 0;
2401 *ecx = 0;
2402 *edx = 0;
2403 break;
2404 default:
2405 /* reserved values: zero */
2406 *eax = 0;
2407 *ebx = 0;
2408 *ecx = 0;
2409 *edx = 0;
2410 break;
2411 }
2412}
2413
2414/* CPUClass::reset() */
2415static void x86_cpu_reset(CPUState *s)
2416{
2417 X86CPU *cpu = X86_CPU(s);
2418 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2419 CPUX86State *env = &cpu->env;
2420 int i;
2421
2422 xcc->parent_reset(s);
2423
2424 memset(env, 0, offsetof(CPUX86State, cpuid_level));
2425
2426 tlb_flush(s, 1);
2427
2428 env->old_exception = -1;
2429
2430 /* init to reset state */
2431
2432#ifdef CONFIG_SOFTMMU
2433 env->hflags |= HF_SOFTMMU_MASK;
2434#endif
2435 env->hflags2 |= HF2_GIF_MASK;
2436
2437 cpu_x86_update_cr0(env, 0x60000010);
2438 env->a20_mask = ~0x0;
2439 env->smbase = 0x30000;
2440
2441 env->idt.limit = 0xffff;
2442 env->gdt.limit = 0xffff;
2443 env->ldt.limit = 0xffff;
2444 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2445 env->tr.limit = 0xffff;
2446 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2447
2448 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2449 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2450 DESC_R_MASK | DESC_A_MASK);
2451 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2452 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2453 DESC_A_MASK);
2454 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2455 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2456 DESC_A_MASK);
2457 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2458 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2459 DESC_A_MASK);
2460 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2461 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2462 DESC_A_MASK);
2463 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2464 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2465 DESC_A_MASK);
2466
2467 env->eip = 0xfff0;
2468 env->regs[R_EDX] = env->cpuid_version;
2469
2470 env->eflags = 0x2;
2471
2472 /* FPU init */
2473 for (i = 0; i < 8; i++) {
2474 env->fptags[i] = 1;
2475 }
2476 env->fpuc = 0x37f;
2477
2478 env->mxcsr = 0x1f80;
2479 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2480
2481 env->pat = 0x0007040600070406ULL;
2482 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2483
2484 memset(env->dr, 0, sizeof(env->dr));
2485 env->dr[6] = DR6_FIXED_1;
2486 env->dr[7] = DR7_FIXED_1;
2487 cpu_breakpoint_remove_all(s, BP_CPU);
2488 cpu_watchpoint_remove_all(s, BP_CPU);
2489
2490 env->xcr0 = 1;
2491
2492#if !defined(CONFIG_USER_ONLY)
2493 /* We hard-wire the BSP to the first CPU. */
2494 if (s->cpu_index == 0) {
2495 apic_designate_bsp(cpu->apic_state);
2496 }
2497
2498 s->halted = !cpu_is_bsp(cpu);
2499
2500 if (kvm_enabled()) {
2501 kvm_arch_reset_vcpu(cpu);
2502 }
2503#endif
2504}
2505
2506#ifndef CONFIG_USER_ONLY
2507bool cpu_is_bsp(X86CPU *cpu)
2508{
2509 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2510}
2511
2512/* TODO: remove me, when reset over QOM tree is implemented */
2513static void x86_cpu_machine_reset_cb(void *opaque)
2514{
2515 X86CPU *cpu = opaque;
2516 cpu_reset(CPU(cpu));
2517}
2518#endif
2519
2520static void mce_init(X86CPU *cpu)
2521{
2522 CPUX86State *cenv = &cpu->env;
2523 unsigned int bank;
2524
2525 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2526 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2527 (CPUID_MCE | CPUID_MCA)) {
2528 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2529 cenv->mcg_ctl = ~(uint64_t)0;
2530 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2531 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2532 }
2533 }
2534}
2535
2536#ifndef CONFIG_USER_ONLY
2537static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2538{
2539 CPUX86State *env = &cpu->env;
2540 DeviceState *dev = DEVICE(cpu);
2541 APICCommonState *apic;
2542 const char *apic_type = "apic";
2543
2544 if (kvm_irqchip_in_kernel()) {
2545 apic_type = "kvm-apic";
2546 } else if (xen_enabled()) {
2547 apic_type = "xen-apic";
2548 }
2549
2550 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2551 if (cpu->apic_state == NULL) {
2552 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2553 return;
2554 }
2555
2556 object_property_add_child(OBJECT(cpu), "apic",
2557 OBJECT(cpu->apic_state), NULL);
2558 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2559 /* TODO: convert to link<> */
2560 apic = APIC_COMMON(cpu->apic_state);
2561 apic->cpu = cpu;
2562}
2563
2564static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2565{
2566 if (cpu->apic_state == NULL) {
2567 return;
2568 }
2569
2570 if (qdev_init(cpu->apic_state)) {
2571 error_setg(errp, "APIC device '%s' could not be initialized",
2572 object_get_typename(OBJECT(cpu->apic_state)));
2573 return;
2574 }
2575}
2576#else
2577static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2578{
2579}
2580#endif
2581
2582static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2583{
2584 CPUState *cs = CPU(dev);
2585 X86CPU *cpu = X86_CPU(dev);
2586 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2587 CPUX86State *env = &cpu->env;
2588 Error *local_err = NULL;
2589
2590 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2591 env->cpuid_level = 7;
2592 }
2593
2594 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2595 * CPUID[1].EDX.
2596 */
2597 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2598 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2599 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2600 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2601 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2602 & CPUID_EXT2_AMD_ALIASES);
2603 }
2604
2605 if (!kvm_enabled()) {
2606 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2607 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2608 env->features[FEAT_7_0_EBX] &= TCG_7_0_EBX_FEATURES;
2609 env->features[FEAT_8000_0001_EDX] &= TCG_EXT2_FEATURES;
2610 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2611 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2612 env->features[FEAT_KVM] &= TCG_KVM_FEATURES;
2613 env->features[FEAT_C000_0001_EDX] &= TCG_EXT4_FEATURES;
2614 } else {
2615 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2616 error_setg(&local_err,
2617 "Host's CPU doesn't support requested features");
2618 goto out;
2619 }
2620 }
2621
2622#ifndef CONFIG_USER_ONLY
2623 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2624
2625 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2626 x86_cpu_apic_create(cpu, &local_err);
2627 if (local_err != NULL) {
2628 goto out;
2629 }
2630 }
2631#endif
2632
2633 mce_init(cpu);
2634 qemu_init_vcpu(cs);
2635
2636 x86_cpu_apic_realize(cpu, &local_err);
2637 if (local_err != NULL) {
2638 goto out;
2639 }
2640 cpu_reset(cs);
2641
2642 xcc->parent_realize(dev, &local_err);
2643out:
2644 if (local_err != NULL) {
2645 error_propagate(errp, local_err);
2646 return;
2647 }
2648}
2649
2650/* Enables contiguous-apic-ID mode, for compatibility */
2651static bool compat_apic_id_mode;
2652
2653void enable_compat_apic_id_mode(void)
2654{
2655 compat_apic_id_mode = true;
2656}
2657
2658/* Calculates initial APIC ID for a specific CPU index
2659 *
2660 * Currently we need to be able to calculate the APIC ID from the CPU index
2661 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2662 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2663 * all CPUs up to max_cpus.
2664 */
2665uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2666{
2667 uint32_t correct_id;
2668 static bool warned;
2669
2670 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2671 if (compat_apic_id_mode) {
2672 if (cpu_index != correct_id && !warned) {
2673 error_report("APIC IDs set in compatibility mode, "
2674 "CPU topology won't match the configuration");
2675 warned = true;
2676 }
2677 return cpu_index;
2678 } else {
2679 return correct_id;
2680 }
2681}
2682
2683static void x86_cpu_initfn(Object *obj)
2684{
2685 CPUState *cs = CPU(obj);
2686 X86CPU *cpu = X86_CPU(obj);
2687 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2688 CPUX86State *env = &cpu->env;
2689 static int inited;
2690
2691 cs->env_ptr = env;
2692 cpu_exec_init(env);
2693
2694 object_property_add(obj, "family", "int",
2695 x86_cpuid_version_get_family,
2696 x86_cpuid_version_set_family, NULL, NULL, NULL);
2697 object_property_add(obj, "model", "int",
2698 x86_cpuid_version_get_model,
2699 x86_cpuid_version_set_model, NULL, NULL, NULL);
2700 object_property_add(obj, "stepping", "int",
2701 x86_cpuid_version_get_stepping,
2702 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2703 object_property_add(obj, "level", "int",
2704 x86_cpuid_get_level,
2705 x86_cpuid_set_level, NULL, NULL, NULL);
2706 object_property_add(obj, "xlevel", "int",
2707 x86_cpuid_get_xlevel,
2708 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2709 object_property_add_str(obj, "vendor",
2710 x86_cpuid_get_vendor,
2711 x86_cpuid_set_vendor, NULL);
2712 object_property_add_str(obj, "model-id",
2713 x86_cpuid_get_model_id,
2714 x86_cpuid_set_model_id, NULL);
2715 object_property_add(obj, "tsc-frequency", "int",
2716 x86_cpuid_get_tsc_freq,
2717 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2718 object_property_add(obj, "apic-id", "int",
2719 x86_cpuid_get_apic_id,
2720 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2721 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2722 x86_cpu_get_feature_words,
2723 NULL, NULL, (void *)env->features, NULL);
2724 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2725 x86_cpu_get_feature_words,
2726 NULL, NULL, (void *)cpu->filtered_features, NULL);
2727
2728 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2729 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2730
2731 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2732
2733 /* init various static tables used in TCG mode */
2734 if (tcg_enabled() && !inited) {
2735 inited = 1;
2736 optimize_flags_init();
2737#ifndef CONFIG_USER_ONLY
2738 cpu_set_debug_excp_handler(breakpoint_handler);
2739#endif
2740 }
2741}
2742
2743static int64_t x86_cpu_get_arch_id(CPUState *cs)
2744{
2745 X86CPU *cpu = X86_CPU(cs);
2746 CPUX86State *env = &cpu->env;
2747
2748 return env->cpuid_apic_id;
2749}
2750
2751static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2752{
2753 X86CPU *cpu = X86_CPU(cs);
2754
2755 return cpu->env.cr[0] & CR0_PG_MASK;
2756}
2757
2758static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2759{
2760 X86CPU *cpu = X86_CPU(cs);
2761
2762 cpu->env.eip = value;
2763}
2764
2765static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2766{
2767 X86CPU *cpu = X86_CPU(cs);
2768
2769 cpu->env.eip = tb->pc - tb->cs_base;
2770}
2771
2772static bool x86_cpu_has_work(CPUState *cs)
2773{
2774 X86CPU *cpu = X86_CPU(cs);
2775 CPUX86State *env = &cpu->env;
2776
2777 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2778 CPU_INTERRUPT_POLL)) &&
2779 (env->eflags & IF_MASK)) ||
2780 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2781 CPU_INTERRUPT_INIT |
2782 CPU_INTERRUPT_SIPI |
2783 CPU_INTERRUPT_MCE));
2784}
2785
2786static Property x86_cpu_properties[] = {
2787 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2788 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2789 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2790 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2791 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2792 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2793 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2794 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
2795 DEFINE_PROP_END_OF_LIST()
2796};
2797
2798static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2799{
2800 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2801 CPUClass *cc = CPU_CLASS(oc);
2802 DeviceClass *dc = DEVICE_CLASS(oc);
2803
2804 xcc->parent_realize = dc->realize;
2805 dc->realize = x86_cpu_realizefn;
2806 dc->bus_type = TYPE_ICC_BUS;
2807 dc->props = x86_cpu_properties;
2808
2809 xcc->parent_reset = cc->reset;
2810 cc->reset = x86_cpu_reset;
2811 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2812
2813 cc->class_by_name = x86_cpu_class_by_name;
2814 cc->parse_features = x86_cpu_parse_featurestr;
2815 cc->has_work = x86_cpu_has_work;
2816 cc->do_interrupt = x86_cpu_do_interrupt;
2817 cc->dump_state = x86_cpu_dump_state;
2818 cc->set_pc = x86_cpu_set_pc;
2819 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2820 cc->gdb_read_register = x86_cpu_gdb_read_register;
2821 cc->gdb_write_register = x86_cpu_gdb_write_register;
2822 cc->get_arch_id = x86_cpu_get_arch_id;
2823 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2824#ifdef CONFIG_USER_ONLY
2825 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2826#else
2827 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2828 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2829 cc->write_elf64_note = x86_cpu_write_elf64_note;
2830 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2831 cc->write_elf32_note = x86_cpu_write_elf32_note;
2832 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2833 cc->vmsd = &vmstate_x86_cpu;
2834#endif
2835 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2836}
2837
2838static const TypeInfo x86_cpu_type_info = {
2839 .name = TYPE_X86_CPU,
2840 .parent = TYPE_CPU,
2841 .instance_size = sizeof(X86CPU),
2842 .instance_init = x86_cpu_initfn,
2843 .abstract = true,
2844 .class_size = sizeof(X86CPUClass),
2845 .class_init = x86_cpu_common_class_init,
2846};
2847
2848static void x86_cpu_register_types(void)
2849{
2850 int i;
2851
2852 type_register_static(&x86_cpu_type_info);
2853 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2854 x86_register_cpudef_type(&builtin_x86_defs[i]);
2855 }
2856#ifdef CONFIG_KVM
2857 type_register_static(&host_x86_cpu_type_info);
2858#endif
2859}
2860
2861type_init(x86_cpu_register_types)
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