]> git.proxmox.com Git - mirror_qemu.git/blame_incremental - target-i386/cpu.c
projects / mirror_qemu.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
target-i386: Add "migratable" property to "host" CPU model
[mirror_qemu.git] / target-i386 / cpu.c
... / ...
CommitLineData
1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "sysemu/kvm.h"
26#include "sysemu/cpus.h"
27#include "kvm_i386.h"
28#include "topology.h"
29
30#include "qemu/option.h"
31#include "qemu/config-file.h"
32#include "qapi/qmp/qerror.h"
33
34#include "qapi-types.h"
35#include "qapi-visit.h"
36#include "qapi/visitor.h"
37#include "sysemu/arch_init.h"
38
39#include "hw/hw.h"
40#if defined(CONFIG_KVM)
41#include <linux/kvm_para.h>
42#endif
43
44#include "sysemu/sysemu.h"
45#include "hw/qdev-properties.h"
46#include "hw/cpu/icc_bus.h"
47#ifndef CONFIG_USER_ONLY
48#include "hw/xen/xen.h"
49#include "hw/i386/apic_internal.h"
50#endif
51
52
53/* Cache topology CPUID constants: */
54
55/* CPUID Leaf 2 Descriptors */
56
57#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58#define CPUID_2_L1I_32KB_8WAY_64B 0x30
59#define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62/* CPUID Leaf 4 constants: */
63
64/* EAX: */
65#define CPUID_4_TYPE_DCACHE 1
66#define CPUID_4_TYPE_ICACHE 2
67#define CPUID_4_TYPE_UNIFIED 3
68
69#define CPUID_4_LEVEL(l) ((l) << 5)
70
71#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72#define CPUID_4_FULLY_ASSOC (1 << 9)
73
74/* EDX: */
75#define CPUID_4_NO_INVD_SHARING (1 << 0)
76#define CPUID_4_INCLUSIVE (1 << 1)
77#define CPUID_4_COMPLEX_IDX (1 << 2)
78
79#define ASSOC_FULL 0xFF
80
81/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96/* Definitions of the hardcoded cache entries we expose: */
97
98/* L1 data cache: */
99#define L1D_LINE_SIZE 64
100#define L1D_ASSOCIATIVITY 8
101#define L1D_SETS 64
102#define L1D_PARTITIONS 1
103/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106#define L1D_LINES_PER_TAG 1
107#define L1D_SIZE_KB_AMD 64
108#define L1D_ASSOCIATIVITY_AMD 2
109
110/* L1 instruction cache: */
111#define L1I_LINE_SIZE 64
112#define L1I_ASSOCIATIVITY 8
113#define L1I_SETS 64
114#define L1I_PARTITIONS 1
115/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118#define L1I_LINES_PER_TAG 1
119#define L1I_SIZE_KB_AMD 64
120#define L1I_ASSOCIATIVITY_AMD 2
121
122/* Level 2 unified cache: */
123#define L2_LINE_SIZE 64
124#define L2_ASSOCIATIVITY 16
125#define L2_SETS 4096
126#define L2_PARTITIONS 1
127/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131#define L2_LINES_PER_TAG 1
132#define L2_SIZE_KB_AMD 512
133
134/* No L3 cache: */
135#define L3_SIZE_KB 0 /* disabled */
136#define L3_ASSOCIATIVITY 0 /* disabled */
137#define L3_LINES_PER_TAG 0 /* disabled */
138#define L3_LINE_SIZE 0 /* disabled */
139
140/* TLB definitions: */
141
142#define L1_DTLB_2M_ASSOC 1
143#define L1_DTLB_2M_ENTRIES 255
144#define L1_DTLB_4K_ASSOC 1
145#define L1_DTLB_4K_ENTRIES 255
146
147#define L1_ITLB_2M_ASSOC 1
148#define L1_ITLB_2M_ENTRIES 255
149#define L1_ITLB_4K_ASSOC 1
150#define L1_ITLB_4K_ENTRIES 255
151
152#define L2_DTLB_2M_ASSOC 0 /* disabled */
153#define L2_DTLB_2M_ENTRIES 0 /* disabled */
154#define L2_DTLB_4K_ASSOC 4
155#define L2_DTLB_4K_ENTRIES 512
156
157#define L2_ITLB_2M_ASSOC 0 /* disabled */
158#define L2_ITLB_2M_ENTRIES 0 /* disabled */
159#define L2_ITLB_4K_ASSOC 4
160#define L2_ITLB_4K_ENTRIES 512
161
162
163
164static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166{
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174}
175
176/* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189};
190static const char *ext_feature_name[] = {
191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
192 "ds_cpl", "vmx", "smx", "est",
193 "tm2", "ssse3", "cid", NULL,
194 "fma", "cx16", "xtpr", "pdcm",
195 NULL, "pcid", "dca", "sse4.1|sse4_1",
196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
197 "tsc-deadline", "aes", "xsave", "osxsave",
198 "avx", "f16c", "rdrand", "hypervisor",
199};
200/* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
205static const char *ext2_feature_name[] = {
206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
213 NULL, "lm|i64", "3dnowext", "3dnow",
214};
215static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
218 "3dnowprefetch", "osvw", "ibs", "xop",
219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
223 NULL, NULL, NULL, NULL,
224};
225
226static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235};
236
237static const char *kvm_feature_name[] = {
238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
246};
247
248static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257};
258
259static const char *cpuid_7_0_ebx_feature_name[] = {
260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264};
265
266#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
267#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
268 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
269#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
270 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
271 CPUID_PSE36 | CPUID_FXSR)
272#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
273#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
274 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
275 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
276 CPUID_PAE | CPUID_SEP | CPUID_APIC)
277
278#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
279 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
280 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
281 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
282 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
283 /* partly implemented:
284 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
285 /* missing:
286 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
287#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
288 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
289 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
290 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
291 /* missing:
292 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
293 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
294 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
295 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
296 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
297 CPUID_EXT_RDRAND */
298
299#ifdef TARGET_X86_64
300#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
301#else
302#define TCG_EXT2_X86_64_FEATURES 0
303#endif
304
305#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
306 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
307 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
308 TCG_EXT2_X86_64_FEATURES)
309#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
310 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
311#define TCG_EXT4_FEATURES 0
312#define TCG_SVM_FEATURES 0
313#define TCG_KVM_FEATURES 0
314#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
315 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
316 /* missing:
317 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
318 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
319 CPUID_7_0_EBX_RDSEED */
320
321
322typedef struct FeatureWordInfo {
323 const char **feat_names;
324 uint32_t cpuid_eax; /* Input EAX for CPUID */
325 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
326 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
327 int cpuid_reg; /* output register (R_* constant) */
328 uint32_t tcg_features; /* Feature flags supported by TCG */
329 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
330} FeatureWordInfo;
331
332static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
333 [FEAT_1_EDX] = {
334 .feat_names = feature_name,
335 .cpuid_eax = 1, .cpuid_reg = R_EDX,
336 .tcg_features = TCG_FEATURES,
337 },
338 [FEAT_1_ECX] = {
339 .feat_names = ext_feature_name,
340 .cpuid_eax = 1, .cpuid_reg = R_ECX,
341 .tcg_features = TCG_EXT_FEATURES,
342 },
343 [FEAT_8000_0001_EDX] = {
344 .feat_names = ext2_feature_name,
345 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
346 .tcg_features = TCG_EXT2_FEATURES,
347 },
348 [FEAT_8000_0001_ECX] = {
349 .feat_names = ext3_feature_name,
350 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
351 .tcg_features = TCG_EXT3_FEATURES,
352 },
353 [FEAT_C000_0001_EDX] = {
354 .feat_names = ext4_feature_name,
355 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
356 .tcg_features = TCG_EXT4_FEATURES,
357 },
358 [FEAT_KVM] = {
359 .feat_names = kvm_feature_name,
360 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
361 .tcg_features = TCG_KVM_FEATURES,
362 },
363 [FEAT_SVM] = {
364 .feat_names = svm_feature_name,
365 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
366 .tcg_features = TCG_SVM_FEATURES,
367 },
368 [FEAT_7_0_EBX] = {
369 .feat_names = cpuid_7_0_ebx_feature_name,
370 .cpuid_eax = 7,
371 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
372 .cpuid_reg = R_EBX,
373 .tcg_features = TCG_7_0_EBX_FEATURES,
374 },
375};
376
377typedef struct X86RegisterInfo32 {
378 /* Name of register */
379 const char *name;
380 /* QAPI enum value register */
381 X86CPURegister32 qapi_enum;
382} X86RegisterInfo32;
383
384#define REGISTER(reg) \
385 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
386static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
387 REGISTER(EAX),
388 REGISTER(ECX),
389 REGISTER(EDX),
390 REGISTER(EBX),
391 REGISTER(ESP),
392 REGISTER(EBP),
393 REGISTER(ESI),
394 REGISTER(EDI),
395};
396#undef REGISTER
397
398typedef struct ExtSaveArea {
399 uint32_t feature, bits;
400 uint32_t offset, size;
401} ExtSaveArea;
402
403static const ExtSaveArea ext_save_areas[] = {
404 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
405 .offset = 0x240, .size = 0x100 },
406 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
407 .offset = 0x3c0, .size = 0x40 },
408 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
409 .offset = 0x400, .size = 0x40 },
410};
411
412const char *get_register_name_32(unsigned int reg)
413{
414 if (reg >= CPU_NB_REGS32) {
415 return NULL;
416 }
417 return x86_reg_info_32[reg].name;
418}
419
420/* collects per-function cpuid data
421 */
422typedef struct model_features_t {
423 uint32_t *guest_feat;
424 uint32_t *host_feat;
425 FeatureWord feat_word;
426} model_features_t;
427
428/* KVM-specific features that are automatically added to all CPU models
429 * when KVM is enabled.
430 */
431static uint32_t kvm_default_features[FEATURE_WORDS] = {
432 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
433 (1 << KVM_FEATURE_NOP_IO_DELAY) |
434 (1 << KVM_FEATURE_CLOCKSOURCE2) |
435 (1 << KVM_FEATURE_ASYNC_PF) |
436 (1 << KVM_FEATURE_STEAL_TIME) |
437 (1 << KVM_FEATURE_PV_EOI) |
438 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
439 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
440};
441
442/* Features that are not added by default to any CPU model when KVM is enabled.
443 */
444static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
445 [FEAT_1_ECX] = CPUID_EXT_MONITOR,
446};
447
448void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
449{
450 kvm_default_features[w] &= ~features;
451}
452
453/*
454 * Returns the set of feature flags that are supported and migratable by
455 * QEMU, for a given FeatureWord.
456 */
457static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
458{
459 FeatureWordInfo *wi = &feature_word_info[w];
460 uint32_t r = 0;
461 int i;
462
463 for (i = 0; i < 32; i++) {
464 uint32_t f = 1U << i;
465 /* If the feature name is unknown, it is not supported by QEMU yet */
466 if (!wi->feat_names[i]) {
467 continue;
468 }
469 /* Skip features known to QEMU, but explicitly marked as unmigratable */
470 if (wi->unmigratable_flags & f) {
471 continue;
472 }
473 r |= f;
474 }
475 return r;
476}
477
478void host_cpuid(uint32_t function, uint32_t count,
479 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
480{
481 uint32_t vec[4];
482
483#ifdef __x86_64__
484 asm volatile("cpuid"
485 : "=a"(vec[0]), "=b"(vec[1]),
486 "=c"(vec[2]), "=d"(vec[3])
487 : "0"(function), "c"(count) : "cc");
488#elif defined(__i386__)
489 asm volatile("pusha \n\t"
490 "cpuid \n\t"
491 "mov %%eax, 0(%2) \n\t"
492 "mov %%ebx, 4(%2) \n\t"
493 "mov %%ecx, 8(%2) \n\t"
494 "mov %%edx, 12(%2) \n\t"
495 "popa"
496 : : "a"(function), "c"(count), "S"(vec)
497 : "memory", "cc");
498#else
499 abort();
500#endif
501
502 if (eax)
503 *eax = vec[0];
504 if (ebx)
505 *ebx = vec[1];
506 if (ecx)
507 *ecx = vec[2];
508 if (edx)
509 *edx = vec[3];
510}
511
512#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
513
514/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
515 * a substring. ex if !NULL points to the first char after a substring,
516 * otherwise the string is assumed to sized by a terminating nul.
517 * Return lexical ordering of *s1:*s2.
518 */
519static int sstrcmp(const char *s1, const char *e1, const char *s2,
520 const char *e2)
521{
522 for (;;) {
523 if (!*s1 || !*s2 || *s1 != *s2)
524 return (*s1 - *s2);
525 ++s1, ++s2;
526 if (s1 == e1 && s2 == e2)
527 return (0);
528 else if (s1 == e1)
529 return (*s2);
530 else if (s2 == e2)
531 return (*s1);
532 }
533}
534
535/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
536 * '|' delimited (possibly empty) strings in which case search for a match
537 * within the alternatives proceeds left to right. Return 0 for success,
538 * non-zero otherwise.
539 */
540static int altcmp(const char *s, const char *e, const char *altstr)
541{
542 const char *p, *q;
543
544 for (q = p = altstr; ; ) {
545 while (*p && *p != '|')
546 ++p;
547 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
548 return (0);
549 if (!*p)
550 return (1);
551 else
552 q = ++p;
553 }
554}
555
556/* search featureset for flag *[s..e), if found set corresponding bit in
557 * *pval and return true, otherwise return false
558 */
559static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
560 const char **featureset)
561{
562 uint32_t mask;
563 const char **ppc;
564 bool found = false;
565
566 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
567 if (*ppc && !altcmp(s, e, *ppc)) {
568 *pval |= mask;
569 found = true;
570 }
571 }
572 return found;
573}
574
575static void add_flagname_to_bitmaps(const char *flagname,
576 FeatureWordArray words)
577{
578 FeatureWord w;
579 for (w = 0; w < FEATURE_WORDS; w++) {
580 FeatureWordInfo *wi = &feature_word_info[w];
581 if (wi->feat_names &&
582 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
583 break;
584 }
585 }
586 if (w == FEATURE_WORDS) {
587 fprintf(stderr, "CPU feature %s not found\n", flagname);
588 }
589}
590
591/* CPU class name definitions: */
592
593#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
594#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
595
596/* Return type name for a given CPU model name
597 * Caller is responsible for freeing the returned string.
598 */
599static char *x86_cpu_type_name(const char *model_name)
600{
601 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
602}
603
604static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
605{
606 ObjectClass *oc;
607 char *typename;
608
609 if (cpu_model == NULL) {
610 return NULL;
611 }
612
613 typename = x86_cpu_type_name(cpu_model);
614 oc = object_class_by_name(typename);
615 g_free(typename);
616 return oc;
617}
618
619struct X86CPUDefinition {
620 const char *name;
621 uint32_t level;
622 uint32_t xlevel;
623 uint32_t xlevel2;
624 /* vendor is zero-terminated, 12 character ASCII string */
625 char vendor[CPUID_VENDOR_SZ + 1];
626 int family;
627 int model;
628 int stepping;
629 FeatureWordArray features;
630 char model_id[48];
631 bool cache_info_passthrough;
632};
633
634static X86CPUDefinition builtin_x86_defs[] = {
635 {
636 .name = "qemu64",
637 .level = 4,
638 .vendor = CPUID_VENDOR_AMD,
639 .family = 6,
640 .model = 6,
641 .stepping = 3,
642 .features[FEAT_1_EDX] =
643 PPRO_FEATURES |
644 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
645 CPUID_PSE36,
646 .features[FEAT_1_ECX] =
647 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
648 .features[FEAT_8000_0001_EDX] =
649 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
650 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
651 .features[FEAT_8000_0001_ECX] =
652 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
653 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
654 .xlevel = 0x8000000A,
655 },
656 {
657 .name = "phenom",
658 .level = 5,
659 .vendor = CPUID_VENDOR_AMD,
660 .family = 16,
661 .model = 2,
662 .stepping = 3,
663 .features[FEAT_1_EDX] =
664 PPRO_FEATURES |
665 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
666 CPUID_PSE36 | CPUID_VME | CPUID_HT,
667 .features[FEAT_1_ECX] =
668 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
669 CPUID_EXT_POPCNT,
670 .features[FEAT_8000_0001_EDX] =
671 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
672 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
673 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
674 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
675 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
676 CPUID_EXT3_CR8LEG,
677 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
678 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
679 .features[FEAT_8000_0001_ECX] =
680 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
681 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
682 .features[FEAT_SVM] =
683 CPUID_SVM_NPT | CPUID_SVM_LBRV,
684 .xlevel = 0x8000001A,
685 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
686 },
687 {
688 .name = "core2duo",
689 .level = 10,
690 .vendor = CPUID_VENDOR_INTEL,
691 .family = 6,
692 .model = 15,
693 .stepping = 11,
694 .features[FEAT_1_EDX] =
695 PPRO_FEATURES |
696 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
697 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
698 CPUID_HT | CPUID_TM | CPUID_PBE,
699 .features[FEAT_1_ECX] =
700 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
701 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
702 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
703 .features[FEAT_8000_0001_EDX] =
704 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
705 .features[FEAT_8000_0001_ECX] =
706 CPUID_EXT3_LAHF_LM,
707 .xlevel = 0x80000008,
708 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
709 },
710 {
711 .name = "kvm64",
712 .level = 5,
713 .vendor = CPUID_VENDOR_INTEL,
714 .family = 15,
715 .model = 6,
716 .stepping = 1,
717 /* Missing: CPUID_VME, CPUID_HT */
718 .features[FEAT_1_EDX] =
719 PPRO_FEATURES |
720 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
721 CPUID_PSE36,
722 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
723 .features[FEAT_1_ECX] =
724 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
725 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
726 .features[FEAT_8000_0001_EDX] =
727 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
728 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
729 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
730 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
731 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
732 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
733 .features[FEAT_8000_0001_ECX] =
734 0,
735 .xlevel = 0x80000008,
736 .model_id = "Common KVM processor"
737 },
738 {
739 .name = "qemu32",
740 .level = 4,
741 .vendor = CPUID_VENDOR_INTEL,
742 .family = 6,
743 .model = 6,
744 .stepping = 3,
745 .features[FEAT_1_EDX] =
746 PPRO_FEATURES,
747 .features[FEAT_1_ECX] =
748 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
749 .xlevel = 0x80000004,
750 },
751 {
752 .name = "kvm32",
753 .level = 5,
754 .vendor = CPUID_VENDOR_INTEL,
755 .family = 15,
756 .model = 6,
757 .stepping = 1,
758 .features[FEAT_1_EDX] =
759 PPRO_FEATURES |
760 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
761 .features[FEAT_1_ECX] =
762 CPUID_EXT_SSE3,
763 .features[FEAT_8000_0001_EDX] =
764 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
765 .features[FEAT_8000_0001_ECX] =
766 0,
767 .xlevel = 0x80000008,
768 .model_id = "Common 32-bit KVM processor"
769 },
770 {
771 .name = "coreduo",
772 .level = 10,
773 .vendor = CPUID_VENDOR_INTEL,
774 .family = 6,
775 .model = 14,
776 .stepping = 8,
777 .features[FEAT_1_EDX] =
778 PPRO_FEATURES | CPUID_VME |
779 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
780 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
781 .features[FEAT_1_ECX] =
782 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
783 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
784 .features[FEAT_8000_0001_EDX] =
785 CPUID_EXT2_NX,
786 .xlevel = 0x80000008,
787 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
788 },
789 {
790 .name = "486",
791 .level = 1,
792 .vendor = CPUID_VENDOR_INTEL,
793 .family = 4,
794 .model = 8,
795 .stepping = 0,
796 .features[FEAT_1_EDX] =
797 I486_FEATURES,
798 .xlevel = 0,
799 },
800 {
801 .name = "pentium",
802 .level = 1,
803 .vendor = CPUID_VENDOR_INTEL,
804 .family = 5,
805 .model = 4,
806 .stepping = 3,
807 .features[FEAT_1_EDX] =
808 PENTIUM_FEATURES,
809 .xlevel = 0,
810 },
811 {
812 .name = "pentium2",
813 .level = 2,
814 .vendor = CPUID_VENDOR_INTEL,
815 .family = 6,
816 .model = 5,
817 .stepping = 2,
818 .features[FEAT_1_EDX] =
819 PENTIUM2_FEATURES,
820 .xlevel = 0,
821 },
822 {
823 .name = "pentium3",
824 .level = 2,
825 .vendor = CPUID_VENDOR_INTEL,
826 .family = 6,
827 .model = 7,
828 .stepping = 3,
829 .features[FEAT_1_EDX] =
830 PENTIUM3_FEATURES,
831 .xlevel = 0,
832 },
833 {
834 .name = "athlon",
835 .level = 2,
836 .vendor = CPUID_VENDOR_AMD,
837 .family = 6,
838 .model = 2,
839 .stepping = 3,
840 .features[FEAT_1_EDX] =
841 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
842 CPUID_MCA,
843 .features[FEAT_8000_0001_EDX] =
844 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
845 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
846 .xlevel = 0x80000008,
847 },
848 {
849 .name = "n270",
850 /* original is on level 10 */
851 .level = 5,
852 .vendor = CPUID_VENDOR_INTEL,
853 .family = 6,
854 .model = 28,
855 .stepping = 2,
856 .features[FEAT_1_EDX] =
857 PPRO_FEATURES |
858 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
859 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
860 /* Some CPUs got no CPUID_SEP */
861 .features[FEAT_1_ECX] =
862 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
863 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
864 CPUID_EXT_MOVBE,
865 .features[FEAT_8000_0001_EDX] =
866 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
867 CPUID_EXT2_NX,
868 .features[FEAT_8000_0001_ECX] =
869 CPUID_EXT3_LAHF_LM,
870 .xlevel = 0x8000000A,
871 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
872 },
873 {
874 .name = "Conroe",
875 .level = 4,
876 .vendor = CPUID_VENDOR_INTEL,
877 .family = 6,
878 .model = 15,
879 .stepping = 3,
880 .features[FEAT_1_EDX] =
881 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
882 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
883 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
884 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
885 CPUID_DE | CPUID_FP87,
886 .features[FEAT_1_ECX] =
887 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
888 .features[FEAT_8000_0001_EDX] =
889 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
890 .features[FEAT_8000_0001_ECX] =
891 CPUID_EXT3_LAHF_LM,
892 .xlevel = 0x8000000A,
893 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
894 },
895 {
896 .name = "Penryn",
897 .level = 4,
898 .vendor = CPUID_VENDOR_INTEL,
899 .family = 6,
900 .model = 23,
901 .stepping = 3,
902 .features[FEAT_1_EDX] =
903 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
904 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
905 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
906 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
907 CPUID_DE | CPUID_FP87,
908 .features[FEAT_1_ECX] =
909 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
910 CPUID_EXT_SSE3,
911 .features[FEAT_8000_0001_EDX] =
912 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
913 .features[FEAT_8000_0001_ECX] =
914 CPUID_EXT3_LAHF_LM,
915 .xlevel = 0x8000000A,
916 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
917 },
918 {
919 .name = "Nehalem",
920 .level = 4,
921 .vendor = CPUID_VENDOR_INTEL,
922 .family = 6,
923 .model = 26,
924 .stepping = 3,
925 .features[FEAT_1_EDX] =
926 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
927 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
928 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
929 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
930 CPUID_DE | CPUID_FP87,
931 .features[FEAT_1_ECX] =
932 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
933 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
934 .features[FEAT_8000_0001_EDX] =
935 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
936 .features[FEAT_8000_0001_ECX] =
937 CPUID_EXT3_LAHF_LM,
938 .xlevel = 0x8000000A,
939 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
940 },
941 {
942 .name = "Westmere",
943 .level = 11,
944 .vendor = CPUID_VENDOR_INTEL,
945 .family = 6,
946 .model = 44,
947 .stepping = 1,
948 .features[FEAT_1_EDX] =
949 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
950 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
951 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
952 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
953 CPUID_DE | CPUID_FP87,
954 .features[FEAT_1_ECX] =
955 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
956 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
957 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
958 .features[FEAT_8000_0001_EDX] =
959 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
960 .features[FEAT_8000_0001_ECX] =
961 CPUID_EXT3_LAHF_LM,
962 .xlevel = 0x8000000A,
963 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
964 },
965 {
966 .name = "SandyBridge",
967 .level = 0xd,
968 .vendor = CPUID_VENDOR_INTEL,
969 .family = 6,
970 .model = 42,
971 .stepping = 1,
972 .features[FEAT_1_EDX] =
973 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
974 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
975 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
976 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
977 CPUID_DE | CPUID_FP87,
978 .features[FEAT_1_ECX] =
979 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
980 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
981 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
982 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
983 CPUID_EXT_SSE3,
984 .features[FEAT_8000_0001_EDX] =
985 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
986 CPUID_EXT2_SYSCALL,
987 .features[FEAT_8000_0001_ECX] =
988 CPUID_EXT3_LAHF_LM,
989 .xlevel = 0x8000000A,
990 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
991 },
992 {
993 .name = "Haswell",
994 .level = 0xd,
995 .vendor = CPUID_VENDOR_INTEL,
996 .family = 6,
997 .model = 60,
998 .stepping = 1,
999 .features[FEAT_1_EDX] =
1000 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1001 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1002 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1003 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1004 CPUID_DE | CPUID_FP87,
1005 .features[FEAT_1_ECX] =
1006 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1007 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1008 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1009 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1010 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1011 CPUID_EXT_PCID,
1012 .features[FEAT_8000_0001_EDX] =
1013 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1014 CPUID_EXT2_SYSCALL,
1015 .features[FEAT_8000_0001_ECX] =
1016 CPUID_EXT3_LAHF_LM,
1017 .features[FEAT_7_0_EBX] =
1018 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1019 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1020 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1021 CPUID_7_0_EBX_RTM,
1022 .xlevel = 0x8000000A,
1023 .model_id = "Intel Core Processor (Haswell)",
1024 },
1025 {
1026 .name = "Opteron_G1",
1027 .level = 5,
1028 .vendor = CPUID_VENDOR_AMD,
1029 .family = 15,
1030 .model = 6,
1031 .stepping = 1,
1032 .features[FEAT_1_EDX] =
1033 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1034 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1035 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1036 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1037 CPUID_DE | CPUID_FP87,
1038 .features[FEAT_1_ECX] =
1039 CPUID_EXT_SSE3,
1040 .features[FEAT_8000_0001_EDX] =
1041 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1042 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1043 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1044 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1045 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1046 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1047 .xlevel = 0x80000008,
1048 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1049 },
1050 {
1051 .name = "Opteron_G2",
1052 .level = 5,
1053 .vendor = CPUID_VENDOR_AMD,
1054 .family = 15,
1055 .model = 6,
1056 .stepping = 1,
1057 .features[FEAT_1_EDX] =
1058 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1059 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1060 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1061 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1062 CPUID_DE | CPUID_FP87,
1063 .features[FEAT_1_ECX] =
1064 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1065 .features[FEAT_8000_0001_EDX] =
1066 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1067 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1068 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1069 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1070 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1071 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1072 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1073 .features[FEAT_8000_0001_ECX] =
1074 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1075 .xlevel = 0x80000008,
1076 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1077 },
1078 {
1079 .name = "Opteron_G3",
1080 .level = 5,
1081 .vendor = CPUID_VENDOR_AMD,
1082 .family = 15,
1083 .model = 6,
1084 .stepping = 1,
1085 .features[FEAT_1_EDX] =
1086 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1087 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1088 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1089 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1090 CPUID_DE | CPUID_FP87,
1091 .features[FEAT_1_ECX] =
1092 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1093 CPUID_EXT_SSE3,
1094 .features[FEAT_8000_0001_EDX] =
1095 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1096 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1097 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1098 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1099 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1100 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1101 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1102 .features[FEAT_8000_0001_ECX] =
1103 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1104 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1105 .xlevel = 0x80000008,
1106 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1107 },
1108 {
1109 .name = "Opteron_G4",
1110 .level = 0xd,
1111 .vendor = CPUID_VENDOR_AMD,
1112 .family = 21,
1113 .model = 1,
1114 .stepping = 2,
1115 .features[FEAT_1_EDX] =
1116 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1117 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1118 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1119 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1120 CPUID_DE | CPUID_FP87,
1121 .features[FEAT_1_ECX] =
1122 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1123 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1124 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1125 CPUID_EXT_SSE3,
1126 .features[FEAT_8000_0001_EDX] =
1127 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1128 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1129 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1130 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1131 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1132 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1133 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1134 .features[FEAT_8000_0001_ECX] =
1135 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1136 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1137 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1138 CPUID_EXT3_LAHF_LM,
1139 .xlevel = 0x8000001A,
1140 .model_id = "AMD Opteron 62xx class CPU",
1141 },
1142 {
1143 .name = "Opteron_G5",
1144 .level = 0xd,
1145 .vendor = CPUID_VENDOR_AMD,
1146 .family = 21,
1147 .model = 2,
1148 .stepping = 0,
1149 .features[FEAT_1_EDX] =
1150 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1151 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1152 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1153 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1154 CPUID_DE | CPUID_FP87,
1155 .features[FEAT_1_ECX] =
1156 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1157 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1158 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1159 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1160 .features[FEAT_8000_0001_EDX] =
1161 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1162 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1163 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1164 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1165 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1166 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1167 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1168 .features[FEAT_8000_0001_ECX] =
1169 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1170 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1171 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1172 CPUID_EXT3_LAHF_LM,
1173 .xlevel = 0x8000001A,
1174 .model_id = "AMD Opteron 63xx class CPU",
1175 },
1176};
1177
1178/**
1179 * x86_cpu_compat_set_features:
1180 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1181 * @w: Identifies the feature word to be changed.
1182 * @feat_add: Feature bits to be added to feature word
1183 * @feat_remove: Feature bits to be removed from feature word
1184 *
1185 * Change CPU model feature bits for compatibility.
1186 *
1187 * This function may be used by machine-type compatibility functions
1188 * to enable or disable feature bits on specific CPU models.
1189 */
1190void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1191 uint32_t feat_add, uint32_t feat_remove)
1192{
1193 X86CPUDefinition *def;
1194 int i;
1195 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1196 def = &builtin_x86_defs[i];
1197 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1198 def->features[w] |= feat_add;
1199 def->features[w] &= ~feat_remove;
1200 }
1201 }
1202}
1203
1204#ifdef CONFIG_KVM
1205
1206static int cpu_x86_fill_model_id(char *str)
1207{
1208 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1209 int i;
1210
1211 for (i = 0; i < 3; i++) {
1212 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1213 memcpy(str + i * 16 + 0, &eax, 4);
1214 memcpy(str + i * 16 + 4, &ebx, 4);
1215 memcpy(str + i * 16 + 8, &ecx, 4);
1216 memcpy(str + i * 16 + 12, &edx, 4);
1217 }
1218 return 0;
1219}
1220
1221static X86CPUDefinition host_cpudef;
1222
1223static Property host_x86_cpu_properties[] = {
1224 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, false),
1225 DEFINE_PROP_END_OF_LIST()
1226};
1227
1228/* class_init for the "host" CPU model
1229 *
1230 * This function may be called before KVM is initialized.
1231 */
1232static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1233{
1234 DeviceClass *dc = DEVICE_CLASS(oc);
1235 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1236 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1237
1238 xcc->kvm_required = true;
1239
1240 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1241 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1242
1243 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1244 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1245 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1246 host_cpudef.stepping = eax & 0x0F;
1247
1248 cpu_x86_fill_model_id(host_cpudef.model_id);
1249
1250 xcc->cpu_def = &host_cpudef;
1251 host_cpudef.cache_info_passthrough = true;
1252
1253 /* level, xlevel, xlevel2, and the feature words are initialized on
1254 * instance_init, because they require KVM to be initialized.
1255 */
1256
1257 dc->props = host_x86_cpu_properties;
1258}
1259
1260static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1261 bool migratable_only);
1262
1263static void host_x86_cpu_initfn(Object *obj)
1264{
1265 X86CPU *cpu = X86_CPU(obj);
1266 CPUX86State *env = &cpu->env;
1267 KVMState *s = kvm_state;
1268 FeatureWord w;
1269
1270 assert(kvm_enabled());
1271
1272 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1273 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1274 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1275
1276 for (w = 0; w < FEATURE_WORDS; w++) {
1277 env->features[w] =
1278 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1279 }
1280 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1281}
1282
1283static const TypeInfo host_x86_cpu_type_info = {
1284 .name = X86_CPU_TYPE_NAME("host"),
1285 .parent = TYPE_X86_CPU,
1286 .instance_init = host_x86_cpu_initfn,
1287 .class_init = host_x86_cpu_class_init,
1288};
1289
1290#endif
1291
1292static void report_unavailable_features(FeatureWord w, uint32_t mask)
1293{
1294 FeatureWordInfo *f = &feature_word_info[w];
1295 int i;
1296
1297 for (i = 0; i < 32; ++i) {
1298 if (1 << i & mask) {
1299 const char *reg = get_register_name_32(f->cpuid_reg);
1300 assert(reg);
1301 fprintf(stderr, "warning: %s doesn't support requested feature: "
1302 "CPUID.%02XH:%s%s%s [bit %d]\n",
1303 kvm_enabled() ? "host" : "TCG",
1304 f->cpuid_eax, reg,
1305 f->feat_names[i] ? "." : "",
1306 f->feat_names[i] ? f->feat_names[i] : "", i);
1307 }
1308 }
1309}
1310
1311static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1312 const char *name, Error **errp)
1313{
1314 X86CPU *cpu = X86_CPU(obj);
1315 CPUX86State *env = &cpu->env;
1316 int64_t value;
1317
1318 value = (env->cpuid_version >> 8) & 0xf;
1319 if (value == 0xf) {
1320 value += (env->cpuid_version >> 20) & 0xff;
1321 }
1322 visit_type_int(v, &value, name, errp);
1323}
1324
1325static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1326 const char *name, Error **errp)
1327{
1328 X86CPU *cpu = X86_CPU(obj);
1329 CPUX86State *env = &cpu->env;
1330 const int64_t min = 0;
1331 const int64_t max = 0xff + 0xf;
1332 Error *local_err = NULL;
1333 int64_t value;
1334
1335 visit_type_int(v, &value, name, &local_err);
1336 if (local_err) {
1337 error_propagate(errp, local_err);
1338 return;
1339 }
1340 if (value < min || value > max) {
1341 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1342 name ? name : "null", value, min, max);
1343 return;
1344 }
1345
1346 env->cpuid_version &= ~0xff00f00;
1347 if (value > 0x0f) {
1348 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1349 } else {
1350 env->cpuid_version |= value << 8;
1351 }
1352}
1353
1354static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1355 const char *name, Error **errp)
1356{
1357 X86CPU *cpu = X86_CPU(obj);
1358 CPUX86State *env = &cpu->env;
1359 int64_t value;
1360
1361 value = (env->cpuid_version >> 4) & 0xf;
1362 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1363 visit_type_int(v, &value, name, errp);
1364}
1365
1366static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1367 const char *name, Error **errp)
1368{
1369 X86CPU *cpu = X86_CPU(obj);
1370 CPUX86State *env = &cpu->env;
1371 const int64_t min = 0;
1372 const int64_t max = 0xff;
1373 Error *local_err = NULL;
1374 int64_t value;
1375
1376 visit_type_int(v, &value, name, &local_err);
1377 if (local_err) {
1378 error_propagate(errp, local_err);
1379 return;
1380 }
1381 if (value < min || value > max) {
1382 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1383 name ? name : "null", value, min, max);
1384 return;
1385 }
1386
1387 env->cpuid_version &= ~0xf00f0;
1388 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1389}
1390
1391static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1392 void *opaque, const char *name,
1393 Error **errp)
1394{
1395 X86CPU *cpu = X86_CPU(obj);
1396 CPUX86State *env = &cpu->env;
1397 int64_t value;
1398
1399 value = env->cpuid_version & 0xf;
1400 visit_type_int(v, &value, name, errp);
1401}
1402
1403static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1404 void *opaque, const char *name,
1405 Error **errp)
1406{
1407 X86CPU *cpu = X86_CPU(obj);
1408 CPUX86State *env = &cpu->env;
1409 const int64_t min = 0;
1410 const int64_t max = 0xf;
1411 Error *local_err = NULL;
1412 int64_t value;
1413
1414 visit_type_int(v, &value, name, &local_err);
1415 if (local_err) {
1416 error_propagate(errp, local_err);
1417 return;
1418 }
1419 if (value < min || value > max) {
1420 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1421 name ? name : "null", value, min, max);
1422 return;
1423 }
1424
1425 env->cpuid_version &= ~0xf;
1426 env->cpuid_version |= value & 0xf;
1427}
1428
1429static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1430 const char *name, Error **errp)
1431{
1432 X86CPU *cpu = X86_CPU(obj);
1433
1434 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1435}
1436
1437static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1438 const char *name, Error **errp)
1439{
1440 X86CPU *cpu = X86_CPU(obj);
1441
1442 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1443}
1444
1445static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1446 const char *name, Error **errp)
1447{
1448 X86CPU *cpu = X86_CPU(obj);
1449
1450 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1451}
1452
1453static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1454 const char *name, Error **errp)
1455{
1456 X86CPU *cpu = X86_CPU(obj);
1457
1458 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1459}
1460
1461static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1462{
1463 X86CPU *cpu = X86_CPU(obj);
1464 CPUX86State *env = &cpu->env;
1465 char *value;
1466
1467 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1468 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1469 env->cpuid_vendor3);
1470 return value;
1471}
1472
1473static void x86_cpuid_set_vendor(Object *obj, const char *value,
1474 Error **errp)
1475{
1476 X86CPU *cpu = X86_CPU(obj);
1477 CPUX86State *env = &cpu->env;
1478 int i;
1479
1480 if (strlen(value) != CPUID_VENDOR_SZ) {
1481 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1482 "vendor", value);
1483 return;
1484 }
1485
1486 env->cpuid_vendor1 = 0;
1487 env->cpuid_vendor2 = 0;
1488 env->cpuid_vendor3 = 0;
1489 for (i = 0; i < 4; i++) {
1490 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1491 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1492 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1493 }
1494}
1495
1496static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1497{
1498 X86CPU *cpu = X86_CPU(obj);
1499 CPUX86State *env = &cpu->env;
1500 char *value;
1501 int i;
1502
1503 value = g_malloc(48 + 1);
1504 for (i = 0; i < 48; i++) {
1505 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1506 }
1507 value[48] = '\0';
1508 return value;
1509}
1510
1511static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1512 Error **errp)
1513{
1514 X86CPU *cpu = X86_CPU(obj);
1515 CPUX86State *env = &cpu->env;
1516 int c, len, i;
1517
1518 if (model_id == NULL) {
1519 model_id = "";
1520 }
1521 len = strlen(model_id);
1522 memset(env->cpuid_model, 0, 48);
1523 for (i = 0; i < 48; i++) {
1524 if (i >= len) {
1525 c = '\0';
1526 } else {
1527 c = (uint8_t)model_id[i];
1528 }
1529 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1530 }
1531}
1532
1533static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1534 const char *name, Error **errp)
1535{
1536 X86CPU *cpu = X86_CPU(obj);
1537 int64_t value;
1538
1539 value = cpu->env.tsc_khz * 1000;
1540 visit_type_int(v, &value, name, errp);
1541}
1542
1543static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1544 const char *name, Error **errp)
1545{
1546 X86CPU *cpu = X86_CPU(obj);
1547 const int64_t min = 0;
1548 const int64_t max = INT64_MAX;
1549 Error *local_err = NULL;
1550 int64_t value;
1551
1552 visit_type_int(v, &value, name, &local_err);
1553 if (local_err) {
1554 error_propagate(errp, local_err);
1555 return;
1556 }
1557 if (value < min || value > max) {
1558 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1559 name ? name : "null", value, min, max);
1560 return;
1561 }
1562
1563 cpu->env.tsc_khz = value / 1000;
1564}
1565
1566static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1567 const char *name, Error **errp)
1568{
1569 X86CPU *cpu = X86_CPU(obj);
1570 int64_t value = cpu->env.cpuid_apic_id;
1571
1572 visit_type_int(v, &value, name, errp);
1573}
1574
1575static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1576 const char *name, Error **errp)
1577{
1578 X86CPU *cpu = X86_CPU(obj);
1579 DeviceState *dev = DEVICE(obj);
1580 const int64_t min = 0;
1581 const int64_t max = UINT32_MAX;
1582 Error *error = NULL;
1583 int64_t value;
1584
1585 if (dev->realized) {
1586 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1587 "it was realized", name, object_get_typename(obj));
1588 return;
1589 }
1590
1591 visit_type_int(v, &value, name, &error);
1592 if (error) {
1593 error_propagate(errp, error);
1594 return;
1595 }
1596 if (value < min || value > max) {
1597 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1598 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1599 object_get_typename(obj), name, value, min, max);
1600 return;
1601 }
1602
1603 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1604 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1605 return;
1606 }
1607 cpu->env.cpuid_apic_id = value;
1608}
1609
1610/* Generic getter for "feature-words" and "filtered-features" properties */
1611static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1612 const char *name, Error **errp)
1613{
1614 uint32_t *array = (uint32_t *)opaque;
1615 FeatureWord w;
1616 Error *err = NULL;
1617 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1618 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1619 X86CPUFeatureWordInfoList *list = NULL;
1620
1621 for (w = 0; w < FEATURE_WORDS; w++) {
1622 FeatureWordInfo *wi = &feature_word_info[w];
1623 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1624 qwi->cpuid_input_eax = wi->cpuid_eax;
1625 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1626 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1627 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1628 qwi->features = array[w];
1629
1630 /* List will be in reverse order, but order shouldn't matter */
1631 list_entries[w].next = list;
1632 list_entries[w].value = &word_infos[w];
1633 list = &list_entries[w];
1634 }
1635
1636 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1637 error_propagate(errp, err);
1638}
1639
1640static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1641 const char *name, Error **errp)
1642{
1643 X86CPU *cpu = X86_CPU(obj);
1644 int64_t value = cpu->hyperv_spinlock_attempts;
1645
1646 visit_type_int(v, &value, name, errp);
1647}
1648
1649static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1650 const char *name, Error **errp)
1651{
1652 const int64_t min = 0xFFF;
1653 const int64_t max = UINT_MAX;
1654 X86CPU *cpu = X86_CPU(obj);
1655 Error *err = NULL;
1656 int64_t value;
1657
1658 visit_type_int(v, &value, name, &err);
1659 if (err) {
1660 error_propagate(errp, err);
1661 return;
1662 }
1663
1664 if (value < min || value > max) {
1665 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1666 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1667 object_get_typename(obj), name ? name : "null",
1668 value, min, max);
1669 return;
1670 }
1671 cpu->hyperv_spinlock_attempts = value;
1672}
1673
1674static PropertyInfo qdev_prop_spinlocks = {
1675 .name = "int",
1676 .get = x86_get_hv_spinlocks,
1677 .set = x86_set_hv_spinlocks,
1678};
1679
1680/* Convert all '_' in a feature string option name to '-', to make feature
1681 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1682 */
1683static inline void feat2prop(char *s)
1684{
1685 while ((s = strchr(s, '_'))) {
1686 *s = '-';
1687 }
1688}
1689
1690/* Parse "+feature,-feature,feature=foo" CPU feature string
1691 */
1692static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1693 Error **errp)
1694{
1695 X86CPU *cpu = X86_CPU(cs);
1696 char *featurestr; /* Single 'key=value" string being parsed */
1697 FeatureWord w;
1698 /* Features to be added */
1699 FeatureWordArray plus_features = { 0 };
1700 /* Features to be removed */
1701 FeatureWordArray minus_features = { 0 };
1702 uint32_t numvalue;
1703 CPUX86State *env = &cpu->env;
1704 Error *local_err = NULL;
1705
1706 featurestr = features ? strtok(features, ",") : NULL;
1707
1708 while (featurestr) {
1709 char *val;
1710 if (featurestr[0] == '+') {
1711 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1712 } else if (featurestr[0] == '-') {
1713 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1714 } else if ((val = strchr(featurestr, '='))) {
1715 *val = 0; val++;
1716 feat2prop(featurestr);
1717 if (!strcmp(featurestr, "xlevel")) {
1718 char *err;
1719 char num[32];
1720
1721 numvalue = strtoul(val, &err, 0);
1722 if (!*val || *err) {
1723 error_setg(errp, "bad numerical value %s", val);
1724 return;
1725 }
1726 if (numvalue < 0x80000000) {
1727 error_report("xlevel value shall always be >= 0x80000000"
1728 ", fixup will be removed in future versions");
1729 numvalue += 0x80000000;
1730 }
1731 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1732 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1733 } else if (!strcmp(featurestr, "tsc-freq")) {
1734 int64_t tsc_freq;
1735 char *err;
1736 char num[32];
1737
1738 tsc_freq = strtosz_suffix_unit(val, &err,
1739 STRTOSZ_DEFSUFFIX_B, 1000);
1740 if (tsc_freq < 0 || *err) {
1741 error_setg(errp, "bad numerical value %s", val);
1742 return;
1743 }
1744 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1745 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1746 &local_err);
1747 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1748 char *err;
1749 const int min = 0xFFF;
1750 char num[32];
1751 numvalue = strtoul(val, &err, 0);
1752 if (!*val || *err) {
1753 error_setg(errp, "bad numerical value %s", val);
1754 return;
1755 }
1756 if (numvalue < min) {
1757 error_report("hv-spinlocks value shall always be >= 0x%x"
1758 ", fixup will be removed in future versions",
1759 min);
1760 numvalue = min;
1761 }
1762 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1763 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1764 } else {
1765 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1766 }
1767 } else {
1768 feat2prop(featurestr);
1769 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1770 }
1771 if (local_err) {
1772 error_propagate(errp, local_err);
1773 return;
1774 }
1775 featurestr = strtok(NULL, ",");
1776 }
1777
1778 for (w = 0; w < FEATURE_WORDS; w++) {
1779 env->features[w] |= plus_features[w];
1780 env->features[w] &= ~minus_features[w];
1781 }
1782}
1783
1784/* generate a composite string into buf of all cpuid names in featureset
1785 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1786 * if flags, suppress names undefined in featureset.
1787 */
1788static void listflags(char *buf, int bufsize, uint32_t fbits,
1789 const char **featureset, uint32_t flags)
1790{
1791 const char **p = &featureset[31];
1792 char *q, *b, bit;
1793 int nc;
1794
1795 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1796 *buf = '\0';
1797 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1798 if (fbits & 1 << bit && (*p || !flags)) {
1799 if (*p)
1800 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1801 else
1802 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1803 if (bufsize <= nc) {
1804 if (b) {
1805 memcpy(b, "...", sizeof("..."));
1806 }
1807 return;
1808 }
1809 q += nc;
1810 bufsize -= nc;
1811 }
1812}
1813
1814/* generate CPU information. */
1815void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1816{
1817 X86CPUDefinition *def;
1818 char buf[256];
1819 int i;
1820
1821 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1822 def = &builtin_x86_defs[i];
1823 snprintf(buf, sizeof(buf), "%s", def->name);
1824 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1825 }
1826#ifdef CONFIG_KVM
1827 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1828 "KVM processor with all supported host features "
1829 "(only available in KVM mode)");
1830#endif
1831
1832 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1833 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1834 FeatureWordInfo *fw = &feature_word_info[i];
1835
1836 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1837 (*cpu_fprintf)(f, " %s\n", buf);
1838 }
1839}
1840
1841CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1842{
1843 CpuDefinitionInfoList *cpu_list = NULL;
1844 X86CPUDefinition *def;
1845 int i;
1846
1847 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1848 CpuDefinitionInfoList *entry;
1849 CpuDefinitionInfo *info;
1850
1851 def = &builtin_x86_defs[i];
1852 info = g_malloc0(sizeof(*info));
1853 info->name = g_strdup(def->name);
1854
1855 entry = g_malloc0(sizeof(*entry));
1856 entry->value = info;
1857 entry->next = cpu_list;
1858 cpu_list = entry;
1859 }
1860
1861 return cpu_list;
1862}
1863
1864static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1865 bool migratable_only)
1866{
1867 FeatureWordInfo *wi = &feature_word_info[w];
1868 uint32_t r;
1869
1870 if (kvm_enabled()) {
1871 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1872 wi->cpuid_ecx,
1873 wi->cpuid_reg);
1874 } else if (tcg_enabled()) {
1875 r = wi->tcg_features;
1876 } else {
1877 return ~0;
1878 }
1879 if (migratable_only) {
1880 r &= x86_cpu_get_migratable_flags(w);
1881 }
1882 return r;
1883}
1884
1885/*
1886 * Filters CPU feature words based on host availability of each feature.
1887 *
1888 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1889 */
1890static int x86_cpu_filter_features(X86CPU *cpu)
1891{
1892 CPUX86State *env = &cpu->env;
1893 FeatureWord w;
1894 int rv = 0;
1895
1896 for (w = 0; w < FEATURE_WORDS; w++) {
1897 uint32_t host_feat =
1898 x86_cpu_get_supported_feature_word(w, cpu->migratable);
1899 uint32_t requested_features = env->features[w];
1900 env->features[w] &= host_feat;
1901 cpu->filtered_features[w] = requested_features & ~env->features[w];
1902 if (cpu->filtered_features[w]) {
1903 if (cpu->check_cpuid || cpu->enforce_cpuid) {
1904 report_unavailable_features(w, cpu->filtered_features[w]);
1905 }
1906 rv = 1;
1907 }
1908 }
1909
1910 return rv;
1911}
1912
1913/* Load data from X86CPUDefinition
1914 */
1915static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1916{
1917 CPUX86State *env = &cpu->env;
1918 const char *vendor;
1919 char host_vendor[CPUID_VENDOR_SZ + 1];
1920 FeatureWord w;
1921
1922 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1923 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1924 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1925 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1926 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1927 env->cpuid_xlevel2 = def->xlevel2;
1928 cpu->cache_info_passthrough = def->cache_info_passthrough;
1929 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1930 for (w = 0; w < FEATURE_WORDS; w++) {
1931 env->features[w] = def->features[w];
1932 }
1933
1934 /* Special cases not set in the X86CPUDefinition structs: */
1935 if (kvm_enabled()) {
1936 FeatureWord w;
1937 for (w = 0; w < FEATURE_WORDS; w++) {
1938 env->features[w] |= kvm_default_features[w];
1939 env->features[w] &= ~kvm_default_unset_features[w];
1940 }
1941 }
1942
1943 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1944
1945 /* sysenter isn't supported in compatibility mode on AMD,
1946 * syscall isn't supported in compatibility mode on Intel.
1947 * Normally we advertise the actual CPU vendor, but you can
1948 * override this using the 'vendor' property if you want to use
1949 * KVM's sysenter/syscall emulation in compatibility mode and
1950 * when doing cross vendor migration
1951 */
1952 vendor = def->vendor;
1953 if (kvm_enabled()) {
1954 uint32_t ebx = 0, ecx = 0, edx = 0;
1955 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1956 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1957 vendor = host_vendor;
1958 }
1959
1960 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1961
1962}
1963
1964X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1965 Error **errp)
1966{
1967 X86CPU *cpu = NULL;
1968 X86CPUClass *xcc;
1969 ObjectClass *oc;
1970 gchar **model_pieces;
1971 char *name, *features;
1972 Error *error = NULL;
1973
1974 model_pieces = g_strsplit(cpu_model, ",", 2);
1975 if (!model_pieces[0]) {
1976 error_setg(&error, "Invalid/empty CPU model name");
1977 goto out;
1978 }
1979 name = model_pieces[0];
1980 features = model_pieces[1];
1981
1982 oc = x86_cpu_class_by_name(name);
1983 if (oc == NULL) {
1984 error_setg(&error, "Unable to find CPU definition: %s", name);
1985 goto out;
1986 }
1987 xcc = X86_CPU_CLASS(oc);
1988
1989 if (xcc->kvm_required && !kvm_enabled()) {
1990 error_setg(&error, "CPU model '%s' requires KVM", name);
1991 goto out;
1992 }
1993
1994 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1995
1996#ifndef CONFIG_USER_ONLY
1997 if (icc_bridge == NULL) {
1998 error_setg(&error, "Invalid icc-bridge value");
1999 goto out;
2000 }
2001 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
2002 object_unref(OBJECT(cpu));
2003#endif
2004
2005 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
2006 if (error) {
2007 goto out;
2008 }
2009
2010out:
2011 if (error != NULL) {
2012 error_propagate(errp, error);
2013 if (cpu) {
2014 object_unref(OBJECT(cpu));
2015 cpu = NULL;
2016 }
2017 }
2018 g_strfreev(model_pieces);
2019 return cpu;
2020}
2021
2022X86CPU *cpu_x86_init(const char *cpu_model)
2023{
2024 Error *error = NULL;
2025 X86CPU *cpu;
2026
2027 cpu = cpu_x86_create(cpu_model, NULL, &error);
2028 if (error) {
2029 goto out;
2030 }
2031
2032 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
2033
2034out:
2035 if (error) {
2036 error_report("%s", error_get_pretty(error));
2037 error_free(error);
2038 if (cpu != NULL) {
2039 object_unref(OBJECT(cpu));
2040 cpu = NULL;
2041 }
2042 }
2043 return cpu;
2044}
2045
2046static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2047{
2048 X86CPUDefinition *cpudef = data;
2049 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2050
2051 xcc->cpu_def = cpudef;
2052}
2053
2054static void x86_register_cpudef_type(X86CPUDefinition *def)
2055{
2056 char *typename = x86_cpu_type_name(def->name);
2057 TypeInfo ti = {
2058 .name = typename,
2059 .parent = TYPE_X86_CPU,
2060 .class_init = x86_cpu_cpudef_class_init,
2061 .class_data = def,
2062 };
2063
2064 type_register(&ti);
2065 g_free(typename);
2066}
2067
2068#if !defined(CONFIG_USER_ONLY)
2069
2070void cpu_clear_apic_feature(CPUX86State *env)
2071{
2072 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2073}
2074
2075#endif /* !CONFIG_USER_ONLY */
2076
2077/* Initialize list of CPU models, filling some non-static fields if necessary
2078 */
2079void x86_cpudef_setup(void)
2080{
2081 int i, j;
2082 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2083
2084 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2085 X86CPUDefinition *def = &builtin_x86_defs[i];
2086
2087 /* Look for specific "cpudef" models that */
2088 /* have the QEMU version in .model_id */
2089 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2090 if (strcmp(model_with_versions[j], def->name) == 0) {
2091 pstrcpy(def->model_id, sizeof(def->model_id),
2092 "QEMU Virtual CPU version ");
2093 pstrcat(def->model_id, sizeof(def->model_id),
2094 qemu_get_version());
2095 break;
2096 }
2097 }
2098 }
2099}
2100
2101static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2102 uint32_t *ecx, uint32_t *edx)
2103{
2104 *ebx = env->cpuid_vendor1;
2105 *edx = env->cpuid_vendor2;
2106 *ecx = env->cpuid_vendor3;
2107}
2108
2109void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2110 uint32_t *eax, uint32_t *ebx,
2111 uint32_t *ecx, uint32_t *edx)
2112{
2113 X86CPU *cpu = x86_env_get_cpu(env);
2114 CPUState *cs = CPU(cpu);
2115
2116 /* test if maximum index reached */
2117 if (index & 0x80000000) {
2118 if (index > env->cpuid_xlevel) {
2119 if (env->cpuid_xlevel2 > 0) {
2120 /* Handle the Centaur's CPUID instruction. */
2121 if (index > env->cpuid_xlevel2) {
2122 index = env->cpuid_xlevel2;
2123 } else if (index < 0xC0000000) {
2124 index = env->cpuid_xlevel;
2125 }
2126 } else {
2127 /* Intel documentation states that invalid EAX input will
2128 * return the same information as EAX=cpuid_level
2129 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2130 */
2131 index = env->cpuid_level;
2132 }
2133 }
2134 } else {
2135 if (index > env->cpuid_level)
2136 index = env->cpuid_level;
2137 }
2138
2139 switch(index) {
2140 case 0:
2141 *eax = env->cpuid_level;
2142 get_cpuid_vendor(env, ebx, ecx, edx);
2143 break;
2144 case 1:
2145 *eax = env->cpuid_version;
2146 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2147 *ecx = env->features[FEAT_1_ECX];
2148 *edx = env->features[FEAT_1_EDX];
2149 if (cs->nr_cores * cs->nr_threads > 1) {
2150 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2151 *edx |= 1 << 28; /* HTT bit */
2152 }
2153 break;
2154 case 2:
2155 /* cache info: needed for Pentium Pro compatibility */
2156 if (cpu->cache_info_passthrough) {
2157 host_cpuid(index, 0, eax, ebx, ecx, edx);
2158 break;
2159 }
2160 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2161 *ebx = 0;
2162 *ecx = 0;
2163 *edx = (L1D_DESCRIPTOR << 16) | \
2164 (L1I_DESCRIPTOR << 8) | \
2165 (L2_DESCRIPTOR);
2166 break;
2167 case 4:
2168 /* cache info: needed for Core compatibility */
2169 if (cpu->cache_info_passthrough) {
2170 host_cpuid(index, count, eax, ebx, ecx, edx);
2171 *eax &= ~0xFC000000;
2172 } else {
2173 *eax = 0;
2174 switch (count) {
2175 case 0: /* L1 dcache info */
2176 *eax |= CPUID_4_TYPE_DCACHE | \
2177 CPUID_4_LEVEL(1) | \
2178 CPUID_4_SELF_INIT_LEVEL;
2179 *ebx = (L1D_LINE_SIZE - 1) | \
2180 ((L1D_PARTITIONS - 1) << 12) | \
2181 ((L1D_ASSOCIATIVITY - 1) << 22);
2182 *ecx = L1D_SETS - 1;
2183 *edx = CPUID_4_NO_INVD_SHARING;
2184 break;
2185 case 1: /* L1 icache info */
2186 *eax |= CPUID_4_TYPE_ICACHE | \
2187 CPUID_4_LEVEL(1) | \
2188 CPUID_4_SELF_INIT_LEVEL;
2189 *ebx = (L1I_LINE_SIZE - 1) | \
2190 ((L1I_PARTITIONS - 1) << 12) | \
2191 ((L1I_ASSOCIATIVITY - 1) << 22);
2192 *ecx = L1I_SETS - 1;
2193 *edx = CPUID_4_NO_INVD_SHARING;
2194 break;
2195 case 2: /* L2 cache info */
2196 *eax |= CPUID_4_TYPE_UNIFIED | \
2197 CPUID_4_LEVEL(2) | \
2198 CPUID_4_SELF_INIT_LEVEL;
2199 if (cs->nr_threads > 1) {
2200 *eax |= (cs->nr_threads - 1) << 14;
2201 }
2202 *ebx = (L2_LINE_SIZE - 1) | \
2203 ((L2_PARTITIONS - 1) << 12) | \
2204 ((L2_ASSOCIATIVITY - 1) << 22);
2205 *ecx = L2_SETS - 1;
2206 *edx = CPUID_4_NO_INVD_SHARING;
2207 break;
2208 default: /* end of info */
2209 *eax = 0;
2210 *ebx = 0;
2211 *ecx = 0;
2212 *edx = 0;
2213 break;
2214 }
2215 }
2216
2217 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2218 if ((*eax & 31) && cs->nr_cores > 1) {
2219 *eax |= (cs->nr_cores - 1) << 26;
2220 }
2221 break;
2222 case 5:
2223 /* mwait info: needed for Core compatibility */
2224 *eax = 0; /* Smallest monitor-line size in bytes */
2225 *ebx = 0; /* Largest monitor-line size in bytes */
2226 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2227 *edx = 0;
2228 break;
2229 case 6:
2230 /* Thermal and Power Leaf */
2231 *eax = 0;
2232 *ebx = 0;
2233 *ecx = 0;
2234 *edx = 0;
2235 break;
2236 case 7:
2237 /* Structured Extended Feature Flags Enumeration Leaf */
2238 if (count == 0) {
2239 *eax = 0; /* Maximum ECX value for sub-leaves */
2240 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2241 *ecx = 0; /* Reserved */
2242 *edx = 0; /* Reserved */
2243 } else {
2244 *eax = 0;
2245 *ebx = 0;
2246 *ecx = 0;
2247 *edx = 0;
2248 }
2249 break;
2250 case 9:
2251 /* Direct Cache Access Information Leaf */
2252 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2253 *ebx = 0;
2254 *ecx = 0;
2255 *edx = 0;
2256 break;
2257 case 0xA:
2258 /* Architectural Performance Monitoring Leaf */
2259 if (kvm_enabled() && cpu->enable_pmu) {
2260 KVMState *s = cs->kvm_state;
2261
2262 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2263 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2264 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2265 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2266 } else {
2267 *eax = 0;
2268 *ebx = 0;
2269 *ecx = 0;
2270 *edx = 0;
2271 }
2272 break;
2273 case 0xD: {
2274 KVMState *s = cs->kvm_state;
2275 uint64_t kvm_mask;
2276 int i;
2277
2278 /* Processor Extended State */
2279 *eax = 0;
2280 *ebx = 0;
2281 *ecx = 0;
2282 *edx = 0;
2283 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2284 break;
2285 }
2286 kvm_mask =
2287 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2288 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2289
2290 if (count == 0) {
2291 *ecx = 0x240;
2292 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2293 const ExtSaveArea *esa = &ext_save_areas[i];
2294 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2295 (kvm_mask & (1 << i)) != 0) {
2296 if (i < 32) {
2297 *eax |= 1 << i;
2298 } else {
2299 *edx |= 1 << (i - 32);
2300 }
2301 *ecx = MAX(*ecx, esa->offset + esa->size);
2302 }
2303 }
2304 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2305 *ebx = *ecx;
2306 } else if (count == 1) {
2307 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2308 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2309 const ExtSaveArea *esa = &ext_save_areas[count];
2310 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2311 (kvm_mask & (1 << count)) != 0) {
2312 *eax = esa->size;
2313 *ebx = esa->offset;
2314 }
2315 }
2316 break;
2317 }
2318 case 0x80000000:
2319 *eax = env->cpuid_xlevel;
2320 *ebx = env->cpuid_vendor1;
2321 *edx = env->cpuid_vendor2;
2322 *ecx = env->cpuid_vendor3;
2323 break;
2324 case 0x80000001:
2325 *eax = env->cpuid_version;
2326 *ebx = 0;
2327 *ecx = env->features[FEAT_8000_0001_ECX];
2328 *edx = env->features[FEAT_8000_0001_EDX];
2329
2330 /* The Linux kernel checks for the CMPLegacy bit and
2331 * discards multiple thread information if it is set.
2332 * So dont set it here for Intel to make Linux guests happy.
2333 */
2334 if (cs->nr_cores * cs->nr_threads > 1) {
2335 uint32_t tebx, tecx, tedx;
2336 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2337 if (tebx != CPUID_VENDOR_INTEL_1 ||
2338 tedx != CPUID_VENDOR_INTEL_2 ||
2339 tecx != CPUID_VENDOR_INTEL_3) {
2340 *ecx |= 1 << 1; /* CmpLegacy bit */
2341 }
2342 }
2343 break;
2344 case 0x80000002:
2345 case 0x80000003:
2346 case 0x80000004:
2347 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2348 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2349 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2350 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2351 break;
2352 case 0x80000005:
2353 /* cache info (L1 cache) */
2354 if (cpu->cache_info_passthrough) {
2355 host_cpuid(index, 0, eax, ebx, ecx, edx);
2356 break;
2357 }
2358 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2359 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2360 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2361 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2362 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2363 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2364 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2365 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2366 break;
2367 case 0x80000006:
2368 /* cache info (L2 cache) */
2369 if (cpu->cache_info_passthrough) {
2370 host_cpuid(index, 0, eax, ebx, ecx, edx);
2371 break;
2372 }
2373 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2374 (L2_DTLB_2M_ENTRIES << 16) | \
2375 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2376 (L2_ITLB_2M_ENTRIES);
2377 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2378 (L2_DTLB_4K_ENTRIES << 16) | \
2379 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2380 (L2_ITLB_4K_ENTRIES);
2381 *ecx = (L2_SIZE_KB_AMD << 16) | \
2382 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2383 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2384 *edx = ((L3_SIZE_KB/512) << 18) | \
2385 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2386 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2387 break;
2388 case 0x80000008:
2389 /* virtual & phys address size in low 2 bytes. */
2390/* XXX: This value must match the one used in the MMU code. */
2391 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2392 /* 64 bit processor */
2393/* XXX: The physical address space is limited to 42 bits in exec.c. */
2394 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2395 } else {
2396 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2397 *eax = 0x00000024; /* 36 bits physical */
2398 } else {
2399 *eax = 0x00000020; /* 32 bits physical */
2400 }
2401 }
2402 *ebx = 0;
2403 *ecx = 0;
2404 *edx = 0;
2405 if (cs->nr_cores * cs->nr_threads > 1) {
2406 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2407 }
2408 break;
2409 case 0x8000000A:
2410 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2411 *eax = 0x00000001; /* SVM Revision */
2412 *ebx = 0x00000010; /* nr of ASIDs */
2413 *ecx = 0;
2414 *edx = env->features[FEAT_SVM]; /* optional features */
2415 } else {
2416 *eax = 0;
2417 *ebx = 0;
2418 *ecx = 0;
2419 *edx = 0;
2420 }
2421 break;
2422 case 0xC0000000:
2423 *eax = env->cpuid_xlevel2;
2424 *ebx = 0;
2425 *ecx = 0;
2426 *edx = 0;
2427 break;
2428 case 0xC0000001:
2429 /* Support for VIA CPU's CPUID instruction */
2430 *eax = env->cpuid_version;
2431 *ebx = 0;
2432 *ecx = 0;
2433 *edx = env->features[FEAT_C000_0001_EDX];
2434 break;
2435 case 0xC0000002:
2436 case 0xC0000003:
2437 case 0xC0000004:
2438 /* Reserved for the future, and now filled with zero */
2439 *eax = 0;
2440 *ebx = 0;
2441 *ecx = 0;
2442 *edx = 0;
2443 break;
2444 default:
2445 /* reserved values: zero */
2446 *eax = 0;
2447 *ebx = 0;
2448 *ecx = 0;
2449 *edx = 0;
2450 break;
2451 }
2452}
2453
2454/* CPUClass::reset() */
2455static void x86_cpu_reset(CPUState *s)
2456{
2457 X86CPU *cpu = X86_CPU(s);
2458 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2459 CPUX86State *env = &cpu->env;
2460 int i;
2461
2462 xcc->parent_reset(s);
2463
2464 memset(env, 0, offsetof(CPUX86State, cpuid_level));
2465
2466 tlb_flush(s, 1);
2467
2468 env->old_exception = -1;
2469
2470 /* init to reset state */
2471
2472#ifdef CONFIG_SOFTMMU
2473 env->hflags |= HF_SOFTMMU_MASK;
2474#endif
2475 env->hflags2 |= HF2_GIF_MASK;
2476
2477 cpu_x86_update_cr0(env, 0x60000010);
2478 env->a20_mask = ~0x0;
2479 env->smbase = 0x30000;
2480
2481 env->idt.limit = 0xffff;
2482 env->gdt.limit = 0xffff;
2483 env->ldt.limit = 0xffff;
2484 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2485 env->tr.limit = 0xffff;
2486 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2487
2488 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2489 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2490 DESC_R_MASK | DESC_A_MASK);
2491 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2492 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2493 DESC_A_MASK);
2494 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2495 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2496 DESC_A_MASK);
2497 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2498 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2499 DESC_A_MASK);
2500 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2501 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2502 DESC_A_MASK);
2503 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2504 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2505 DESC_A_MASK);
2506
2507 env->eip = 0xfff0;
2508 env->regs[R_EDX] = env->cpuid_version;
2509
2510 env->eflags = 0x2;
2511
2512 /* FPU init */
2513 for (i = 0; i < 8; i++) {
2514 env->fptags[i] = 1;
2515 }
2516 env->fpuc = 0x37f;
2517
2518 env->mxcsr = 0x1f80;
2519 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2520
2521 env->pat = 0x0007040600070406ULL;
2522 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2523
2524 memset(env->dr, 0, sizeof(env->dr));
2525 env->dr[6] = DR6_FIXED_1;
2526 env->dr[7] = DR7_FIXED_1;
2527 cpu_breakpoint_remove_all(s, BP_CPU);
2528 cpu_watchpoint_remove_all(s, BP_CPU);
2529
2530 env->xcr0 = 1;
2531
2532#if !defined(CONFIG_USER_ONLY)
2533 /* We hard-wire the BSP to the first CPU. */
2534 if (s->cpu_index == 0) {
2535 apic_designate_bsp(cpu->apic_state);
2536 }
2537
2538 s->halted = !cpu_is_bsp(cpu);
2539
2540 if (kvm_enabled()) {
2541 kvm_arch_reset_vcpu(cpu);
2542 }
2543#endif
2544}
2545
2546#ifndef CONFIG_USER_ONLY
2547bool cpu_is_bsp(X86CPU *cpu)
2548{
2549 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2550}
2551
2552/* TODO: remove me, when reset over QOM tree is implemented */
2553static void x86_cpu_machine_reset_cb(void *opaque)
2554{
2555 X86CPU *cpu = opaque;
2556 cpu_reset(CPU(cpu));
2557}
2558#endif
2559
2560static void mce_init(X86CPU *cpu)
2561{
2562 CPUX86State *cenv = &cpu->env;
2563 unsigned int bank;
2564
2565 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2566 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2567 (CPUID_MCE | CPUID_MCA)) {
2568 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2569 cenv->mcg_ctl = ~(uint64_t)0;
2570 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2571 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2572 }
2573 }
2574}
2575
2576#ifndef CONFIG_USER_ONLY
2577static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2578{
2579 CPUX86State *env = &cpu->env;
2580 DeviceState *dev = DEVICE(cpu);
2581 APICCommonState *apic;
2582 const char *apic_type = "apic";
2583
2584 if (kvm_irqchip_in_kernel()) {
2585 apic_type = "kvm-apic";
2586 } else if (xen_enabled()) {
2587 apic_type = "xen-apic";
2588 }
2589
2590 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2591 if (cpu->apic_state == NULL) {
2592 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2593 return;
2594 }
2595
2596 object_property_add_child(OBJECT(cpu), "apic",
2597 OBJECT(cpu->apic_state), NULL);
2598 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2599 /* TODO: convert to link<> */
2600 apic = APIC_COMMON(cpu->apic_state);
2601 apic->cpu = cpu;
2602}
2603
2604static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2605{
2606 if (cpu->apic_state == NULL) {
2607 return;
2608 }
2609
2610 if (qdev_init(cpu->apic_state)) {
2611 error_setg(errp, "APIC device '%s' could not be initialized",
2612 object_get_typename(OBJECT(cpu->apic_state)));
2613 return;
2614 }
2615}
2616#else
2617static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2618{
2619}
2620#endif
2621
2622static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2623{
2624 CPUState *cs = CPU(dev);
2625 X86CPU *cpu = X86_CPU(dev);
2626 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2627 CPUX86State *env = &cpu->env;
2628 Error *local_err = NULL;
2629
2630 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2631 env->cpuid_level = 7;
2632 }
2633
2634 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2635 * CPUID[1].EDX.
2636 */
2637 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2638 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2639 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2640 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2641 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2642 & CPUID_EXT2_AMD_ALIASES);
2643 }
2644
2645
2646 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2647 error_setg(&local_err,
2648 kvm_enabled() ?
2649 "Host doesn't support requested features" :
2650 "TCG doesn't support requested features");
2651 goto out;
2652 }
2653
2654#ifndef CONFIG_USER_ONLY
2655 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2656
2657 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2658 x86_cpu_apic_create(cpu, &local_err);
2659 if (local_err != NULL) {
2660 goto out;
2661 }
2662 }
2663#endif
2664
2665 mce_init(cpu);
2666 qemu_init_vcpu(cs);
2667
2668 x86_cpu_apic_realize(cpu, &local_err);
2669 if (local_err != NULL) {
2670 goto out;
2671 }
2672 cpu_reset(cs);
2673
2674 xcc->parent_realize(dev, &local_err);
2675out:
2676 if (local_err != NULL) {
2677 error_propagate(errp, local_err);
2678 return;
2679 }
2680}
2681
2682/* Enables contiguous-apic-ID mode, for compatibility */
2683static bool compat_apic_id_mode;
2684
2685void enable_compat_apic_id_mode(void)
2686{
2687 compat_apic_id_mode = true;
2688}
2689
2690/* Calculates initial APIC ID for a specific CPU index
2691 *
2692 * Currently we need to be able to calculate the APIC ID from the CPU index
2693 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2694 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2695 * all CPUs up to max_cpus.
2696 */
2697uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2698{
2699 uint32_t correct_id;
2700 static bool warned;
2701
2702 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2703 if (compat_apic_id_mode) {
2704 if (cpu_index != correct_id && !warned) {
2705 error_report("APIC IDs set in compatibility mode, "
2706 "CPU topology won't match the configuration");
2707 warned = true;
2708 }
2709 return cpu_index;
2710 } else {
2711 return correct_id;
2712 }
2713}
2714
2715static void x86_cpu_initfn(Object *obj)
2716{
2717 CPUState *cs = CPU(obj);
2718 X86CPU *cpu = X86_CPU(obj);
2719 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2720 CPUX86State *env = &cpu->env;
2721 static int inited;
2722
2723 cs->env_ptr = env;
2724 cpu_exec_init(env);
2725
2726 object_property_add(obj, "family", "int",
2727 x86_cpuid_version_get_family,
2728 x86_cpuid_version_set_family, NULL, NULL, NULL);
2729 object_property_add(obj, "model", "int",
2730 x86_cpuid_version_get_model,
2731 x86_cpuid_version_set_model, NULL, NULL, NULL);
2732 object_property_add(obj, "stepping", "int",
2733 x86_cpuid_version_get_stepping,
2734 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2735 object_property_add(obj, "level", "int",
2736 x86_cpuid_get_level,
2737 x86_cpuid_set_level, NULL, NULL, NULL);
2738 object_property_add(obj, "xlevel", "int",
2739 x86_cpuid_get_xlevel,
2740 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2741 object_property_add_str(obj, "vendor",
2742 x86_cpuid_get_vendor,
2743 x86_cpuid_set_vendor, NULL);
2744 object_property_add_str(obj, "model-id",
2745 x86_cpuid_get_model_id,
2746 x86_cpuid_set_model_id, NULL);
2747 object_property_add(obj, "tsc-frequency", "int",
2748 x86_cpuid_get_tsc_freq,
2749 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2750 object_property_add(obj, "apic-id", "int",
2751 x86_cpuid_get_apic_id,
2752 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2753 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2754 x86_cpu_get_feature_words,
2755 NULL, NULL, (void *)env->features, NULL);
2756 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2757 x86_cpu_get_feature_words,
2758 NULL, NULL, (void *)cpu->filtered_features, NULL);
2759
2760 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2761 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2762
2763 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2764
2765 /* init various static tables used in TCG mode */
2766 if (tcg_enabled() && !inited) {
2767 inited = 1;
2768 optimize_flags_init();
2769#ifndef CONFIG_USER_ONLY
2770 cpu_set_debug_excp_handler(breakpoint_handler);
2771#endif
2772 }
2773}
2774
2775static int64_t x86_cpu_get_arch_id(CPUState *cs)
2776{
2777 X86CPU *cpu = X86_CPU(cs);
2778 CPUX86State *env = &cpu->env;
2779
2780 return env->cpuid_apic_id;
2781}
2782
2783static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2784{
2785 X86CPU *cpu = X86_CPU(cs);
2786
2787 return cpu->env.cr[0] & CR0_PG_MASK;
2788}
2789
2790static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2791{
2792 X86CPU *cpu = X86_CPU(cs);
2793
2794 cpu->env.eip = value;
2795}
2796
2797static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2798{
2799 X86CPU *cpu = X86_CPU(cs);
2800
2801 cpu->env.eip = tb->pc - tb->cs_base;
2802}
2803
2804static bool x86_cpu_has_work(CPUState *cs)
2805{
2806 X86CPU *cpu = X86_CPU(cs);
2807 CPUX86State *env = &cpu->env;
2808
2809 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2810 CPU_INTERRUPT_POLL)) &&
2811 (env->eflags & IF_MASK)) ||
2812 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2813 CPU_INTERRUPT_INIT |
2814 CPU_INTERRUPT_SIPI |
2815 CPU_INTERRUPT_MCE));
2816}
2817
2818static Property x86_cpu_properties[] = {
2819 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2820 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2821 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2822 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2823 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2824 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2825 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2826 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
2827 DEFINE_PROP_END_OF_LIST()
2828};
2829
2830static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2831{
2832 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2833 CPUClass *cc = CPU_CLASS(oc);
2834 DeviceClass *dc = DEVICE_CLASS(oc);
2835
2836 xcc->parent_realize = dc->realize;
2837 dc->realize = x86_cpu_realizefn;
2838 dc->bus_type = TYPE_ICC_BUS;
2839 dc->props = x86_cpu_properties;
2840
2841 xcc->parent_reset = cc->reset;
2842 cc->reset = x86_cpu_reset;
2843 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2844
2845 cc->class_by_name = x86_cpu_class_by_name;
2846 cc->parse_features = x86_cpu_parse_featurestr;
2847 cc->has_work = x86_cpu_has_work;
2848 cc->do_interrupt = x86_cpu_do_interrupt;
2849 cc->dump_state = x86_cpu_dump_state;
2850 cc->set_pc = x86_cpu_set_pc;
2851 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2852 cc->gdb_read_register = x86_cpu_gdb_read_register;
2853 cc->gdb_write_register = x86_cpu_gdb_write_register;
2854 cc->get_arch_id = x86_cpu_get_arch_id;
2855 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2856#ifdef CONFIG_USER_ONLY
2857 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2858#else
2859 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2860 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2861 cc->write_elf64_note = x86_cpu_write_elf64_note;
2862 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2863 cc->write_elf32_note = x86_cpu_write_elf32_note;
2864 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2865 cc->vmsd = &vmstate_x86_cpu;
2866#endif
2867 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2868}
2869
2870static const TypeInfo x86_cpu_type_info = {
2871 .name = TYPE_X86_CPU,
2872 .parent = TYPE_CPU,
2873 .instance_size = sizeof(X86CPU),
2874 .instance_init = x86_cpu_initfn,
2875 .abstract = true,
2876 .class_size = sizeof(X86CPUClass),
2877 .class_init = x86_cpu_common_class_init,
2878};
2879
2880static void x86_cpu_register_types(void)
2881{
2882 int i;
2883
2884 type_register_static(&x86_cpu_type_info);
2885 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2886 x86_register_cpudef_type(&builtin_x86_defs[i]);
2887 }
2888#ifdef CONFIG_KVM
2889 type_register_static(&host_x86_cpu_type_info);
2890#endif
2891}
2892
2893type_init(x86_cpu_register_types)
QEMU mirror