| | 1 | /* |
| | 2 | * i386 virtual CPU header |
| | 3 | * |
| | 4 | * Copyright (c) 2003 Fabrice Bellard |
| | 5 | * |
| | 6 | * This library is free software; you can redistribute it and/or |
| | 7 | * modify it under the terms of the GNU Lesser General Public |
| | 8 | * License as published by the Free Software Foundation; either |
| | 9 | * version 2 of the License, or (at your option) any later version. |
| | 10 | * |
| | 11 | * This library is distributed in the hope that it will be useful, |
| | 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| | 14 | * Lesser General Public License for more details. |
| | 15 | * |
| | 16 | * You should have received a copy of the GNU Lesser General Public |
| | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| | 18 | */ |
| | 19 | #ifndef CPU_I386_H |
| | 20 | #define CPU_I386_H |
| | 21 | |
| | 22 | #include "qemu-common.h" |
| | 23 | #include "cpu-qom.h" |
| | 24 | #include "standard-headers/asm-x86/hyperv.h" |
| | 25 | |
| | 26 | #ifdef TARGET_X86_64 |
| | 27 | #define TARGET_LONG_BITS 64 |
| | 28 | #else |
| | 29 | #define TARGET_LONG_BITS 32 |
| | 30 | #endif |
| | 31 | |
| | 32 | /* Maximum instruction code size */ |
| | 33 | #define TARGET_MAX_INSN_SIZE 16 |
| | 34 | |
| | 35 | /* support for self modifying code even if the modified instruction is |
| | 36 | close to the modifying instruction */ |
| | 37 | #define TARGET_HAS_PRECISE_SMC |
| | 38 | |
| | 39 | #ifdef TARGET_X86_64 |
| | 40 | #define I386_ELF_MACHINE EM_X86_64 |
| | 41 | #define ELF_MACHINE_UNAME "x86_64" |
| | 42 | #else |
| | 43 | #define I386_ELF_MACHINE EM_386 |
| | 44 | #define ELF_MACHINE_UNAME "i686" |
| | 45 | #endif |
| | 46 | |
| | 47 | #define CPUArchState struct CPUX86State |
| | 48 | |
| | 49 | #include "exec/cpu-defs.h" |
| | 50 | |
| | 51 | #include "fpu/softfloat.h" |
| | 52 | |
| | 53 | #define R_EAX 0 |
| | 54 | #define R_ECX 1 |
| | 55 | #define R_EDX 2 |
| | 56 | #define R_EBX 3 |
| | 57 | #define R_ESP 4 |
| | 58 | #define R_EBP 5 |
| | 59 | #define R_ESI 6 |
| | 60 | #define R_EDI 7 |
| | 61 | |
| | 62 | #define R_AL 0 |
| | 63 | #define R_CL 1 |
| | 64 | #define R_DL 2 |
| | 65 | #define R_BL 3 |
| | 66 | #define R_AH 4 |
| | 67 | #define R_CH 5 |
| | 68 | #define R_DH 6 |
| | 69 | #define R_BH 7 |
| | 70 | |
| | 71 | #define R_ES 0 |
| | 72 | #define R_CS 1 |
| | 73 | #define R_SS 2 |
| | 74 | #define R_DS 3 |
| | 75 | #define R_FS 4 |
| | 76 | #define R_GS 5 |
| | 77 | |
| | 78 | /* segment descriptor fields */ |
| | 79 | #define DESC_G_MASK (1 << 23) |
| | 80 | #define DESC_B_SHIFT 22 |
| | 81 | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
| | 82 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
| | 83 | #define DESC_L_MASK (1 << DESC_L_SHIFT) |
| | 84 | #define DESC_AVL_MASK (1 << 20) |
| | 85 | #define DESC_P_MASK (1 << 15) |
| | 86 | #define DESC_DPL_SHIFT 13 |
| | 87 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) |
| | 88 | #define DESC_S_MASK (1 << 12) |
| | 89 | #define DESC_TYPE_SHIFT 8 |
| | 90 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) |
| | 91 | #define DESC_A_MASK (1 << 8) |
| | 92 | |
| | 93 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
| | 94 | #define DESC_C_MASK (1 << 10) /* code: conforming */ |
| | 95 | #define DESC_R_MASK (1 << 9) /* code: readable */ |
| | 96 | |
| | 97 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
| | 98 | #define DESC_W_MASK (1 << 9) /* data: writable */ |
| | 99 | |
| | 100 | #define DESC_TSS_BUSY_MASK (1 << 9) |
| | 101 | |
| | 102 | /* eflags masks */ |
| | 103 | #define CC_C 0x0001 |
| | 104 | #define CC_P 0x0004 |
| | 105 | #define CC_A 0x0010 |
| | 106 | #define CC_Z 0x0040 |
| | 107 | #define CC_S 0x0080 |
| | 108 | #define CC_O 0x0800 |
| | 109 | |
| | 110 | #define TF_SHIFT 8 |
| | 111 | #define IOPL_SHIFT 12 |
| | 112 | #define VM_SHIFT 17 |
| | 113 | |
| | 114 | #define TF_MASK 0x00000100 |
| | 115 | #define IF_MASK 0x00000200 |
| | 116 | #define DF_MASK 0x00000400 |
| | 117 | #define IOPL_MASK 0x00003000 |
| | 118 | #define NT_MASK 0x00004000 |
| | 119 | #define RF_MASK 0x00010000 |
| | 120 | #define VM_MASK 0x00020000 |
| | 121 | #define AC_MASK 0x00040000 |
| | 122 | #define VIF_MASK 0x00080000 |
| | 123 | #define VIP_MASK 0x00100000 |
| | 124 | #define ID_MASK 0x00200000 |
| | 125 | |
| | 126 | /* hidden flags - used internally by qemu to represent additional cpu |
| | 127 | states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We |
| | 128 | avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit |
| | 129 | positions to ease oring with eflags. */ |
| | 130 | /* current cpl */ |
| | 131 | #define HF_CPL_SHIFT 0 |
| | 132 | /* true if soft mmu is being used */ |
| | 133 | #define HF_SOFTMMU_SHIFT 2 |
| | 134 | /* true if hardware interrupts must be disabled for next instruction */ |
| | 135 | #define HF_INHIBIT_IRQ_SHIFT 3 |
| | 136 | /* 16 or 32 segments */ |
| | 137 | #define HF_CS32_SHIFT 4 |
| | 138 | #define HF_SS32_SHIFT 5 |
| | 139 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
| | 140 | #define HF_ADDSEG_SHIFT 6 |
| | 141 | /* copy of CR0.PE (protected mode) */ |
| | 142 | #define HF_PE_SHIFT 7 |
| | 143 | #define HF_TF_SHIFT 8 /* must be same as eflags */ |
| | 144 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
| | 145 | #define HF_EM_SHIFT 10 |
| | 146 | #define HF_TS_SHIFT 11 |
| | 147 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
| | 148 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
| | 149 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
| | 150 | #define HF_RF_SHIFT 16 /* must be same as eflags */ |
| | 151 | #define HF_VM_SHIFT 17 /* must be same as eflags */ |
| | 152 | #define HF_AC_SHIFT 18 /* must be same as eflags */ |
| | 153 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
| | 154 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
| | 155 | #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ |
| | 156 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ |
| | 157 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ |
| | 158 | #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */ |
| | 159 | #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */ |
| | 160 | #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */ |
| | 161 | |
| | 162 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
| | 163 | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
| | 164 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
| | 165 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
| | 166 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
| | 167 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
| | 168 | #define HF_PE_MASK (1 << HF_PE_SHIFT) |
| | 169 | #define HF_TF_MASK (1 << HF_TF_SHIFT) |
| | 170 | #define HF_MP_MASK (1 << HF_MP_SHIFT) |
| | 171 | #define HF_EM_MASK (1 << HF_EM_SHIFT) |
| | 172 | #define HF_TS_MASK (1 << HF_TS_SHIFT) |
| | 173 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
| | 174 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
| | 175 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
| | 176 | #define HF_RF_MASK (1 << HF_RF_SHIFT) |
| | 177 | #define HF_VM_MASK (1 << HF_VM_SHIFT) |
| | 178 | #define HF_AC_MASK (1 << HF_AC_SHIFT) |
| | 179 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
| | 180 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
| | 181 | #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) |
| | 182 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
| | 183 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) |
| | 184 | #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT) |
| | 185 | #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT) |
| | 186 | #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT) |
| | 187 | |
| | 188 | /* hflags2 */ |
| | 189 | |
| | 190 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
| | 191 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ |
| | 192 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ |
| | 193 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ |
| | 194 | #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */ |
| | 195 | #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */ |
| | 196 | |
| | 197 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) |
| | 198 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) |
| | 199 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) |
| | 200 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) |
| | 201 | #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT) |
| | 202 | #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT) |
| | 203 | |
| | 204 | #define CR0_PE_SHIFT 0 |
| | 205 | #define CR0_MP_SHIFT 1 |
| | 206 | |
| | 207 | #define CR0_PE_MASK (1U << 0) |
| | 208 | #define CR0_MP_MASK (1U << 1) |
| | 209 | #define CR0_EM_MASK (1U << 2) |
| | 210 | #define CR0_TS_MASK (1U << 3) |
| | 211 | #define CR0_ET_MASK (1U << 4) |
| | 212 | #define CR0_NE_MASK (1U << 5) |
| | 213 | #define CR0_WP_MASK (1U << 16) |
| | 214 | #define CR0_AM_MASK (1U << 18) |
| | 215 | #define CR0_PG_MASK (1U << 31) |
| | 216 | |
| | 217 | #define CR4_VME_MASK (1U << 0) |
| | 218 | #define CR4_PVI_MASK (1U << 1) |
| | 219 | #define CR4_TSD_MASK (1U << 2) |
| | 220 | #define CR4_DE_MASK (1U << 3) |
| | 221 | #define CR4_PSE_MASK (1U << 4) |
| | 222 | #define CR4_PAE_MASK (1U << 5) |
| | 223 | #define CR4_MCE_MASK (1U << 6) |
| | 224 | #define CR4_PGE_MASK (1U << 7) |
| | 225 | #define CR4_PCE_MASK (1U << 8) |
| | 226 | #define CR4_OSFXSR_SHIFT 9 |
| | 227 | #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) |
| | 228 | #define CR4_OSXMMEXCPT_MASK (1U << 10) |
| | 229 | #define CR4_VMXE_MASK (1U << 13) |
| | 230 | #define CR4_SMXE_MASK (1U << 14) |
| | 231 | #define CR4_FSGSBASE_MASK (1U << 16) |
| | 232 | #define CR4_PCIDE_MASK (1U << 17) |
| | 233 | #define CR4_OSXSAVE_MASK (1U << 18) |
| | 234 | #define CR4_SMEP_MASK (1U << 20) |
| | 235 | #define CR4_SMAP_MASK (1U << 21) |
| | 236 | #define CR4_PKE_MASK (1U << 22) |
| | 237 | |
| | 238 | #define DR6_BD (1 << 13) |
| | 239 | #define DR6_BS (1 << 14) |
| | 240 | #define DR6_BT (1 << 15) |
| | 241 | #define DR6_FIXED_1 0xffff0ff0 |
| | 242 | |
| | 243 | #define DR7_GD (1 << 13) |
| | 244 | #define DR7_TYPE_SHIFT 16 |
| | 245 | #define DR7_LEN_SHIFT 18 |
| | 246 | #define DR7_FIXED_1 0x00000400 |
| | 247 | #define DR7_GLOBAL_BP_MASK 0xaa |
| | 248 | #define DR7_LOCAL_BP_MASK 0x55 |
| | 249 | #define DR7_MAX_BP 4 |
| | 250 | #define DR7_TYPE_BP_INST 0x0 |
| | 251 | #define DR7_TYPE_DATA_WR 0x1 |
| | 252 | #define DR7_TYPE_IO_RW 0x2 |
| | 253 | #define DR7_TYPE_DATA_RW 0x3 |
| | 254 | |
| | 255 | #define PG_PRESENT_BIT 0 |
| | 256 | #define PG_RW_BIT 1 |
| | 257 | #define PG_USER_BIT 2 |
| | 258 | #define PG_PWT_BIT 3 |
| | 259 | #define PG_PCD_BIT 4 |
| | 260 | #define PG_ACCESSED_BIT 5 |
| | 261 | #define PG_DIRTY_BIT 6 |
| | 262 | #define PG_PSE_BIT 7 |
| | 263 | #define PG_GLOBAL_BIT 8 |
| | 264 | #define PG_PSE_PAT_BIT 12 |
| | 265 | #define PG_PKRU_BIT 59 |
| | 266 | #define PG_NX_BIT 63 |
| | 267 | |
| | 268 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
| | 269 | #define PG_RW_MASK (1 << PG_RW_BIT) |
| | 270 | #define PG_USER_MASK (1 << PG_USER_BIT) |
| | 271 | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
| | 272 | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
| | 273 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
| | 274 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
| | 275 | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
| | 276 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
| | 277 | #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT) |
| | 278 | #define PG_ADDRESS_MASK 0x000ffffffffff000LL |
| | 279 | #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK) |
| | 280 | #define PG_HI_USER_MASK 0x7ff0000000000000LL |
| | 281 | #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT) |
| | 282 | #define PG_NX_MASK (1ULL << PG_NX_BIT) |
| | 283 | |
| | 284 | #define PG_ERROR_W_BIT 1 |
| | 285 | |
| | 286 | #define PG_ERROR_P_MASK 0x01 |
| | 287 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
| | 288 | #define PG_ERROR_U_MASK 0x04 |
| | 289 | #define PG_ERROR_RSVD_MASK 0x08 |
| | 290 | #define PG_ERROR_I_D_MASK 0x10 |
| | 291 | #define PG_ERROR_PK_MASK 0x20 |
| | 292 | |
| | 293 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ |
| | 294 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ |
| | 295 | #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */ |
| | 296 | |
| | 297 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) |
| | 298 | #define MCE_BANKS_DEF 10 |
| | 299 | |
| | 300 | #define MCG_CAP_BANKS_MASK 0xff |
| | 301 | |
| | 302 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ |
| | 303 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ |
| | 304 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ |
| | 305 | #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */ |
| | 306 | |
| | 307 | #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */ |
| | 308 | |
| | 309 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ |
| | 310 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ |
| | 311 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ |
| | 312 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ |
| | 313 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ |
| | 314 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ |
| | 315 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ |
| | 316 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ |
| | 317 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ |
| | 318 | |
| | 319 | /* MISC register defines */ |
| | 320 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ |
| | 321 | #define MCM_ADDR_LINEAR 1 /* linear address */ |
| | 322 | #define MCM_ADDR_PHYS 2 /* physical address */ |
| | 323 | #define MCM_ADDR_MEM 3 /* memory address */ |
| | 324 | #define MCM_ADDR_GENERIC 7 /* generic */ |
| | 325 | |
| | 326 | #define MSR_IA32_TSC 0x10 |
| | 327 | #define MSR_IA32_APICBASE 0x1b |
| | 328 | #define MSR_IA32_APICBASE_BSP (1<<8) |
| | 329 | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
| | 330 | #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) |
| | 331 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a |
| | 332 | #define MSR_TSC_ADJUST 0x0000003b |
| | 333 | #define MSR_IA32_TSCDEADLINE 0x6e0 |
| | 334 | |
| | 335 | #define FEATURE_CONTROL_LOCKED (1<<0) |
| | 336 | #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) |
| | 337 | #define FEATURE_CONTROL_LMCE (1<<20) |
| | 338 | |
| | 339 | #define MSR_P6_PERFCTR0 0xc1 |
| | 340 | |
| | 341 | #define MSR_IA32_SMBASE 0x9e |
| | 342 | #define MSR_MTRRcap 0xfe |
| | 343 | #define MSR_MTRRcap_VCNT 8 |
| | 344 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) |
| | 345 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) |
| | 346 | |
| | 347 | #define MSR_IA32_SYSENTER_CS 0x174 |
| | 348 | #define MSR_IA32_SYSENTER_ESP 0x175 |
| | 349 | #define MSR_IA32_SYSENTER_EIP 0x176 |
| | 350 | |
| | 351 | #define MSR_MCG_CAP 0x179 |
| | 352 | #define MSR_MCG_STATUS 0x17a |
| | 353 | #define MSR_MCG_CTL 0x17b |
| | 354 | #define MSR_MCG_EXT_CTL 0x4d0 |
| | 355 | |
| | 356 | #define MSR_P6_EVNTSEL0 0x186 |
| | 357 | |
| | 358 | #define MSR_IA32_PERF_STATUS 0x198 |
| | 359 | |
| | 360 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
| | 361 | /* Indicates good rep/movs microcode on some processors: */ |
| | 362 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 |
| | 363 | |
| | 364 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) |
| | 365 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) |
| | 366 | |
| | 367 | #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2) |
| | 368 | |
| | 369 | #define MSR_MTRRfix64K_00000 0x250 |
| | 370 | #define MSR_MTRRfix16K_80000 0x258 |
| | 371 | #define MSR_MTRRfix16K_A0000 0x259 |
| | 372 | #define MSR_MTRRfix4K_C0000 0x268 |
| | 373 | #define MSR_MTRRfix4K_C8000 0x269 |
| | 374 | #define MSR_MTRRfix4K_D0000 0x26a |
| | 375 | #define MSR_MTRRfix4K_D8000 0x26b |
| | 376 | #define MSR_MTRRfix4K_E0000 0x26c |
| | 377 | #define MSR_MTRRfix4K_E8000 0x26d |
| | 378 | #define MSR_MTRRfix4K_F0000 0x26e |
| | 379 | #define MSR_MTRRfix4K_F8000 0x26f |
| | 380 | |
| | 381 | #define MSR_PAT 0x277 |
| | 382 | |
| | 383 | #define MSR_MTRRdefType 0x2ff |
| | 384 | |
| | 385 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 |
| | 386 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a |
| | 387 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b |
| | 388 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d |
| | 389 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e |
| | 390 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f |
| | 391 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 |
| | 392 | |
| | 393 | #define MSR_MC0_CTL 0x400 |
| | 394 | #define MSR_MC0_STATUS 0x401 |
| | 395 | #define MSR_MC0_ADDR 0x402 |
| | 396 | #define MSR_MC0_MISC 0x403 |
| | 397 | |
| | 398 | #define MSR_EFER 0xc0000080 |
| | 399 | |
| | 400 | #define MSR_EFER_SCE (1 << 0) |
| | 401 | #define MSR_EFER_LME (1 << 8) |
| | 402 | #define MSR_EFER_LMA (1 << 10) |
| | 403 | #define MSR_EFER_NXE (1 << 11) |
| | 404 | #define MSR_EFER_SVME (1 << 12) |
| | 405 | #define MSR_EFER_FFXSR (1 << 14) |
| | 406 | |
| | 407 | #define MSR_STAR 0xc0000081 |
| | 408 | #define MSR_LSTAR 0xc0000082 |
| | 409 | #define MSR_CSTAR 0xc0000083 |
| | 410 | #define MSR_FMASK 0xc0000084 |
| | 411 | #define MSR_FSBASE 0xc0000100 |
| | 412 | #define MSR_GSBASE 0xc0000101 |
| | 413 | #define MSR_KERNELGSBASE 0xc0000102 |
| | 414 | #define MSR_TSC_AUX 0xc0000103 |
| | 415 | |
| | 416 | #define MSR_VM_HSAVE_PA 0xc0010117 |
| | 417 | |
| | 418 | #define MSR_IA32_BNDCFGS 0x00000d90 |
| | 419 | #define MSR_IA32_XSS 0x00000da0 |
| | 420 | |
| | 421 | #define XSTATE_FP_BIT 0 |
| | 422 | #define XSTATE_SSE_BIT 1 |
| | 423 | #define XSTATE_YMM_BIT 2 |
| | 424 | #define XSTATE_BNDREGS_BIT 3 |
| | 425 | #define XSTATE_BNDCSR_BIT 4 |
| | 426 | #define XSTATE_OPMASK_BIT 5 |
| | 427 | #define XSTATE_ZMM_Hi256_BIT 6 |
| | 428 | #define XSTATE_Hi16_ZMM_BIT 7 |
| | 429 | #define XSTATE_PKRU_BIT 9 |
| | 430 | |
| | 431 | #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) |
| | 432 | #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) |
| | 433 | #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT) |
| | 434 | #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT) |
| | 435 | #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT) |
| | 436 | #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT) |
| | 437 | #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) |
| | 438 | #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) |
| | 439 | #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) |
| | 440 | |
| | 441 | /* CPUID feature words */ |
| | 442 | typedef enum FeatureWord { |
| | 443 | FEAT_1_EDX, /* CPUID[1].EDX */ |
| | 444 | FEAT_1_ECX, /* CPUID[1].ECX */ |
| | 445 | FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ |
| | 446 | FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */ |
| | 447 | FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ |
| | 448 | FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ |
| | 449 | FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ |
| | 450 | FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ |
| | 451 | FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ |
| | 452 | FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */ |
| | 453 | FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */ |
| | 454 | FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */ |
| | 455 | FEAT_SVM, /* CPUID[8000_000A].EDX */ |
| | 456 | FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ |
| | 457 | FEAT_6_EAX, /* CPUID[6].EAX */ |
| | 458 | FEATURE_WORDS, |
| | 459 | } FeatureWord; |
| | 460 | |
| | 461 | typedef uint32_t FeatureWordArray[FEATURE_WORDS]; |
| | 462 | |
| | 463 | /* cpuid_features bits */ |
| | 464 | #define CPUID_FP87 (1U << 0) |
| | 465 | #define CPUID_VME (1U << 1) |
| | 466 | #define CPUID_DE (1U << 2) |
| | 467 | #define CPUID_PSE (1U << 3) |
| | 468 | #define CPUID_TSC (1U << 4) |
| | 469 | #define CPUID_MSR (1U << 5) |
| | 470 | #define CPUID_PAE (1U << 6) |
| | 471 | #define CPUID_MCE (1U << 7) |
| | 472 | #define CPUID_CX8 (1U << 8) |
| | 473 | #define CPUID_APIC (1U << 9) |
| | 474 | #define CPUID_SEP (1U << 11) /* sysenter/sysexit */ |
| | 475 | #define CPUID_MTRR (1U << 12) |
| | 476 | #define CPUID_PGE (1U << 13) |
| | 477 | #define CPUID_MCA (1U << 14) |
| | 478 | #define CPUID_CMOV (1U << 15) |
| | 479 | #define CPUID_PAT (1U << 16) |
| | 480 | #define CPUID_PSE36 (1U << 17) |
| | 481 | #define CPUID_PN (1U << 18) |
| | 482 | #define CPUID_CLFLUSH (1U << 19) |
| | 483 | #define CPUID_DTS (1U << 21) |
| | 484 | #define CPUID_ACPI (1U << 22) |
| | 485 | #define CPUID_MMX (1U << 23) |
| | 486 | #define CPUID_FXSR (1U << 24) |
| | 487 | #define CPUID_SSE (1U << 25) |
| | 488 | #define CPUID_SSE2 (1U << 26) |
| | 489 | #define CPUID_SS (1U << 27) |
| | 490 | #define CPUID_HT (1U << 28) |
| | 491 | #define CPUID_TM (1U << 29) |
| | 492 | #define CPUID_IA64 (1U << 30) |
| | 493 | #define CPUID_PBE (1U << 31) |
| | 494 | |
| | 495 | #define CPUID_EXT_SSE3 (1U << 0) |
| | 496 | #define CPUID_EXT_PCLMULQDQ (1U << 1) |
| | 497 | #define CPUID_EXT_DTES64 (1U << 2) |
| | 498 | #define CPUID_EXT_MONITOR (1U << 3) |
| | 499 | #define CPUID_EXT_DSCPL (1U << 4) |
| | 500 | #define CPUID_EXT_VMX (1U << 5) |
| | 501 | #define CPUID_EXT_SMX (1U << 6) |
| | 502 | #define CPUID_EXT_EST (1U << 7) |
| | 503 | #define CPUID_EXT_TM2 (1U << 8) |
| | 504 | #define CPUID_EXT_SSSE3 (1U << 9) |
| | 505 | #define CPUID_EXT_CID (1U << 10) |
| | 506 | #define CPUID_EXT_FMA (1U << 12) |
| | 507 | #define CPUID_EXT_CX16 (1U << 13) |
| | 508 | #define CPUID_EXT_XTPR (1U << 14) |
| | 509 | #define CPUID_EXT_PDCM (1U << 15) |
| | 510 | #define CPUID_EXT_PCID (1U << 17) |
| | 511 | #define CPUID_EXT_DCA (1U << 18) |
| | 512 | #define CPUID_EXT_SSE41 (1U << 19) |
| | 513 | #define CPUID_EXT_SSE42 (1U << 20) |
| | 514 | #define CPUID_EXT_X2APIC (1U << 21) |
| | 515 | #define CPUID_EXT_MOVBE (1U << 22) |
| | 516 | #define CPUID_EXT_POPCNT (1U << 23) |
| | 517 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) |
| | 518 | #define CPUID_EXT_AES (1U << 25) |
| | 519 | #define CPUID_EXT_XSAVE (1U << 26) |
| | 520 | #define CPUID_EXT_OSXSAVE (1U << 27) |
| | 521 | #define CPUID_EXT_AVX (1U << 28) |
| | 522 | #define CPUID_EXT_F16C (1U << 29) |
| | 523 | #define CPUID_EXT_RDRAND (1U << 30) |
| | 524 | #define CPUID_EXT_HYPERVISOR (1U << 31) |
| | 525 | |
| | 526 | #define CPUID_EXT2_FPU (1U << 0) |
| | 527 | #define CPUID_EXT2_VME (1U << 1) |
| | 528 | #define CPUID_EXT2_DE (1U << 2) |
| | 529 | #define CPUID_EXT2_PSE (1U << 3) |
| | 530 | #define CPUID_EXT2_TSC (1U << 4) |
| | 531 | #define CPUID_EXT2_MSR (1U << 5) |
| | 532 | #define CPUID_EXT2_PAE (1U << 6) |
| | 533 | #define CPUID_EXT2_MCE (1U << 7) |
| | 534 | #define CPUID_EXT2_CX8 (1U << 8) |
| | 535 | #define CPUID_EXT2_APIC (1U << 9) |
| | 536 | #define CPUID_EXT2_SYSCALL (1U << 11) |
| | 537 | #define CPUID_EXT2_MTRR (1U << 12) |
| | 538 | #define CPUID_EXT2_PGE (1U << 13) |
| | 539 | #define CPUID_EXT2_MCA (1U << 14) |
| | 540 | #define CPUID_EXT2_CMOV (1U << 15) |
| | 541 | #define CPUID_EXT2_PAT (1U << 16) |
| | 542 | #define CPUID_EXT2_PSE36 (1U << 17) |
| | 543 | #define CPUID_EXT2_MP (1U << 19) |
| | 544 | #define CPUID_EXT2_NX (1U << 20) |
| | 545 | #define CPUID_EXT2_MMXEXT (1U << 22) |
| | 546 | #define CPUID_EXT2_MMX (1U << 23) |
| | 547 | #define CPUID_EXT2_FXSR (1U << 24) |
| | 548 | #define CPUID_EXT2_FFXSR (1U << 25) |
| | 549 | #define CPUID_EXT2_PDPE1GB (1U << 26) |
| | 550 | #define CPUID_EXT2_RDTSCP (1U << 27) |
| | 551 | #define CPUID_EXT2_LM (1U << 29) |
| | 552 | #define CPUID_EXT2_3DNOWEXT (1U << 30) |
| | 553 | #define CPUID_EXT2_3DNOW (1U << 31) |
| | 554 | |
| | 555 | /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ |
| | 556 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ |
| | 557 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ |
| | 558 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ |
| | 559 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ |
| | 560 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ |
| | 561 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ |
| | 562 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ |
| | 563 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ |
| | 564 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) |
| | 565 | |
| | 566 | #define CPUID_EXT3_LAHF_LM (1U << 0) |
| | 567 | #define CPUID_EXT3_CMP_LEG (1U << 1) |
| | 568 | #define CPUID_EXT3_SVM (1U << 2) |
| | 569 | #define CPUID_EXT3_EXTAPIC (1U << 3) |
| | 570 | #define CPUID_EXT3_CR8LEG (1U << 4) |
| | 571 | #define CPUID_EXT3_ABM (1U << 5) |
| | 572 | #define CPUID_EXT3_SSE4A (1U << 6) |
| | 573 | #define CPUID_EXT3_MISALIGNSSE (1U << 7) |
| | 574 | #define CPUID_EXT3_3DNOWPREFETCH (1U << 8) |
| | 575 | #define CPUID_EXT3_OSVW (1U << 9) |
| | 576 | #define CPUID_EXT3_IBS (1U << 10) |
| | 577 | #define CPUID_EXT3_XOP (1U << 11) |
| | 578 | #define CPUID_EXT3_SKINIT (1U << 12) |
| | 579 | #define CPUID_EXT3_WDT (1U << 13) |
| | 580 | #define CPUID_EXT3_LWP (1U << 15) |
| | 581 | #define CPUID_EXT3_FMA4 (1U << 16) |
| | 582 | #define CPUID_EXT3_TCE (1U << 17) |
| | 583 | #define CPUID_EXT3_NODEID (1U << 19) |
| | 584 | #define CPUID_EXT3_TBM (1U << 21) |
| | 585 | #define CPUID_EXT3_TOPOEXT (1U << 22) |
| | 586 | #define CPUID_EXT3_PERFCORE (1U << 23) |
| | 587 | #define CPUID_EXT3_PERFNB (1U << 24) |
| | 588 | |
| | 589 | #define CPUID_SVM_NPT (1U << 0) |
| | 590 | #define CPUID_SVM_LBRV (1U << 1) |
| | 591 | #define CPUID_SVM_SVMLOCK (1U << 2) |
| | 592 | #define CPUID_SVM_NRIPSAVE (1U << 3) |
| | 593 | #define CPUID_SVM_TSCSCALE (1U << 4) |
| | 594 | #define CPUID_SVM_VMCBCLEAN (1U << 5) |
| | 595 | #define CPUID_SVM_FLUSHASID (1U << 6) |
| | 596 | #define CPUID_SVM_DECODEASSIST (1U << 7) |
| | 597 | #define CPUID_SVM_PAUSEFILTER (1U << 10) |
| | 598 | #define CPUID_SVM_PFTHRESHOLD (1U << 12) |
| | 599 | |
| | 600 | #define CPUID_7_0_EBX_FSGSBASE (1U << 0) |
| | 601 | #define CPUID_7_0_EBX_BMI1 (1U << 3) |
| | 602 | #define CPUID_7_0_EBX_HLE (1U << 4) |
| | 603 | #define CPUID_7_0_EBX_AVX2 (1U << 5) |
| | 604 | #define CPUID_7_0_EBX_SMEP (1U << 7) |
| | 605 | #define CPUID_7_0_EBX_BMI2 (1U << 8) |
| | 606 | #define CPUID_7_0_EBX_ERMS (1U << 9) |
| | 607 | #define CPUID_7_0_EBX_INVPCID (1U << 10) |
| | 608 | #define CPUID_7_0_EBX_RTM (1U << 11) |
| | 609 | #define CPUID_7_0_EBX_MPX (1U << 14) |
| | 610 | #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */ |
| | 611 | #define CPUID_7_0_EBX_RDSEED (1U << 18) |
| | 612 | #define CPUID_7_0_EBX_ADX (1U << 19) |
| | 613 | #define CPUID_7_0_EBX_SMAP (1U << 20) |
| | 614 | #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ |
| | 615 | #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ |
| | 616 | #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ |
| | 617 | #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ |
| | 618 | #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ |
| | 619 | #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ |
| | 620 | |
| | 621 | #define CPUID_7_0_ECX_PKU (1U << 3) |
| | 622 | #define CPUID_7_0_ECX_OSPKE (1U << 4) |
| | 623 | |
| | 624 | #define CPUID_XSAVE_XSAVEOPT (1U << 0) |
| | 625 | #define CPUID_XSAVE_XSAVEC (1U << 1) |
| | 626 | #define CPUID_XSAVE_XGETBV1 (1U << 2) |
| | 627 | #define CPUID_XSAVE_XSAVES (1U << 3) |
| | 628 | |
| | 629 | #define CPUID_6_EAX_ARAT (1U << 2) |
| | 630 | |
| | 631 | /* CPUID[0x80000007].EDX flags: */ |
| | 632 | #define CPUID_APM_INVTSC (1U << 8) |
| | 633 | |
| | 634 | #define CPUID_VENDOR_SZ 12 |
| | 635 | |
| | 636 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
| | 637 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ |
| | 638 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ |
| | 639 | #define CPUID_VENDOR_INTEL "GenuineIntel" |
| | 640 | |
| | 641 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ |
| | 642 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
| | 643 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
| | 644 | #define CPUID_VENDOR_AMD "AuthenticAMD" |
| | 645 | |
| | 646 | #define CPUID_VENDOR_VIA "CentaurHauls" |
| | 647 | |
| | 648 | #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ |
| | 649 | #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ |
| | 650 | |
| | 651 | /* CPUID[0xB].ECX level types */ |
| | 652 | #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) |
| | 653 | #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) |
| | 654 | #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) |
| | 655 | |
| | 656 | #ifndef HYPERV_SPINLOCK_NEVER_RETRY |
| | 657 | #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF |
| | 658 | #endif |
| | 659 | |
| | 660 | #define EXCP00_DIVZ 0 |
| | 661 | #define EXCP01_DB 1 |
| | 662 | #define EXCP02_NMI 2 |
| | 663 | #define EXCP03_INT3 3 |
| | 664 | #define EXCP04_INTO 4 |
| | 665 | #define EXCP05_BOUND 5 |
| | 666 | #define EXCP06_ILLOP 6 |
| | 667 | #define EXCP07_PREX 7 |
| | 668 | #define EXCP08_DBLE 8 |
| | 669 | #define EXCP09_XERR 9 |
| | 670 | #define EXCP0A_TSS 10 |
| | 671 | #define EXCP0B_NOSEG 11 |
| | 672 | #define EXCP0C_STACK 12 |
| | 673 | #define EXCP0D_GPF 13 |
| | 674 | #define EXCP0E_PAGE 14 |
| | 675 | #define EXCP10_COPR 16 |
| | 676 | #define EXCP11_ALGN 17 |
| | 677 | #define EXCP12_MCHK 18 |
| | 678 | |
| | 679 | #define EXCP_SYSCALL 0x100 /* only happens in user only emulation |
| | 680 | for syscall instruction */ |
| | 681 | |
| | 682 | /* i386-specific interrupt pending bits. */ |
| | 683 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 |
| | 684 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 |
| | 685 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 |
| | 686 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 |
| | 687 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 |
| | 688 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1 |
| | 689 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2 |
| | 690 | |
| | 691 | /* Use a clearer name for this. */ |
| | 692 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET |
| | 693 | |
| | 694 | typedef enum { |
| | 695 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ |
| | 696 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ |
| | 697 | |
| | 698 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ |
| | 699 | CC_OP_MULW, |
| | 700 | CC_OP_MULL, |
| | 701 | CC_OP_MULQ, |
| | 702 | |
| | 703 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| | 704 | CC_OP_ADDW, |
| | 705 | CC_OP_ADDL, |
| | 706 | CC_OP_ADDQ, |
| | 707 | |
| | 708 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| | 709 | CC_OP_ADCW, |
| | 710 | CC_OP_ADCL, |
| | 711 | CC_OP_ADCQ, |
| | 712 | |
| | 713 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| | 714 | CC_OP_SUBW, |
| | 715 | CC_OP_SUBL, |
| | 716 | CC_OP_SUBQ, |
| | 717 | |
| | 718 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
| | 719 | CC_OP_SBBW, |
| | 720 | CC_OP_SBBL, |
| | 721 | CC_OP_SBBQ, |
| | 722 | |
| | 723 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ |
| | 724 | CC_OP_LOGICW, |
| | 725 | CC_OP_LOGICL, |
| | 726 | CC_OP_LOGICQ, |
| | 727 | |
| | 728 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
| | 729 | CC_OP_INCW, |
| | 730 | CC_OP_INCL, |
| | 731 | CC_OP_INCQ, |
| | 732 | |
| | 733 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
| | 734 | CC_OP_DECW, |
| | 735 | CC_OP_DECL, |
| | 736 | CC_OP_DECQ, |
| | 737 | |
| | 738 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
| | 739 | CC_OP_SHLW, |
| | 740 | CC_OP_SHLL, |
| | 741 | CC_OP_SHLQ, |
| | 742 | |
| | 743 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ |
| | 744 | CC_OP_SARW, |
| | 745 | CC_OP_SARL, |
| | 746 | CC_OP_SARQ, |
| | 747 | |
| | 748 | CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ |
| | 749 | CC_OP_BMILGW, |
| | 750 | CC_OP_BMILGL, |
| | 751 | CC_OP_BMILGQ, |
| | 752 | |
| | 753 | CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ |
| | 754 | CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ |
| | 755 | CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ |
| | 756 | |
| | 757 | CC_OP_CLR, /* Z set, all other flags clear. */ |
| | 758 | |
| | 759 | CC_OP_NB, |
| | 760 | } CCOp; |
| | 761 | |
| | 762 | typedef struct SegmentCache { |
| | 763 | uint32_t selector; |
| | 764 | target_ulong base; |
| | 765 | uint32_t limit; |
| | 766 | uint32_t flags; |
| | 767 | } SegmentCache; |
| | 768 | |
| | 769 | #define MMREG_UNION(n, bits) \ |
| | 770 | union n { \ |
| | 771 | uint8_t _b_##n[(bits)/8]; \ |
| | 772 | uint16_t _w_##n[(bits)/16]; \ |
| | 773 | uint32_t _l_##n[(bits)/32]; \ |
| | 774 | uint64_t _q_##n[(bits)/64]; \ |
| | 775 | float32 _s_##n[(bits)/32]; \ |
| | 776 | float64 _d_##n[(bits)/64]; \ |
| | 777 | } |
| | 778 | |
| | 779 | typedef MMREG_UNION(ZMMReg, 512) ZMMReg; |
| | 780 | typedef MMREG_UNION(MMXReg, 64) MMXReg; |
| | 781 | |
| | 782 | typedef struct BNDReg { |
| | 783 | uint64_t lb; |
| | 784 | uint64_t ub; |
| | 785 | } BNDReg; |
| | 786 | |
| | 787 | typedef struct BNDCSReg { |
| | 788 | uint64_t cfgu; |
| | 789 | uint64_t sts; |
| | 790 | } BNDCSReg; |
| | 791 | |
| | 792 | #define BNDCFG_ENABLE 1ULL |
| | 793 | #define BNDCFG_BNDPRESERVE 2ULL |
| | 794 | #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK |
| | 795 | |
| | 796 | #ifdef HOST_WORDS_BIGENDIAN |
| | 797 | #define ZMM_B(n) _b_ZMMReg[63 - (n)] |
| | 798 | #define ZMM_W(n) _w_ZMMReg[31 - (n)] |
| | 799 | #define ZMM_L(n) _l_ZMMReg[15 - (n)] |
| | 800 | #define ZMM_S(n) _s_ZMMReg[15 - (n)] |
| | 801 | #define ZMM_Q(n) _q_ZMMReg[7 - (n)] |
| | 802 | #define ZMM_D(n) _d_ZMMReg[7 - (n)] |
| | 803 | |
| | 804 | #define MMX_B(n) _b_MMXReg[7 - (n)] |
| | 805 | #define MMX_W(n) _w_MMXReg[3 - (n)] |
| | 806 | #define MMX_L(n) _l_MMXReg[1 - (n)] |
| | 807 | #define MMX_S(n) _s_MMXReg[1 - (n)] |
| | 808 | #else |
| | 809 | #define ZMM_B(n) _b_ZMMReg[n] |
| | 810 | #define ZMM_W(n) _w_ZMMReg[n] |
| | 811 | #define ZMM_L(n) _l_ZMMReg[n] |
| | 812 | #define ZMM_S(n) _s_ZMMReg[n] |
| | 813 | #define ZMM_Q(n) _q_ZMMReg[n] |
| | 814 | #define ZMM_D(n) _d_ZMMReg[n] |
| | 815 | |
| | 816 | #define MMX_B(n) _b_MMXReg[n] |
| | 817 | #define MMX_W(n) _w_MMXReg[n] |
| | 818 | #define MMX_L(n) _l_MMXReg[n] |
| | 819 | #define MMX_S(n) _s_MMXReg[n] |
| | 820 | #endif |
| | 821 | #define MMX_Q(n) _q_MMXReg[n] |
| | 822 | |
| | 823 | typedef union { |
| | 824 | floatx80 d __attribute__((aligned(16))); |
| | 825 | MMXReg mmx; |
| | 826 | } FPReg; |
| | 827 | |
| | 828 | typedef struct { |
| | 829 | uint64_t base; |
| | 830 | uint64_t mask; |
| | 831 | } MTRRVar; |
| | 832 | |
| | 833 | #define CPU_NB_REGS64 16 |
| | 834 | #define CPU_NB_REGS32 8 |
| | 835 | |
| | 836 | #ifdef TARGET_X86_64 |
| | 837 | #define CPU_NB_REGS CPU_NB_REGS64 |
| | 838 | #else |
| | 839 | #define CPU_NB_REGS CPU_NB_REGS32 |
| | 840 | #endif |
| | 841 | |
| | 842 | #define MAX_FIXED_COUNTERS 3 |
| | 843 | #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) |
| | 844 | |
| | 845 | #define NB_MMU_MODES 3 |
| | 846 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
| | 847 | |
| | 848 | #define NB_OPMASK_REGS 8 |
| | 849 | |
| | 850 | typedef union X86LegacyXSaveArea { |
| | 851 | struct { |
| | 852 | uint16_t fcw; |
| | 853 | uint16_t fsw; |
| | 854 | uint8_t ftw; |
| | 855 | uint8_t reserved; |
| | 856 | uint16_t fpop; |
| | 857 | uint64_t fpip; |
| | 858 | uint64_t fpdp; |
| | 859 | uint32_t mxcsr; |
| | 860 | uint32_t mxcsr_mask; |
| | 861 | FPReg fpregs[8]; |
| | 862 | uint8_t xmm_regs[16][16]; |
| | 863 | }; |
| | 864 | uint8_t data[512]; |
| | 865 | } X86LegacyXSaveArea; |
| | 866 | |
| | 867 | typedef struct X86XSaveHeader { |
| | 868 | uint64_t xstate_bv; |
| | 869 | uint64_t xcomp_bv; |
| | 870 | uint8_t reserved[48]; |
| | 871 | } X86XSaveHeader; |
| | 872 | |
| | 873 | /* Ext. save area 2: AVX State */ |
| | 874 | typedef struct XSaveAVX { |
| | 875 | uint8_t ymmh[16][16]; |
| | 876 | } XSaveAVX; |
| | 877 | |
| | 878 | /* Ext. save area 3: BNDREG */ |
| | 879 | typedef struct XSaveBNDREG { |
| | 880 | BNDReg bnd_regs[4]; |
| | 881 | } XSaveBNDREG; |
| | 882 | |
| | 883 | /* Ext. save area 4: BNDCSR */ |
| | 884 | typedef union XSaveBNDCSR { |
| | 885 | BNDCSReg bndcsr; |
| | 886 | uint8_t data[64]; |
| | 887 | } XSaveBNDCSR; |
| | 888 | |
| | 889 | /* Ext. save area 5: Opmask */ |
| | 890 | typedef struct XSaveOpmask { |
| | 891 | uint64_t opmask_regs[NB_OPMASK_REGS]; |
| | 892 | } XSaveOpmask; |
| | 893 | |
| | 894 | /* Ext. save area 6: ZMM_Hi256 */ |
| | 895 | typedef struct XSaveZMM_Hi256 { |
| | 896 | uint8_t zmm_hi256[16][32]; |
| | 897 | } XSaveZMM_Hi256; |
| | 898 | |
| | 899 | /* Ext. save area 7: Hi16_ZMM */ |
| | 900 | typedef struct XSaveHi16_ZMM { |
| | 901 | uint8_t hi16_zmm[16][64]; |
| | 902 | } XSaveHi16_ZMM; |
| | 903 | |
| | 904 | /* Ext. save area 9: PKRU state */ |
| | 905 | typedef struct XSavePKRU { |
| | 906 | uint32_t pkru; |
| | 907 | uint32_t padding; |
| | 908 | } XSavePKRU; |
| | 909 | |
| | 910 | typedef struct X86XSaveArea { |
| | 911 | X86LegacyXSaveArea legacy; |
| | 912 | X86XSaveHeader header; |
| | 913 | |
| | 914 | /* Extended save areas: */ |
| | 915 | |
| | 916 | /* AVX State: */ |
| | 917 | XSaveAVX avx_state; |
| | 918 | uint8_t padding[960 - 576 - sizeof(XSaveAVX)]; |
| | 919 | /* MPX State: */ |
| | 920 | XSaveBNDREG bndreg_state; |
| | 921 | XSaveBNDCSR bndcsr_state; |
| | 922 | /* AVX-512 State: */ |
| | 923 | XSaveOpmask opmask_state; |
| | 924 | XSaveZMM_Hi256 zmm_hi256_state; |
| | 925 | XSaveHi16_ZMM hi16_zmm_state; |
| | 926 | /* PKRU State: */ |
| | 927 | XSavePKRU pkru_state; |
| | 928 | } X86XSaveArea; |
| | 929 | |
| | 930 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240); |
| | 931 | QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); |
| | 932 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0); |
| | 933 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); |
| | 934 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400); |
| | 935 | QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); |
| | 936 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440); |
| | 937 | QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40); |
| | 938 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480); |
| | 939 | QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); |
| | 940 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680); |
| | 941 | QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); |
| | 942 | QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80); |
| | 943 | QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); |
| | 944 | |
| | 945 | typedef enum TPRAccess { |
| | 946 | TPR_ACCESS_READ, |
| | 947 | TPR_ACCESS_WRITE, |
| | 948 | } TPRAccess; |
| | 949 | |
| | 950 | typedef struct CPUX86State { |
| | 951 | /* standard registers */ |
| | 952 | target_ulong regs[CPU_NB_REGS]; |
| | 953 | target_ulong eip; |
| | 954 | target_ulong eflags; /* eflags register. During CPU emulation, CC |
| | 955 | flags and DF are set to zero because they are |
| | 956 | stored elsewhere */ |
| | 957 | |
| | 958 | /* emulator internal eflags handling */ |
| | 959 | target_ulong cc_dst; |
| | 960 | target_ulong cc_src; |
| | 961 | target_ulong cc_src2; |
| | 962 | uint32_t cc_op; |
| | 963 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ |
| | 964 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
| | 965 | are known at translation time. */ |
| | 966 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ |
| | 967 | |
| | 968 | /* segments */ |
| | 969 | SegmentCache segs[6]; /* selector values */ |
| | 970 | SegmentCache ldt; |
| | 971 | SegmentCache tr; |
| | 972 | SegmentCache gdt; /* only base and limit are used */ |
| | 973 | SegmentCache idt; /* only base and limit are used */ |
| | 974 | |
| | 975 | target_ulong cr[5]; /* NOTE: cr1 is unused */ |
| | 976 | int32_t a20_mask; |
| | 977 | |
| | 978 | BNDReg bnd_regs[4]; |
| | 979 | BNDCSReg bndcs_regs; |
| | 980 | uint64_t msr_bndcfgs; |
| | 981 | uint64_t efer; |
| | 982 | |
| | 983 | /* Beginning of state preserved by INIT (dummy marker). */ |
| | 984 | struct {} start_init_save; |
| | 985 | |
| | 986 | /* FPU state */ |
| | 987 | unsigned int fpstt; /* top of stack index */ |
| | 988 | uint16_t fpus; |
| | 989 | uint16_t fpuc; |
| | 990 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
| | 991 | FPReg fpregs[8]; |
| | 992 | /* KVM-only so far */ |
| | 993 | uint16_t fpop; |
| | 994 | uint64_t fpip; |
| | 995 | uint64_t fpdp; |
| | 996 | |
| | 997 | /* emulator internal variables */ |
| | 998 | float_status fp_status; |
| | 999 | floatx80 ft0; |
| | 1000 | |
| | 1001 | float_status mmx_status; /* for 3DNow! float ops */ |
| | 1002 | float_status sse_status; |
| | 1003 | uint32_t mxcsr; |
| | 1004 | ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; |
| | 1005 | ZMMReg xmm_t0; |
| | 1006 | MMXReg mmx_t0; |
| | 1007 | |
| | 1008 | uint64_t opmask_regs[NB_OPMASK_REGS]; |
| | 1009 | |
| | 1010 | /* sysenter registers */ |
| | 1011 | uint32_t sysenter_cs; |
| | 1012 | target_ulong sysenter_esp; |
| | 1013 | target_ulong sysenter_eip; |
| | 1014 | uint64_t star; |
| | 1015 | |
| | 1016 | uint64_t vm_hsave; |
| | 1017 | |
| | 1018 | #ifdef TARGET_X86_64 |
| | 1019 | target_ulong lstar; |
| | 1020 | target_ulong cstar; |
| | 1021 | target_ulong fmask; |
| | 1022 | target_ulong kernelgsbase; |
| | 1023 | #endif |
| | 1024 | |
| | 1025 | uint64_t tsc; |
| | 1026 | uint64_t tsc_adjust; |
| | 1027 | uint64_t tsc_deadline; |
| | 1028 | |
| | 1029 | uint64_t mcg_status; |
| | 1030 | uint64_t msr_ia32_misc_enable; |
| | 1031 | uint64_t msr_ia32_feature_control; |
| | 1032 | |
| | 1033 | uint64_t msr_fixed_ctr_ctrl; |
| | 1034 | uint64_t msr_global_ctrl; |
| | 1035 | uint64_t msr_global_status; |
| | 1036 | uint64_t msr_global_ovf_ctrl; |
| | 1037 | uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; |
| | 1038 | uint64_t msr_gp_counters[MAX_GP_COUNTERS]; |
| | 1039 | uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; |
| | 1040 | |
| | 1041 | uint64_t pat; |
| | 1042 | uint32_t smbase; |
| | 1043 | |
| | 1044 | /* End of state preserved by INIT (dummy marker). */ |
| | 1045 | struct {} end_init_save; |
| | 1046 | |
| | 1047 | uint64_t system_time_msr; |
| | 1048 | uint64_t wall_clock_msr; |
| | 1049 | uint64_t steal_time_msr; |
| | 1050 | uint64_t async_pf_en_msr; |
| | 1051 | uint64_t pv_eoi_en_msr; |
| | 1052 | |
| | 1053 | uint64_t msr_hv_hypercall; |
| | 1054 | uint64_t msr_hv_guest_os_id; |
| | 1055 | uint64_t msr_hv_vapic; |
| | 1056 | uint64_t msr_hv_tsc; |
| | 1057 | uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS]; |
| | 1058 | uint64_t msr_hv_runtime; |
| | 1059 | uint64_t msr_hv_synic_control; |
| | 1060 | uint64_t msr_hv_synic_version; |
| | 1061 | uint64_t msr_hv_synic_evt_page; |
| | 1062 | uint64_t msr_hv_synic_msg_page; |
| | 1063 | uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT]; |
| | 1064 | uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT]; |
| | 1065 | uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT]; |
| | 1066 | |
| | 1067 | /* exception/interrupt handling */ |
| | 1068 | int error_code; |
| | 1069 | int exception_is_int; |
| | 1070 | target_ulong exception_next_eip; |
| | 1071 | target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */ |
| | 1072 | union { |
| | 1073 | struct CPUBreakpoint *cpu_breakpoint[4]; |
| | 1074 | struct CPUWatchpoint *cpu_watchpoint[4]; |
| | 1075 | }; /* break/watchpoints for dr[0..3] */ |
| | 1076 | int old_exception; /* exception in flight */ |
| | 1077 | |
| | 1078 | uint64_t vm_vmcb; |
| | 1079 | uint64_t tsc_offset; |
| | 1080 | uint64_t intercept; |
| | 1081 | uint16_t intercept_cr_read; |
| | 1082 | uint16_t intercept_cr_write; |
| | 1083 | uint16_t intercept_dr_read; |
| | 1084 | uint16_t intercept_dr_write; |
| | 1085 | uint32_t intercept_exceptions; |
| | 1086 | uint8_t v_tpr; |
| | 1087 | |
| | 1088 | /* KVM states, automatically cleared on reset */ |
| | 1089 | uint8_t nmi_injected; |
| | 1090 | uint8_t nmi_pending; |
| | 1091 | |
| | 1092 | CPU_COMMON |
| | 1093 | |
| | 1094 | /* Fields from here on are preserved across CPU reset. */ |
| | 1095 | |
| | 1096 | /* processor features (e.g. for CPUID insn) */ |
| | 1097 | uint32_t cpuid_level; |
| | 1098 | uint32_t cpuid_xlevel; |
| | 1099 | uint32_t cpuid_xlevel2; |
| | 1100 | uint32_t cpuid_vendor1; |
| | 1101 | uint32_t cpuid_vendor2; |
| | 1102 | uint32_t cpuid_vendor3; |
| | 1103 | uint32_t cpuid_version; |
| | 1104 | FeatureWordArray features; |
| | 1105 | uint32_t cpuid_model[12]; |
| | 1106 | |
| | 1107 | /* MTRRs */ |
| | 1108 | uint64_t mtrr_fixed[11]; |
| | 1109 | uint64_t mtrr_deftype; |
| | 1110 | MTRRVar mtrr_var[MSR_MTRRcap_VCNT]; |
| | 1111 | |
| | 1112 | /* For KVM */ |
| | 1113 | uint32_t mp_state; |
| | 1114 | int32_t exception_injected; |
| | 1115 | int32_t interrupt_injected; |
| | 1116 | uint8_t soft_interrupt; |
| | 1117 | uint8_t has_error_code; |
| | 1118 | uint32_t sipi_vector; |
| | 1119 | bool tsc_valid; |
| | 1120 | int64_t tsc_khz; |
| | 1121 | int64_t user_tsc_khz; /* for sanity check only */ |
| | 1122 | void *kvm_xsave_buf; |
| | 1123 | |
| | 1124 | uint64_t mcg_cap; |
| | 1125 | uint64_t mcg_ctl; |
| | 1126 | uint64_t mcg_ext_ctl; |
| | 1127 | uint64_t mce_banks[MCE_BANKS_DEF*4]; |
| | 1128 | |
| | 1129 | uint64_t tsc_aux; |
| | 1130 | |
| | 1131 | /* vmstate */ |
| | 1132 | uint16_t fpus_vmstate; |
| | 1133 | uint16_t fptag_vmstate; |
| | 1134 | uint16_t fpregs_format_vmstate; |
| | 1135 | uint64_t xstate_bv; |
| | 1136 | |
| | 1137 | uint64_t xcr0; |
| | 1138 | uint64_t xss; |
| | 1139 | |
| | 1140 | uint32_t pkru; |
| | 1141 | |
| | 1142 | TPRAccess tpr_access_type; |
| | 1143 | } CPUX86State; |
| | 1144 | |
| | 1145 | struct kvm_msrs; |
| | 1146 | |
| | 1147 | /** |
| | 1148 | * X86CPU: |
| | 1149 | * @env: #CPUX86State |
| | 1150 | * @migratable: If set, only migratable flags will be accepted when "enforce" |
| | 1151 | * mode is used, and only migratable flags will be included in the "host" |
| | 1152 | * CPU model. |
| | 1153 | * |
| | 1154 | * An x86 CPU. |
| | 1155 | */ |
| | 1156 | struct X86CPU { |
| | 1157 | /*< private >*/ |
| | 1158 | CPUState parent_obj; |
| | 1159 | /*< public >*/ |
| | 1160 | |
| | 1161 | CPUX86State env; |
| | 1162 | |
| | 1163 | bool hyperv_vapic; |
| | 1164 | bool hyperv_relaxed_timing; |
| | 1165 | int hyperv_spinlock_attempts; |
| | 1166 | char *hyperv_vendor_id; |
| | 1167 | bool hyperv_time; |
| | 1168 | bool hyperv_crash; |
| | 1169 | bool hyperv_reset; |
| | 1170 | bool hyperv_vpindex; |
| | 1171 | bool hyperv_runtime; |
| | 1172 | bool hyperv_synic; |
| | 1173 | bool hyperv_stimer; |
| | 1174 | bool check_cpuid; |
| | 1175 | bool enforce_cpuid; |
| | 1176 | bool expose_kvm; |
| | 1177 | bool migratable; |
| | 1178 | bool host_features; |
| | 1179 | int64_t apic_id; |
| | 1180 | |
| | 1181 | /* if true the CPUID code directly forward host cache leaves to the guest */ |
| | 1182 | bool cache_info_passthrough; |
| | 1183 | |
| | 1184 | /* Features that were filtered out because of missing host capabilities */ |
| | 1185 | uint32_t filtered_features[FEATURE_WORDS]; |
| | 1186 | |
| | 1187 | /* Enable PMU CPUID bits. This can't be enabled by default yet because |
| | 1188 | * it doesn't have ABI stability guarantees, as it passes all PMU CPUID |
| | 1189 | * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel |
| | 1190 | * capabilities) directly to the guest. |
| | 1191 | */ |
| | 1192 | bool enable_pmu; |
| | 1193 | |
| | 1194 | /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is |
| | 1195 | * disabled by default to avoid breaking migration between QEMU with |
| | 1196 | * different LMCE configurations. |
| | 1197 | */ |
| | 1198 | bool enable_lmce; |
| | 1199 | |
| | 1200 | /* Compatibility bits for old machine types: */ |
| | 1201 | bool enable_cpuid_0xb; |
| | 1202 | |
| | 1203 | /* in order to simplify APIC support, we leave this pointer to the |
| | 1204 | user */ |
| | 1205 | struct DeviceState *apic_state; |
| | 1206 | struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram; |
| | 1207 | Notifier machine_done; |
| | 1208 | |
| | 1209 | struct kvm_msrs *kvm_msr_buf; |
| | 1210 | }; |
| | 1211 | |
| | 1212 | static inline X86CPU *x86_env_get_cpu(CPUX86State *env) |
| | 1213 | { |
| | 1214 | return container_of(env, X86CPU, env); |
| | 1215 | } |
| | 1216 | |
| | 1217 | #define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e)) |
| | 1218 | |
| | 1219 | #define ENV_OFFSET offsetof(X86CPU, env) |
| | 1220 | |
| | 1221 | #ifndef CONFIG_USER_ONLY |
| | 1222 | extern struct VMStateDescription vmstate_x86_cpu; |
| | 1223 | #endif |
| | 1224 | |
| | 1225 | /** |
| | 1226 | * x86_cpu_do_interrupt: |
| | 1227 | * @cpu: vCPU the interrupt is to be handled by. |
| | 1228 | */ |
| | 1229 | void x86_cpu_do_interrupt(CPUState *cpu); |
| | 1230 | bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); |
| | 1231 | |
| | 1232 | int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, |
| | 1233 | int cpuid, void *opaque); |
| | 1234 | int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, |
| | 1235 | int cpuid, void *opaque); |
| | 1236 | int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
| | 1237 | void *opaque); |
| | 1238 | int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
| | 1239 | void *opaque); |
| | 1240 | |
| | 1241 | void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, |
| | 1242 | Error **errp); |
| | 1243 | |
| | 1244 | void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
| | 1245 | int flags); |
| | 1246 | |
| | 1247 | hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
| | 1248 | |
| | 1249 | int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); |
| | 1250 | int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
| | 1251 | |
| | 1252 | void x86_cpu_exec_enter(CPUState *cpu); |
| | 1253 | void x86_cpu_exec_exit(CPUState *cpu); |
| | 1254 | |
| | 1255 | X86CPU *cpu_x86_init(const char *cpu_model); |
| | 1256 | void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
| | 1257 | int cpu_x86_support_mca_broadcast(CPUX86State *env); |
| | 1258 | |
| | 1259 | int cpu_get_pic_interrupt(CPUX86State *s); |
| | 1260 | /* MSDOS compatibility mode FPU exception support */ |
| | 1261 | void cpu_set_ferr(CPUX86State *s); |
| | 1262 | |
| | 1263 | /* this function must always be used to load data in the segment |
| | 1264 | cache: it synchronizes the hflags with the segment cache values */ |
| | 1265 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
| | 1266 | int seg_reg, unsigned int selector, |
| | 1267 | target_ulong base, |
| | 1268 | unsigned int limit, |
| | 1269 | unsigned int flags) |
| | 1270 | { |
| | 1271 | SegmentCache *sc; |
| | 1272 | unsigned int new_hflags; |
| | 1273 | |
| | 1274 | sc = &env->segs[seg_reg]; |
| | 1275 | sc->selector = selector; |
| | 1276 | sc->base = base; |
| | 1277 | sc->limit = limit; |
| | 1278 | sc->flags = flags; |
| | 1279 | |
| | 1280 | /* update the hidden flags */ |
| | 1281 | { |
| | 1282 | if (seg_reg == R_CS) { |
| | 1283 | #ifdef TARGET_X86_64 |
| | 1284 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { |
| | 1285 | /* long mode */ |
| | 1286 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
| | 1287 | env->hflags &= ~(HF_ADDSEG_MASK); |
| | 1288 | } else |
| | 1289 | #endif |
| | 1290 | { |
| | 1291 | /* legacy / compatibility case */ |
| | 1292 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
| | 1293 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
| | 1294 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
| | 1295 | new_hflags; |
| | 1296 | } |
| | 1297 | } |
| | 1298 | if (seg_reg == R_SS) { |
| | 1299 | int cpl = (flags >> DESC_DPL_SHIFT) & 3; |
| | 1300 | #if HF_CPL_MASK != 3 |
| | 1301 | #error HF_CPL_MASK is hardcoded |
| | 1302 | #endif |
| | 1303 | env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl; |
| | 1304 | } |
| | 1305 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
| | 1306 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
| | 1307 | if (env->hflags & HF_CS64_MASK) { |
| | 1308 | /* zero base assumed for DS, ES and SS in long mode */ |
| | 1309 | } else if (!(env->cr[0] & CR0_PE_MASK) || |
| | 1310 | (env->eflags & VM_MASK) || |
| | 1311 | !(env->hflags & HF_CS32_MASK)) { |
| | 1312 | /* XXX: try to avoid this test. The problem comes from the |
| | 1313 | fact that is real mode or vm86 mode we only modify the |
| | 1314 | 'base' and 'selector' fields of the segment cache to go |
| | 1315 | faster. A solution may be to force addseg to one in |
| | 1316 | translate-i386.c. */ |
| | 1317 | new_hflags |= HF_ADDSEG_MASK; |
| | 1318 | } else { |
| | 1319 | new_hflags |= ((env->segs[R_DS].base | |
| | 1320 | env->segs[R_ES].base | |
| | 1321 | env->segs[R_SS].base) != 0) << |
| | 1322 | HF_ADDSEG_SHIFT; |
| | 1323 | } |
| | 1324 | env->hflags = (env->hflags & |
| | 1325 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
| | 1326 | } |
| | 1327 | } |
| | 1328 | |
| | 1329 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, |
| | 1330 | uint8_t sipi_vector) |
| | 1331 | { |
| | 1332 | CPUState *cs = CPU(cpu); |
| | 1333 | CPUX86State *env = &cpu->env; |
| | 1334 | |
| | 1335 | env->eip = 0; |
| | 1336 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, |
| | 1337 | sipi_vector << 12, |
| | 1338 | env->segs[R_CS].limit, |
| | 1339 | env->segs[R_CS].flags); |
| | 1340 | cs->halted = 0; |
| | 1341 | } |
| | 1342 | |
| | 1343 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, |
| | 1344 | target_ulong *base, unsigned int *limit, |
| | 1345 | unsigned int *flags); |
| | 1346 | |
| | 1347 | /* op_helper.c */ |
| | 1348 | /* used for debug or cpu save/restore */ |
| | 1349 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f); |
| | 1350 | floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); |
| | 1351 | |
| | 1352 | /* cpu-exec.c */ |
| | 1353 | /* the following helpers are only usable in user mode simulation as |
| | 1354 | they can trigger unexpected exceptions */ |
| | 1355 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
| | 1356 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
| | 1357 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); |
| | 1358 | |
| | 1359 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
| | 1360 | signal handlers to inform the virtual CPU of exceptions. non zero |
| | 1361 | is returned if the signal was handled by the virtual CPU. */ |
| | 1362 | int cpu_x86_signal_handler(int host_signum, void *pinfo, |
| | 1363 | void *puc); |
| | 1364 | |
| | 1365 | /* cpu.c */ |
| | 1366 | typedef struct ExtSaveArea { |
| | 1367 | uint32_t feature, bits; |
| | 1368 | uint32_t offset, size; |
| | 1369 | } ExtSaveArea; |
| | 1370 | |
| | 1371 | extern const ExtSaveArea x86_ext_save_areas[]; |
| | 1372 | |
| | 1373 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, |
| | 1374 | uint32_t *eax, uint32_t *ebx, |
| | 1375 | uint32_t *ecx, uint32_t *edx); |
| | 1376 | void cpu_clear_apic_feature(CPUX86State *env); |
| | 1377 | void host_cpuid(uint32_t function, uint32_t count, |
| | 1378 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); |
| | 1379 | |
| | 1380 | /* helper.c */ |
| | 1381 | int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr, |
| | 1382 | int is_write, int mmu_idx); |
| | 1383 | void x86_cpu_set_a20(X86CPU *cpu, int a20_state); |
| | 1384 | |
| | 1385 | #ifndef CONFIG_USER_ONLY |
| | 1386 | uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr); |
| | 1387 | uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr); |
| | 1388 | uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr); |
| | 1389 | uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr); |
| | 1390 | void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val); |
| | 1391 | void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val); |
| | 1392 | void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val); |
| | 1393 | void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val); |
| | 1394 | void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); |
| | 1395 | #endif |
| | 1396 | |
| | 1397 | void breakpoint_handler(CPUState *cs); |
| | 1398 | |
| | 1399 | /* will be suppressed */ |
| | 1400 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); |
| | 1401 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); |
| | 1402 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); |
| | 1403 | void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); |
| | 1404 | |
| | 1405 | /* hw/pc.c */ |
| | 1406 | uint64_t cpu_get_tsc(CPUX86State *env); |
| | 1407 | |
| | 1408 | #define TARGET_PAGE_BITS 12 |
| | 1409 | |
| | 1410 | #ifdef TARGET_X86_64 |
| | 1411 | #define TARGET_PHYS_ADDR_SPACE_BITS 52 |
| | 1412 | /* ??? This is really 48 bits, sign-extended, but the only thing |
| | 1413 | accessible to userland with bit 48 set is the VSYSCALL, and that |
| | 1414 | is handled via other mechanisms. */ |
| | 1415 | #define TARGET_VIRT_ADDR_SPACE_BITS 47 |
| | 1416 | #else |
| | 1417 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
| | 1418 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
| | 1419 | #endif |
| | 1420 | |
| | 1421 | /* XXX: This value should match the one returned by CPUID |
| | 1422 | * and in exec.c */ |
| | 1423 | # if defined(TARGET_X86_64) |
| | 1424 | # define PHYS_ADDR_MASK 0xffffffffffLL |
| | 1425 | # else |
| | 1426 | # define PHYS_ADDR_MASK 0xfffffffffLL |
| | 1427 | # endif |
| | 1428 | |
| | 1429 | #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model)) |
| | 1430 | |
| | 1431 | #define cpu_signal_handler cpu_x86_signal_handler |
| | 1432 | #define cpu_list x86_cpu_list |
| | 1433 | |
| | 1434 | /* MMU modes definitions */ |
| | 1435 | #define MMU_MODE0_SUFFIX _ksmap |
| | 1436 | #define MMU_MODE1_SUFFIX _user |
| | 1437 | #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */ |
| | 1438 | #define MMU_KSMAP_IDX 0 |
| | 1439 | #define MMU_USER_IDX 1 |
| | 1440 | #define MMU_KNOSMAP_IDX 2 |
| | 1441 | static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) |
| | 1442 | { |
| | 1443 | return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : |
| | 1444 | (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) |
| | 1445 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; |
| | 1446 | } |
| | 1447 | |
| | 1448 | static inline int cpu_mmu_index_kernel(CPUX86State *env) |
| | 1449 | { |
| | 1450 | return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : |
| | 1451 | ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK)) |
| | 1452 | ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; |
| | 1453 | } |
| | 1454 | |
| | 1455 | #define CC_DST (env->cc_dst) |
| | 1456 | #define CC_SRC (env->cc_src) |
| | 1457 | #define CC_SRC2 (env->cc_src2) |
| | 1458 | #define CC_OP (env->cc_op) |
| | 1459 | |
| | 1460 | /* n must be a constant to be efficient */ |
| | 1461 | static inline target_long lshift(target_long x, int n) |
| | 1462 | { |
| | 1463 | if (n >= 0) { |
| | 1464 | return x << n; |
| | 1465 | } else { |
| | 1466 | return x >> (-n); |
| | 1467 | } |
| | 1468 | } |
| | 1469 | |
| | 1470 | /* float macros */ |
| | 1471 | #define FT0 (env->ft0) |
| | 1472 | #define ST0 (env->fpregs[env->fpstt].d) |
| | 1473 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) |
| | 1474 | #define ST1 ST(1) |
| | 1475 | |
| | 1476 | /* translate.c */ |
| | 1477 | void tcg_x86_init(void); |
| | 1478 | |
| | 1479 | #include "exec/cpu-all.h" |
| | 1480 | #include "svm.h" |
| | 1481 | |
| | 1482 | #if !defined(CONFIG_USER_ONLY) |
| | 1483 | #include "hw/i386/apic.h" |
| | 1484 | #endif |
| | 1485 | |
| | 1486 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, |
| | 1487 | target_ulong *cs_base, uint32_t *flags) |
| | 1488 | { |
| | 1489 | *cs_base = env->segs[R_CS].base; |
| | 1490 | *pc = *cs_base + env->eip; |
| | 1491 | *flags = env->hflags | |
| | 1492 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); |
| | 1493 | } |
| | 1494 | |
| | 1495 | void do_cpu_init(X86CPU *cpu); |
| | 1496 | void do_cpu_sipi(X86CPU *cpu); |
| | 1497 | |
| | 1498 | #define MCE_INJECT_BROADCAST 1 |
| | 1499 | #define MCE_INJECT_UNCOND_AO 2 |
| | 1500 | |
| | 1501 | void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, |
| | 1502 | uint64_t status, uint64_t mcg_status, uint64_t addr, |
| | 1503 | uint64_t misc, int flags); |
| | 1504 | |
| | 1505 | /* excp_helper.c */ |
| | 1506 | void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); |
| | 1507 | void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index, |
| | 1508 | uintptr_t retaddr); |
| | 1509 | void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, |
| | 1510 | int error_code); |
| | 1511 | void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index, |
| | 1512 | int error_code, uintptr_t retaddr); |
| | 1513 | void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, |
| | 1514 | int error_code, int next_eip_addend); |
| | 1515 | |
| | 1516 | /* cc_helper.c */ |
| | 1517 | extern const uint8_t parity_table[256]; |
| | 1518 | uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); |
| | 1519 | void update_fp_status(CPUX86State *env); |
| | 1520 | |
| | 1521 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) |
| | 1522 | { |
| | 1523 | return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); |
| | 1524 | } |
| | 1525 | |
| | 1526 | /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS |
| | 1527 | * after generating a call to a helper that uses this. |
| | 1528 | */ |
| | 1529 | static inline void cpu_load_eflags(CPUX86State *env, int eflags, |
| | 1530 | int update_mask) |
| | 1531 | { |
| | 1532 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); |
| | 1533 | CC_OP = CC_OP_EFLAGS; |
| | 1534 | env->df = 1 - (2 * ((eflags >> 10) & 1)); |
| | 1535 | env->eflags = (env->eflags & ~update_mask) | |
| | 1536 | (eflags & update_mask) | 0x2; |
| | 1537 | } |
| | 1538 | |
| | 1539 | /* load efer and update the corresponding hflags. XXX: do consistency |
| | 1540 | checks with cpuid bits? */ |
| | 1541 | static inline void cpu_load_efer(CPUX86State *env, uint64_t val) |
| | 1542 | { |
| | 1543 | env->efer = val; |
| | 1544 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); |
| | 1545 | if (env->efer & MSR_EFER_LMA) { |
| | 1546 | env->hflags |= HF_LMA_MASK; |
| | 1547 | } |
| | 1548 | if (env->efer & MSR_EFER_SVME) { |
| | 1549 | env->hflags |= HF_SVME_MASK; |
| | 1550 | } |
| | 1551 | } |
| | 1552 | |
| | 1553 | static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env) |
| | 1554 | { |
| | 1555 | return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 }); |
| | 1556 | } |
| | 1557 | |
| | 1558 | /* fpu_helper.c */ |
| | 1559 | void cpu_set_mxcsr(CPUX86State *env, uint32_t val); |
| | 1560 | void cpu_set_fpuc(CPUX86State *env, uint16_t val); |
| | 1561 | |
| | 1562 | /* mem_helper.c */ |
| | 1563 | void helper_lock_init(void); |
| | 1564 | |
| | 1565 | /* svm_helper.c */ |
| | 1566 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, |
| | 1567 | uint64_t param); |
| | 1568 | void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1); |
| | 1569 | |
| | 1570 | /* seg_helper.c */ |
| | 1571 | void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); |
| | 1572 | |
| | 1573 | /* smm_helper.c */ |
| | 1574 | void do_smm_enter(X86CPU *cpu); |
| | 1575 | void cpu_smm_update(X86CPU *cpu); |
| | 1576 | |
| | 1577 | /* apic.c */ |
| | 1578 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); |
| | 1579 | void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, |
| | 1580 | TPRAccess access); |
| | 1581 | |
| | 1582 | |
| | 1583 | /* Change the value of a KVM-specific default |
| | 1584 | * |
| | 1585 | * If value is NULL, no default will be set and the original |
| | 1586 | * value from the CPU model table will be kept. |
| | 1587 | * |
| | 1588 | * It is valid to call this function only for properties that |
| | 1589 | * are already present in the kvm_default_props table. |
| | 1590 | */ |
| | 1591 | void x86_cpu_change_kvm_default(const char *prop, const char *value); |
| | 1592 | |
| | 1593 | /* mpx_helper.c */ |
| | 1594 | void cpu_sync_bndcs_hflags(CPUX86State *env); |
| | 1595 | |
| | 1596 | /* Return name of 32-bit register, from a R_* constant */ |
| | 1597 | const char *get_register_name_32(unsigned int reg); |
| | 1598 | |
| | 1599 | void enable_compat_apic_id_mode(void); |
| | 1600 | |
| | 1601 | #define APIC_DEFAULT_ADDRESS 0xfee00000 |
| | 1602 | #define APIC_SPACE_SIZE 0x100000 |
| | 1603 | |
| | 1604 | void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f, |
| | 1605 | fprintf_function cpu_fprintf, int flags); |
| | 1606 | |
| | 1607 | /* cpu.c */ |
| | 1608 | bool cpu_is_bsp(X86CPU *cpu); |
| | 1609 | |
| | 1610 | #endif /* CPU_I386_H */ |
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