]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * i386 virtual CPU header | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #ifndef CPU_I386_H | |
20 | #define CPU_I386_H | |
21 | ||
22 | #include "config.h" | |
23 | #include "qemu-common.h" | |
24 | ||
25 | #ifdef TARGET_X86_64 | |
26 | #define TARGET_LONG_BITS 64 | |
27 | #else | |
28 | #define TARGET_LONG_BITS 32 | |
29 | #endif | |
30 | ||
31 | /* target supports implicit self modifying code */ | |
32 | #define TARGET_HAS_SMC | |
33 | /* support for self modifying code even if the modified instruction is | |
34 | close to the modifying instruction */ | |
35 | #define TARGET_HAS_PRECISE_SMC | |
36 | ||
37 | #define TARGET_HAS_ICE 1 | |
38 | ||
39 | #ifdef TARGET_X86_64 | |
40 | #define ELF_MACHINE EM_X86_64 | |
41 | #define ELF_MACHINE_UNAME "x86_64" | |
42 | #else | |
43 | #define ELF_MACHINE EM_386 | |
44 | #define ELF_MACHINE_UNAME "i686" | |
45 | #endif | |
46 | ||
47 | #define CPUArchState struct CPUX86State | |
48 | ||
49 | #include "exec/cpu-defs.h" | |
50 | ||
51 | #include "fpu/softfloat.h" | |
52 | ||
53 | #define R_EAX 0 | |
54 | #define R_ECX 1 | |
55 | #define R_EDX 2 | |
56 | #define R_EBX 3 | |
57 | #define R_ESP 4 | |
58 | #define R_EBP 5 | |
59 | #define R_ESI 6 | |
60 | #define R_EDI 7 | |
61 | ||
62 | #define R_AL 0 | |
63 | #define R_CL 1 | |
64 | #define R_DL 2 | |
65 | #define R_BL 3 | |
66 | #define R_AH 4 | |
67 | #define R_CH 5 | |
68 | #define R_DH 6 | |
69 | #define R_BH 7 | |
70 | ||
71 | #define R_ES 0 | |
72 | #define R_CS 1 | |
73 | #define R_SS 2 | |
74 | #define R_DS 3 | |
75 | #define R_FS 4 | |
76 | #define R_GS 5 | |
77 | ||
78 | /* segment descriptor fields */ | |
79 | #define DESC_G_MASK (1 << 23) | |
80 | #define DESC_B_SHIFT 22 | |
81 | #define DESC_B_MASK (1 << DESC_B_SHIFT) | |
82 | #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ | |
83 | #define DESC_L_MASK (1 << DESC_L_SHIFT) | |
84 | #define DESC_AVL_MASK (1 << 20) | |
85 | #define DESC_P_MASK (1 << 15) | |
86 | #define DESC_DPL_SHIFT 13 | |
87 | #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT) | |
88 | #define DESC_S_MASK (1 << 12) | |
89 | #define DESC_TYPE_SHIFT 8 | |
90 | #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT) | |
91 | #define DESC_A_MASK (1 << 8) | |
92 | ||
93 | #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ | |
94 | #define DESC_C_MASK (1 << 10) /* code: conforming */ | |
95 | #define DESC_R_MASK (1 << 9) /* code: readable */ | |
96 | ||
97 | #define DESC_E_MASK (1 << 10) /* data: expansion direction */ | |
98 | #define DESC_W_MASK (1 << 9) /* data: writable */ | |
99 | ||
100 | #define DESC_TSS_BUSY_MASK (1 << 9) | |
101 | ||
102 | /* eflags masks */ | |
103 | #define CC_C 0x0001 | |
104 | #define CC_P 0x0004 | |
105 | #define CC_A 0x0010 | |
106 | #define CC_Z 0x0040 | |
107 | #define CC_S 0x0080 | |
108 | #define CC_O 0x0800 | |
109 | ||
110 | #define TF_SHIFT 8 | |
111 | #define IOPL_SHIFT 12 | |
112 | #define VM_SHIFT 17 | |
113 | ||
114 | #define TF_MASK 0x00000100 | |
115 | #define IF_MASK 0x00000200 | |
116 | #define DF_MASK 0x00000400 | |
117 | #define IOPL_MASK 0x00003000 | |
118 | #define NT_MASK 0x00004000 | |
119 | #define RF_MASK 0x00010000 | |
120 | #define VM_MASK 0x00020000 | |
121 | #define AC_MASK 0x00040000 | |
122 | #define VIF_MASK 0x00080000 | |
123 | #define VIP_MASK 0x00100000 | |
124 | #define ID_MASK 0x00200000 | |
125 | ||
126 | /* hidden flags - used internally by qemu to represent additional cpu | |
127 | states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not | |
128 | redundant. We avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK | |
129 | bit positions to ease oring with eflags. */ | |
130 | /* current cpl */ | |
131 | #define HF_CPL_SHIFT 0 | |
132 | /* true if soft mmu is being used */ | |
133 | #define HF_SOFTMMU_SHIFT 2 | |
134 | /* true if hardware interrupts must be disabled for next instruction */ | |
135 | #define HF_INHIBIT_IRQ_SHIFT 3 | |
136 | /* 16 or 32 segments */ | |
137 | #define HF_CS32_SHIFT 4 | |
138 | #define HF_SS32_SHIFT 5 | |
139 | /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ | |
140 | #define HF_ADDSEG_SHIFT 6 | |
141 | /* copy of CR0.PE (protected mode) */ | |
142 | #define HF_PE_SHIFT 7 | |
143 | #define HF_TF_SHIFT 8 /* must be same as eflags */ | |
144 | #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ | |
145 | #define HF_EM_SHIFT 10 | |
146 | #define HF_TS_SHIFT 11 | |
147 | #define HF_IOPL_SHIFT 12 /* must be same as eflags */ | |
148 | #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ | |
149 | #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ | |
150 | #define HF_RF_SHIFT 16 /* must be same as eflags */ | |
151 | #define HF_VM_SHIFT 17 /* must be same as eflags */ | |
152 | #define HF_AC_SHIFT 18 /* must be same as eflags */ | |
153 | #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ | |
154 | #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ | |
155 | #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ | |
156 | #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */ | |
157 | #define HF_SMAP_SHIFT 23 /* CR4.SMAP */ | |
158 | ||
159 | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) | |
160 | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) | |
161 | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) | |
162 | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) | |
163 | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) | |
164 | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) | |
165 | #define HF_PE_MASK (1 << HF_PE_SHIFT) | |
166 | #define HF_TF_MASK (1 << HF_TF_SHIFT) | |
167 | #define HF_MP_MASK (1 << HF_MP_SHIFT) | |
168 | #define HF_EM_MASK (1 << HF_EM_SHIFT) | |
169 | #define HF_TS_MASK (1 << HF_TS_SHIFT) | |
170 | #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) | |
171 | #define HF_LMA_MASK (1 << HF_LMA_SHIFT) | |
172 | #define HF_CS64_MASK (1 << HF_CS64_SHIFT) | |
173 | #define HF_RF_MASK (1 << HF_RF_SHIFT) | |
174 | #define HF_VM_MASK (1 << HF_VM_SHIFT) | |
175 | #define HF_AC_MASK (1 << HF_AC_SHIFT) | |
176 | #define HF_SMM_MASK (1 << HF_SMM_SHIFT) | |
177 | #define HF_SVME_MASK (1 << HF_SVME_SHIFT) | |
178 | #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) | |
179 | #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) | |
180 | #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT) | |
181 | ||
182 | /* hflags2 */ | |
183 | ||
184 | #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ | |
185 | #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ | |
186 | #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ | |
187 | #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ | |
188 | ||
189 | #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) | |
190 | #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) | |
191 | #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) | |
192 | #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) | |
193 | ||
194 | #define CR0_PE_SHIFT 0 | |
195 | #define CR0_MP_SHIFT 1 | |
196 | ||
197 | #define CR0_PE_MASK (1 << 0) | |
198 | #define CR0_MP_MASK (1 << 1) | |
199 | #define CR0_EM_MASK (1 << 2) | |
200 | #define CR0_TS_MASK (1 << 3) | |
201 | #define CR0_ET_MASK (1 << 4) | |
202 | #define CR0_NE_MASK (1 << 5) | |
203 | #define CR0_WP_MASK (1 << 16) | |
204 | #define CR0_AM_MASK (1 << 18) | |
205 | #define CR0_PG_MASK (1 << 31) | |
206 | ||
207 | #define CR4_VME_MASK (1 << 0) | |
208 | #define CR4_PVI_MASK (1 << 1) | |
209 | #define CR4_TSD_MASK (1 << 2) | |
210 | #define CR4_DE_MASK (1 << 3) | |
211 | #define CR4_PSE_MASK (1 << 4) | |
212 | #define CR4_PAE_MASK (1 << 5) | |
213 | #define CR4_MCE_MASK (1 << 6) | |
214 | #define CR4_PGE_MASK (1 << 7) | |
215 | #define CR4_PCE_MASK (1 << 8) | |
216 | #define CR4_OSFXSR_SHIFT 9 | |
217 | #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) | |
218 | #define CR4_OSXMMEXCPT_MASK (1 << 10) | |
219 | #define CR4_VMXE_MASK (1 << 13) | |
220 | #define CR4_SMXE_MASK (1 << 14) | |
221 | #define CR4_FSGSBASE_MASK (1 << 16) | |
222 | #define CR4_PCIDE_MASK (1 << 17) | |
223 | #define CR4_OSXSAVE_MASK (1 << 18) | |
224 | #define CR4_SMEP_MASK (1 << 20) | |
225 | #define CR4_SMAP_MASK (1 << 21) | |
226 | ||
227 | #define DR6_BD (1 << 13) | |
228 | #define DR6_BS (1 << 14) | |
229 | #define DR6_BT (1 << 15) | |
230 | #define DR6_FIXED_1 0xffff0ff0 | |
231 | ||
232 | #define DR7_GD (1 << 13) | |
233 | #define DR7_TYPE_SHIFT 16 | |
234 | #define DR7_LEN_SHIFT 18 | |
235 | #define DR7_FIXED_1 0x00000400 | |
236 | #define DR7_LOCAL_BP_MASK 0x55 | |
237 | #define DR7_MAX_BP 4 | |
238 | #define DR7_TYPE_BP_INST 0x0 | |
239 | #define DR7_TYPE_DATA_WR 0x1 | |
240 | #define DR7_TYPE_IO_RW 0x2 | |
241 | #define DR7_TYPE_DATA_RW 0x3 | |
242 | ||
243 | #define PG_PRESENT_BIT 0 | |
244 | #define PG_RW_BIT 1 | |
245 | #define PG_USER_BIT 2 | |
246 | #define PG_PWT_BIT 3 | |
247 | #define PG_PCD_BIT 4 | |
248 | #define PG_ACCESSED_BIT 5 | |
249 | #define PG_DIRTY_BIT 6 | |
250 | #define PG_PSE_BIT 7 | |
251 | #define PG_GLOBAL_BIT 8 | |
252 | #define PG_NX_BIT 63 | |
253 | ||
254 | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) | |
255 | #define PG_RW_MASK (1 << PG_RW_BIT) | |
256 | #define PG_USER_MASK (1 << PG_USER_BIT) | |
257 | #define PG_PWT_MASK (1 << PG_PWT_BIT) | |
258 | #define PG_PCD_MASK (1 << PG_PCD_BIT) | |
259 | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) | |
260 | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) | |
261 | #define PG_PSE_MASK (1 << PG_PSE_BIT) | |
262 | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) | |
263 | #define PG_HI_USER_MASK 0x7ff0000000000000LL | |
264 | #define PG_NX_MASK (1LL << PG_NX_BIT) | |
265 | ||
266 | #define PG_ERROR_W_BIT 1 | |
267 | ||
268 | #define PG_ERROR_P_MASK 0x01 | |
269 | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) | |
270 | #define PG_ERROR_U_MASK 0x04 | |
271 | #define PG_ERROR_RSVD_MASK 0x08 | |
272 | #define PG_ERROR_I_D_MASK 0x10 | |
273 | ||
274 | #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ | |
275 | #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */ | |
276 | ||
277 | #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) | |
278 | #define MCE_BANKS_DEF 10 | |
279 | ||
280 | #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ | |
281 | #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */ | |
282 | #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */ | |
283 | ||
284 | #define MCI_STATUS_VAL (1ULL<<63) /* valid error */ | |
285 | #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */ | |
286 | #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */ | |
287 | #define MCI_STATUS_EN (1ULL<<60) /* error enabled */ | |
288 | #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */ | |
289 | #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */ | |
290 | #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */ | |
291 | #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */ | |
292 | #define MCI_STATUS_AR (1ULL<<55) /* Action required */ | |
293 | ||
294 | /* MISC register defines */ | |
295 | #define MCM_ADDR_SEGOFF 0 /* segment offset */ | |
296 | #define MCM_ADDR_LINEAR 1 /* linear address */ | |
297 | #define MCM_ADDR_PHYS 2 /* physical address */ | |
298 | #define MCM_ADDR_MEM 3 /* memory address */ | |
299 | #define MCM_ADDR_GENERIC 7 /* generic */ | |
300 | ||
301 | #define MSR_IA32_TSC 0x10 | |
302 | #define MSR_IA32_APICBASE 0x1b | |
303 | #define MSR_IA32_APICBASE_BSP (1<<8) | |
304 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | |
305 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | |
306 | #define MSR_IA32_FEATURE_CONTROL 0x0000003a | |
307 | #define MSR_TSC_ADJUST 0x0000003b | |
308 | #define MSR_IA32_TSCDEADLINE 0x6e0 | |
309 | ||
310 | #define MSR_P6_PERFCTR0 0xc1 | |
311 | ||
312 | #define MSR_MTRRcap 0xfe | |
313 | #define MSR_MTRRcap_VCNT 8 | |
314 | #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8) | |
315 | #define MSR_MTRRcap_WC_SUPPORTED (1 << 10) | |
316 | ||
317 | #define MSR_IA32_SYSENTER_CS 0x174 | |
318 | #define MSR_IA32_SYSENTER_ESP 0x175 | |
319 | #define MSR_IA32_SYSENTER_EIP 0x176 | |
320 | ||
321 | #define MSR_MCG_CAP 0x179 | |
322 | #define MSR_MCG_STATUS 0x17a | |
323 | #define MSR_MCG_CTL 0x17b | |
324 | ||
325 | #define MSR_P6_EVNTSEL0 0x186 | |
326 | ||
327 | #define MSR_IA32_PERF_STATUS 0x198 | |
328 | ||
329 | #define MSR_IA32_MISC_ENABLE 0x1a0 | |
330 | /* Indicates good rep/movs microcode on some processors: */ | |
331 | #define MSR_IA32_MISC_ENABLE_DEFAULT 1 | |
332 | ||
333 | #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg)) | |
334 | #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1) | |
335 | ||
336 | #define MSR_MTRRfix64K_00000 0x250 | |
337 | #define MSR_MTRRfix16K_80000 0x258 | |
338 | #define MSR_MTRRfix16K_A0000 0x259 | |
339 | #define MSR_MTRRfix4K_C0000 0x268 | |
340 | #define MSR_MTRRfix4K_C8000 0x269 | |
341 | #define MSR_MTRRfix4K_D0000 0x26a | |
342 | #define MSR_MTRRfix4K_D8000 0x26b | |
343 | #define MSR_MTRRfix4K_E0000 0x26c | |
344 | #define MSR_MTRRfix4K_E8000 0x26d | |
345 | #define MSR_MTRRfix4K_F0000 0x26e | |
346 | #define MSR_MTRRfix4K_F8000 0x26f | |
347 | ||
348 | #define MSR_PAT 0x277 | |
349 | ||
350 | #define MSR_MTRRdefType 0x2ff | |
351 | ||
352 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 | |
353 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | |
354 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | |
355 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | |
356 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | |
357 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | |
358 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | |
359 | ||
360 | #define MSR_MC0_CTL 0x400 | |
361 | #define MSR_MC0_STATUS 0x401 | |
362 | #define MSR_MC0_ADDR 0x402 | |
363 | #define MSR_MC0_MISC 0x403 | |
364 | ||
365 | #define MSR_EFER 0xc0000080 | |
366 | ||
367 | #define MSR_EFER_SCE (1 << 0) | |
368 | #define MSR_EFER_LME (1 << 8) | |
369 | #define MSR_EFER_LMA (1 << 10) | |
370 | #define MSR_EFER_NXE (1 << 11) | |
371 | #define MSR_EFER_SVME (1 << 12) | |
372 | #define MSR_EFER_FFXSR (1 << 14) | |
373 | ||
374 | #define MSR_STAR 0xc0000081 | |
375 | #define MSR_LSTAR 0xc0000082 | |
376 | #define MSR_CSTAR 0xc0000083 | |
377 | #define MSR_FMASK 0xc0000084 | |
378 | #define MSR_FSBASE 0xc0000100 | |
379 | #define MSR_GSBASE 0xc0000101 | |
380 | #define MSR_KERNELGSBASE 0xc0000102 | |
381 | #define MSR_TSC_AUX 0xc0000103 | |
382 | ||
383 | #define MSR_VM_HSAVE_PA 0xc0010117 | |
384 | ||
385 | #define MSR_IA32_BNDCFGS 0x00000d90 | |
386 | ||
387 | #define XSTATE_FP (1ULL << 0) | |
388 | #define XSTATE_SSE (1ULL << 1) | |
389 | #define XSTATE_YMM (1ULL << 2) | |
390 | #define XSTATE_BNDREGS (1ULL << 3) | |
391 | #define XSTATE_BNDCSR (1ULL << 4) | |
392 | ||
393 | ||
394 | /* CPUID feature words */ | |
395 | typedef enum FeatureWord { | |
396 | FEAT_1_EDX, /* CPUID[1].EDX */ | |
397 | FEAT_1_ECX, /* CPUID[1].ECX */ | |
398 | FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */ | |
399 | FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ | |
400 | FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ | |
401 | FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ | |
402 | FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ | |
403 | FEAT_SVM, /* CPUID[8000_000A].EDX */ | |
404 | FEATURE_WORDS, | |
405 | } FeatureWord; | |
406 | ||
407 | typedef uint32_t FeatureWordArray[FEATURE_WORDS]; | |
408 | ||
409 | /* cpuid_features bits */ | |
410 | #define CPUID_FP87 (1 << 0) | |
411 | #define CPUID_VME (1 << 1) | |
412 | #define CPUID_DE (1 << 2) | |
413 | #define CPUID_PSE (1 << 3) | |
414 | #define CPUID_TSC (1 << 4) | |
415 | #define CPUID_MSR (1 << 5) | |
416 | #define CPUID_PAE (1 << 6) | |
417 | #define CPUID_MCE (1 << 7) | |
418 | #define CPUID_CX8 (1 << 8) | |
419 | #define CPUID_APIC (1 << 9) | |
420 | #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ | |
421 | #define CPUID_MTRR (1 << 12) | |
422 | #define CPUID_PGE (1 << 13) | |
423 | #define CPUID_MCA (1 << 14) | |
424 | #define CPUID_CMOV (1 << 15) | |
425 | #define CPUID_PAT (1 << 16) | |
426 | #define CPUID_PSE36 (1 << 17) | |
427 | #define CPUID_PN (1 << 18) | |
428 | #define CPUID_CLFLUSH (1 << 19) | |
429 | #define CPUID_DTS (1 << 21) | |
430 | #define CPUID_ACPI (1 << 22) | |
431 | #define CPUID_MMX (1 << 23) | |
432 | #define CPUID_FXSR (1 << 24) | |
433 | #define CPUID_SSE (1 << 25) | |
434 | #define CPUID_SSE2 (1 << 26) | |
435 | #define CPUID_SS (1 << 27) | |
436 | #define CPUID_HT (1 << 28) | |
437 | #define CPUID_TM (1 << 29) | |
438 | #define CPUID_IA64 (1 << 30) | |
439 | #define CPUID_PBE (1 << 31) | |
440 | ||
441 | #define CPUID_EXT_SSE3 (1 << 0) | |
442 | #define CPUID_EXT_PCLMULQDQ (1 << 1) | |
443 | #define CPUID_EXT_DTES64 (1 << 2) | |
444 | #define CPUID_EXT_MONITOR (1 << 3) | |
445 | #define CPUID_EXT_DSCPL (1 << 4) | |
446 | #define CPUID_EXT_VMX (1 << 5) | |
447 | #define CPUID_EXT_SMX (1 << 6) | |
448 | #define CPUID_EXT_EST (1 << 7) | |
449 | #define CPUID_EXT_TM2 (1 << 8) | |
450 | #define CPUID_EXT_SSSE3 (1 << 9) | |
451 | #define CPUID_EXT_CID (1 << 10) | |
452 | #define CPUID_EXT_FMA (1 << 12) | |
453 | #define CPUID_EXT_CX16 (1 << 13) | |
454 | #define CPUID_EXT_XTPR (1 << 14) | |
455 | #define CPUID_EXT_PDCM (1 << 15) | |
456 | #define CPUID_EXT_PCID (1 << 17) | |
457 | #define CPUID_EXT_DCA (1 << 18) | |
458 | #define CPUID_EXT_SSE41 (1 << 19) | |
459 | #define CPUID_EXT_SSE42 (1 << 20) | |
460 | #define CPUID_EXT_X2APIC (1 << 21) | |
461 | #define CPUID_EXT_MOVBE (1 << 22) | |
462 | #define CPUID_EXT_POPCNT (1 << 23) | |
463 | #define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24) | |
464 | #define CPUID_EXT_AES (1 << 25) | |
465 | #define CPUID_EXT_XSAVE (1 << 26) | |
466 | #define CPUID_EXT_OSXSAVE (1 << 27) | |
467 | #define CPUID_EXT_AVX (1 << 28) | |
468 | #define CPUID_EXT_F16C (1 << 29) | |
469 | #define CPUID_EXT_RDRAND (1 << 30) | |
470 | #define CPUID_EXT_HYPERVISOR (1 << 31) | |
471 | ||
472 | #define CPUID_EXT2_FPU (1 << 0) | |
473 | #define CPUID_EXT2_VME (1 << 1) | |
474 | #define CPUID_EXT2_DE (1 << 2) | |
475 | #define CPUID_EXT2_PSE (1 << 3) | |
476 | #define CPUID_EXT2_TSC (1 << 4) | |
477 | #define CPUID_EXT2_MSR (1 << 5) | |
478 | #define CPUID_EXT2_PAE (1 << 6) | |
479 | #define CPUID_EXT2_MCE (1 << 7) | |
480 | #define CPUID_EXT2_CX8 (1 << 8) | |
481 | #define CPUID_EXT2_APIC (1 << 9) | |
482 | #define CPUID_EXT2_SYSCALL (1 << 11) | |
483 | #define CPUID_EXT2_MTRR (1 << 12) | |
484 | #define CPUID_EXT2_PGE (1 << 13) | |
485 | #define CPUID_EXT2_MCA (1 << 14) | |
486 | #define CPUID_EXT2_CMOV (1 << 15) | |
487 | #define CPUID_EXT2_PAT (1 << 16) | |
488 | #define CPUID_EXT2_PSE36 (1 << 17) | |
489 | #define CPUID_EXT2_MP (1 << 19) | |
490 | #define CPUID_EXT2_NX (1 << 20) | |
491 | #define CPUID_EXT2_MMXEXT (1 << 22) | |
492 | #define CPUID_EXT2_MMX (1 << 23) | |
493 | #define CPUID_EXT2_FXSR (1 << 24) | |
494 | #define CPUID_EXT2_FFXSR (1 << 25) | |
495 | #define CPUID_EXT2_PDPE1GB (1 << 26) | |
496 | #define CPUID_EXT2_RDTSCP (1 << 27) | |
497 | #define CPUID_EXT2_LM (1 << 29) | |
498 | #define CPUID_EXT2_3DNOWEXT (1 << 30) | |
499 | #define CPUID_EXT2_3DNOW (1 << 31) | |
500 | ||
501 | /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ | |
502 | #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ | |
503 | CPUID_EXT2_DE | CPUID_EXT2_PSE | \ | |
504 | CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ | |
505 | CPUID_EXT2_PAE | CPUID_EXT2_MCE | \ | |
506 | CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \ | |
507 | CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \ | |
508 | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \ | |
509 | CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ | |
510 | CPUID_EXT2_MMX | CPUID_EXT2_FXSR) | |
511 | ||
512 | #define CPUID_EXT3_LAHF_LM (1 << 0) | |
513 | #define CPUID_EXT3_CMP_LEG (1 << 1) | |
514 | #define CPUID_EXT3_SVM (1 << 2) | |
515 | #define CPUID_EXT3_EXTAPIC (1 << 3) | |
516 | #define CPUID_EXT3_CR8LEG (1 << 4) | |
517 | #define CPUID_EXT3_ABM (1 << 5) | |
518 | #define CPUID_EXT3_SSE4A (1 << 6) | |
519 | #define CPUID_EXT3_MISALIGNSSE (1 << 7) | |
520 | #define CPUID_EXT3_3DNOWPREFETCH (1 << 8) | |
521 | #define CPUID_EXT3_OSVW (1 << 9) | |
522 | #define CPUID_EXT3_IBS (1 << 10) | |
523 | #define CPUID_EXT3_XOP (1 << 11) | |
524 | #define CPUID_EXT3_SKINIT (1 << 12) | |
525 | #define CPUID_EXT3_WDT (1 << 13) | |
526 | #define CPUID_EXT3_LWP (1 << 15) | |
527 | #define CPUID_EXT3_FMA4 (1 << 16) | |
528 | #define CPUID_EXT3_TCE (1 << 17) | |
529 | #define CPUID_EXT3_NODEID (1 << 19) | |
530 | #define CPUID_EXT3_TBM (1 << 21) | |
531 | #define CPUID_EXT3_TOPOEXT (1 << 22) | |
532 | #define CPUID_EXT3_PERFCORE (1 << 23) | |
533 | #define CPUID_EXT3_PERFNB (1 << 24) | |
534 | ||
535 | #define CPUID_SVM_NPT (1 << 0) | |
536 | #define CPUID_SVM_LBRV (1 << 1) | |
537 | #define CPUID_SVM_SVMLOCK (1 << 2) | |
538 | #define CPUID_SVM_NRIPSAVE (1 << 3) | |
539 | #define CPUID_SVM_TSCSCALE (1 << 4) | |
540 | #define CPUID_SVM_VMCBCLEAN (1 << 5) | |
541 | #define CPUID_SVM_FLUSHASID (1 << 6) | |
542 | #define CPUID_SVM_DECODEASSIST (1 << 7) | |
543 | #define CPUID_SVM_PAUSEFILTER (1 << 10) | |
544 | #define CPUID_SVM_PFTHRESHOLD (1 << 12) | |
545 | ||
546 | #define CPUID_7_0_EBX_FSGSBASE (1 << 0) | |
547 | #define CPUID_7_0_EBX_BMI1 (1 << 3) | |
548 | #define CPUID_7_0_EBX_HLE (1 << 4) | |
549 | #define CPUID_7_0_EBX_AVX2 (1 << 5) | |
550 | #define CPUID_7_0_EBX_SMEP (1 << 7) | |
551 | #define CPUID_7_0_EBX_BMI2 (1 << 8) | |
552 | #define CPUID_7_0_EBX_ERMS (1 << 9) | |
553 | #define CPUID_7_0_EBX_INVPCID (1 << 10) | |
554 | #define CPUID_7_0_EBX_RTM (1 << 11) | |
555 | #define CPUID_7_0_EBX_MPX (1 << 14) | |
556 | #define CPUID_7_0_EBX_RDSEED (1 << 18) | |
557 | #define CPUID_7_0_EBX_ADX (1 << 19) | |
558 | #define CPUID_7_0_EBX_SMAP (1 << 20) | |
559 | ||
560 | #define CPUID_VENDOR_SZ 12 | |
561 | ||
562 | #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ | |
563 | #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ | |
564 | #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ | |
565 | #define CPUID_VENDOR_INTEL "GenuineIntel" | |
566 | ||
567 | #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ | |
568 | #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ | |
569 | #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ | |
570 | #define CPUID_VENDOR_AMD "AuthenticAMD" | |
571 | ||
572 | #define CPUID_VENDOR_VIA "CentaurHauls" | |
573 | ||
574 | #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ | |
575 | #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ | |
576 | ||
577 | #ifndef HYPERV_SPINLOCK_NEVER_RETRY | |
578 | #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF | |
579 | #endif | |
580 | ||
581 | #define EXCP00_DIVZ 0 | |
582 | #define EXCP01_DB 1 | |
583 | #define EXCP02_NMI 2 | |
584 | #define EXCP03_INT3 3 | |
585 | #define EXCP04_INTO 4 | |
586 | #define EXCP05_BOUND 5 | |
587 | #define EXCP06_ILLOP 6 | |
588 | #define EXCP07_PREX 7 | |
589 | #define EXCP08_DBLE 8 | |
590 | #define EXCP09_XERR 9 | |
591 | #define EXCP0A_TSS 10 | |
592 | #define EXCP0B_NOSEG 11 | |
593 | #define EXCP0C_STACK 12 | |
594 | #define EXCP0D_GPF 13 | |
595 | #define EXCP0E_PAGE 14 | |
596 | #define EXCP10_COPR 16 | |
597 | #define EXCP11_ALGN 17 | |
598 | #define EXCP12_MCHK 18 | |
599 | ||
600 | #define EXCP_SYSCALL 0x100 /* only happens in user only emulation | |
601 | for syscall instruction */ | |
602 | ||
603 | /* i386-specific interrupt pending bits. */ | |
604 | #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1 | |
605 | #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2 | |
606 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 | |
607 | #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4 | |
608 | #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 | |
609 | #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 | |
610 | #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 | |
611 | #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3 | |
612 | ||
613 | ||
614 | typedef enum { | |
615 | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ | |
616 | CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ | |
617 | ||
618 | CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ | |
619 | CC_OP_MULW, | |
620 | CC_OP_MULL, | |
621 | CC_OP_MULQ, | |
622 | ||
623 | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
624 | CC_OP_ADDW, | |
625 | CC_OP_ADDL, | |
626 | CC_OP_ADDQ, | |
627 | ||
628 | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
629 | CC_OP_ADCW, | |
630 | CC_OP_ADCL, | |
631 | CC_OP_ADCQ, | |
632 | ||
633 | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
634 | CC_OP_SUBW, | |
635 | CC_OP_SUBL, | |
636 | CC_OP_SUBQ, | |
637 | ||
638 | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ | |
639 | CC_OP_SBBW, | |
640 | CC_OP_SBBL, | |
641 | CC_OP_SBBQ, | |
642 | ||
643 | CC_OP_LOGICB, /* modify all flags, CC_DST = res */ | |
644 | CC_OP_LOGICW, | |
645 | CC_OP_LOGICL, | |
646 | CC_OP_LOGICQ, | |
647 | ||
648 | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
649 | CC_OP_INCW, | |
650 | CC_OP_INCL, | |
651 | CC_OP_INCQ, | |
652 | ||
653 | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ | |
654 | CC_OP_DECW, | |
655 | CC_OP_DECL, | |
656 | CC_OP_DECQ, | |
657 | ||
658 | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ | |
659 | CC_OP_SHLW, | |
660 | CC_OP_SHLL, | |
661 | CC_OP_SHLQ, | |
662 | ||
663 | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ | |
664 | CC_OP_SARW, | |
665 | CC_OP_SARL, | |
666 | CC_OP_SARQ, | |
667 | ||
668 | CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ | |
669 | CC_OP_BMILGW, | |
670 | CC_OP_BMILGL, | |
671 | CC_OP_BMILGQ, | |
672 | ||
673 | CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ | |
674 | CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ | |
675 | CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ | |
676 | ||
677 | CC_OP_CLR, /* Z set, all other flags clear. */ | |
678 | ||
679 | CC_OP_NB, | |
680 | } CCOp; | |
681 | ||
682 | typedef struct SegmentCache { | |
683 | uint32_t selector; | |
684 | target_ulong base; | |
685 | uint32_t limit; | |
686 | uint32_t flags; | |
687 | } SegmentCache; | |
688 | ||
689 | typedef union { | |
690 | uint8_t _b[16]; | |
691 | uint16_t _w[8]; | |
692 | uint32_t _l[4]; | |
693 | uint64_t _q[2]; | |
694 | float32 _s[4]; | |
695 | float64 _d[2]; | |
696 | } XMMReg; | |
697 | ||
698 | typedef union { | |
699 | uint8_t _b[8]; | |
700 | uint16_t _w[4]; | |
701 | uint32_t _l[2]; | |
702 | float32 _s[2]; | |
703 | uint64_t q; | |
704 | } MMXReg; | |
705 | ||
706 | typedef struct BNDReg { | |
707 | uint64_t lb; | |
708 | uint64_t ub; | |
709 | } BNDReg; | |
710 | ||
711 | typedef struct BNDCSReg { | |
712 | uint64_t cfgu; | |
713 | uint64_t sts; | |
714 | } BNDCSReg; | |
715 | ||
716 | #ifdef HOST_WORDS_BIGENDIAN | |
717 | #define XMM_B(n) _b[15 - (n)] | |
718 | #define XMM_W(n) _w[7 - (n)] | |
719 | #define XMM_L(n) _l[3 - (n)] | |
720 | #define XMM_S(n) _s[3 - (n)] | |
721 | #define XMM_Q(n) _q[1 - (n)] | |
722 | #define XMM_D(n) _d[1 - (n)] | |
723 | ||
724 | #define MMX_B(n) _b[7 - (n)] | |
725 | #define MMX_W(n) _w[3 - (n)] | |
726 | #define MMX_L(n) _l[1 - (n)] | |
727 | #define MMX_S(n) _s[1 - (n)] | |
728 | #else | |
729 | #define XMM_B(n) _b[n] | |
730 | #define XMM_W(n) _w[n] | |
731 | #define XMM_L(n) _l[n] | |
732 | #define XMM_S(n) _s[n] | |
733 | #define XMM_Q(n) _q[n] | |
734 | #define XMM_D(n) _d[n] | |
735 | ||
736 | #define MMX_B(n) _b[n] | |
737 | #define MMX_W(n) _w[n] | |
738 | #define MMX_L(n) _l[n] | |
739 | #define MMX_S(n) _s[n] | |
740 | #endif | |
741 | #define MMX_Q(n) q | |
742 | ||
743 | typedef union { | |
744 | floatx80 d __attribute__((aligned(16))); | |
745 | MMXReg mmx; | |
746 | } FPReg; | |
747 | ||
748 | typedef struct { | |
749 | uint64_t base; | |
750 | uint64_t mask; | |
751 | } MTRRVar; | |
752 | ||
753 | #define CPU_NB_REGS64 16 | |
754 | #define CPU_NB_REGS32 8 | |
755 | ||
756 | #ifdef TARGET_X86_64 | |
757 | #define CPU_NB_REGS CPU_NB_REGS64 | |
758 | #else | |
759 | #define CPU_NB_REGS CPU_NB_REGS32 | |
760 | #endif | |
761 | ||
762 | #define MAX_FIXED_COUNTERS 3 | |
763 | #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) | |
764 | ||
765 | #define NB_MMU_MODES 3 | |
766 | ||
767 | typedef enum TPRAccess { | |
768 | TPR_ACCESS_READ, | |
769 | TPR_ACCESS_WRITE, | |
770 | } TPRAccess; | |
771 | ||
772 | typedef struct CPUX86State { | |
773 | /* standard registers */ | |
774 | target_ulong regs[CPU_NB_REGS]; | |
775 | target_ulong eip; | |
776 | target_ulong eflags; /* eflags register. During CPU emulation, CC | |
777 | flags and DF are set to zero because they are | |
778 | stored elsewhere */ | |
779 | ||
780 | /* emulator internal eflags handling */ | |
781 | target_ulong cc_dst; | |
782 | target_ulong cc_src; | |
783 | target_ulong cc_src2; | |
784 | uint32_t cc_op; | |
785 | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ | |
786 | uint32_t hflags; /* TB flags, see HF_xxx constants. These flags | |
787 | are known at translation time. */ | |
788 | uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ | |
789 | ||
790 | /* segments */ | |
791 | SegmentCache segs[6]; /* selector values */ | |
792 | SegmentCache ldt; | |
793 | SegmentCache tr; | |
794 | SegmentCache gdt; /* only base and limit are used */ | |
795 | SegmentCache idt; /* only base and limit are used */ | |
796 | ||
797 | target_ulong cr[5]; /* NOTE: cr1 is unused */ | |
798 | int32_t a20_mask; | |
799 | ||
800 | /* FPU state */ | |
801 | unsigned int fpstt; /* top of stack index */ | |
802 | uint16_t fpus; | |
803 | uint16_t fpuc; | |
804 | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ | |
805 | FPReg fpregs[8]; | |
806 | /* KVM-only so far */ | |
807 | uint16_t fpop; | |
808 | uint64_t fpip; | |
809 | uint64_t fpdp; | |
810 | ||
811 | /* emulator internal variables */ | |
812 | float_status fp_status; | |
813 | floatx80 ft0; | |
814 | ||
815 | float_status mmx_status; /* for 3DNow! float ops */ | |
816 | float_status sse_status; | |
817 | uint32_t mxcsr; | |
818 | XMMReg xmm_regs[CPU_NB_REGS]; | |
819 | XMMReg xmm_t0; | |
820 | MMXReg mmx_t0; | |
821 | ||
822 | /* sysenter registers */ | |
823 | uint32_t sysenter_cs; | |
824 | target_ulong sysenter_esp; | |
825 | target_ulong sysenter_eip; | |
826 | uint64_t efer; | |
827 | uint64_t star; | |
828 | ||
829 | uint64_t vm_hsave; | |
830 | uint64_t vm_vmcb; | |
831 | uint64_t tsc_offset; | |
832 | uint64_t intercept; | |
833 | uint16_t intercept_cr_read; | |
834 | uint16_t intercept_cr_write; | |
835 | uint16_t intercept_dr_read; | |
836 | uint16_t intercept_dr_write; | |
837 | uint32_t intercept_exceptions; | |
838 | uint8_t v_tpr; | |
839 | ||
840 | #ifdef TARGET_X86_64 | |
841 | target_ulong lstar; | |
842 | target_ulong cstar; | |
843 | target_ulong fmask; | |
844 | target_ulong kernelgsbase; | |
845 | #endif | |
846 | uint64_t system_time_msr; | |
847 | uint64_t wall_clock_msr; | |
848 | uint64_t steal_time_msr; | |
849 | uint64_t async_pf_en_msr; | |
850 | uint64_t pv_eoi_en_msr; | |
851 | ||
852 | uint64_t tsc; | |
853 | uint64_t tsc_adjust; | |
854 | uint64_t tsc_deadline; | |
855 | ||
856 | uint64_t mcg_status; | |
857 | uint64_t msr_ia32_misc_enable; | |
858 | uint64_t msr_ia32_feature_control; | |
859 | ||
860 | uint64_t msr_fixed_ctr_ctrl; | |
861 | uint64_t msr_global_ctrl; | |
862 | uint64_t msr_global_status; | |
863 | uint64_t msr_global_ovf_ctrl; | |
864 | uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; | |
865 | uint64_t msr_gp_counters[MAX_GP_COUNTERS]; | |
866 | uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; | |
867 | uint64_t msr_hv_hypercall; | |
868 | uint64_t msr_hv_guest_os_id; | |
869 | uint64_t msr_hv_vapic; | |
870 | uint64_t msr_hv_tsc; | |
871 | ||
872 | /* exception/interrupt handling */ | |
873 | int error_code; | |
874 | int exception_is_int; | |
875 | target_ulong exception_next_eip; | |
876 | target_ulong dr[8]; /* debug registers */ | |
877 | union { | |
878 | CPUBreakpoint *cpu_breakpoint[4]; | |
879 | CPUWatchpoint *cpu_watchpoint[4]; | |
880 | }; /* break/watchpoints for dr[0..3] */ | |
881 | uint32_t smbase; | |
882 | int old_exception; /* exception in flight */ | |
883 | ||
884 | /* KVM states, automatically cleared on reset */ | |
885 | uint8_t nmi_injected; | |
886 | uint8_t nmi_pending; | |
887 | ||
888 | CPU_COMMON | |
889 | ||
890 | uint64_t pat; | |
891 | ||
892 | /* processor features (e.g. for CPUID insn) */ | |
893 | uint32_t cpuid_level; | |
894 | uint32_t cpuid_xlevel; | |
895 | uint32_t cpuid_xlevel2; | |
896 | uint32_t cpuid_vendor1; | |
897 | uint32_t cpuid_vendor2; | |
898 | uint32_t cpuid_vendor3; | |
899 | uint32_t cpuid_version; | |
900 | FeatureWordArray features; | |
901 | uint32_t cpuid_model[12]; | |
902 | uint32_t cpuid_apic_id; | |
903 | ||
904 | /* MTRRs */ | |
905 | uint64_t mtrr_fixed[11]; | |
906 | uint64_t mtrr_deftype; | |
907 | MTRRVar mtrr_var[8]; | |
908 | ||
909 | /* For KVM */ | |
910 | uint32_t mp_state; | |
911 | int32_t exception_injected; | |
912 | int32_t interrupt_injected; | |
913 | uint8_t soft_interrupt; | |
914 | uint8_t has_error_code; | |
915 | uint32_t sipi_vector; | |
916 | bool tsc_valid; | |
917 | int tsc_khz; | |
918 | void *kvm_xsave_buf; | |
919 | ||
920 | uint64_t mcg_cap; | |
921 | uint64_t mcg_ctl; | |
922 | uint64_t mce_banks[MCE_BANKS_DEF*4]; | |
923 | ||
924 | uint64_t tsc_aux; | |
925 | ||
926 | /* vmstate */ | |
927 | uint16_t fpus_vmstate; | |
928 | uint16_t fptag_vmstate; | |
929 | uint16_t fpregs_format_vmstate; | |
930 | ||
931 | uint64_t xstate_bv; | |
932 | XMMReg ymmh_regs[CPU_NB_REGS]; | |
933 | BNDReg bnd_regs[4]; | |
934 | BNDCSReg bndcs_regs; | |
935 | uint64_t msr_bndcfgs; | |
936 | ||
937 | uint64_t xcr0; | |
938 | ||
939 | TPRAccess tpr_access_type; | |
940 | } CPUX86State; | |
941 | ||
942 | #include "cpu-qom.h" | |
943 | ||
944 | X86CPU *cpu_x86_init(const char *cpu_model); | |
945 | X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge, | |
946 | Error **errp); | |
947 | int cpu_x86_exec(CPUX86State *s); | |
948 | void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
949 | void x86_cpudef_setup(void); | |
950 | int cpu_x86_support_mca_broadcast(CPUX86State *env); | |
951 | ||
952 | int cpu_get_pic_interrupt(CPUX86State *s); | |
953 | /* MSDOS compatibility mode FPU exception support */ | |
954 | void cpu_set_ferr(CPUX86State *s); | |
955 | ||
956 | /* this function must always be used to load data in the segment | |
957 | cache: it synchronizes the hflags with the segment cache values */ | |
958 | static inline void cpu_x86_load_seg_cache(CPUX86State *env, | |
959 | int seg_reg, unsigned int selector, | |
960 | target_ulong base, | |
961 | unsigned int limit, | |
962 | unsigned int flags) | |
963 | { | |
964 | SegmentCache *sc; | |
965 | unsigned int new_hflags; | |
966 | ||
967 | sc = &env->segs[seg_reg]; | |
968 | sc->selector = selector; | |
969 | sc->base = base; | |
970 | sc->limit = limit; | |
971 | sc->flags = flags; | |
972 | ||
973 | /* update the hidden flags */ | |
974 | { | |
975 | if (seg_reg == R_CS) { | |
976 | #ifdef TARGET_X86_64 | |
977 | if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { | |
978 | /* long mode */ | |
979 | env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; | |
980 | env->hflags &= ~(HF_ADDSEG_MASK); | |
981 | } else | |
982 | #endif | |
983 | { | |
984 | /* legacy / compatibility case */ | |
985 | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) | |
986 | >> (DESC_B_SHIFT - HF_CS32_SHIFT); | |
987 | env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | | |
988 | new_hflags; | |
989 | } | |
990 | } | |
991 | new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) | |
992 | >> (DESC_B_SHIFT - HF_SS32_SHIFT); | |
993 | if (env->hflags & HF_CS64_MASK) { | |
994 | /* zero base assumed for DS, ES and SS in long mode */ | |
995 | } else if (!(env->cr[0] & CR0_PE_MASK) || | |
996 | (env->eflags & VM_MASK) || | |
997 | !(env->hflags & HF_CS32_MASK)) { | |
998 | /* XXX: try to avoid this test. The problem comes from the | |
999 | fact that is real mode or vm86 mode we only modify the | |
1000 | 'base' and 'selector' fields of the segment cache to go | |
1001 | faster. A solution may be to force addseg to one in | |
1002 | translate-i386.c. */ | |
1003 | new_hflags |= HF_ADDSEG_MASK; | |
1004 | } else { | |
1005 | new_hflags |= ((env->segs[R_DS].base | | |
1006 | env->segs[R_ES].base | | |
1007 | env->segs[R_SS].base) != 0) << | |
1008 | HF_ADDSEG_SHIFT; | |
1009 | } | |
1010 | env->hflags = (env->hflags & | |
1011 | ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; | |
1012 | } | |
1013 | } | |
1014 | ||
1015 | static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, | |
1016 | int sipi_vector) | |
1017 | { | |
1018 | CPUState *cs = CPU(cpu); | |
1019 | CPUX86State *env = &cpu->env; | |
1020 | ||
1021 | env->eip = 0; | |
1022 | cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, | |
1023 | sipi_vector << 12, | |
1024 | env->segs[R_CS].limit, | |
1025 | env->segs[R_CS].flags); | |
1026 | cs->halted = 0; | |
1027 | } | |
1028 | ||
1029 | int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, | |
1030 | target_ulong *base, unsigned int *limit, | |
1031 | unsigned int *flags); | |
1032 | ||
1033 | /* wrapper, just in case memory mappings must be changed */ | |
1034 | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) | |
1035 | { | |
1036 | #if HF_CPL_MASK == 3 | |
1037 | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; | |
1038 | #else | |
1039 | #error HF_CPL_MASK is hardcoded | |
1040 | #endif | |
1041 | } | |
1042 | ||
1043 | /* op_helper.c */ | |
1044 | /* used for debug or cpu save/restore */ | |
1045 | void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f); | |
1046 | floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper); | |
1047 | ||
1048 | /* cpu-exec.c */ | |
1049 | /* the following helpers are only usable in user mode simulation as | |
1050 | they can trigger unexpected exceptions */ | |
1051 | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); | |
1052 | void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); | |
1053 | void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); | |
1054 | ||
1055 | /* you can call this signal handler from your SIGBUS and SIGSEGV | |
1056 | signal handlers to inform the virtual CPU of exceptions. non zero | |
1057 | is returned if the signal was handled by the virtual CPU. */ | |
1058 | int cpu_x86_signal_handler(int host_signum, void *pinfo, | |
1059 | void *puc); | |
1060 | ||
1061 | /* cpuid.c */ | |
1062 | void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, | |
1063 | uint32_t *eax, uint32_t *ebx, | |
1064 | uint32_t *ecx, uint32_t *edx); | |
1065 | void cpu_clear_apic_feature(CPUX86State *env); | |
1066 | void host_cpuid(uint32_t function, uint32_t count, | |
1067 | uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); | |
1068 | ||
1069 | /* helper.c */ | |
1070 | int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, | |
1071 | int is_write, int mmu_idx); | |
1072 | #define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault | |
1073 | void x86_cpu_set_a20(X86CPU *cpu, int a20_state); | |
1074 | ||
1075 | static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index) | |
1076 | { | |
1077 | return (dr7 >> (index * 2)) & 1; | |
1078 | } | |
1079 | ||
1080 | static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index) | |
1081 | { | |
1082 | return (dr7 >> (index * 2)) & 2; | |
1083 | ||
1084 | } | |
1085 | static inline bool hw_breakpoint_enabled(unsigned long dr7, int index) | |
1086 | { | |
1087 | return hw_global_breakpoint_enabled(dr7, index) || | |
1088 | hw_local_breakpoint_enabled(dr7, index); | |
1089 | } | |
1090 | ||
1091 | static inline int hw_breakpoint_type(unsigned long dr7, int index) | |
1092 | { | |
1093 | return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3; | |
1094 | } | |
1095 | ||
1096 | static inline int hw_breakpoint_len(unsigned long dr7, int index) | |
1097 | { | |
1098 | int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3); | |
1099 | return (len == 2) ? 8 : len + 1; | |
1100 | } | |
1101 | ||
1102 | void hw_breakpoint_insert(CPUX86State *env, int index); | |
1103 | void hw_breakpoint_remove(CPUX86State *env, int index); | |
1104 | bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update); | |
1105 | void breakpoint_handler(CPUX86State *env); | |
1106 | ||
1107 | /* will be suppressed */ | |
1108 | void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); | |
1109 | void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); | |
1110 | void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); | |
1111 | ||
1112 | /* hw/pc.c */ | |
1113 | void cpu_smm_update(CPUX86State *env); | |
1114 | uint64_t cpu_get_tsc(CPUX86State *env); | |
1115 | ||
1116 | #define TARGET_PAGE_BITS 12 | |
1117 | ||
1118 | #ifdef TARGET_X86_64 | |
1119 | #define TARGET_PHYS_ADDR_SPACE_BITS 52 | |
1120 | /* ??? This is really 48 bits, sign-extended, but the only thing | |
1121 | accessible to userland with bit 48 set is the VSYSCALL, and that | |
1122 | is handled via other mechanisms. */ | |
1123 | #define TARGET_VIRT_ADDR_SPACE_BITS 47 | |
1124 | #else | |
1125 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 | |
1126 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
1127 | #endif | |
1128 | ||
1129 | static inline CPUX86State *cpu_init(const char *cpu_model) | |
1130 | { | |
1131 | X86CPU *cpu = cpu_x86_init(cpu_model); | |
1132 | if (cpu == NULL) { | |
1133 | return NULL; | |
1134 | } | |
1135 | return &cpu->env; | |
1136 | } | |
1137 | ||
1138 | #define cpu_exec cpu_x86_exec | |
1139 | #define cpu_gen_code cpu_x86_gen_code | |
1140 | #define cpu_signal_handler cpu_x86_signal_handler | |
1141 | #define cpu_list x86_cpu_list | |
1142 | #define cpudef_setup x86_cpudef_setup | |
1143 | ||
1144 | /* MMU modes definitions */ | |
1145 | #define MMU_MODE0_SUFFIX _kernel | |
1146 | #define MMU_MODE1_SUFFIX _user | |
1147 | #define MMU_MODE2_SUFFIX _ksmap /* Kernel with SMAP override */ | |
1148 | #define MMU_KERNEL_IDX 0 | |
1149 | #define MMU_USER_IDX 1 | |
1150 | #define MMU_KSMAP_IDX 2 | |
1151 | static inline int cpu_mmu_index (CPUX86State *env) | |
1152 | { | |
1153 | return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : | |
1154 | ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK)) | |
1155 | ? MMU_KSMAP_IDX : MMU_KERNEL_IDX; | |
1156 | } | |
1157 | ||
1158 | #define CC_DST (env->cc_dst) | |
1159 | #define CC_SRC (env->cc_src) | |
1160 | #define CC_SRC2 (env->cc_src2) | |
1161 | #define CC_OP (env->cc_op) | |
1162 | ||
1163 | /* n must be a constant to be efficient */ | |
1164 | static inline target_long lshift(target_long x, int n) | |
1165 | { | |
1166 | if (n >= 0) { | |
1167 | return x << n; | |
1168 | } else { | |
1169 | return x >> (-n); | |
1170 | } | |
1171 | } | |
1172 | ||
1173 | /* float macros */ | |
1174 | #define FT0 (env->ft0) | |
1175 | #define ST0 (env->fpregs[env->fpstt].d) | |
1176 | #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) | |
1177 | #define ST1 ST(1) | |
1178 | ||
1179 | /* translate.c */ | |
1180 | void optimize_flags_init(void); | |
1181 | ||
1182 | #include "exec/cpu-all.h" | |
1183 | #include "svm.h" | |
1184 | ||
1185 | #if !defined(CONFIG_USER_ONLY) | |
1186 | #include "hw/i386/apic.h" | |
1187 | #endif | |
1188 | ||
1189 | #include "exec/exec-all.h" | |
1190 | ||
1191 | static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, | |
1192 | target_ulong *cs_base, int *flags) | |
1193 | { | |
1194 | *cs_base = env->segs[R_CS].base; | |
1195 | *pc = *cs_base + env->eip; | |
1196 | *flags = env->hflags | | |
1197 | (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); | |
1198 | } | |
1199 | ||
1200 | void do_cpu_init(X86CPU *cpu); | |
1201 | void do_cpu_sipi(X86CPU *cpu); | |
1202 | ||
1203 | #define MCE_INJECT_BROADCAST 1 | |
1204 | #define MCE_INJECT_UNCOND_AO 2 | |
1205 | ||
1206 | void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, | |
1207 | uint64_t status, uint64_t mcg_status, uint64_t addr, | |
1208 | uint64_t misc, int flags); | |
1209 | ||
1210 | /* excp_helper.c */ | |
1211 | void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); | |
1212 | void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index, | |
1213 | int error_code); | |
1214 | void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int, | |
1215 | int error_code, int next_eip_addend); | |
1216 | ||
1217 | /* cc_helper.c */ | |
1218 | extern const uint8_t parity_table[256]; | |
1219 | uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); | |
1220 | ||
1221 | static inline uint32_t cpu_compute_eflags(CPUX86State *env) | |
1222 | { | |
1223 | return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK); | |
1224 | } | |
1225 | ||
1226 | /* NOTE: CC_OP must be modified manually to CC_OP_EFLAGS */ | |
1227 | static inline void cpu_load_eflags(CPUX86State *env, int eflags, | |
1228 | int update_mask) | |
1229 | { | |
1230 | CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); | |
1231 | env->df = 1 - (2 * ((eflags >> 10) & 1)); | |
1232 | env->eflags = (env->eflags & ~update_mask) | | |
1233 | (eflags & update_mask) | 0x2; | |
1234 | } | |
1235 | ||
1236 | /* load efer and update the corresponding hflags. XXX: do consistency | |
1237 | checks with cpuid bits? */ | |
1238 | static inline void cpu_load_efer(CPUX86State *env, uint64_t val) | |
1239 | { | |
1240 | env->efer = val; | |
1241 | env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); | |
1242 | if (env->efer & MSR_EFER_LMA) { | |
1243 | env->hflags |= HF_LMA_MASK; | |
1244 | } | |
1245 | if (env->efer & MSR_EFER_SVME) { | |
1246 | env->hflags |= HF_SVME_MASK; | |
1247 | } | |
1248 | } | |
1249 | ||
1250 | /* fpu_helper.c */ | |
1251 | void cpu_set_mxcsr(CPUX86State *env, uint32_t val); | |
1252 | ||
1253 | /* svm_helper.c */ | |
1254 | void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, | |
1255 | uint64_t param); | |
1256 | void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1); | |
1257 | ||
1258 | /* seg_helper.c */ | |
1259 | void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); | |
1260 | ||
1261 | void do_smm_enter(X86CPU *cpu); | |
1262 | ||
1263 | void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); | |
1264 | ||
1265 | void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w, | |
1266 | uint32_t feat_add, uint32_t feat_remove); | |
1267 | ||
1268 | void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features); | |
1269 | ||
1270 | ||
1271 | /* Return name of 32-bit register, from a R_* constant */ | |
1272 | const char *get_register_name_32(unsigned int reg); | |
1273 | ||
1274 | uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index); | |
1275 | void enable_compat_apic_id_mode(void); | |
1276 | ||
1277 | #define APIC_DEFAULT_ADDRESS 0xfee00000 | |
1278 | #define APIC_SPACE_SIZE 0x100000 | |
1279 | ||
1280 | #endif /* CPU_I386_H */ |