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1 | /* | |
2 | * MIPS emulation helpers for qemu. | |
3 | * | |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | #include <stdarg.h> | |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
25 | ||
26 | #include "cpu.h" | |
27 | #include "exec-all.h" | |
28 | ||
29 | enum { | |
30 | TLBRET_DIRTY = -4, | |
31 | TLBRET_INVALID = -3, | |
32 | TLBRET_NOMATCH = -2, | |
33 | TLBRET_BADADDR = -1, | |
34 | TLBRET_MATCH = 0 | |
35 | }; | |
36 | ||
37 | /* no MMU emulation */ | |
38 | int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, | |
39 | target_ulong address, int rw, int access_type) | |
40 | { | |
41 | *physical = address; | |
42 | *prot = PAGE_READ | PAGE_WRITE; | |
43 | return TLBRET_MATCH; | |
44 | } | |
45 | ||
46 | /* fixed mapping MMU emulation */ | |
47 | int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, | |
48 | target_ulong address, int rw, int access_type) | |
49 | { | |
50 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
51 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
52 | *physical = address + 0x40000000UL; | |
53 | else | |
54 | *physical = address; | |
55 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
56 | *physical = address & 0x1FFFFFFF; | |
57 | else | |
58 | *physical = address; | |
59 | ||
60 | *prot = PAGE_READ | PAGE_WRITE; | |
61 | return TLBRET_MATCH; | |
62 | } | |
63 | ||
64 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
65 | int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot, | |
66 | target_ulong address, int rw, int access_type) | |
67 | { | |
68 | uint8_t ASID = env->CP0_EntryHi & 0xFF; | |
69 | int i; | |
70 | ||
71 | for (i = 0; i < env->tlb->tlb_in_use; i++) { | |
72 | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; | |
73 | /* 1k pages are not supported. */ | |
74 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
75 | target_ulong tag = address & ~mask; | |
76 | target_ulong VPN = tlb->VPN & ~mask; | |
77 | #if defined(TARGET_MIPS64) | |
78 | tag &= env->SEGMask; | |
79 | #endif | |
80 | ||
81 | /* Check ASID, virtual page number & size */ | |
82 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { | |
83 | /* TLB match */ | |
84 | int n = !!(address & mask & ~(mask >> 1)); | |
85 | /* Check access rights */ | |
86 | if (!(n ? tlb->V1 : tlb->V0)) | |
87 | return TLBRET_INVALID; | |
88 | if (rw == 0 || (n ? tlb->D1 : tlb->D0)) { | |
89 | *physical = tlb->PFN[n] | (address & (mask >> 1)); | |
90 | *prot = PAGE_READ; | |
91 | if (n ? tlb->D1 : tlb->D0) | |
92 | *prot |= PAGE_WRITE; | |
93 | return TLBRET_MATCH; | |
94 | } | |
95 | return TLBRET_DIRTY; | |
96 | } | |
97 | } | |
98 | return TLBRET_NOMATCH; | |
99 | } | |
100 | ||
101 | #if !defined(CONFIG_USER_ONLY) | |
102 | static int get_physical_address (CPUState *env, target_phys_addr_t *physical, | |
103 | int *prot, target_ulong address, | |
104 | int rw, int access_type) | |
105 | { | |
106 | /* User mode can only access useg/xuseg */ | |
107 | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; | |
108 | int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; | |
109 | int kernel_mode = !user_mode && !supervisor_mode; | |
110 | #if defined(TARGET_MIPS64) | |
111 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
112 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
113 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
114 | #endif | |
115 | int ret = TLBRET_MATCH; | |
116 | ||
117 | #if 0 | |
118 | qemu_log("user mode %d h %08x\n", user_mode, env->hflags); | |
119 | #endif | |
120 | ||
121 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
122 | /* useg */ | |
123 | if (env->CP0_Status & (1 << CP0St_ERL)) { | |
124 | *physical = address & 0xFFFFFFFF; | |
125 | *prot = PAGE_READ | PAGE_WRITE; | |
126 | } else { | |
127 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
128 | } | |
129 | #if defined(TARGET_MIPS64) | |
130 | } else if (address < 0x4000000000000000ULL) { | |
131 | /* xuseg */ | |
132 | if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { | |
133 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
134 | } else { | |
135 | ret = TLBRET_BADADDR; | |
136 | } | |
137 | } else if (address < 0x8000000000000000ULL) { | |
138 | /* xsseg */ | |
139 | if ((supervisor_mode || kernel_mode) && | |
140 | SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { | |
141 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
142 | } else { | |
143 | ret = TLBRET_BADADDR; | |
144 | } | |
145 | } else if (address < 0xC000000000000000ULL) { | |
146 | /* xkphys */ | |
147 | if (kernel_mode && KX && | |
148 | (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { | |
149 | *physical = address & env->PAMask; | |
150 | *prot = PAGE_READ | PAGE_WRITE; | |
151 | } else { | |
152 | ret = TLBRET_BADADDR; | |
153 | } | |
154 | } else if (address < 0xFFFFFFFF80000000ULL) { | |
155 | /* xkseg */ | |
156 | if (kernel_mode && KX && | |
157 | address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { | |
158 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
159 | } else { | |
160 | ret = TLBRET_BADADDR; | |
161 | } | |
162 | #endif | |
163 | } else if (address < (int32_t)0xA0000000UL) { | |
164 | /* kseg0 */ | |
165 | if (kernel_mode) { | |
166 | *physical = address - (int32_t)0x80000000UL; | |
167 | *prot = PAGE_READ | PAGE_WRITE; | |
168 | } else { | |
169 | ret = TLBRET_BADADDR; | |
170 | } | |
171 | } else if (address < (int32_t)0xC0000000UL) { | |
172 | /* kseg1 */ | |
173 | if (kernel_mode) { | |
174 | *physical = address - (int32_t)0xA0000000UL; | |
175 | *prot = PAGE_READ | PAGE_WRITE; | |
176 | } else { | |
177 | ret = TLBRET_BADADDR; | |
178 | } | |
179 | } else if (address < (int32_t)0xE0000000UL) { | |
180 | /* sseg (kseg2) */ | |
181 | if (supervisor_mode || kernel_mode) { | |
182 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
183 | } else { | |
184 | ret = TLBRET_BADADDR; | |
185 | } | |
186 | } else { | |
187 | /* kseg3 */ | |
188 | /* XXX: debug segment is not emulated */ | |
189 | if (kernel_mode) { | |
190 | ret = env->tlb->map_address(env, physical, prot, address, rw, access_type); | |
191 | } else { | |
192 | ret = TLBRET_BADADDR; | |
193 | } | |
194 | } | |
195 | #if 0 | |
196 | qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n", | |
197 | address, rw, access_type, *physical, *prot, ret); | |
198 | #endif | |
199 | ||
200 | return ret; | |
201 | } | |
202 | #endif | |
203 | ||
204 | static void raise_mmu_exception(CPUState *env, target_ulong address, | |
205 | int rw, int tlb_error) | |
206 | { | |
207 | int exception = 0, error_code = 0; | |
208 | ||
209 | switch (tlb_error) { | |
210 | default: | |
211 | case TLBRET_BADADDR: | |
212 | /* Reference to kernel address from user mode or supervisor mode */ | |
213 | /* Reference to supervisor address from user mode */ | |
214 | if (rw) | |
215 | exception = EXCP_AdES; | |
216 | else | |
217 | exception = EXCP_AdEL; | |
218 | break; | |
219 | case TLBRET_NOMATCH: | |
220 | /* No TLB match for a mapped address */ | |
221 | if (rw) | |
222 | exception = EXCP_TLBS; | |
223 | else | |
224 | exception = EXCP_TLBL; | |
225 | error_code = 1; | |
226 | break; | |
227 | case TLBRET_INVALID: | |
228 | /* TLB match with no valid bit */ | |
229 | if (rw) | |
230 | exception = EXCP_TLBS; | |
231 | else | |
232 | exception = EXCP_TLBL; | |
233 | break; | |
234 | case TLBRET_DIRTY: | |
235 | /* TLB match but 'D' bit is cleared */ | |
236 | exception = EXCP_LTLBL; | |
237 | break; | |
238 | ||
239 | } | |
240 | /* Raise exception */ | |
241 | env->CP0_BadVAddr = address; | |
242 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | | |
243 | ((address >> 9) & 0x007ffff0); | |
244 | env->CP0_EntryHi = | |
245 | (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1)); | |
246 | #if defined(TARGET_MIPS64) | |
247 | env->CP0_EntryHi &= env->SEGMask; | |
248 | env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | | |
249 | ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) | | |
250 | ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9); | |
251 | #endif | |
252 | env->exception_index = exception; | |
253 | env->error_code = error_code; | |
254 | } | |
255 | ||
256 | #if !defined(CONFIG_USER_ONLY) | |
257 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) | |
258 | { | |
259 | target_phys_addr_t phys_addr; | |
260 | int prot; | |
261 | ||
262 | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0) | |
263 | return -1; | |
264 | return phys_addr; | |
265 | } | |
266 | #endif | |
267 | ||
268 | int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, | |
269 | int mmu_idx, int is_softmmu) | |
270 | { | |
271 | #if !defined(CONFIG_USER_ONLY) | |
272 | target_phys_addr_t physical; | |
273 | int prot; | |
274 | #endif | |
275 | int access_type; | |
276 | int ret = 0; | |
277 | ||
278 | #if 0 | |
279 | log_cpu_state(env, 0); | |
280 | #endif | |
281 | qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n", | |
282 | __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu); | |
283 | ||
284 | rw &= 1; | |
285 | ||
286 | /* data access */ | |
287 | /* XXX: put correct access by using cpu_restore_state() | |
288 | correctly */ | |
289 | access_type = ACCESS_INT; | |
290 | #if defined(CONFIG_USER_ONLY) | |
291 | ret = TLBRET_NOMATCH; | |
292 | #else | |
293 | ret = get_physical_address(env, &physical, &prot, | |
294 | address, rw, access_type); | |
295 | qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n", | |
296 | __func__, address, ret, physical, prot); | |
297 | if (ret == TLBRET_MATCH) { | |
298 | ret = tlb_set_page(env, address & TARGET_PAGE_MASK, | |
299 | physical & TARGET_PAGE_MASK, prot, | |
300 | mmu_idx, is_softmmu); | |
301 | } else if (ret < 0) | |
302 | #endif | |
303 | { | |
304 | raise_mmu_exception(env, address, rw, ret); | |
305 | ret = 1; | |
306 | } | |
307 | ||
308 | return ret; | |
309 | } | |
310 | ||
311 | #if !defined(CONFIG_USER_ONLY) | |
312 | target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw) | |
313 | { | |
314 | target_phys_addr_t physical; | |
315 | int prot; | |
316 | int access_type; | |
317 | int ret = 0; | |
318 | ||
319 | rw &= 1; | |
320 | ||
321 | /* data access */ | |
322 | access_type = ACCESS_INT; | |
323 | ret = get_physical_address(env, &physical, &prot, | |
324 | address, rw, access_type); | |
325 | if (ret != TLBRET_MATCH) { | |
326 | raise_mmu_exception(env, address, rw, ret); | |
327 | return -1LL; | |
328 | } else { | |
329 | return physical; | |
330 | } | |
331 | } | |
332 | #endif | |
333 | ||
334 | static const char * const excp_names[EXCP_LAST + 1] = { | |
335 | [EXCP_RESET] = "reset", | |
336 | [EXCP_SRESET] = "soft reset", | |
337 | [EXCP_DSS] = "debug single step", | |
338 | [EXCP_DINT] = "debug interrupt", | |
339 | [EXCP_NMI] = "non-maskable interrupt", | |
340 | [EXCP_MCHECK] = "machine check", | |
341 | [EXCP_EXT_INTERRUPT] = "interrupt", | |
342 | [EXCP_DFWATCH] = "deferred watchpoint", | |
343 | [EXCP_DIB] = "debug instruction breakpoint", | |
344 | [EXCP_IWATCH] = "instruction fetch watchpoint", | |
345 | [EXCP_AdEL] = "address error load", | |
346 | [EXCP_AdES] = "address error store", | |
347 | [EXCP_TLBF] = "TLB refill", | |
348 | [EXCP_IBE] = "instruction bus error", | |
349 | [EXCP_DBp] = "debug breakpoint", | |
350 | [EXCP_SYSCALL] = "syscall", | |
351 | [EXCP_BREAK] = "break", | |
352 | [EXCP_CpU] = "coprocessor unusable", | |
353 | [EXCP_RI] = "reserved instruction", | |
354 | [EXCP_OVERFLOW] = "arithmetic overflow", | |
355 | [EXCP_TRAP] = "trap", | |
356 | [EXCP_FPE] = "floating point", | |
357 | [EXCP_DDBS] = "debug data break store", | |
358 | [EXCP_DWATCH] = "data watchpoint", | |
359 | [EXCP_LTLBL] = "TLB modify", | |
360 | [EXCP_TLBL] = "TLB load", | |
361 | [EXCP_TLBS] = "TLB store", | |
362 | [EXCP_DBE] = "data bus error", | |
363 | [EXCP_DDBL] = "debug data break load", | |
364 | [EXCP_THREAD] = "thread", | |
365 | [EXCP_MDMX] = "MDMX", | |
366 | [EXCP_C2E] = "precise coprocessor 2", | |
367 | [EXCP_CACHE] = "cache error", | |
368 | }; | |
369 | ||
370 | #if !defined(CONFIG_USER_ONLY) | |
371 | static target_ulong exception_resume_pc (CPUState *env) | |
372 | { | |
373 | target_ulong bad_pc; | |
374 | target_ulong isa_mode; | |
375 | ||
376 | isa_mode = !!(env->hflags & MIPS_HFLAG_M16); | |
377 | bad_pc = env->active_tc.PC | isa_mode; | |
378 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
379 | /* If the exception was raised from a delay slot, come back to | |
380 | the jump. */ | |
381 | bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); | |
382 | } | |
383 | ||
384 | return bad_pc; | |
385 | } | |
386 | #endif | |
387 | ||
388 | void do_interrupt (CPUState *env) | |
389 | { | |
390 | #if !defined(CONFIG_USER_ONLY) | |
391 | target_ulong offset; | |
392 | int cause = -1; | |
393 | const char *name; | |
394 | ||
395 | if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { | |
396 | if (env->exception_index < 0 || env->exception_index > EXCP_LAST) | |
397 | name = "unknown"; | |
398 | else | |
399 | name = excp_names[env->exception_index]; | |
400 | ||
401 | qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n", | |
402 | __func__, env->active_tc.PC, env->CP0_EPC, name); | |
403 | } | |
404 | if (env->exception_index == EXCP_EXT_INTERRUPT && | |
405 | (env->hflags & MIPS_HFLAG_DM)) | |
406 | env->exception_index = EXCP_DINT; | |
407 | offset = 0x180; | |
408 | switch (env->exception_index) { | |
409 | case EXCP_DSS: | |
410 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
411 | /* Debug single step cannot be raised inside a delay slot and | |
412 | resume will always occur on the next instruction | |
413 | (but we assume the pc has always been updated during | |
414 | code translation). */ | |
415 | env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); | |
416 | goto enter_debug_mode; | |
417 | case EXCP_DINT: | |
418 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
419 | goto set_DEPC; | |
420 | case EXCP_DIB: | |
421 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
422 | goto set_DEPC; | |
423 | case EXCP_DBp: | |
424 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
425 | goto set_DEPC; | |
426 | case EXCP_DDBS: | |
427 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
428 | goto set_DEPC; | |
429 | case EXCP_DDBL: | |
430 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
431 | set_DEPC: | |
432 | env->CP0_DEPC = exception_resume_pc(env); | |
433 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
434 | enter_debug_mode: | |
435 | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0; | |
436 | env->hflags &= ~(MIPS_HFLAG_KSU); | |
437 | /* EJTAG probe trap enable is not implemented... */ | |
438 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
439 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
440 | env->active_tc.PC = (int32_t)0xBFC00480; | |
441 | /* Exception handlers are entered in 32-bit mode. */ | |
442 | env->hflags &= ~(MIPS_HFLAG_M16); | |
443 | break; | |
444 | case EXCP_RESET: | |
445 | cpu_reset(env); | |
446 | break; | |
447 | case EXCP_SRESET: | |
448 | env->CP0_Status |= (1 << CP0St_SR); | |
449 | memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo)); | |
450 | goto set_error_EPC; | |
451 | case EXCP_NMI: | |
452 | env->CP0_Status |= (1 << CP0St_NMI); | |
453 | set_error_EPC: | |
454 | env->CP0_ErrorEPC = exception_resume_pc(env); | |
455 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
456 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); | |
457 | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; | |
458 | env->hflags &= ~(MIPS_HFLAG_KSU); | |
459 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
460 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
461 | env->active_tc.PC = (int32_t)0xBFC00000; | |
462 | /* Exception handlers are entered in 32-bit mode. */ | |
463 | env->hflags &= ~(MIPS_HFLAG_M16); | |
464 | break; | |
465 | case EXCP_EXT_INTERRUPT: | |
466 | cause = 0; | |
467 | if (env->CP0_Cause & (1 << CP0Ca_IV)) | |
468 | offset = 0x200; | |
469 | goto set_EPC; | |
470 | case EXCP_LTLBL: | |
471 | cause = 1; | |
472 | goto set_EPC; | |
473 | case EXCP_TLBL: | |
474 | cause = 2; | |
475 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { | |
476 | #if defined(TARGET_MIPS64) | |
477 | int R = env->CP0_BadVAddr >> 62; | |
478 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
479 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
480 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
481 | ||
482 | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) | |
483 | offset = 0x080; | |
484 | else | |
485 | #endif | |
486 | offset = 0x000; | |
487 | } | |
488 | goto set_EPC; | |
489 | case EXCP_TLBS: | |
490 | cause = 3; | |
491 | if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) { | |
492 | #if defined(TARGET_MIPS64) | |
493 | int R = env->CP0_BadVAddr >> 62; | |
494 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
495 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
496 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
497 | ||
498 | if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) | |
499 | offset = 0x080; | |
500 | else | |
501 | #endif | |
502 | offset = 0x000; | |
503 | } | |
504 | goto set_EPC; | |
505 | case EXCP_AdEL: | |
506 | cause = 4; | |
507 | goto set_EPC; | |
508 | case EXCP_AdES: | |
509 | cause = 5; | |
510 | goto set_EPC; | |
511 | case EXCP_IBE: | |
512 | cause = 6; | |
513 | goto set_EPC; | |
514 | case EXCP_DBE: | |
515 | cause = 7; | |
516 | goto set_EPC; | |
517 | case EXCP_SYSCALL: | |
518 | cause = 8; | |
519 | goto set_EPC; | |
520 | case EXCP_BREAK: | |
521 | cause = 9; | |
522 | goto set_EPC; | |
523 | case EXCP_RI: | |
524 | cause = 10; | |
525 | goto set_EPC; | |
526 | case EXCP_CpU: | |
527 | cause = 11; | |
528 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | | |
529 | (env->error_code << CP0Ca_CE); | |
530 | goto set_EPC; | |
531 | case EXCP_OVERFLOW: | |
532 | cause = 12; | |
533 | goto set_EPC; | |
534 | case EXCP_TRAP: | |
535 | cause = 13; | |
536 | goto set_EPC; | |
537 | case EXCP_FPE: | |
538 | cause = 15; | |
539 | goto set_EPC; | |
540 | case EXCP_C2E: | |
541 | cause = 18; | |
542 | goto set_EPC; | |
543 | case EXCP_MDMX: | |
544 | cause = 22; | |
545 | goto set_EPC; | |
546 | case EXCP_DWATCH: | |
547 | cause = 23; | |
548 | /* XXX: TODO: manage defered watch exceptions */ | |
549 | goto set_EPC; | |
550 | case EXCP_MCHECK: | |
551 | cause = 24; | |
552 | goto set_EPC; | |
553 | case EXCP_THREAD: | |
554 | cause = 25; | |
555 | goto set_EPC; | |
556 | case EXCP_CACHE: | |
557 | cause = 30; | |
558 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
559 | offset = 0x100; | |
560 | } else { | |
561 | offset = 0x20000100; | |
562 | } | |
563 | set_EPC: | |
564 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { | |
565 | env->CP0_EPC = exception_resume_pc(env); | |
566 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
567 | env->CP0_Cause |= (1 << CP0Ca_BD); | |
568 | } else { | |
569 | env->CP0_Cause &= ~(1 << CP0Ca_BD); | |
570 | } | |
571 | env->CP0_Status |= (1 << CP0St_EXL); | |
572 | env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; | |
573 | env->hflags &= ~(MIPS_HFLAG_KSU); | |
574 | } | |
575 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
576 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
577 | env->active_tc.PC = (int32_t)0xBFC00200; | |
578 | } else { | |
579 | env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff); | |
580 | } | |
581 | env->active_tc.PC += offset; | |
582 | /* Exception handlers are entered in 32-bit mode. */ | |
583 | env->hflags &= ~(MIPS_HFLAG_M16); | |
584 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); | |
585 | break; | |
586 | default: | |
587 | qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index); | |
588 | printf("Invalid MIPS exception %d. Exiting\n", env->exception_index); | |
589 | exit(1); | |
590 | } | |
591 | if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) { | |
592 | qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" | |
593 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", | |
594 | __func__, env->active_tc.PC, env->CP0_EPC, cause, | |
595 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, | |
596 | env->CP0_DEPC); | |
597 | } | |
598 | #endif | |
599 | env->exception_index = EXCP_NONE; | |
600 | } | |
601 | ||
602 | void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra) | |
603 | { | |
604 | r4k_tlb_t *tlb; | |
605 | target_ulong addr; | |
606 | target_ulong end; | |
607 | uint8_t ASID = env->CP0_EntryHi & 0xFF; | |
608 | target_ulong mask; | |
609 | ||
610 | tlb = &env->tlb->mmu.r4k.tlb[idx]; | |
611 | /* The qemu TLB is flushed when the ASID changes, so no need to | |
612 | flush these entries again. */ | |
613 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
614 | return; | |
615 | } | |
616 | ||
617 | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { | |
618 | /* For tlbwr, we can shadow the discarded entry into | |
619 | a new (fake) TLB entry, as long as the guest can not | |
620 | tell that it's there. */ | |
621 | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; | |
622 | env->tlb->tlb_in_use++; | |
623 | return; | |
624 | } | |
625 | ||
626 | /* 1k pages are not supported. */ | |
627 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
628 | if (tlb->V0) { | |
629 | addr = tlb->VPN & ~mask; | |
630 | #if defined(TARGET_MIPS64) | |
631 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { | |
632 | addr |= 0x3FFFFF0000000000ULL; | |
633 | } | |
634 | #endif | |
635 | end = addr | (mask >> 1); | |
636 | while (addr < end) { | |
637 | tlb_flush_page (env, addr); | |
638 | addr += TARGET_PAGE_SIZE; | |
639 | } | |
640 | } | |
641 | if (tlb->V1) { | |
642 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); | |
643 | #if defined(TARGET_MIPS64) | |
644 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { | |
645 | addr |= 0x3FFFFF0000000000ULL; | |
646 | } | |
647 | #endif | |
648 | end = addr | mask; | |
649 | while (addr - 1 < end) { | |
650 | tlb_flush_page (env, addr); | |
651 | addr += TARGET_PAGE_SIZE; | |
652 | } | |
653 | } | |
654 | } |