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1/*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include "cpu.h"
22#include "disas.h"
23#include "tcg-op.h"
24#include "host-utils.h"
25
26#include "helper.h"
27#define GEN_HELPER 1
28#include "helper.h"
29
30#define CPU_SINGLE_STEP 0x1
31#define CPU_BRANCH_STEP 0x2
32#define GDBSTUB_SINGLE_STEP 0x4
33
34/* Include definitions for instructions classes and implementations flags */
35//#define PPC_DEBUG_DISAS
36//#define DO_PPC_STATISTICS
37
38#ifdef PPC_DEBUG_DISAS
39# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40#else
41# define LOG_DISAS(...) do { } while (0)
42#endif
43/*****************************************************************************/
44/* Code translation helpers */
45
46/* global register indexes */
47static TCGv_ptr cpu_env;
48static char cpu_reg_names[10*3 + 22*4 /* GPR */
49#if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51#endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55static TCGv cpu_gpr[32];
56#if !defined(TARGET_PPC64)
57static TCGv cpu_gprh[32];
58#endif
59static TCGv_i64 cpu_fpr[32];
60static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61static TCGv_i32 cpu_crf[8];
62static TCGv cpu_nip;
63static TCGv cpu_msr;
64static TCGv cpu_ctr;
65static TCGv cpu_lr;
66#if defined(TARGET_PPC64)
67static TCGv cpu_cfar;
68#endif
69static TCGv cpu_xer;
70static TCGv cpu_reserve;
71static TCGv cpu_fpscr;
72static TCGv_i32 cpu_access_type;
73
74#include "gen-icount.h"
75
76void ppc_translate_init(void)
77{
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105#if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111#endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120#ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123#else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126#endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131#ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134#else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137#endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154#if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157#endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161
162 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, reserve_addr),
164 "reserve_addr");
165
166 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, fpscr), "fpscr");
168
169 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
170 offsetof(CPUPPCState, access_type), "access_type");
171
172 /* register helpers */
173#define GEN_HELPER 2
174#include "helper.h"
175
176 done_init = 1;
177}
178
179/* internal defines */
180typedef struct DisasContext {
181 struct TranslationBlock *tb;
182 target_ulong nip;
183 uint32_t opcode;
184 uint32_t exception;
185 /* Routine used to access memory */
186 int mem_idx;
187 int access_type;
188 /* Translation flags */
189 int le_mode;
190#if defined(TARGET_PPC64)
191 int sf_mode;
192 int has_cfar;
193#endif
194 int fpu_enabled;
195 int altivec_enabled;
196 int spe_enabled;
197 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
198 int singlestep_enabled;
199} DisasContext;
200
201struct opc_handler_t {
202 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
203 uint32_t inval1;
204 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
205 uint32_t inval2;
206 /* instruction type */
207 uint64_t type;
208 /* extended instruction type */
209 uint64_t type2;
210 /* handler */
211 void (*handler)(DisasContext *ctx);
212#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
213 const char *oname;
214#endif
215#if defined(DO_PPC_STATISTICS)
216 uint64_t count;
217#endif
218};
219
220static inline void gen_reset_fpstatus(void)
221{
222 gen_helper_reset_fpstatus(cpu_env);
223}
224
225static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
226{
227 TCGv_i32 t0 = tcg_temp_new_i32();
228
229 if (set_fprf != 0) {
230 /* This case might be optimized later */
231 tcg_gen_movi_i32(t0, 1);
232 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
233 if (unlikely(set_rc)) {
234 tcg_gen_mov_i32(cpu_crf[1], t0);
235 }
236 gen_helper_float_check_status(cpu_env);
237 } else if (unlikely(set_rc)) {
238 /* We always need to compute fpcc */
239 tcg_gen_movi_i32(t0, 0);
240 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
241 tcg_gen_mov_i32(cpu_crf[1], t0);
242 }
243
244 tcg_temp_free_i32(t0);
245}
246
247static inline void gen_set_access_type(DisasContext *ctx, int access_type)
248{
249 if (ctx->access_type != access_type) {
250 tcg_gen_movi_i32(cpu_access_type, access_type);
251 ctx->access_type = access_type;
252 }
253}
254
255static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
256{
257#if defined(TARGET_PPC64)
258 if (ctx->sf_mode)
259 tcg_gen_movi_tl(cpu_nip, nip);
260 else
261#endif
262 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
263}
264
265static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
266{
267 TCGv_i32 t0, t1;
268 if (ctx->exception == POWERPC_EXCP_NONE) {
269 gen_update_nip(ctx, ctx->nip);
270 }
271 t0 = tcg_const_i32(excp);
272 t1 = tcg_const_i32(error);
273 gen_helper_raise_exception_err(cpu_env, t0, t1);
274 tcg_temp_free_i32(t0);
275 tcg_temp_free_i32(t1);
276 ctx->exception = (excp);
277}
278
279static inline void gen_exception(DisasContext *ctx, uint32_t excp)
280{
281 TCGv_i32 t0;
282 if (ctx->exception == POWERPC_EXCP_NONE) {
283 gen_update_nip(ctx, ctx->nip);
284 }
285 t0 = tcg_const_i32(excp);
286 gen_helper_raise_exception(cpu_env, t0);
287 tcg_temp_free_i32(t0);
288 ctx->exception = (excp);
289}
290
291static inline void gen_debug_exception(DisasContext *ctx)
292{
293 TCGv_i32 t0;
294
295 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
296 (ctx->exception != POWERPC_EXCP_SYNC)) {
297 gen_update_nip(ctx, ctx->nip);
298 }
299 t0 = tcg_const_i32(EXCP_DEBUG);
300 gen_helper_raise_exception(cpu_env, t0);
301 tcg_temp_free_i32(t0);
302}
303
304static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
305{
306 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
307}
308
309/* Stop translation */
310static inline void gen_stop_exception(DisasContext *ctx)
311{
312 gen_update_nip(ctx, ctx->nip);
313 ctx->exception = POWERPC_EXCP_STOP;
314}
315
316/* No need to update nip here, as execution flow will change */
317static inline void gen_sync_exception(DisasContext *ctx)
318{
319 ctx->exception = POWERPC_EXCP_SYNC;
320}
321
322#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
323GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
324
325#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
326GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
327
328#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
329GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
332GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
333
334typedef struct opcode_t {
335 unsigned char opc1, opc2, opc3;
336#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
337 unsigned char pad[5];
338#else
339 unsigned char pad[1];
340#endif
341 opc_handler_t handler;
342 const char *oname;
343} opcode_t;
344
345/*****************************************************************************/
346/*** Instruction decoding ***/
347#define EXTRACT_HELPER(name, shift, nb) \
348static inline uint32_t name(uint32_t opcode) \
349{ \
350 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
351}
352
353#define EXTRACT_SHELPER(name, shift, nb) \
354static inline int32_t name(uint32_t opcode) \
355{ \
356 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
357}
358
359/* Opcode part 1 */
360EXTRACT_HELPER(opc1, 26, 6);
361/* Opcode part 2 */
362EXTRACT_HELPER(opc2, 1, 5);
363/* Opcode part 3 */
364EXTRACT_HELPER(opc3, 6, 5);
365/* Update Cr0 flags */
366EXTRACT_HELPER(Rc, 0, 1);
367/* Destination */
368EXTRACT_HELPER(rD, 21, 5);
369/* Source */
370EXTRACT_HELPER(rS, 21, 5);
371/* First operand */
372EXTRACT_HELPER(rA, 16, 5);
373/* Second operand */
374EXTRACT_HELPER(rB, 11, 5);
375/* Third operand */
376EXTRACT_HELPER(rC, 6, 5);
377/*** Get CRn ***/
378EXTRACT_HELPER(crfD, 23, 3);
379EXTRACT_HELPER(crfS, 18, 3);
380EXTRACT_HELPER(crbD, 21, 5);
381EXTRACT_HELPER(crbA, 16, 5);
382EXTRACT_HELPER(crbB, 11, 5);
383/* SPR / TBL */
384EXTRACT_HELPER(_SPR, 11, 10);
385static inline uint32_t SPR(uint32_t opcode)
386{
387 uint32_t sprn = _SPR(opcode);
388
389 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
390}
391/*** Get constants ***/
392EXTRACT_HELPER(IMM, 12, 8);
393/* 16 bits signed immediate value */
394EXTRACT_SHELPER(SIMM, 0, 16);
395/* 16 bits unsigned immediate value */
396EXTRACT_HELPER(UIMM, 0, 16);
397/* 5 bits signed immediate value */
398EXTRACT_HELPER(SIMM5, 16, 5);
399/* 5 bits signed immediate value */
400EXTRACT_HELPER(UIMM5, 16, 5);
401/* Bit count */
402EXTRACT_HELPER(NB, 11, 5);
403/* Shift count */
404EXTRACT_HELPER(SH, 11, 5);
405/* Vector shift count */
406EXTRACT_HELPER(VSH, 6, 4);
407/* Mask start */
408EXTRACT_HELPER(MB, 6, 5);
409/* Mask end */
410EXTRACT_HELPER(ME, 1, 5);
411/* Trap operand */
412EXTRACT_HELPER(TO, 21, 5);
413
414EXTRACT_HELPER(CRM, 12, 8);
415EXTRACT_HELPER(FM, 17, 8);
416EXTRACT_HELPER(SR, 16, 4);
417EXTRACT_HELPER(FPIMM, 12, 4);
418
419/*** Jump target decoding ***/
420/* Displacement */
421EXTRACT_SHELPER(d, 0, 16);
422/* Immediate address */
423static inline target_ulong LI(uint32_t opcode)
424{
425 return (opcode >> 0) & 0x03FFFFFC;
426}
427
428static inline uint32_t BD(uint32_t opcode)
429{
430 return (opcode >> 0) & 0xFFFC;
431}
432
433EXTRACT_HELPER(BO, 21, 5);
434EXTRACT_HELPER(BI, 16, 5);
435/* Absolute/relative address */
436EXTRACT_HELPER(AA, 1, 1);
437/* Link */
438EXTRACT_HELPER(LK, 0, 1);
439
440/* Create a mask between <start> and <end> bits */
441static inline target_ulong MASK(uint32_t start, uint32_t end)
442{
443 target_ulong ret;
444
445#if defined(TARGET_PPC64)
446 if (likely(start == 0)) {
447 ret = UINT64_MAX << (63 - end);
448 } else if (likely(end == 63)) {
449 ret = UINT64_MAX >> start;
450 }
451#else
452 if (likely(start == 0)) {
453 ret = UINT32_MAX << (31 - end);
454 } else if (likely(end == 31)) {
455 ret = UINT32_MAX >> start;
456 }
457#endif
458 else {
459 ret = (((target_ulong)(-1ULL)) >> (start)) ^
460 (((target_ulong)(-1ULL) >> (end)) >> 1);
461 if (unlikely(start > end))
462 return ~ret;
463 }
464
465 return ret;
466}
467
468/*****************************************************************************/
469/* PowerPC instructions table */
470
471#if defined(DO_PPC_STATISTICS)
472#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
473{ \
474 .opc1 = op1, \
475 .opc2 = op2, \
476 .opc3 = op3, \
477 .pad = { 0, }, \
478 .handler = { \
479 .inval1 = invl, \
480 .type = _typ, \
481 .type2 = _typ2, \
482 .handler = &gen_##name, \
483 .oname = stringify(name), \
484 }, \
485 .oname = stringify(name), \
486}
487#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
488{ \
489 .opc1 = op1, \
490 .opc2 = op2, \
491 .opc3 = op3, \
492 .pad = { 0, }, \
493 .handler = { \
494 .inval1 = invl1, \
495 .inval2 = invl2, \
496 .type = _typ, \
497 .type2 = _typ2, \
498 .handler = &gen_##name, \
499 .oname = stringify(name), \
500 }, \
501 .oname = stringify(name), \
502}
503#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
504{ \
505 .opc1 = op1, \
506 .opc2 = op2, \
507 .opc3 = op3, \
508 .pad = { 0, }, \
509 .handler = { \
510 .inval1 = invl, \
511 .type = _typ, \
512 .type2 = _typ2, \
513 .handler = &gen_##name, \
514 .oname = onam, \
515 }, \
516 .oname = onam, \
517}
518#else
519#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
520{ \
521 .opc1 = op1, \
522 .opc2 = op2, \
523 .opc3 = op3, \
524 .pad = { 0, }, \
525 .handler = { \
526 .inval1 = invl, \
527 .type = _typ, \
528 .type2 = _typ2, \
529 .handler = &gen_##name, \
530 }, \
531 .oname = stringify(name), \
532}
533#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
534{ \
535 .opc1 = op1, \
536 .opc2 = op2, \
537 .opc3 = op3, \
538 .pad = { 0, }, \
539 .handler = { \
540 .inval1 = invl1, \
541 .inval2 = invl2, \
542 .type = _typ, \
543 .type2 = _typ2, \
544 .handler = &gen_##name, \
545 }, \
546 .oname = stringify(name), \
547}
548#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
549{ \
550 .opc1 = op1, \
551 .opc2 = op2, \
552 .opc3 = op3, \
553 .pad = { 0, }, \
554 .handler = { \
555 .inval1 = invl, \
556 .type = _typ, \
557 .type2 = _typ2, \
558 .handler = &gen_##name, \
559 }, \
560 .oname = onam, \
561}
562#endif
563
564/* SPR load/store helpers */
565static inline void gen_load_spr(TCGv t, int reg)
566{
567 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
568}
569
570static inline void gen_store_spr(int reg, TCGv t)
571{
572 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
573}
574
575/* Invalid instruction */
576static void gen_invalid(DisasContext *ctx)
577{
578 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
579}
580
581static opc_handler_t invalid_handler = {
582 .inval1 = 0xFFFFFFFF,
583 .inval2 = 0xFFFFFFFF,
584 .type = PPC_NONE,
585 .type2 = PPC_NONE,
586 .handler = gen_invalid,
587};
588
589/*** Integer comparison ***/
590
591static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
592{
593 int l1, l2, l3;
594
595 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
596 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
597 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
598
599 l1 = gen_new_label();
600 l2 = gen_new_label();
601 l3 = gen_new_label();
602 if (s) {
603 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
604 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
605 } else {
606 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
607 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
608 }
609 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
610 tcg_gen_br(l3);
611 gen_set_label(l1);
612 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
613 tcg_gen_br(l3);
614 gen_set_label(l2);
615 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
616 gen_set_label(l3);
617}
618
619static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
620{
621 TCGv t0 = tcg_const_local_tl(arg1);
622 gen_op_cmp(arg0, t0, s, crf);
623 tcg_temp_free(t0);
624}
625
626#if defined(TARGET_PPC64)
627static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
628{
629 TCGv t0, t1;
630 t0 = tcg_temp_local_new();
631 t1 = tcg_temp_local_new();
632 if (s) {
633 tcg_gen_ext32s_tl(t0, arg0);
634 tcg_gen_ext32s_tl(t1, arg1);
635 } else {
636 tcg_gen_ext32u_tl(t0, arg0);
637 tcg_gen_ext32u_tl(t1, arg1);
638 }
639 gen_op_cmp(t0, t1, s, crf);
640 tcg_temp_free(t1);
641 tcg_temp_free(t0);
642}
643
644static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
645{
646 TCGv t0 = tcg_const_local_tl(arg1);
647 gen_op_cmp32(arg0, t0, s, crf);
648 tcg_temp_free(t0);
649}
650#endif
651
652static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
653{
654#if defined(TARGET_PPC64)
655 if (!(ctx->sf_mode))
656 gen_op_cmpi32(reg, 0, 1, 0);
657 else
658#endif
659 gen_op_cmpi(reg, 0, 1, 0);
660}
661
662/* cmp */
663static void gen_cmp(DisasContext *ctx)
664{
665#if defined(TARGET_PPC64)
666 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
667 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
668 1, crfD(ctx->opcode));
669 else
670#endif
671 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673}
674
675/* cmpi */
676static void gen_cmpi(DisasContext *ctx)
677{
678#if defined(TARGET_PPC64)
679 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
680 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
681 1, crfD(ctx->opcode));
682 else
683#endif
684 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686}
687
688/* cmpl */
689static void gen_cmpl(DisasContext *ctx)
690{
691#if defined(TARGET_PPC64)
692 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
693 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
694 0, crfD(ctx->opcode));
695 else
696#endif
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699}
700
701/* cmpli */
702static void gen_cmpli(DisasContext *ctx)
703{
704#if defined(TARGET_PPC64)
705 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
706 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
707 0, crfD(ctx->opcode));
708 else
709#endif
710 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712}
713
714/* isel (PowerPC 2.03 specification) */
715static void gen_isel(DisasContext *ctx)
716{
717 int l1, l2;
718 uint32_t bi = rC(ctx->opcode);
719 uint32_t mask;
720 TCGv_i32 t0;
721
722 l1 = gen_new_label();
723 l2 = gen_new_label();
724
725 mask = 1 << (3 - (bi & 0x03));
726 t0 = tcg_temp_new_i32();
727 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
728 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
729 if (rA(ctx->opcode) == 0)
730 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
731 else
732 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
733 tcg_gen_br(l2);
734 gen_set_label(l1);
735 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
736 gen_set_label(l2);
737 tcg_temp_free_i32(t0);
738}
739
740/*** Integer arithmetic ***/
741
742static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
743 TCGv arg1, TCGv arg2, int sub)
744{
745 int l1;
746 TCGv t0;
747
748 l1 = gen_new_label();
749 /* Start with XER OV disabled, the most likely case */
750 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
751 t0 = tcg_temp_local_new();
752 tcg_gen_xor_tl(t0, arg0, arg1);
753#if defined(TARGET_PPC64)
754 if (!ctx->sf_mode)
755 tcg_gen_ext32s_tl(t0, t0);
756#endif
757 if (sub)
758 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
759 else
760 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
761 tcg_gen_xor_tl(t0, arg1, arg2);
762#if defined(TARGET_PPC64)
763 if (!ctx->sf_mode)
764 tcg_gen_ext32s_tl(t0, t0);
765#endif
766 if (sub)
767 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
768 else
769 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
770 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
771 gen_set_label(l1);
772 tcg_temp_free(t0);
773}
774
775static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
776 TCGv arg2, int sub)
777{
778 int l1 = gen_new_label();
779
780#if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode)) {
782 TCGv t0, t1;
783 t0 = tcg_temp_new();
784 t1 = tcg_temp_new();
785
786 tcg_gen_ext32u_tl(t0, arg1);
787 tcg_gen_ext32u_tl(t1, arg2);
788 if (sub) {
789 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
790 } else {
791 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
792 }
793 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
794 gen_set_label(l1);
795 tcg_temp_free(t0);
796 tcg_temp_free(t1);
797 } else
798#endif
799 {
800 if (sub) {
801 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
802 } else {
803 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
804 }
805 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
806 gen_set_label(l1);
807 }
808}
809
810/* Common add function */
811static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
812 TCGv arg2, int add_ca, int compute_ca,
813 int compute_ov)
814{
815 TCGv t0, t1;
816
817 if ((!compute_ca && !compute_ov) ||
818 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
819 t0 = ret;
820 } else {
821 t0 = tcg_temp_local_new();
822 }
823
824 if (add_ca) {
825 t1 = tcg_temp_local_new();
826 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
827 tcg_gen_shri_tl(t1, t1, XER_CA);
828 } else {
829 TCGV_UNUSED(t1);
830 }
831
832 if (compute_ca && compute_ov) {
833 /* Start with XER CA and OV disabled, the most likely case */
834 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
835 } else if (compute_ca) {
836 /* Start with XER CA disabled, the most likely case */
837 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
838 } else if (compute_ov) {
839 /* Start with XER OV disabled, the most likely case */
840 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
841 }
842
843 tcg_gen_add_tl(t0, arg1, arg2);
844
845 if (compute_ca) {
846 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
847 }
848 if (add_ca) {
849 tcg_gen_add_tl(t0, t0, t1);
850 gen_op_arith_compute_ca(ctx, t0, t1, 0);
851 tcg_temp_free(t1);
852 }
853 if (compute_ov) {
854 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
855 }
856
857 if (unlikely(Rc(ctx->opcode) != 0))
858 gen_set_Rc0(ctx, t0);
859
860 if (!TCGV_EQUAL(t0, ret)) {
861 tcg_gen_mov_tl(ret, t0);
862 tcg_temp_free(t0);
863 }
864}
865/* Add functions with two operands */
866#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
867static void glue(gen_, name)(DisasContext *ctx) \
868{ \
869 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
870 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
871 add_ca, compute_ca, compute_ov); \
872}
873/* Add functions with one operand and one immediate */
874#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
875 add_ca, compute_ca, compute_ov) \
876static void glue(gen_, name)(DisasContext *ctx) \
877{ \
878 TCGv t0 = tcg_const_local_tl(const_val); \
879 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
880 cpu_gpr[rA(ctx->opcode)], t0, \
881 add_ca, compute_ca, compute_ov); \
882 tcg_temp_free(t0); \
883}
884
885/* add add. addo addo. */
886GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
887GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
888/* addc addc. addco addco. */
889GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
890GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
891/* adde adde. addeo addeo. */
892GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
893GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
894/* addme addme. addmeo addmeo. */
895GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
896GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
897/* addze addze. addzeo addzeo.*/
898GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
899GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
900/* addi */
901static void gen_addi(DisasContext *ctx)
902{
903 target_long simm = SIMM(ctx->opcode);
904
905 if (rA(ctx->opcode) == 0) {
906 /* li case */
907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
908 } else {
909 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
910 }
911}
912/* addic addic.*/
913static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
914 int compute_Rc0)
915{
916 target_long simm = SIMM(ctx->opcode);
917
918 /* Start with XER CA and OV disabled, the most likely case */
919 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
920
921 if (likely(simm != 0)) {
922 TCGv t0 = tcg_temp_local_new();
923 tcg_gen_addi_tl(t0, arg1, simm);
924 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
925 tcg_gen_mov_tl(ret, t0);
926 tcg_temp_free(t0);
927 } else {
928 tcg_gen_mov_tl(ret, arg1);
929 }
930 if (compute_Rc0) {
931 gen_set_Rc0(ctx, ret);
932 }
933}
934
935static void gen_addic(DisasContext *ctx)
936{
937 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
938}
939
940static void gen_addic_(DisasContext *ctx)
941{
942 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
943}
944
945/* addis */
946static void gen_addis(DisasContext *ctx)
947{
948 target_long simm = SIMM(ctx->opcode);
949
950 if (rA(ctx->opcode) == 0) {
951 /* lis case */
952 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
953 } else {
954 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
955 }
956}
957
958static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
959 TCGv arg2, int sign, int compute_ov)
960{
961 int l1 = gen_new_label();
962 int l2 = gen_new_label();
963 TCGv_i32 t0 = tcg_temp_local_new_i32();
964 TCGv_i32 t1 = tcg_temp_local_new_i32();
965
966 tcg_gen_trunc_tl_i32(t0, arg1);
967 tcg_gen_trunc_tl_i32(t1, arg2);
968 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
969 if (sign) {
970 int l3 = gen_new_label();
971 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
972 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
973 gen_set_label(l3);
974 tcg_gen_div_i32(t0, t0, t1);
975 } else {
976 tcg_gen_divu_i32(t0, t0, t1);
977 }
978 if (compute_ov) {
979 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
980 }
981 tcg_gen_br(l2);
982 gen_set_label(l1);
983 if (sign) {
984 tcg_gen_sari_i32(t0, t0, 31);
985 } else {
986 tcg_gen_movi_i32(t0, 0);
987 }
988 if (compute_ov) {
989 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
990 }
991 gen_set_label(l2);
992 tcg_gen_extu_i32_tl(ret, t0);
993 tcg_temp_free_i32(t0);
994 tcg_temp_free_i32(t1);
995 if (unlikely(Rc(ctx->opcode) != 0))
996 gen_set_Rc0(ctx, ret);
997}
998/* Div functions */
999#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1000static void glue(gen_, name)(DisasContext *ctx) \
1001{ \
1002 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1003 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1004 sign, compute_ov); \
1005}
1006/* divwu divwu. divwuo divwuo. */
1007GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1008GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1009/* divw divw. divwo divwo. */
1010GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1011GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1012#if defined(TARGET_PPC64)
1013static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1014 TCGv arg2, int sign, int compute_ov)
1015{
1016 int l1 = gen_new_label();
1017 int l2 = gen_new_label();
1018
1019 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1020 if (sign) {
1021 int l3 = gen_new_label();
1022 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1023 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1024 gen_set_label(l3);
1025 tcg_gen_div_i64(ret, arg1, arg2);
1026 } else {
1027 tcg_gen_divu_i64(ret, arg1, arg2);
1028 }
1029 if (compute_ov) {
1030 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1031 }
1032 tcg_gen_br(l2);
1033 gen_set_label(l1);
1034 if (sign) {
1035 tcg_gen_sari_i64(ret, arg1, 63);
1036 } else {
1037 tcg_gen_movi_i64(ret, 0);
1038 }
1039 if (compute_ov) {
1040 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1041 }
1042 gen_set_label(l2);
1043 if (unlikely(Rc(ctx->opcode) != 0))
1044 gen_set_Rc0(ctx, ret);
1045}
1046#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1047static void glue(gen_, name)(DisasContext *ctx) \
1048{ \
1049 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1050 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1051 sign, compute_ov); \
1052}
1053/* divwu divwu. divwuo divwuo. */
1054GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1055GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1056/* divw divw. divwo divwo. */
1057GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1058GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1059#endif
1060
1061/* mulhw mulhw. */
1062static void gen_mulhw(DisasContext *ctx)
1063{
1064 TCGv_i64 t0, t1;
1065
1066 t0 = tcg_temp_new_i64();
1067 t1 = tcg_temp_new_i64();
1068#if defined(TARGET_PPC64)
1069 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1070 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1071 tcg_gen_mul_i64(t0, t0, t1);
1072 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1073#else
1074 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1075 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1076 tcg_gen_mul_i64(t0, t0, t1);
1077 tcg_gen_shri_i64(t0, t0, 32);
1078 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1079#endif
1080 tcg_temp_free_i64(t0);
1081 tcg_temp_free_i64(t1);
1082 if (unlikely(Rc(ctx->opcode) != 0))
1083 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1084}
1085
1086/* mulhwu mulhwu. */
1087static void gen_mulhwu(DisasContext *ctx)
1088{
1089 TCGv_i64 t0, t1;
1090
1091 t0 = tcg_temp_new_i64();
1092 t1 = tcg_temp_new_i64();
1093#if defined(TARGET_PPC64)
1094 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1095 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1096 tcg_gen_mul_i64(t0, t0, t1);
1097 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1098#else
1099 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1100 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1101 tcg_gen_mul_i64(t0, t0, t1);
1102 tcg_gen_shri_i64(t0, t0, 32);
1103 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1104#endif
1105 tcg_temp_free_i64(t0);
1106 tcg_temp_free_i64(t1);
1107 if (unlikely(Rc(ctx->opcode) != 0))
1108 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1109}
1110
1111/* mullw mullw. */
1112static void gen_mullw(DisasContext *ctx)
1113{
1114 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1115 cpu_gpr[rB(ctx->opcode)]);
1116 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1117 if (unlikely(Rc(ctx->opcode) != 0))
1118 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1119}
1120
1121/* mullwo mullwo. */
1122static void gen_mullwo(DisasContext *ctx)
1123{
1124 int l1;
1125 TCGv_i64 t0, t1;
1126
1127 t0 = tcg_temp_new_i64();
1128 t1 = tcg_temp_new_i64();
1129 l1 = gen_new_label();
1130 /* Start with XER OV disabled, the most likely case */
1131 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1132#if defined(TARGET_PPC64)
1133 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1134 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1135#else
1136 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1137 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1138#endif
1139 tcg_gen_mul_i64(t0, t0, t1);
1140#if defined(TARGET_PPC64)
1141 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1142 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1143#else
1144 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1145 tcg_gen_ext32s_i64(t1, t0);
1146 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1147#endif
1148 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1149 gen_set_label(l1);
1150 tcg_temp_free_i64(t0);
1151 tcg_temp_free_i64(t1);
1152 if (unlikely(Rc(ctx->opcode) != 0))
1153 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1154}
1155
1156/* mulli */
1157static void gen_mulli(DisasContext *ctx)
1158{
1159 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1160 SIMM(ctx->opcode));
1161}
1162#if defined(TARGET_PPC64)
1163#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1164static void glue(gen_, name)(DisasContext *ctx) \
1165{ \
1166 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1168 if (unlikely(Rc(ctx->opcode) != 0)) \
1169 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1170}
1171/* mulhd mulhd. */
1172GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1173/* mulhdu mulhdu. */
1174GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1175
1176/* mulld mulld. */
1177static void gen_mulld(DisasContext *ctx)
1178{
1179 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1180 cpu_gpr[rB(ctx->opcode)]);
1181 if (unlikely(Rc(ctx->opcode) != 0))
1182 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1183}
1184
1185/* mulldo mulldo. */
1186static void gen_mulldo(DisasContext *ctx)
1187{
1188 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1189 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1190 if (unlikely(Rc(ctx->opcode) != 0)) {
1191 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1192 }
1193}
1194#endif
1195
1196/* neg neg. nego nego. */
1197static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
1198 int ov_check)
1199{
1200 int l1 = gen_new_label();
1201 int l2 = gen_new_label();
1202 TCGv t0 = tcg_temp_local_new();
1203#if defined(TARGET_PPC64)
1204 if (ctx->sf_mode) {
1205 tcg_gen_mov_tl(t0, arg1);
1206 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1207 } else
1208#endif
1209 {
1210 tcg_gen_ext32s_tl(t0, arg1);
1211 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1212 }
1213 tcg_gen_neg_tl(ret, arg1);
1214 if (ov_check) {
1215 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1216 }
1217 tcg_gen_br(l2);
1218 gen_set_label(l1);
1219 tcg_gen_mov_tl(ret, t0);
1220 if (ov_check) {
1221 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1222 }
1223 gen_set_label(l2);
1224 tcg_temp_free(t0);
1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, ret);
1227}
1228
1229static void gen_neg(DisasContext *ctx)
1230{
1231 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1232}
1233
1234static void gen_nego(DisasContext *ctx)
1235{
1236 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1237}
1238
1239/* Common subf function */
1240static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1241 TCGv arg2, int add_ca, int compute_ca,
1242 int compute_ov)
1243{
1244 TCGv t0, t1;
1245
1246 if ((!compute_ca && !compute_ov) ||
1247 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
1248 t0 = ret;
1249 } else {
1250 t0 = tcg_temp_local_new();
1251 }
1252
1253 if (add_ca) {
1254 t1 = tcg_temp_local_new();
1255 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1256 tcg_gen_shri_tl(t1, t1, XER_CA);
1257 } else {
1258 TCGV_UNUSED(t1);
1259 }
1260
1261 if (compute_ca && compute_ov) {
1262 /* Start with XER CA and OV disabled, the most likely case */
1263 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1264 } else if (compute_ca) {
1265 /* Start with XER CA disabled, the most likely case */
1266 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1267 } else if (compute_ov) {
1268 /* Start with XER OV disabled, the most likely case */
1269 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1270 }
1271
1272 if (add_ca) {
1273 tcg_gen_not_tl(t0, arg1);
1274 tcg_gen_add_tl(t0, t0, arg2);
1275 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1276 tcg_gen_add_tl(t0, t0, t1);
1277 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1278 tcg_temp_free(t1);
1279 } else {
1280 tcg_gen_sub_tl(t0, arg2, arg1);
1281 if (compute_ca) {
1282 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1283 }
1284 }
1285 if (compute_ov) {
1286 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1287 }
1288
1289 if (unlikely(Rc(ctx->opcode) != 0))
1290 gen_set_Rc0(ctx, t0);
1291
1292 if (!TCGV_EQUAL(t0, ret)) {
1293 tcg_gen_mov_tl(ret, t0);
1294 tcg_temp_free(t0);
1295 }
1296}
1297/* Sub functions with Two operands functions */
1298#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1299static void glue(gen_, name)(DisasContext *ctx) \
1300{ \
1301 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1302 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1303 add_ca, compute_ca, compute_ov); \
1304}
1305/* Sub functions with one operand and one immediate */
1306#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1307 add_ca, compute_ca, compute_ov) \
1308static void glue(gen_, name)(DisasContext *ctx) \
1309{ \
1310 TCGv t0 = tcg_const_local_tl(const_val); \
1311 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1312 cpu_gpr[rA(ctx->opcode)], t0, \
1313 add_ca, compute_ca, compute_ov); \
1314 tcg_temp_free(t0); \
1315}
1316/* subf subf. subfo subfo. */
1317GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1318GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1319/* subfc subfc. subfco subfco. */
1320GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1321GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1322/* subfe subfe. subfeo subfo. */
1323GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1324GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1325/* subfme subfme. subfmeo subfmeo. */
1326GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1327GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1328/* subfze subfze. subfzeo subfzeo.*/
1329GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1330GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1331
1332/* subfic */
1333static void gen_subfic(DisasContext *ctx)
1334{
1335 /* Start with XER CA and OV disabled, the most likely case */
1336 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1337 TCGv t0 = tcg_temp_local_new();
1338 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1339 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1340 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1341 tcg_temp_free(t1);
1342 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1343 tcg_temp_free(t0);
1344}
1345
1346/*** Integer logical ***/
1347#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1348static void glue(gen_, name)(DisasContext *ctx) \
1349{ \
1350 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1351 cpu_gpr[rB(ctx->opcode)]); \
1352 if (unlikely(Rc(ctx->opcode) != 0)) \
1353 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1354}
1355
1356#define GEN_LOGICAL1(name, tcg_op, opc, type) \
1357static void glue(gen_, name)(DisasContext *ctx) \
1358{ \
1359 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1360 if (unlikely(Rc(ctx->opcode) != 0)) \
1361 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1362}
1363
1364/* and & and. */
1365GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1366/* andc & andc. */
1367GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1368
1369/* andi. */
1370static void gen_andi_(DisasContext *ctx)
1371{
1372 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1373 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1374}
1375
1376/* andis. */
1377static void gen_andis_(DisasContext *ctx)
1378{
1379 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1380 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1381}
1382
1383/* cntlzw */
1384static void gen_cntlzw(DisasContext *ctx)
1385{
1386 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1387 if (unlikely(Rc(ctx->opcode) != 0))
1388 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1389}
1390/* eqv & eqv. */
1391GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1392/* extsb & extsb. */
1393GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1394/* extsh & extsh. */
1395GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1396/* nand & nand. */
1397GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1398/* nor & nor. */
1399GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1400
1401/* or & or. */
1402static void gen_or(DisasContext *ctx)
1403{
1404 int rs, ra, rb;
1405
1406 rs = rS(ctx->opcode);
1407 ra = rA(ctx->opcode);
1408 rb = rB(ctx->opcode);
1409 /* Optimisation for mr. ri case */
1410 if (rs != ra || rs != rb) {
1411 if (rs != rb)
1412 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1413 else
1414 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1415 if (unlikely(Rc(ctx->opcode) != 0))
1416 gen_set_Rc0(ctx, cpu_gpr[ra]);
1417 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1418 gen_set_Rc0(ctx, cpu_gpr[rs]);
1419#if defined(TARGET_PPC64)
1420 } else {
1421 int prio = 0;
1422
1423 switch (rs) {
1424 case 1:
1425 /* Set process priority to low */
1426 prio = 2;
1427 break;
1428 case 6:
1429 /* Set process priority to medium-low */
1430 prio = 3;
1431 break;
1432 case 2:
1433 /* Set process priority to normal */
1434 prio = 4;
1435 break;
1436#if !defined(CONFIG_USER_ONLY)
1437 case 31:
1438 if (ctx->mem_idx > 0) {
1439 /* Set process priority to very low */
1440 prio = 1;
1441 }
1442 break;
1443 case 5:
1444 if (ctx->mem_idx > 0) {
1445 /* Set process priority to medium-hight */
1446 prio = 5;
1447 }
1448 break;
1449 case 3:
1450 if (ctx->mem_idx > 0) {
1451 /* Set process priority to high */
1452 prio = 6;
1453 }
1454 break;
1455 case 7:
1456 if (ctx->mem_idx > 1) {
1457 /* Set process priority to very high */
1458 prio = 7;
1459 }
1460 break;
1461#endif
1462 default:
1463 /* nop */
1464 break;
1465 }
1466 if (prio) {
1467 TCGv t0 = tcg_temp_new();
1468 gen_load_spr(t0, SPR_PPR);
1469 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1470 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1471 gen_store_spr(SPR_PPR, t0);
1472 tcg_temp_free(t0);
1473 }
1474#endif
1475 }
1476}
1477/* orc & orc. */
1478GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1479
1480/* xor & xor. */
1481static void gen_xor(DisasContext *ctx)
1482{
1483 /* Optimisation for "set to zero" case */
1484 if (rS(ctx->opcode) != rB(ctx->opcode))
1485 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1486 else
1487 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1488 if (unlikely(Rc(ctx->opcode) != 0))
1489 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1490}
1491
1492/* ori */
1493static void gen_ori(DisasContext *ctx)
1494{
1495 target_ulong uimm = UIMM(ctx->opcode);
1496
1497 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1498 /* NOP */
1499 /* XXX: should handle special NOPs for POWER series */
1500 return;
1501 }
1502 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1503}
1504
1505/* oris */
1506static void gen_oris(DisasContext *ctx)
1507{
1508 target_ulong uimm = UIMM(ctx->opcode);
1509
1510 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1511 /* NOP */
1512 return;
1513 }
1514 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1515}
1516
1517/* xori */
1518static void gen_xori(DisasContext *ctx)
1519{
1520 target_ulong uimm = UIMM(ctx->opcode);
1521
1522 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1523 /* NOP */
1524 return;
1525 }
1526 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1527}
1528
1529/* xoris */
1530static void gen_xoris(DisasContext *ctx)
1531{
1532 target_ulong uimm = UIMM(ctx->opcode);
1533
1534 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1535 /* NOP */
1536 return;
1537 }
1538 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1539}
1540
1541/* popcntb : PowerPC 2.03 specification */
1542static void gen_popcntb(DisasContext *ctx)
1543{
1544 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545}
1546
1547static void gen_popcntw(DisasContext *ctx)
1548{
1549 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1550}
1551
1552#if defined(TARGET_PPC64)
1553/* popcntd: PowerPC 2.06 specification */
1554static void gen_popcntd(DisasContext *ctx)
1555{
1556 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1557}
1558#endif
1559
1560#if defined(TARGET_PPC64)
1561/* extsw & extsw. */
1562GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1563
1564/* cntlzd */
1565static void gen_cntlzd(DisasContext *ctx)
1566{
1567 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1568 if (unlikely(Rc(ctx->opcode) != 0))
1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1570}
1571#endif
1572
1573/*** Integer rotate ***/
1574
1575/* rlwimi & rlwimi. */
1576static void gen_rlwimi(DisasContext *ctx)
1577{
1578 uint32_t mb, me, sh;
1579
1580 mb = MB(ctx->opcode);
1581 me = ME(ctx->opcode);
1582 sh = SH(ctx->opcode);
1583 if (likely(sh == 0 && mb == 0 && me == 31)) {
1584 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1585 } else {
1586 target_ulong mask;
1587 TCGv t1;
1588 TCGv t0 = tcg_temp_new();
1589#if defined(TARGET_PPC64)
1590 TCGv_i32 t2 = tcg_temp_new_i32();
1591 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1592 tcg_gen_rotli_i32(t2, t2, sh);
1593 tcg_gen_extu_i32_i64(t0, t2);
1594 tcg_temp_free_i32(t2);
1595#else
1596 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1597#endif
1598#if defined(TARGET_PPC64)
1599 mb += 32;
1600 me += 32;
1601#endif
1602 mask = MASK(mb, me);
1603 t1 = tcg_temp_new();
1604 tcg_gen_andi_tl(t0, t0, mask);
1605 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1606 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1607 tcg_temp_free(t0);
1608 tcg_temp_free(t1);
1609 }
1610 if (unlikely(Rc(ctx->opcode) != 0))
1611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1612}
1613
1614/* rlwinm & rlwinm. */
1615static void gen_rlwinm(DisasContext *ctx)
1616{
1617 uint32_t mb, me, sh;
1618
1619 sh = SH(ctx->opcode);
1620 mb = MB(ctx->opcode);
1621 me = ME(ctx->opcode);
1622
1623 if (likely(mb == 0 && me == (31 - sh))) {
1624 if (likely(sh == 0)) {
1625 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1626 } else {
1627 TCGv t0 = tcg_temp_new();
1628 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1629 tcg_gen_shli_tl(t0, t0, sh);
1630 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1631 tcg_temp_free(t0);
1632 }
1633 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1634 TCGv t0 = tcg_temp_new();
1635 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1636 tcg_gen_shri_tl(t0, t0, mb);
1637 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1638 tcg_temp_free(t0);
1639 } else {
1640 TCGv t0 = tcg_temp_new();
1641#if defined(TARGET_PPC64)
1642 TCGv_i32 t1 = tcg_temp_new_i32();
1643 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1644 tcg_gen_rotli_i32(t1, t1, sh);
1645 tcg_gen_extu_i32_i64(t0, t1);
1646 tcg_temp_free_i32(t1);
1647#else
1648 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1649#endif
1650#if defined(TARGET_PPC64)
1651 mb += 32;
1652 me += 32;
1653#endif
1654 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1655 tcg_temp_free(t0);
1656 }
1657 if (unlikely(Rc(ctx->opcode) != 0))
1658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1659}
1660
1661/* rlwnm & rlwnm. */
1662static void gen_rlwnm(DisasContext *ctx)
1663{
1664 uint32_t mb, me;
1665 TCGv t0;
1666#if defined(TARGET_PPC64)
1667 TCGv_i32 t1, t2;
1668#endif
1669
1670 mb = MB(ctx->opcode);
1671 me = ME(ctx->opcode);
1672 t0 = tcg_temp_new();
1673 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1674#if defined(TARGET_PPC64)
1675 t1 = tcg_temp_new_i32();
1676 t2 = tcg_temp_new_i32();
1677 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1678 tcg_gen_trunc_i64_i32(t2, t0);
1679 tcg_gen_rotl_i32(t1, t1, t2);
1680 tcg_gen_extu_i32_i64(t0, t1);
1681 tcg_temp_free_i32(t1);
1682 tcg_temp_free_i32(t2);
1683#else
1684 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1685#endif
1686 if (unlikely(mb != 0 || me != 31)) {
1687#if defined(TARGET_PPC64)
1688 mb += 32;
1689 me += 32;
1690#endif
1691 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1692 } else {
1693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1694 }
1695 tcg_temp_free(t0);
1696 if (unlikely(Rc(ctx->opcode) != 0))
1697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1698}
1699
1700#if defined(TARGET_PPC64)
1701#define GEN_PPC64_R2(name, opc1, opc2) \
1702static void glue(gen_, name##0)(DisasContext *ctx) \
1703{ \
1704 gen_##name(ctx, 0); \
1705} \
1706 \
1707static void glue(gen_, name##1)(DisasContext *ctx) \
1708{ \
1709 gen_##name(ctx, 1); \
1710}
1711#define GEN_PPC64_R4(name, opc1, opc2) \
1712static void glue(gen_, name##0)(DisasContext *ctx) \
1713{ \
1714 gen_##name(ctx, 0, 0); \
1715} \
1716 \
1717static void glue(gen_, name##1)(DisasContext *ctx) \
1718{ \
1719 gen_##name(ctx, 0, 1); \
1720} \
1721 \
1722static void glue(gen_, name##2)(DisasContext *ctx) \
1723{ \
1724 gen_##name(ctx, 1, 0); \
1725} \
1726 \
1727static void glue(gen_, name##3)(DisasContext *ctx) \
1728{ \
1729 gen_##name(ctx, 1, 1); \
1730}
1731
1732static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1733 uint32_t sh)
1734{
1735 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1736 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1737 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1738 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1739 } else {
1740 TCGv t0 = tcg_temp_new();
1741 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1742 if (likely(mb == 0 && me == 63)) {
1743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1744 } else {
1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746 }
1747 tcg_temp_free(t0);
1748 }
1749 if (unlikely(Rc(ctx->opcode) != 0))
1750 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1751}
1752/* rldicl - rldicl. */
1753static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1754{
1755 uint32_t sh, mb;
1756
1757 sh = SH(ctx->opcode) | (shn << 5);
1758 mb = MB(ctx->opcode) | (mbn << 5);
1759 gen_rldinm(ctx, mb, 63, sh);
1760}
1761GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1762/* rldicr - rldicr. */
1763static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1764{
1765 uint32_t sh, me;
1766
1767 sh = SH(ctx->opcode) | (shn << 5);
1768 me = MB(ctx->opcode) | (men << 5);
1769 gen_rldinm(ctx, 0, me, sh);
1770}
1771GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1772/* rldic - rldic. */
1773static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1774{
1775 uint32_t sh, mb;
1776
1777 sh = SH(ctx->opcode) | (shn << 5);
1778 mb = MB(ctx->opcode) | (mbn << 5);
1779 gen_rldinm(ctx, mb, 63 - sh, sh);
1780}
1781GEN_PPC64_R4(rldic, 0x1E, 0x04);
1782
1783static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1784{
1785 TCGv t0;
1786
1787 mb = MB(ctx->opcode);
1788 me = ME(ctx->opcode);
1789 t0 = tcg_temp_new();
1790 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1791 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1792 if (unlikely(mb != 0 || me != 63)) {
1793 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1794 } else {
1795 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1796 }
1797 tcg_temp_free(t0);
1798 if (unlikely(Rc(ctx->opcode) != 0))
1799 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1800}
1801
1802/* rldcl - rldcl. */
1803static inline void gen_rldcl(DisasContext *ctx, int mbn)
1804{
1805 uint32_t mb;
1806
1807 mb = MB(ctx->opcode) | (mbn << 5);
1808 gen_rldnm(ctx, mb, 63);
1809}
1810GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1811/* rldcr - rldcr. */
1812static inline void gen_rldcr(DisasContext *ctx, int men)
1813{
1814 uint32_t me;
1815
1816 me = MB(ctx->opcode) | (men << 5);
1817 gen_rldnm(ctx, 0, me);
1818}
1819GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1820/* rldimi - rldimi. */
1821static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1822{
1823 uint32_t sh, mb, me;
1824
1825 sh = SH(ctx->opcode) | (shn << 5);
1826 mb = MB(ctx->opcode) | (mbn << 5);
1827 me = 63 - sh;
1828 if (unlikely(sh == 0 && mb == 0)) {
1829 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1830 } else {
1831 TCGv t0, t1;
1832 target_ulong mask;
1833
1834 t0 = tcg_temp_new();
1835 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1836 t1 = tcg_temp_new();
1837 mask = MASK(mb, me);
1838 tcg_gen_andi_tl(t0, t0, mask);
1839 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1840 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1841 tcg_temp_free(t0);
1842 tcg_temp_free(t1);
1843 }
1844 if (unlikely(Rc(ctx->opcode) != 0))
1845 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1846}
1847GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1848#endif
1849
1850/*** Integer shift ***/
1851
1852/* slw & slw. */
1853static void gen_slw(DisasContext *ctx)
1854{
1855 TCGv t0, t1;
1856
1857 t0 = tcg_temp_new();
1858 /* AND rS with a mask that is 0 when rB >= 0x20 */
1859#if defined(TARGET_PPC64)
1860 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1861 tcg_gen_sari_tl(t0, t0, 0x3f);
1862#else
1863 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1864 tcg_gen_sari_tl(t0, t0, 0x1f);
1865#endif
1866 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1867 t1 = tcg_temp_new();
1868 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1869 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1870 tcg_temp_free(t1);
1871 tcg_temp_free(t0);
1872 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1873 if (unlikely(Rc(ctx->opcode) != 0))
1874 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1875}
1876
1877/* sraw & sraw. */
1878static void gen_sraw(DisasContext *ctx)
1879{
1880 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1881 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1882 if (unlikely(Rc(ctx->opcode) != 0))
1883 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1884}
1885
1886/* srawi & srawi. */
1887static void gen_srawi(DisasContext *ctx)
1888{
1889 int sh = SH(ctx->opcode);
1890 if (sh != 0) {
1891 int l1, l2;
1892 TCGv t0;
1893 l1 = gen_new_label();
1894 l2 = gen_new_label();
1895 t0 = tcg_temp_local_new();
1896 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1897 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1898 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1899 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1900 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1901 tcg_gen_br(l2);
1902 gen_set_label(l1);
1903 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1904 gen_set_label(l2);
1905 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1906 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1907 tcg_temp_free(t0);
1908 } else {
1909 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1910 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1911 }
1912 if (unlikely(Rc(ctx->opcode) != 0))
1913 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1914}
1915
1916/* srw & srw. */
1917static void gen_srw(DisasContext *ctx)
1918{
1919 TCGv t0, t1;
1920
1921 t0 = tcg_temp_new();
1922 /* AND rS with a mask that is 0 when rB >= 0x20 */
1923#if defined(TARGET_PPC64)
1924 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1925 tcg_gen_sari_tl(t0, t0, 0x3f);
1926#else
1927 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1928 tcg_gen_sari_tl(t0, t0, 0x1f);
1929#endif
1930 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1931 tcg_gen_ext32u_tl(t0, t0);
1932 t1 = tcg_temp_new();
1933 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1934 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1935 tcg_temp_free(t1);
1936 tcg_temp_free(t0);
1937 if (unlikely(Rc(ctx->opcode) != 0))
1938 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1939}
1940
1941#if defined(TARGET_PPC64)
1942/* sld & sld. */
1943static void gen_sld(DisasContext *ctx)
1944{
1945 TCGv t0, t1;
1946
1947 t0 = tcg_temp_new();
1948 /* AND rS with a mask that is 0 when rB >= 0x40 */
1949 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1950 tcg_gen_sari_tl(t0, t0, 0x3f);
1951 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1952 t1 = tcg_temp_new();
1953 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1954 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1955 tcg_temp_free(t1);
1956 tcg_temp_free(t0);
1957 if (unlikely(Rc(ctx->opcode) != 0))
1958 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1959}
1960
1961/* srad & srad. */
1962static void gen_srad(DisasContext *ctx)
1963{
1964 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1965 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1966 if (unlikely(Rc(ctx->opcode) != 0))
1967 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1968}
1969/* sradi & sradi. */
1970static inline void gen_sradi(DisasContext *ctx, int n)
1971{
1972 int sh = SH(ctx->opcode) + (n << 5);
1973 if (sh != 0) {
1974 int l1, l2;
1975 TCGv t0;
1976 l1 = gen_new_label();
1977 l2 = gen_new_label();
1978 t0 = tcg_temp_local_new();
1979 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
1980 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1981 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
1982 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
1983 tcg_gen_br(l2);
1984 gen_set_label(l1);
1985 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1986 gen_set_label(l2);
1987 tcg_temp_free(t0);
1988 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1989 } else {
1990 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1991 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1992 }
1993 if (unlikely(Rc(ctx->opcode) != 0))
1994 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1995}
1996
1997static void gen_sradi0(DisasContext *ctx)
1998{
1999 gen_sradi(ctx, 0);
2000}
2001
2002static void gen_sradi1(DisasContext *ctx)
2003{
2004 gen_sradi(ctx, 1);
2005}
2006
2007/* srd & srd. */
2008static void gen_srd(DisasContext *ctx)
2009{
2010 TCGv t0, t1;
2011
2012 t0 = tcg_temp_new();
2013 /* AND rS with a mask that is 0 when rB >= 0x40 */
2014 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2015 tcg_gen_sari_tl(t0, t0, 0x3f);
2016 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2017 t1 = tcg_temp_new();
2018 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2019 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2020 tcg_temp_free(t1);
2021 tcg_temp_free(t0);
2022 if (unlikely(Rc(ctx->opcode) != 0))
2023 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2024}
2025#endif
2026
2027/*** Floating-Point arithmetic ***/
2028#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2029static void gen_f##name(DisasContext *ctx) \
2030{ \
2031 if (unlikely(!ctx->fpu_enabled)) { \
2032 gen_exception(ctx, POWERPC_EXCP_FPU); \
2033 return; \
2034 } \
2035 /* NIP cannot be restored if the memory exception comes from an helper */ \
2036 gen_update_nip(ctx, ctx->nip - 4); \
2037 gen_reset_fpstatus(); \
2038 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2039 cpu_fpr[rA(ctx->opcode)], \
2040 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2041 if (isfloat) { \
2042 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2043 cpu_fpr[rD(ctx->opcode)]); \
2044 } \
2045 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2046 Rc(ctx->opcode) != 0); \
2047}
2048
2049#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2050_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2051_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2052
2053#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2054static void gen_f##name(DisasContext *ctx) \
2055{ \
2056 if (unlikely(!ctx->fpu_enabled)) { \
2057 gen_exception(ctx, POWERPC_EXCP_FPU); \
2058 return; \
2059 } \
2060 /* NIP cannot be restored if the memory exception comes from an helper */ \
2061 gen_update_nip(ctx, ctx->nip - 4); \
2062 gen_reset_fpstatus(); \
2063 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2064 cpu_fpr[rA(ctx->opcode)], \
2065 cpu_fpr[rB(ctx->opcode)]); \
2066 if (isfloat) { \
2067 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2068 cpu_fpr[rD(ctx->opcode)]); \
2069 } \
2070 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2071 set_fprf, Rc(ctx->opcode) != 0); \
2072}
2073#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2074_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2075_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2076
2077#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2078static void gen_f##name(DisasContext *ctx) \
2079{ \
2080 if (unlikely(!ctx->fpu_enabled)) { \
2081 gen_exception(ctx, POWERPC_EXCP_FPU); \
2082 return; \
2083 } \
2084 /* NIP cannot be restored if the memory exception comes from an helper */ \
2085 gen_update_nip(ctx, ctx->nip - 4); \
2086 gen_reset_fpstatus(); \
2087 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2088 cpu_fpr[rA(ctx->opcode)], \
2089 cpu_fpr[rC(ctx->opcode)]); \
2090 if (isfloat) { \
2091 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2092 cpu_fpr[rD(ctx->opcode)]); \
2093 } \
2094 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2095 set_fprf, Rc(ctx->opcode) != 0); \
2096}
2097#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2098_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2099_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2100
2101#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2102static void gen_f##name(DisasContext *ctx) \
2103{ \
2104 if (unlikely(!ctx->fpu_enabled)) { \
2105 gen_exception(ctx, POWERPC_EXCP_FPU); \
2106 return; \
2107 } \
2108 /* NIP cannot be restored if the memory exception comes from an helper */ \
2109 gen_update_nip(ctx, ctx->nip - 4); \
2110 gen_reset_fpstatus(); \
2111 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2112 cpu_fpr[rB(ctx->opcode)]); \
2113 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2114 set_fprf, Rc(ctx->opcode) != 0); \
2115}
2116
2117#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2118static void gen_f##name(DisasContext *ctx) \
2119{ \
2120 if (unlikely(!ctx->fpu_enabled)) { \
2121 gen_exception(ctx, POWERPC_EXCP_FPU); \
2122 return; \
2123 } \
2124 /* NIP cannot be restored if the memory exception comes from an helper */ \
2125 gen_update_nip(ctx, ctx->nip - 4); \
2126 gen_reset_fpstatus(); \
2127 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2128 cpu_fpr[rB(ctx->opcode)]); \
2129 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2130 set_fprf, Rc(ctx->opcode) != 0); \
2131}
2132
2133/* fadd - fadds */
2134GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2135/* fdiv - fdivs */
2136GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2137/* fmul - fmuls */
2138GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2139
2140/* fre */
2141GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2142
2143/* fres */
2144GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2145
2146/* frsqrte */
2147GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2148
2149/* frsqrtes */
2150static void gen_frsqrtes(DisasContext *ctx)
2151{
2152 if (unlikely(!ctx->fpu_enabled)) {
2153 gen_exception(ctx, POWERPC_EXCP_FPU);
2154 return;
2155 }
2156 /* NIP cannot be restored if the memory exception comes from an helper */
2157 gen_update_nip(ctx, ctx->nip - 4);
2158 gen_reset_fpstatus();
2159 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2160 cpu_fpr[rB(ctx->opcode)]);
2161 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2162 cpu_fpr[rD(ctx->opcode)]);
2163 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2164}
2165
2166/* fsel */
2167_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2168/* fsub - fsubs */
2169GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2170/* Optional: */
2171
2172/* fsqrt */
2173static void gen_fsqrt(DisasContext *ctx)
2174{
2175 if (unlikely(!ctx->fpu_enabled)) {
2176 gen_exception(ctx, POWERPC_EXCP_FPU);
2177 return;
2178 }
2179 /* NIP cannot be restored if the memory exception comes from an helper */
2180 gen_update_nip(ctx, ctx->nip - 4);
2181 gen_reset_fpstatus();
2182 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2183 cpu_fpr[rB(ctx->opcode)]);
2184 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2185}
2186
2187static void gen_fsqrts(DisasContext *ctx)
2188{
2189 if (unlikely(!ctx->fpu_enabled)) {
2190 gen_exception(ctx, POWERPC_EXCP_FPU);
2191 return;
2192 }
2193 /* NIP cannot be restored if the memory exception comes from an helper */
2194 gen_update_nip(ctx, ctx->nip - 4);
2195 gen_reset_fpstatus();
2196 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2197 cpu_fpr[rB(ctx->opcode)]);
2198 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2199 cpu_fpr[rD(ctx->opcode)]);
2200 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2201}
2202
2203/*** Floating-Point multiply-and-add ***/
2204/* fmadd - fmadds */
2205GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2206/* fmsub - fmsubs */
2207GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2208/* fnmadd - fnmadds */
2209GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2210/* fnmsub - fnmsubs */
2211GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2212
2213/*** Floating-Point round & convert ***/
2214/* fctiw */
2215GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2216/* fctiwz */
2217GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2218/* frsp */
2219GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2220#if defined(TARGET_PPC64)
2221/* fcfid */
2222GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2223/* fctid */
2224GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2225/* fctidz */
2226GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2227#endif
2228
2229/* frin */
2230GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2231/* friz */
2232GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2233/* frip */
2234GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2235/* frim */
2236GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2237
2238/*** Floating-Point compare ***/
2239
2240/* fcmpo */
2241static void gen_fcmpo(DisasContext *ctx)
2242{
2243 TCGv_i32 crf;
2244 if (unlikely(!ctx->fpu_enabled)) {
2245 gen_exception(ctx, POWERPC_EXCP_FPU);
2246 return;
2247 }
2248 /* NIP cannot be restored if the memory exception comes from an helper */
2249 gen_update_nip(ctx, ctx->nip - 4);
2250 gen_reset_fpstatus();
2251 crf = tcg_const_i32(crfD(ctx->opcode));
2252 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2253 cpu_fpr[rB(ctx->opcode)], crf);
2254 tcg_temp_free_i32(crf);
2255 gen_helper_float_check_status(cpu_env);
2256}
2257
2258/* fcmpu */
2259static void gen_fcmpu(DisasContext *ctx)
2260{
2261 TCGv_i32 crf;
2262 if (unlikely(!ctx->fpu_enabled)) {
2263 gen_exception(ctx, POWERPC_EXCP_FPU);
2264 return;
2265 }
2266 /* NIP cannot be restored if the memory exception comes from an helper */
2267 gen_update_nip(ctx, ctx->nip - 4);
2268 gen_reset_fpstatus();
2269 crf = tcg_const_i32(crfD(ctx->opcode));
2270 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2271 cpu_fpr[rB(ctx->opcode)], crf);
2272 tcg_temp_free_i32(crf);
2273 gen_helper_float_check_status(cpu_env);
2274}
2275
2276/*** Floating-point move ***/
2277/* fabs */
2278/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2279GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2280
2281/* fmr - fmr. */
2282/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2283static void gen_fmr(DisasContext *ctx)
2284{
2285 if (unlikely(!ctx->fpu_enabled)) {
2286 gen_exception(ctx, POWERPC_EXCP_FPU);
2287 return;
2288 }
2289 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2290 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2291}
2292
2293/* fnabs */
2294/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2295GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2296/* fneg */
2297/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2298GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2299
2300/*** Floating-Point status & ctrl register ***/
2301
2302/* mcrfs */
2303static void gen_mcrfs(DisasContext *ctx)
2304{
2305 TCGv tmp = tcg_temp_new();
2306 int bfa;
2307
2308 if (unlikely(!ctx->fpu_enabled)) {
2309 gen_exception(ctx, POWERPC_EXCP_FPU);
2310 return;
2311 }
2312 bfa = 4 * (7 - crfS(ctx->opcode));
2313 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2314 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2315 tcg_temp_free(tmp);
2316 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2317 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2318}
2319
2320/* mffs */
2321static void gen_mffs(DisasContext *ctx)
2322{
2323 if (unlikely(!ctx->fpu_enabled)) {
2324 gen_exception(ctx, POWERPC_EXCP_FPU);
2325 return;
2326 }
2327 gen_reset_fpstatus();
2328 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2329 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2330}
2331
2332/* mtfsb0 */
2333static void gen_mtfsb0(DisasContext *ctx)
2334{
2335 uint8_t crb;
2336
2337 if (unlikely(!ctx->fpu_enabled)) {
2338 gen_exception(ctx, POWERPC_EXCP_FPU);
2339 return;
2340 }
2341 crb = 31 - crbD(ctx->opcode);
2342 gen_reset_fpstatus();
2343 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2344 TCGv_i32 t0;
2345 /* NIP cannot be restored if the memory exception comes from an helper */
2346 gen_update_nip(ctx, ctx->nip - 4);
2347 t0 = tcg_const_i32(crb);
2348 gen_helper_fpscr_clrbit(cpu_env, t0);
2349 tcg_temp_free_i32(t0);
2350 }
2351 if (unlikely(Rc(ctx->opcode) != 0)) {
2352 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2353 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2354 }
2355}
2356
2357/* mtfsb1 */
2358static void gen_mtfsb1(DisasContext *ctx)
2359{
2360 uint8_t crb;
2361
2362 if (unlikely(!ctx->fpu_enabled)) {
2363 gen_exception(ctx, POWERPC_EXCP_FPU);
2364 return;
2365 }
2366 crb = 31 - crbD(ctx->opcode);
2367 gen_reset_fpstatus();
2368 /* XXX: we pretend we can only do IEEE floating-point computations */
2369 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2370 TCGv_i32 t0;
2371 /* NIP cannot be restored if the memory exception comes from an helper */
2372 gen_update_nip(ctx, ctx->nip - 4);
2373 t0 = tcg_const_i32(crb);
2374 gen_helper_fpscr_setbit(cpu_env, t0);
2375 tcg_temp_free_i32(t0);
2376 }
2377 if (unlikely(Rc(ctx->opcode) != 0)) {
2378 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2379 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2380 }
2381 /* We can raise a differed exception */
2382 gen_helper_float_check_status(cpu_env);
2383}
2384
2385/* mtfsf */
2386static void gen_mtfsf(DisasContext *ctx)
2387{
2388 TCGv_i32 t0;
2389 int L = ctx->opcode & 0x02000000;
2390
2391 if (unlikely(!ctx->fpu_enabled)) {
2392 gen_exception(ctx, POWERPC_EXCP_FPU);
2393 return;
2394 }
2395 /* NIP cannot be restored if the memory exception comes from an helper */
2396 gen_update_nip(ctx, ctx->nip - 4);
2397 gen_reset_fpstatus();
2398 if (L)
2399 t0 = tcg_const_i32(0xff);
2400 else
2401 t0 = tcg_const_i32(FM(ctx->opcode));
2402 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2403 tcg_temp_free_i32(t0);
2404 if (unlikely(Rc(ctx->opcode) != 0)) {
2405 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2406 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2407 }
2408 /* We can raise a differed exception */
2409 gen_helper_float_check_status(cpu_env);
2410}
2411
2412/* mtfsfi */
2413static void gen_mtfsfi(DisasContext *ctx)
2414{
2415 int bf, sh;
2416 TCGv_i64 t0;
2417 TCGv_i32 t1;
2418
2419 if (unlikely(!ctx->fpu_enabled)) {
2420 gen_exception(ctx, POWERPC_EXCP_FPU);
2421 return;
2422 }
2423 bf = crbD(ctx->opcode) >> 2;
2424 sh = 7 - bf;
2425 /* NIP cannot be restored if the memory exception comes from an helper */
2426 gen_update_nip(ctx, ctx->nip - 4);
2427 gen_reset_fpstatus();
2428 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2429 t1 = tcg_const_i32(1 << sh);
2430 gen_helper_store_fpscr(cpu_env, t0, t1);
2431 tcg_temp_free_i64(t0);
2432 tcg_temp_free_i32(t1);
2433 if (unlikely(Rc(ctx->opcode) != 0)) {
2434 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2435 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2436 }
2437 /* We can raise a differed exception */
2438 gen_helper_float_check_status(cpu_env);
2439}
2440
2441/*** Addressing modes ***/
2442/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2443static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2444 target_long maskl)
2445{
2446 target_long simm = SIMM(ctx->opcode);
2447
2448 simm &= ~maskl;
2449 if (rA(ctx->opcode) == 0) {
2450#if defined(TARGET_PPC64)
2451 if (!ctx->sf_mode) {
2452 tcg_gen_movi_tl(EA, (uint32_t)simm);
2453 } else
2454#endif
2455 tcg_gen_movi_tl(EA, simm);
2456 } else if (likely(simm != 0)) {
2457 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2458#if defined(TARGET_PPC64)
2459 if (!ctx->sf_mode) {
2460 tcg_gen_ext32u_tl(EA, EA);
2461 }
2462#endif
2463 } else {
2464#if defined(TARGET_PPC64)
2465 if (!ctx->sf_mode) {
2466 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2467 } else
2468#endif
2469 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2470 }
2471}
2472
2473static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2474{
2475 if (rA(ctx->opcode) == 0) {
2476#if defined(TARGET_PPC64)
2477 if (!ctx->sf_mode) {
2478 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2479 } else
2480#endif
2481 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2482 } else {
2483 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2484#if defined(TARGET_PPC64)
2485 if (!ctx->sf_mode) {
2486 tcg_gen_ext32u_tl(EA, EA);
2487 }
2488#endif
2489 }
2490}
2491
2492static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2493{
2494 if (rA(ctx->opcode) == 0) {
2495 tcg_gen_movi_tl(EA, 0);
2496 } else {
2497#if defined(TARGET_PPC64)
2498 if (!ctx->sf_mode) {
2499 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2500 } else
2501#endif
2502 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2503 }
2504}
2505
2506static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2507 target_long val)
2508{
2509 tcg_gen_addi_tl(ret, arg1, val);
2510#if defined(TARGET_PPC64)
2511 if (!ctx->sf_mode) {
2512 tcg_gen_ext32u_tl(ret, ret);
2513 }
2514#endif
2515}
2516
2517static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2518{
2519 int l1 = gen_new_label();
2520 TCGv t0 = tcg_temp_new();
2521 TCGv_i32 t1, t2;
2522 /* NIP cannot be restored if the memory exception comes from an helper */
2523 gen_update_nip(ctx, ctx->nip - 4);
2524 tcg_gen_andi_tl(t0, EA, mask);
2525 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2526 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2527 t2 = tcg_const_i32(0);
2528 gen_helper_raise_exception_err(cpu_env, t1, t2);
2529 tcg_temp_free_i32(t1);
2530 tcg_temp_free_i32(t2);
2531 gen_set_label(l1);
2532 tcg_temp_free(t0);
2533}
2534
2535/*** Integer load ***/
2536static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2537{
2538 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2539}
2540
2541static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2542{
2543 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2544}
2545
2546static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2547{
2548 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2549 if (unlikely(ctx->le_mode)) {
2550 tcg_gen_bswap16_tl(arg1, arg1);
2551 }
2552}
2553
2554static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2555{
2556 if (unlikely(ctx->le_mode)) {
2557 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2558 tcg_gen_bswap16_tl(arg1, arg1);
2559 tcg_gen_ext16s_tl(arg1, arg1);
2560 } else {
2561 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2562 }
2563}
2564
2565static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2566{
2567 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2568 if (unlikely(ctx->le_mode)) {
2569 tcg_gen_bswap32_tl(arg1, arg1);
2570 }
2571}
2572
2573#if defined(TARGET_PPC64)
2574static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2575{
2576 if (unlikely(ctx->le_mode)) {
2577 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2578 tcg_gen_bswap32_tl(arg1, arg1);
2579 tcg_gen_ext32s_tl(arg1, arg1);
2580 } else
2581 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2582}
2583#endif
2584
2585static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2586{
2587 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2588 if (unlikely(ctx->le_mode)) {
2589 tcg_gen_bswap64_i64(arg1, arg1);
2590 }
2591}
2592
2593static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2594{
2595 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2596}
2597
2598static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2599{
2600 if (unlikely(ctx->le_mode)) {
2601 TCGv t0 = tcg_temp_new();
2602 tcg_gen_ext16u_tl(t0, arg1);
2603 tcg_gen_bswap16_tl(t0, t0);
2604 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2605 tcg_temp_free(t0);
2606 } else {
2607 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2608 }
2609}
2610
2611static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2612{
2613 if (unlikely(ctx->le_mode)) {
2614 TCGv t0 = tcg_temp_new();
2615 tcg_gen_ext32u_tl(t0, arg1);
2616 tcg_gen_bswap32_tl(t0, t0);
2617 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2618 tcg_temp_free(t0);
2619 } else {
2620 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2621 }
2622}
2623
2624static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2625{
2626 if (unlikely(ctx->le_mode)) {
2627 TCGv_i64 t0 = tcg_temp_new_i64();
2628 tcg_gen_bswap64_i64(t0, arg1);
2629 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2630 tcg_temp_free_i64(t0);
2631 } else
2632 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2633}
2634
2635#define GEN_LD(name, ldop, opc, type) \
2636static void glue(gen_, name)(DisasContext *ctx) \
2637{ \
2638 TCGv EA; \
2639 gen_set_access_type(ctx, ACCESS_INT); \
2640 EA = tcg_temp_new(); \
2641 gen_addr_imm_index(ctx, EA, 0); \
2642 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2643 tcg_temp_free(EA); \
2644}
2645
2646#define GEN_LDU(name, ldop, opc, type) \
2647static void glue(gen_, name##u)(DisasContext *ctx) \
2648{ \
2649 TCGv EA; \
2650 if (unlikely(rA(ctx->opcode) == 0 || \
2651 rA(ctx->opcode) == rD(ctx->opcode))) { \
2652 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2653 return; \
2654 } \
2655 gen_set_access_type(ctx, ACCESS_INT); \
2656 EA = tcg_temp_new(); \
2657 if (type == PPC_64B) \
2658 gen_addr_imm_index(ctx, EA, 0x03); \
2659 else \
2660 gen_addr_imm_index(ctx, EA, 0); \
2661 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2662 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2663 tcg_temp_free(EA); \
2664}
2665
2666#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2667static void glue(gen_, name##ux)(DisasContext *ctx) \
2668{ \
2669 TCGv EA; \
2670 if (unlikely(rA(ctx->opcode) == 0 || \
2671 rA(ctx->opcode) == rD(ctx->opcode))) { \
2672 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2673 return; \
2674 } \
2675 gen_set_access_type(ctx, ACCESS_INT); \
2676 EA = tcg_temp_new(); \
2677 gen_addr_reg_index(ctx, EA); \
2678 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2679 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2680 tcg_temp_free(EA); \
2681}
2682
2683#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2684static void glue(gen_, name##x)(DisasContext *ctx) \
2685{ \
2686 TCGv EA; \
2687 gen_set_access_type(ctx, ACCESS_INT); \
2688 EA = tcg_temp_new(); \
2689 gen_addr_reg_index(ctx, EA); \
2690 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2691 tcg_temp_free(EA); \
2692}
2693#define GEN_LDX(name, ldop, opc2, opc3, type) \
2694 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2695
2696#define GEN_LDS(name, ldop, op, type) \
2697GEN_LD(name, ldop, op | 0x20, type); \
2698GEN_LDU(name, ldop, op | 0x21, type); \
2699GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2700GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2701
2702/* lbz lbzu lbzux lbzx */
2703GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2704/* lha lhau lhaux lhax */
2705GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2706/* lhz lhzu lhzux lhzx */
2707GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2708/* lwz lwzu lwzux lwzx */
2709GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2710#if defined(TARGET_PPC64)
2711/* lwaux */
2712GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2713/* lwax */
2714GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2715/* ldux */
2716GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2717/* ldx */
2718GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2719
2720static void gen_ld(DisasContext *ctx)
2721{
2722 TCGv EA;
2723 if (Rc(ctx->opcode)) {
2724 if (unlikely(rA(ctx->opcode) == 0 ||
2725 rA(ctx->opcode) == rD(ctx->opcode))) {
2726 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2727 return;
2728 }
2729 }
2730 gen_set_access_type(ctx, ACCESS_INT);
2731 EA = tcg_temp_new();
2732 gen_addr_imm_index(ctx, EA, 0x03);
2733 if (ctx->opcode & 0x02) {
2734 /* lwa (lwau is undefined) */
2735 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2736 } else {
2737 /* ld - ldu */
2738 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2739 }
2740 if (Rc(ctx->opcode))
2741 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2742 tcg_temp_free(EA);
2743}
2744
2745/* lq */
2746static void gen_lq(DisasContext *ctx)
2747{
2748#if defined(CONFIG_USER_ONLY)
2749 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2750#else
2751 int ra, rd;
2752 TCGv EA;
2753
2754 /* Restore CPU state */
2755 if (unlikely(ctx->mem_idx == 0)) {
2756 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2757 return;
2758 }
2759 ra = rA(ctx->opcode);
2760 rd = rD(ctx->opcode);
2761 if (unlikely((rd & 1) || rd == ra)) {
2762 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2763 return;
2764 }
2765 if (unlikely(ctx->le_mode)) {
2766 /* Little-endian mode is not handled */
2767 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2768 return;
2769 }
2770 gen_set_access_type(ctx, ACCESS_INT);
2771 EA = tcg_temp_new();
2772 gen_addr_imm_index(ctx, EA, 0x0F);
2773 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2774 gen_addr_add(ctx, EA, EA, 8);
2775 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2776 tcg_temp_free(EA);
2777#endif
2778}
2779#endif
2780
2781/*** Integer store ***/
2782#define GEN_ST(name, stop, opc, type) \
2783static void glue(gen_, name)(DisasContext *ctx) \
2784{ \
2785 TCGv EA; \
2786 gen_set_access_type(ctx, ACCESS_INT); \
2787 EA = tcg_temp_new(); \
2788 gen_addr_imm_index(ctx, EA, 0); \
2789 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2790 tcg_temp_free(EA); \
2791}
2792
2793#define GEN_STU(name, stop, opc, type) \
2794static void glue(gen_, stop##u)(DisasContext *ctx) \
2795{ \
2796 TCGv EA; \
2797 if (unlikely(rA(ctx->opcode) == 0)) { \
2798 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2799 return; \
2800 } \
2801 gen_set_access_type(ctx, ACCESS_INT); \
2802 EA = tcg_temp_new(); \
2803 if (type == PPC_64B) \
2804 gen_addr_imm_index(ctx, EA, 0x03); \
2805 else \
2806 gen_addr_imm_index(ctx, EA, 0); \
2807 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2808 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2809 tcg_temp_free(EA); \
2810}
2811
2812#define GEN_STUX(name, stop, opc2, opc3, type) \
2813static void glue(gen_, name##ux)(DisasContext *ctx) \
2814{ \
2815 TCGv EA; \
2816 if (unlikely(rA(ctx->opcode) == 0)) { \
2817 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2818 return; \
2819 } \
2820 gen_set_access_type(ctx, ACCESS_INT); \
2821 EA = tcg_temp_new(); \
2822 gen_addr_reg_index(ctx, EA); \
2823 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2824 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2825 tcg_temp_free(EA); \
2826}
2827
2828#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2829static void glue(gen_, name##x)(DisasContext *ctx) \
2830{ \
2831 TCGv EA; \
2832 gen_set_access_type(ctx, ACCESS_INT); \
2833 EA = tcg_temp_new(); \
2834 gen_addr_reg_index(ctx, EA); \
2835 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2836 tcg_temp_free(EA); \
2837}
2838#define GEN_STX(name, stop, opc2, opc3, type) \
2839 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2840
2841#define GEN_STS(name, stop, op, type) \
2842GEN_ST(name, stop, op | 0x20, type); \
2843GEN_STU(name, stop, op | 0x21, type); \
2844GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2845GEN_STX(name, stop, 0x17, op | 0x00, type)
2846
2847/* stb stbu stbux stbx */
2848GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2849/* sth sthu sthux sthx */
2850GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2851/* stw stwu stwux stwx */
2852GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2853#if defined(TARGET_PPC64)
2854GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2855GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2856
2857static void gen_std(DisasContext *ctx)
2858{
2859 int rs;
2860 TCGv EA;
2861
2862 rs = rS(ctx->opcode);
2863 if ((ctx->opcode & 0x3) == 0x2) {
2864#if defined(CONFIG_USER_ONLY)
2865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2866#else
2867 /* stq */
2868 if (unlikely(ctx->mem_idx == 0)) {
2869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2870 return;
2871 }
2872 if (unlikely(rs & 1)) {
2873 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2874 return;
2875 }
2876 if (unlikely(ctx->le_mode)) {
2877 /* Little-endian mode is not handled */
2878 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2879 return;
2880 }
2881 gen_set_access_type(ctx, ACCESS_INT);
2882 EA = tcg_temp_new();
2883 gen_addr_imm_index(ctx, EA, 0x03);
2884 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2885 gen_addr_add(ctx, EA, EA, 8);
2886 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2887 tcg_temp_free(EA);
2888#endif
2889 } else {
2890 /* std / stdu */
2891 if (Rc(ctx->opcode)) {
2892 if (unlikely(rA(ctx->opcode) == 0)) {
2893 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2894 return;
2895 }
2896 }
2897 gen_set_access_type(ctx, ACCESS_INT);
2898 EA = tcg_temp_new();
2899 gen_addr_imm_index(ctx, EA, 0x03);
2900 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2901 if (Rc(ctx->opcode))
2902 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2903 tcg_temp_free(EA);
2904 }
2905}
2906#endif
2907/*** Integer load and store with byte reverse ***/
2908/* lhbrx */
2909static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2910{
2911 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2912 if (likely(!ctx->le_mode)) {
2913 tcg_gen_bswap16_tl(arg1, arg1);
2914 }
2915}
2916GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2917
2918/* lwbrx */
2919static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2920{
2921 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2922 if (likely(!ctx->le_mode)) {
2923 tcg_gen_bswap32_tl(arg1, arg1);
2924 }
2925}
2926GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2927
2928#if defined(TARGET_PPC64)
2929/* ldbrx */
2930static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2931{
2932 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2933 if (likely(!ctx->le_mode)) {
2934 tcg_gen_bswap64_tl(arg1, arg1);
2935 }
2936}
2937GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2938#endif /* TARGET_PPC64 */
2939
2940/* sthbrx */
2941static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2942{
2943 if (likely(!ctx->le_mode)) {
2944 TCGv t0 = tcg_temp_new();
2945 tcg_gen_ext16u_tl(t0, arg1);
2946 tcg_gen_bswap16_tl(t0, t0);
2947 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2948 tcg_temp_free(t0);
2949 } else {
2950 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2951 }
2952}
2953GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2954
2955/* stwbrx */
2956static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2957{
2958 if (likely(!ctx->le_mode)) {
2959 TCGv t0 = tcg_temp_new();
2960 tcg_gen_ext32u_tl(t0, arg1);
2961 tcg_gen_bswap32_tl(t0, t0);
2962 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2963 tcg_temp_free(t0);
2964 } else {
2965 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2966 }
2967}
2968GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2969
2970#if defined(TARGET_PPC64)
2971/* stdbrx */
2972static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2973{
2974 if (likely(!ctx->le_mode)) {
2975 TCGv t0 = tcg_temp_new();
2976 tcg_gen_bswap64_tl(t0, arg1);
2977 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2978 tcg_temp_free(t0);
2979 } else {
2980 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2981 }
2982}
2983GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2984#endif /* TARGET_PPC64 */
2985
2986/*** Integer load and store multiple ***/
2987
2988/* lmw */
2989static void gen_lmw(DisasContext *ctx)
2990{
2991 TCGv t0;
2992 TCGv_i32 t1;
2993 gen_set_access_type(ctx, ACCESS_INT);
2994 /* NIP cannot be restored if the memory exception comes from an helper */
2995 gen_update_nip(ctx, ctx->nip - 4);
2996 t0 = tcg_temp_new();
2997 t1 = tcg_const_i32(rD(ctx->opcode));
2998 gen_addr_imm_index(ctx, t0, 0);
2999 gen_helper_lmw(cpu_env, t0, t1);
3000 tcg_temp_free(t0);
3001 tcg_temp_free_i32(t1);
3002}
3003
3004/* stmw */
3005static void gen_stmw(DisasContext *ctx)
3006{
3007 TCGv t0;
3008 TCGv_i32 t1;
3009 gen_set_access_type(ctx, ACCESS_INT);
3010 /* NIP cannot be restored if the memory exception comes from an helper */
3011 gen_update_nip(ctx, ctx->nip - 4);
3012 t0 = tcg_temp_new();
3013 t1 = tcg_const_i32(rS(ctx->opcode));
3014 gen_addr_imm_index(ctx, t0, 0);
3015 gen_helper_stmw(cpu_env, t0, t1);
3016 tcg_temp_free(t0);
3017 tcg_temp_free_i32(t1);
3018}
3019
3020/*** Integer load and store strings ***/
3021
3022/* lswi */
3023/* PowerPC32 specification says we must generate an exception if
3024 * rA is in the range of registers to be loaded.
3025 * In an other hand, IBM says this is valid, but rA won't be loaded.
3026 * For now, I'll follow the spec...
3027 */
3028static void gen_lswi(DisasContext *ctx)
3029{
3030 TCGv t0;
3031 TCGv_i32 t1, t2;
3032 int nb = NB(ctx->opcode);
3033 int start = rD(ctx->opcode);
3034 int ra = rA(ctx->opcode);
3035 int nr;
3036
3037 if (nb == 0)
3038 nb = 32;
3039 nr = nb / 4;
3040 if (unlikely(((start + nr) > 32 &&
3041 start <= ra && (start + nr - 32) > ra) ||
3042 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3043 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3044 return;
3045 }
3046 gen_set_access_type(ctx, ACCESS_INT);
3047 /* NIP cannot be restored if the memory exception comes from an helper */
3048 gen_update_nip(ctx, ctx->nip - 4);
3049 t0 = tcg_temp_new();
3050 gen_addr_register(ctx, t0);
3051 t1 = tcg_const_i32(nb);
3052 t2 = tcg_const_i32(start);
3053 gen_helper_lsw(cpu_env, t0, t1, t2);
3054 tcg_temp_free(t0);
3055 tcg_temp_free_i32(t1);
3056 tcg_temp_free_i32(t2);
3057}
3058
3059/* lswx */
3060static void gen_lswx(DisasContext *ctx)
3061{
3062 TCGv t0;
3063 TCGv_i32 t1, t2, t3;
3064 gen_set_access_type(ctx, ACCESS_INT);
3065 /* NIP cannot be restored if the memory exception comes from an helper */
3066 gen_update_nip(ctx, ctx->nip - 4);
3067 t0 = tcg_temp_new();
3068 gen_addr_reg_index(ctx, t0);
3069 t1 = tcg_const_i32(rD(ctx->opcode));
3070 t2 = tcg_const_i32(rA(ctx->opcode));
3071 t3 = tcg_const_i32(rB(ctx->opcode));
3072 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3073 tcg_temp_free(t0);
3074 tcg_temp_free_i32(t1);
3075 tcg_temp_free_i32(t2);
3076 tcg_temp_free_i32(t3);
3077}
3078
3079/* stswi */
3080static void gen_stswi(DisasContext *ctx)
3081{
3082 TCGv t0;
3083 TCGv_i32 t1, t2;
3084 int nb = NB(ctx->opcode);
3085 gen_set_access_type(ctx, ACCESS_INT);
3086 /* NIP cannot be restored if the memory exception comes from an helper */
3087 gen_update_nip(ctx, ctx->nip - 4);
3088 t0 = tcg_temp_new();
3089 gen_addr_register(ctx, t0);
3090 if (nb == 0)
3091 nb = 32;
3092 t1 = tcg_const_i32(nb);
3093 t2 = tcg_const_i32(rS(ctx->opcode));
3094 gen_helper_stsw(cpu_env, t0, t1, t2);
3095 tcg_temp_free(t0);
3096 tcg_temp_free_i32(t1);
3097 tcg_temp_free_i32(t2);
3098}
3099
3100/* stswx */
3101static void gen_stswx(DisasContext *ctx)
3102{
3103 TCGv t0;
3104 TCGv_i32 t1, t2;
3105 gen_set_access_type(ctx, ACCESS_INT);
3106 /* NIP cannot be restored if the memory exception comes from an helper */
3107 gen_update_nip(ctx, ctx->nip - 4);
3108 t0 = tcg_temp_new();
3109 gen_addr_reg_index(ctx, t0);
3110 t1 = tcg_temp_new_i32();
3111 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3112 tcg_gen_andi_i32(t1, t1, 0x7F);
3113 t2 = tcg_const_i32(rS(ctx->opcode));
3114 gen_helper_stsw(cpu_env, t0, t1, t2);
3115 tcg_temp_free(t0);
3116 tcg_temp_free_i32(t1);
3117 tcg_temp_free_i32(t2);
3118}
3119
3120/*** Memory synchronisation ***/
3121/* eieio */
3122static void gen_eieio(DisasContext *ctx)
3123{
3124}
3125
3126/* isync */
3127static void gen_isync(DisasContext *ctx)
3128{
3129 gen_stop_exception(ctx);
3130}
3131
3132/* lwarx */
3133static void gen_lwarx(DisasContext *ctx)
3134{
3135 TCGv t0;
3136 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3137 gen_set_access_type(ctx, ACCESS_RES);
3138 t0 = tcg_temp_local_new();
3139 gen_addr_reg_index(ctx, t0);
3140 gen_check_align(ctx, t0, 0x03);
3141 gen_qemu_ld32u(ctx, gpr, t0);
3142 tcg_gen_mov_tl(cpu_reserve, t0);
3143 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3144 tcg_temp_free(t0);
3145}
3146
3147#if defined(CONFIG_USER_ONLY)
3148static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3149 int reg, int size)
3150{
3151 TCGv t0 = tcg_temp_new();
3152 uint32_t save_exception = ctx->exception;
3153
3154 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3155 tcg_gen_movi_tl(t0, (size << 5) | reg);
3156 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3157 tcg_temp_free(t0);
3158 gen_update_nip(ctx, ctx->nip-4);
3159 ctx->exception = POWERPC_EXCP_BRANCH;
3160 gen_exception(ctx, POWERPC_EXCP_STCX);
3161 ctx->exception = save_exception;
3162}
3163#endif
3164
3165/* stwcx. */
3166static void gen_stwcx_(DisasContext *ctx)
3167{
3168 TCGv t0;
3169 gen_set_access_type(ctx, ACCESS_RES);
3170 t0 = tcg_temp_local_new();
3171 gen_addr_reg_index(ctx, t0);
3172 gen_check_align(ctx, t0, 0x03);
3173#if defined(CONFIG_USER_ONLY)
3174 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3175#else
3176 {
3177 int l1;
3178
3179 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3180 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3181 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3182 l1 = gen_new_label();
3183 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3184 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3185 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3186 gen_set_label(l1);
3187 tcg_gen_movi_tl(cpu_reserve, -1);
3188 }
3189#endif
3190 tcg_temp_free(t0);
3191}
3192
3193#if defined(TARGET_PPC64)
3194/* ldarx */
3195static void gen_ldarx(DisasContext *ctx)
3196{
3197 TCGv t0;
3198 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3199 gen_set_access_type(ctx, ACCESS_RES);
3200 t0 = tcg_temp_local_new();
3201 gen_addr_reg_index(ctx, t0);
3202 gen_check_align(ctx, t0, 0x07);
3203 gen_qemu_ld64(ctx, gpr, t0);
3204 tcg_gen_mov_tl(cpu_reserve, t0);
3205 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3206 tcg_temp_free(t0);
3207}
3208
3209/* stdcx. */
3210static void gen_stdcx_(DisasContext *ctx)
3211{
3212 TCGv t0;
3213 gen_set_access_type(ctx, ACCESS_RES);
3214 t0 = tcg_temp_local_new();
3215 gen_addr_reg_index(ctx, t0);
3216 gen_check_align(ctx, t0, 0x07);
3217#if defined(CONFIG_USER_ONLY)
3218 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3219#else
3220 {
3221 int l1;
3222 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3223 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3224 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
3225 l1 = gen_new_label();
3226 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3227 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3228 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3229 gen_set_label(l1);
3230 tcg_gen_movi_tl(cpu_reserve, -1);
3231 }
3232#endif
3233 tcg_temp_free(t0);
3234}
3235#endif /* defined(TARGET_PPC64) */
3236
3237/* sync */
3238static void gen_sync(DisasContext *ctx)
3239{
3240}
3241
3242/* wait */
3243static void gen_wait(DisasContext *ctx)
3244{
3245 TCGv_i32 t0 = tcg_temp_new_i32();
3246 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3247 tcg_temp_free_i32(t0);
3248 /* Stop translation, as the CPU is supposed to sleep from now */
3249 gen_exception_err(ctx, EXCP_HLT, 1);
3250}
3251
3252/*** Floating-point load ***/
3253#define GEN_LDF(name, ldop, opc, type) \
3254static void glue(gen_, name)(DisasContext *ctx) \
3255{ \
3256 TCGv EA; \
3257 if (unlikely(!ctx->fpu_enabled)) { \
3258 gen_exception(ctx, POWERPC_EXCP_FPU); \
3259 return; \
3260 } \
3261 gen_set_access_type(ctx, ACCESS_FLOAT); \
3262 EA = tcg_temp_new(); \
3263 gen_addr_imm_index(ctx, EA, 0); \
3264 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3265 tcg_temp_free(EA); \
3266}
3267
3268#define GEN_LDUF(name, ldop, opc, type) \
3269static void glue(gen_, name##u)(DisasContext *ctx) \
3270{ \
3271 TCGv EA; \
3272 if (unlikely(!ctx->fpu_enabled)) { \
3273 gen_exception(ctx, POWERPC_EXCP_FPU); \
3274 return; \
3275 } \
3276 if (unlikely(rA(ctx->opcode) == 0)) { \
3277 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3278 return; \
3279 } \
3280 gen_set_access_type(ctx, ACCESS_FLOAT); \
3281 EA = tcg_temp_new(); \
3282 gen_addr_imm_index(ctx, EA, 0); \
3283 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3284 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3285 tcg_temp_free(EA); \
3286}
3287
3288#define GEN_LDUXF(name, ldop, opc, type) \
3289static void glue(gen_, name##ux)(DisasContext *ctx) \
3290{ \
3291 TCGv EA; \
3292 if (unlikely(!ctx->fpu_enabled)) { \
3293 gen_exception(ctx, POWERPC_EXCP_FPU); \
3294 return; \
3295 } \
3296 if (unlikely(rA(ctx->opcode) == 0)) { \
3297 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3298 return; \
3299 } \
3300 gen_set_access_type(ctx, ACCESS_FLOAT); \
3301 EA = tcg_temp_new(); \
3302 gen_addr_reg_index(ctx, EA); \
3303 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3304 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3305 tcg_temp_free(EA); \
3306}
3307
3308#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3309static void glue(gen_, name##x)(DisasContext *ctx) \
3310{ \
3311 TCGv EA; \
3312 if (unlikely(!ctx->fpu_enabled)) { \
3313 gen_exception(ctx, POWERPC_EXCP_FPU); \
3314 return; \
3315 } \
3316 gen_set_access_type(ctx, ACCESS_FLOAT); \
3317 EA = tcg_temp_new(); \
3318 gen_addr_reg_index(ctx, EA); \
3319 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3320 tcg_temp_free(EA); \
3321}
3322
3323#define GEN_LDFS(name, ldop, op, type) \
3324GEN_LDF(name, ldop, op | 0x20, type); \
3325GEN_LDUF(name, ldop, op | 0x21, type); \
3326GEN_LDUXF(name, ldop, op | 0x01, type); \
3327GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3328
3329static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3330{
3331 TCGv t0 = tcg_temp_new();
3332 TCGv_i32 t1 = tcg_temp_new_i32();
3333 gen_qemu_ld32u(ctx, t0, arg2);
3334 tcg_gen_trunc_tl_i32(t1, t0);
3335 tcg_temp_free(t0);
3336 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3337 tcg_temp_free_i32(t1);
3338}
3339
3340 /* lfd lfdu lfdux lfdx */
3341GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3342 /* lfs lfsu lfsux lfsx */
3343GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3344
3345/*** Floating-point store ***/
3346#define GEN_STF(name, stop, opc, type) \
3347static void glue(gen_, name)(DisasContext *ctx) \
3348{ \
3349 TCGv EA; \
3350 if (unlikely(!ctx->fpu_enabled)) { \
3351 gen_exception(ctx, POWERPC_EXCP_FPU); \
3352 return; \
3353 } \
3354 gen_set_access_type(ctx, ACCESS_FLOAT); \
3355 EA = tcg_temp_new(); \
3356 gen_addr_imm_index(ctx, EA, 0); \
3357 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3358 tcg_temp_free(EA); \
3359}
3360
3361#define GEN_STUF(name, stop, opc, type) \
3362static void glue(gen_, name##u)(DisasContext *ctx) \
3363{ \
3364 TCGv EA; \
3365 if (unlikely(!ctx->fpu_enabled)) { \
3366 gen_exception(ctx, POWERPC_EXCP_FPU); \
3367 return; \
3368 } \
3369 if (unlikely(rA(ctx->opcode) == 0)) { \
3370 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3371 return; \
3372 } \
3373 gen_set_access_type(ctx, ACCESS_FLOAT); \
3374 EA = tcg_temp_new(); \
3375 gen_addr_imm_index(ctx, EA, 0); \
3376 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3377 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3378 tcg_temp_free(EA); \
3379}
3380
3381#define GEN_STUXF(name, stop, opc, type) \
3382static void glue(gen_, name##ux)(DisasContext *ctx) \
3383{ \
3384 TCGv EA; \
3385 if (unlikely(!ctx->fpu_enabled)) { \
3386 gen_exception(ctx, POWERPC_EXCP_FPU); \
3387 return; \
3388 } \
3389 if (unlikely(rA(ctx->opcode) == 0)) { \
3390 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3391 return; \
3392 } \
3393 gen_set_access_type(ctx, ACCESS_FLOAT); \
3394 EA = tcg_temp_new(); \
3395 gen_addr_reg_index(ctx, EA); \
3396 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3397 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3398 tcg_temp_free(EA); \
3399}
3400
3401#define GEN_STXF(name, stop, opc2, opc3, type) \
3402static void glue(gen_, name##x)(DisasContext *ctx) \
3403{ \
3404 TCGv EA; \
3405 if (unlikely(!ctx->fpu_enabled)) { \
3406 gen_exception(ctx, POWERPC_EXCP_FPU); \
3407 return; \
3408 } \
3409 gen_set_access_type(ctx, ACCESS_FLOAT); \
3410 EA = tcg_temp_new(); \
3411 gen_addr_reg_index(ctx, EA); \
3412 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3413 tcg_temp_free(EA); \
3414}
3415
3416#define GEN_STFS(name, stop, op, type) \
3417GEN_STF(name, stop, op | 0x20, type); \
3418GEN_STUF(name, stop, op | 0x21, type); \
3419GEN_STUXF(name, stop, op | 0x01, type); \
3420GEN_STXF(name, stop, 0x17, op | 0x00, type)
3421
3422static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3423{
3424 TCGv_i32 t0 = tcg_temp_new_i32();
3425 TCGv t1 = tcg_temp_new();
3426 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3427 tcg_gen_extu_i32_tl(t1, t0);
3428 tcg_temp_free_i32(t0);
3429 gen_qemu_st32(ctx, t1, arg2);
3430 tcg_temp_free(t1);
3431}
3432
3433/* stfd stfdu stfdux stfdx */
3434GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3435/* stfs stfsu stfsux stfsx */
3436GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3437
3438/* Optional: */
3439static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3440{
3441 TCGv t0 = tcg_temp_new();
3442 tcg_gen_trunc_i64_tl(t0, arg1),
3443 gen_qemu_st32(ctx, t0, arg2);
3444 tcg_temp_free(t0);
3445}
3446/* stfiwx */
3447GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3448
3449static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3450{
3451#if defined(TARGET_PPC64)
3452 if (ctx->has_cfar)
3453 tcg_gen_movi_tl(cpu_cfar, nip);
3454#endif
3455}
3456
3457/*** Branch ***/
3458static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3459{
3460 TranslationBlock *tb;
3461 tb = ctx->tb;
3462#if defined(TARGET_PPC64)
3463 if (!ctx->sf_mode)
3464 dest = (uint32_t) dest;
3465#endif
3466 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3467 likely(!ctx->singlestep_enabled)) {
3468 tcg_gen_goto_tb(n);
3469 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3470 tcg_gen_exit_tb((tcg_target_long)tb + n);
3471 } else {
3472 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3473 if (unlikely(ctx->singlestep_enabled)) {
3474 if ((ctx->singlestep_enabled &
3475 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3476 (ctx->exception == POWERPC_EXCP_BRANCH ||
3477 ctx->exception == POWERPC_EXCP_TRACE)) {
3478 target_ulong tmp = ctx->nip;
3479 ctx->nip = dest;
3480 gen_exception(ctx, POWERPC_EXCP_TRACE);
3481 ctx->nip = tmp;
3482 }
3483 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3484 gen_debug_exception(ctx);
3485 }
3486 }
3487 tcg_gen_exit_tb(0);
3488 }
3489}
3490
3491static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3492{
3493#if defined(TARGET_PPC64)
3494 if (ctx->sf_mode == 0)
3495 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3496 else
3497#endif
3498 tcg_gen_movi_tl(cpu_lr, nip);
3499}
3500
3501/* b ba bl bla */
3502static void gen_b(DisasContext *ctx)
3503{
3504 target_ulong li, target;
3505
3506 ctx->exception = POWERPC_EXCP_BRANCH;
3507 /* sign extend LI */
3508#if defined(TARGET_PPC64)
3509 if (ctx->sf_mode)
3510 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3511 else
3512#endif
3513 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3514 if (likely(AA(ctx->opcode) == 0))
3515 target = ctx->nip + li - 4;
3516 else
3517 target = li;
3518 if (LK(ctx->opcode))
3519 gen_setlr(ctx, ctx->nip);
3520 gen_update_cfar(ctx, ctx->nip);
3521 gen_goto_tb(ctx, 0, target);
3522}
3523
3524#define BCOND_IM 0
3525#define BCOND_LR 1
3526#define BCOND_CTR 2
3527
3528static inline void gen_bcond(DisasContext *ctx, int type)
3529{
3530 uint32_t bo = BO(ctx->opcode);
3531 int l1;
3532 TCGv target;
3533
3534 ctx->exception = POWERPC_EXCP_BRANCH;
3535 if (type == BCOND_LR || type == BCOND_CTR) {
3536 target = tcg_temp_local_new();
3537 if (type == BCOND_CTR)
3538 tcg_gen_mov_tl(target, cpu_ctr);
3539 else
3540 tcg_gen_mov_tl(target, cpu_lr);
3541 } else {
3542 TCGV_UNUSED(target);
3543 }
3544 if (LK(ctx->opcode))
3545 gen_setlr(ctx, ctx->nip);
3546 l1 = gen_new_label();
3547 if ((bo & 0x4) == 0) {
3548 /* Decrement and test CTR */
3549 TCGv temp = tcg_temp_new();
3550 if (unlikely(type == BCOND_CTR)) {
3551 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3552 return;
3553 }
3554 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3555#if defined(TARGET_PPC64)
3556 if (!ctx->sf_mode)
3557 tcg_gen_ext32u_tl(temp, cpu_ctr);
3558 else
3559#endif
3560 tcg_gen_mov_tl(temp, cpu_ctr);
3561 if (bo & 0x2) {
3562 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3563 } else {
3564 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3565 }
3566 tcg_temp_free(temp);
3567 }
3568 if ((bo & 0x10) == 0) {
3569 /* Test CR */
3570 uint32_t bi = BI(ctx->opcode);
3571 uint32_t mask = 1 << (3 - (bi & 0x03));
3572 TCGv_i32 temp = tcg_temp_new_i32();
3573
3574 if (bo & 0x8) {
3575 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3576 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3577 } else {
3578 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3579 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3580 }
3581 tcg_temp_free_i32(temp);
3582 }
3583 gen_update_cfar(ctx, ctx->nip);
3584 if (type == BCOND_IM) {
3585 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3586 if (likely(AA(ctx->opcode) == 0)) {
3587 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3588 } else {
3589 gen_goto_tb(ctx, 0, li);
3590 }
3591 gen_set_label(l1);
3592 gen_goto_tb(ctx, 1, ctx->nip);
3593 } else {
3594#if defined(TARGET_PPC64)
3595 if (!(ctx->sf_mode))
3596 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3597 else
3598#endif
3599 tcg_gen_andi_tl(cpu_nip, target, ~3);
3600 tcg_gen_exit_tb(0);
3601 gen_set_label(l1);
3602#if defined(TARGET_PPC64)
3603 if (!(ctx->sf_mode))
3604 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3605 else
3606#endif
3607 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3608 tcg_gen_exit_tb(0);
3609 }
3610}
3611
3612static void gen_bc(DisasContext *ctx)
3613{
3614 gen_bcond(ctx, BCOND_IM);
3615}
3616
3617static void gen_bcctr(DisasContext *ctx)
3618{
3619 gen_bcond(ctx, BCOND_CTR);
3620}
3621
3622static void gen_bclr(DisasContext *ctx)
3623{
3624 gen_bcond(ctx, BCOND_LR);
3625}
3626
3627/*** Condition register logical ***/
3628#define GEN_CRLOGIC(name, tcg_op, opc) \
3629static void glue(gen_, name)(DisasContext *ctx) \
3630{ \
3631 uint8_t bitmask; \
3632 int sh; \
3633 TCGv_i32 t0, t1; \
3634 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3635 t0 = tcg_temp_new_i32(); \
3636 if (sh > 0) \
3637 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3638 else if (sh < 0) \
3639 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3640 else \
3641 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3642 t1 = tcg_temp_new_i32(); \
3643 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3644 if (sh > 0) \
3645 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3646 else if (sh < 0) \
3647 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3648 else \
3649 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3650 tcg_op(t0, t0, t1); \
3651 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3652 tcg_gen_andi_i32(t0, t0, bitmask); \
3653 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3654 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3655 tcg_temp_free_i32(t0); \
3656 tcg_temp_free_i32(t1); \
3657}
3658
3659/* crand */
3660GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3661/* crandc */
3662GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3663/* creqv */
3664GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3665/* crnand */
3666GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3667/* crnor */
3668GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3669/* cror */
3670GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3671/* crorc */
3672GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3673/* crxor */
3674GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3675
3676/* mcrf */
3677static void gen_mcrf(DisasContext *ctx)
3678{
3679 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3680}
3681
3682/*** System linkage ***/
3683
3684/* rfi (mem_idx only) */
3685static void gen_rfi(DisasContext *ctx)
3686{
3687#if defined(CONFIG_USER_ONLY)
3688 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3689#else
3690 /* Restore CPU state */
3691 if (unlikely(!ctx->mem_idx)) {
3692 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3693 return;
3694 }
3695 gen_update_cfar(ctx, ctx->nip);
3696 gen_helper_rfi(cpu_env);
3697 gen_sync_exception(ctx);
3698#endif
3699}
3700
3701#if defined(TARGET_PPC64)
3702static void gen_rfid(DisasContext *ctx)
3703{
3704#if defined(CONFIG_USER_ONLY)
3705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3706#else
3707 /* Restore CPU state */
3708 if (unlikely(!ctx->mem_idx)) {
3709 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3710 return;
3711 }
3712 gen_update_cfar(ctx, ctx->nip);
3713 gen_helper_rfid(cpu_env);
3714 gen_sync_exception(ctx);
3715#endif
3716}
3717
3718static void gen_hrfid(DisasContext *ctx)
3719{
3720#if defined(CONFIG_USER_ONLY)
3721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3722#else
3723 /* Restore CPU state */
3724 if (unlikely(ctx->mem_idx <= 1)) {
3725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3726 return;
3727 }
3728 gen_helper_hrfid(cpu_env);
3729 gen_sync_exception(ctx);
3730#endif
3731}
3732#endif
3733
3734/* sc */
3735#if defined(CONFIG_USER_ONLY)
3736#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3737#else
3738#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3739#endif
3740static void gen_sc(DisasContext *ctx)
3741{
3742 uint32_t lev;
3743
3744 lev = (ctx->opcode >> 5) & 0x7F;
3745 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3746}
3747
3748/*** Trap ***/
3749
3750/* tw */
3751static void gen_tw(DisasContext *ctx)
3752{
3753 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3754 /* Update the nip since this might generate a trap exception */
3755 gen_update_nip(ctx, ctx->nip);
3756 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3757 t0);
3758 tcg_temp_free_i32(t0);
3759}
3760
3761/* twi */
3762static void gen_twi(DisasContext *ctx)
3763{
3764 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3765 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3766 /* Update the nip since this might generate a trap exception */
3767 gen_update_nip(ctx, ctx->nip);
3768 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3769 tcg_temp_free(t0);
3770 tcg_temp_free_i32(t1);
3771}
3772
3773#if defined(TARGET_PPC64)
3774/* td */
3775static void gen_td(DisasContext *ctx)
3776{
3777 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3778 /* Update the nip since this might generate a trap exception */
3779 gen_update_nip(ctx, ctx->nip);
3780 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3781 t0);
3782 tcg_temp_free_i32(t0);
3783}
3784
3785/* tdi */
3786static void gen_tdi(DisasContext *ctx)
3787{
3788 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3789 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3790 /* Update the nip since this might generate a trap exception */
3791 gen_update_nip(ctx, ctx->nip);
3792 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3793 tcg_temp_free(t0);
3794 tcg_temp_free_i32(t1);
3795}
3796#endif
3797
3798/*** Processor control ***/
3799
3800/* mcrxr */
3801static void gen_mcrxr(DisasContext *ctx)
3802{
3803 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3804 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3805 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
3806}
3807
3808/* mfcr mfocrf */
3809static void gen_mfcr(DisasContext *ctx)
3810{
3811 uint32_t crm, crn;
3812
3813 if (likely(ctx->opcode & 0x00100000)) {
3814 crm = CRM(ctx->opcode);
3815 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3816 crn = ctz32 (crm);
3817 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3818 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3819 cpu_gpr[rD(ctx->opcode)], crn * 4);
3820 }
3821 } else {
3822 TCGv_i32 t0 = tcg_temp_new_i32();
3823 tcg_gen_mov_i32(t0, cpu_crf[0]);
3824 tcg_gen_shli_i32(t0, t0, 4);
3825 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3826 tcg_gen_shli_i32(t0, t0, 4);
3827 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3828 tcg_gen_shli_i32(t0, t0, 4);
3829 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3830 tcg_gen_shli_i32(t0, t0, 4);
3831 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3832 tcg_gen_shli_i32(t0, t0, 4);
3833 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3834 tcg_gen_shli_i32(t0, t0, 4);
3835 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3836 tcg_gen_shli_i32(t0, t0, 4);
3837 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3838 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3839 tcg_temp_free_i32(t0);
3840 }
3841}
3842
3843/* mfmsr */
3844static void gen_mfmsr(DisasContext *ctx)
3845{
3846#if defined(CONFIG_USER_ONLY)
3847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3848#else
3849 if (unlikely(!ctx->mem_idx)) {
3850 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3851 return;
3852 }
3853 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3854#endif
3855}
3856
3857static void spr_noaccess(void *opaque, int gprn, int sprn)
3858{
3859#if 0
3860 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3861 printf("ERROR: try to access SPR %d !\n", sprn);
3862#endif
3863}
3864#define SPR_NOACCESS (&spr_noaccess)
3865
3866/* mfspr */
3867static inline void gen_op_mfspr(DisasContext *ctx)
3868{
3869 void (*read_cb)(void *opaque, int gprn, int sprn);
3870 uint32_t sprn = SPR(ctx->opcode);
3871
3872#if !defined(CONFIG_USER_ONLY)
3873 if (ctx->mem_idx == 2)
3874 read_cb = ctx->spr_cb[sprn].hea_read;
3875 else if (ctx->mem_idx)
3876 read_cb = ctx->spr_cb[sprn].oea_read;
3877 else
3878#endif
3879 read_cb = ctx->spr_cb[sprn].uea_read;
3880 if (likely(read_cb != NULL)) {
3881 if (likely(read_cb != SPR_NOACCESS)) {
3882 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3883 } else {
3884 /* Privilege exception */
3885 /* This is a hack to avoid warnings when running Linux:
3886 * this OS breaks the PowerPC virtualisation model,
3887 * allowing userland application to read the PVR
3888 */
3889 if (sprn != SPR_PVR) {
3890 qemu_log("Trying to read privileged spr %d %03x at "
3891 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3892 printf("Trying to read privileged spr %d %03x at "
3893 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3894 }
3895 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3896 }
3897 } else {
3898 /* Not defined */
3899 qemu_log("Trying to read invalid spr %d %03x at "
3900 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3901 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3902 sprn, sprn, ctx->nip);
3903 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3904 }
3905}
3906
3907static void gen_mfspr(DisasContext *ctx)
3908{
3909 gen_op_mfspr(ctx);
3910}
3911
3912/* mftb */
3913static void gen_mftb(DisasContext *ctx)
3914{
3915 gen_op_mfspr(ctx);
3916}
3917
3918/* mtcrf mtocrf*/
3919static void gen_mtcrf(DisasContext *ctx)
3920{
3921 uint32_t crm, crn;
3922
3923 crm = CRM(ctx->opcode);
3924 if (likely((ctx->opcode & 0x00100000))) {
3925 if (crm && ((crm & (crm - 1)) == 0)) {
3926 TCGv_i32 temp = tcg_temp_new_i32();
3927 crn = ctz32 (crm);
3928 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3929 tcg_gen_shri_i32(temp, temp, crn * 4);
3930 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3931 tcg_temp_free_i32(temp);
3932 }
3933 } else {
3934 TCGv_i32 temp = tcg_temp_new_i32();
3935 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3936 for (crn = 0 ; crn < 8 ; crn++) {
3937 if (crm & (1 << crn)) {
3938 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3939 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3940 }
3941 }
3942 tcg_temp_free_i32(temp);
3943 }
3944}
3945
3946/* mtmsr */
3947#if defined(TARGET_PPC64)
3948static void gen_mtmsrd(DisasContext *ctx)
3949{
3950#if defined(CONFIG_USER_ONLY)
3951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3952#else
3953 if (unlikely(!ctx->mem_idx)) {
3954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3955 return;
3956 }
3957 if (ctx->opcode & 0x00010000) {
3958 /* Special form that does not need any synchronisation */
3959 TCGv t0 = tcg_temp_new();
3960 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3961 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3962 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3963 tcg_temp_free(t0);
3964 } else {
3965 /* XXX: we need to update nip before the store
3966 * if we enter power saving mode, we will exit the loop
3967 * directly from ppc_store_msr
3968 */
3969 gen_update_nip(ctx, ctx->nip);
3970 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3971 /* Must stop the translation as machine state (may have) changed */
3972 /* Note that mtmsr is not always defined as context-synchronizing */
3973 gen_stop_exception(ctx);
3974 }
3975#endif
3976}
3977#endif
3978
3979static void gen_mtmsr(DisasContext *ctx)
3980{
3981#if defined(CONFIG_USER_ONLY)
3982 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3983#else
3984 if (unlikely(!ctx->mem_idx)) {
3985 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3986 return;
3987 }
3988 if (ctx->opcode & 0x00010000) {
3989 /* Special form that does not need any synchronisation */
3990 TCGv t0 = tcg_temp_new();
3991 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3992 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3993 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3994 tcg_temp_free(t0);
3995 } else {
3996 TCGv msr = tcg_temp_new();
3997
3998 /* XXX: we need to update nip before the store
3999 * if we enter power saving mode, we will exit the loop
4000 * directly from ppc_store_msr
4001 */
4002 gen_update_nip(ctx, ctx->nip);
4003#if defined(TARGET_PPC64)
4004 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4005#else
4006 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4007#endif
4008 gen_helper_store_msr(cpu_env, msr);
4009 /* Must stop the translation as machine state (may have) changed */
4010 /* Note that mtmsr is not always defined as context-synchronizing */
4011 gen_stop_exception(ctx);
4012 }
4013#endif
4014}
4015
4016/* mtspr */
4017static void gen_mtspr(DisasContext *ctx)
4018{
4019 void (*write_cb)(void *opaque, int sprn, int gprn);
4020 uint32_t sprn = SPR(ctx->opcode);
4021
4022#if !defined(CONFIG_USER_ONLY)
4023 if (ctx->mem_idx == 2)
4024 write_cb = ctx->spr_cb[sprn].hea_write;
4025 else if (ctx->mem_idx)
4026 write_cb = ctx->spr_cb[sprn].oea_write;
4027 else
4028#endif
4029 write_cb = ctx->spr_cb[sprn].uea_write;
4030 if (likely(write_cb != NULL)) {
4031 if (likely(write_cb != SPR_NOACCESS)) {
4032 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4033 } else {
4034 /* Privilege exception */
4035 qemu_log("Trying to write privileged spr %d %03x at "
4036 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4037 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
4038 "\n", sprn, sprn, ctx->nip);
4039 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4040 }
4041 } else {
4042 /* Not defined */
4043 qemu_log("Trying to write invalid spr %d %03x at "
4044 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
4045 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
4046 sprn, sprn, ctx->nip);
4047 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4048 }
4049}
4050
4051/*** Cache management ***/
4052
4053/* dcbf */
4054static void gen_dcbf(DisasContext *ctx)
4055{
4056 /* XXX: specification says this is treated as a load by the MMU */
4057 TCGv t0;
4058 gen_set_access_type(ctx, ACCESS_CACHE);
4059 t0 = tcg_temp_new();
4060 gen_addr_reg_index(ctx, t0);
4061 gen_qemu_ld8u(ctx, t0, t0);
4062 tcg_temp_free(t0);
4063}
4064
4065/* dcbi (Supervisor only) */
4066static void gen_dcbi(DisasContext *ctx)
4067{
4068#if defined(CONFIG_USER_ONLY)
4069 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4070#else
4071 TCGv EA, val;
4072 if (unlikely(!ctx->mem_idx)) {
4073 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4074 return;
4075 }
4076 EA = tcg_temp_new();
4077 gen_set_access_type(ctx, ACCESS_CACHE);
4078 gen_addr_reg_index(ctx, EA);
4079 val = tcg_temp_new();
4080 /* XXX: specification says this should be treated as a store by the MMU */
4081 gen_qemu_ld8u(ctx, val, EA);
4082 gen_qemu_st8(ctx, val, EA);
4083 tcg_temp_free(val);
4084 tcg_temp_free(EA);
4085#endif
4086}
4087
4088/* dcdst */
4089static void gen_dcbst(DisasContext *ctx)
4090{
4091 /* XXX: specification say this is treated as a load by the MMU */
4092 TCGv t0;
4093 gen_set_access_type(ctx, ACCESS_CACHE);
4094 t0 = tcg_temp_new();
4095 gen_addr_reg_index(ctx, t0);
4096 gen_qemu_ld8u(ctx, t0, t0);
4097 tcg_temp_free(t0);
4098}
4099
4100/* dcbt */
4101static void gen_dcbt(DisasContext *ctx)
4102{
4103 /* interpreted as no-op */
4104 /* XXX: specification say this is treated as a load by the MMU
4105 * but does not generate any exception
4106 */
4107}
4108
4109/* dcbtst */
4110static void gen_dcbtst(DisasContext *ctx)
4111{
4112 /* interpreted as no-op */
4113 /* XXX: specification say this is treated as a load by the MMU
4114 * but does not generate any exception
4115 */
4116}
4117
4118/* dcbz */
4119static void gen_dcbz(DisasContext *ctx)
4120{
4121 TCGv t0;
4122 gen_set_access_type(ctx, ACCESS_CACHE);
4123 /* NIP cannot be restored if the memory exception comes from an helper */
4124 gen_update_nip(ctx, ctx->nip - 4);
4125 t0 = tcg_temp_new();
4126 gen_addr_reg_index(ctx, t0);
4127 gen_helper_dcbz(cpu_env, t0);
4128 tcg_temp_free(t0);
4129}
4130
4131static void gen_dcbz_970(DisasContext *ctx)
4132{
4133 TCGv t0;
4134 gen_set_access_type(ctx, ACCESS_CACHE);
4135 /* NIP cannot be restored if the memory exception comes from an helper */
4136 gen_update_nip(ctx, ctx->nip - 4);
4137 t0 = tcg_temp_new();
4138 gen_addr_reg_index(ctx, t0);
4139 if (ctx->opcode & 0x00200000)
4140 gen_helper_dcbz(cpu_env, t0);
4141 else
4142 gen_helper_dcbz_970(cpu_env, t0);
4143 tcg_temp_free(t0);
4144}
4145
4146/* dst / dstt */
4147static void gen_dst(DisasContext *ctx)
4148{
4149 if (rA(ctx->opcode) == 0) {
4150 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4151 } else {
4152 /* interpreted as no-op */
4153 }
4154}
4155
4156/* dstst /dststt */
4157static void gen_dstst(DisasContext *ctx)
4158{
4159 if (rA(ctx->opcode) == 0) {
4160 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4161 } else {
4162 /* interpreted as no-op */
4163 }
4164
4165}
4166
4167/* dss / dssall */
4168static void gen_dss(DisasContext *ctx)
4169{
4170 /* interpreted as no-op */
4171}
4172
4173/* icbi */
4174static void gen_icbi(DisasContext *ctx)
4175{
4176 TCGv t0;
4177 gen_set_access_type(ctx, ACCESS_CACHE);
4178 /* NIP cannot be restored if the memory exception comes from an helper */
4179 gen_update_nip(ctx, ctx->nip - 4);
4180 t0 = tcg_temp_new();
4181 gen_addr_reg_index(ctx, t0);
4182 gen_helper_icbi(cpu_env, t0);
4183 tcg_temp_free(t0);
4184}
4185
4186/* Optional: */
4187/* dcba */
4188static void gen_dcba(DisasContext *ctx)
4189{
4190 /* interpreted as no-op */
4191 /* XXX: specification say this is treated as a store by the MMU
4192 * but does not generate any exception
4193 */
4194}
4195
4196/*** Segment register manipulation ***/
4197/* Supervisor only: */
4198
4199/* mfsr */
4200static void gen_mfsr(DisasContext *ctx)
4201{
4202#if defined(CONFIG_USER_ONLY)
4203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4204#else
4205 TCGv t0;
4206 if (unlikely(!ctx->mem_idx)) {
4207 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4208 return;
4209 }
4210 t0 = tcg_const_tl(SR(ctx->opcode));
4211 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4212 tcg_temp_free(t0);
4213#endif
4214}
4215
4216/* mfsrin */
4217static void gen_mfsrin(DisasContext *ctx)
4218{
4219#if defined(CONFIG_USER_ONLY)
4220 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4221#else
4222 TCGv t0;
4223 if (unlikely(!ctx->mem_idx)) {
4224 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4225 return;
4226 }
4227 t0 = tcg_temp_new();
4228 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4229 tcg_gen_andi_tl(t0, t0, 0xF);
4230 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4231 tcg_temp_free(t0);
4232#endif
4233}
4234
4235/* mtsr */
4236static void gen_mtsr(DisasContext *ctx)
4237{
4238#if defined(CONFIG_USER_ONLY)
4239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4240#else
4241 TCGv t0;
4242 if (unlikely(!ctx->mem_idx)) {
4243 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4244 return;
4245 }
4246 t0 = tcg_const_tl(SR(ctx->opcode));
4247 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4248 tcg_temp_free(t0);
4249#endif
4250}
4251
4252/* mtsrin */
4253static void gen_mtsrin(DisasContext *ctx)
4254{
4255#if defined(CONFIG_USER_ONLY)
4256 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4257#else
4258 TCGv t0;
4259 if (unlikely(!ctx->mem_idx)) {
4260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4261 return;
4262 }
4263 t0 = tcg_temp_new();
4264 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4265 tcg_gen_andi_tl(t0, t0, 0xF);
4266 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4267 tcg_temp_free(t0);
4268#endif
4269}
4270
4271#if defined(TARGET_PPC64)
4272/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4273
4274/* mfsr */
4275static void gen_mfsr_64b(DisasContext *ctx)
4276{
4277#if defined(CONFIG_USER_ONLY)
4278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4279#else
4280 TCGv t0;
4281 if (unlikely(!ctx->mem_idx)) {
4282 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4283 return;
4284 }
4285 t0 = tcg_const_tl(SR(ctx->opcode));
4286 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4287 tcg_temp_free(t0);
4288#endif
4289}
4290
4291/* mfsrin */
4292static void gen_mfsrin_64b(DisasContext *ctx)
4293{
4294#if defined(CONFIG_USER_ONLY)
4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4296#else
4297 TCGv t0;
4298 if (unlikely(!ctx->mem_idx)) {
4299 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4300 return;
4301 }
4302 t0 = tcg_temp_new();
4303 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4304 tcg_gen_andi_tl(t0, t0, 0xF);
4305 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4306 tcg_temp_free(t0);
4307#endif
4308}
4309
4310/* mtsr */
4311static void gen_mtsr_64b(DisasContext *ctx)
4312{
4313#if defined(CONFIG_USER_ONLY)
4314 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4315#else
4316 TCGv t0;
4317 if (unlikely(!ctx->mem_idx)) {
4318 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4319 return;
4320 }
4321 t0 = tcg_const_tl(SR(ctx->opcode));
4322 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4323 tcg_temp_free(t0);
4324#endif
4325}
4326
4327/* mtsrin */
4328static void gen_mtsrin_64b(DisasContext *ctx)
4329{
4330#if defined(CONFIG_USER_ONLY)
4331 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4332#else
4333 TCGv t0;
4334 if (unlikely(!ctx->mem_idx)) {
4335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4336 return;
4337 }
4338 t0 = tcg_temp_new();
4339 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4340 tcg_gen_andi_tl(t0, t0, 0xF);
4341 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4342 tcg_temp_free(t0);
4343#endif
4344}
4345
4346/* slbmte */
4347static void gen_slbmte(DisasContext *ctx)
4348{
4349#if defined(CONFIG_USER_ONLY)
4350 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4351#else
4352 if (unlikely(!ctx->mem_idx)) {
4353 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4354 return;
4355 }
4356 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4357 cpu_gpr[rS(ctx->opcode)]);
4358#endif
4359}
4360
4361static void gen_slbmfee(DisasContext *ctx)
4362{
4363#if defined(CONFIG_USER_ONLY)
4364 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4365#else
4366 if (unlikely(!ctx->mem_idx)) {
4367 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4368 return;
4369 }
4370 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4371 cpu_gpr[rB(ctx->opcode)]);
4372#endif
4373}
4374
4375static void gen_slbmfev(DisasContext *ctx)
4376{
4377#if defined(CONFIG_USER_ONLY)
4378 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4379#else
4380 if (unlikely(!ctx->mem_idx)) {
4381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4382 return;
4383 }
4384 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4385 cpu_gpr[rB(ctx->opcode)]);
4386#endif
4387}
4388#endif /* defined(TARGET_PPC64) */
4389
4390/*** Lookaside buffer management ***/
4391/* Optional & mem_idx only: */
4392
4393/* tlbia */
4394static void gen_tlbia(DisasContext *ctx)
4395{
4396#if defined(CONFIG_USER_ONLY)
4397 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4398#else
4399 if (unlikely(!ctx->mem_idx)) {
4400 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4401 return;
4402 }
4403 gen_helper_tlbia(cpu_env);
4404#endif
4405}
4406
4407/* tlbiel */
4408static void gen_tlbiel(DisasContext *ctx)
4409{
4410#if defined(CONFIG_USER_ONLY)
4411 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4412#else
4413 if (unlikely(!ctx->mem_idx)) {
4414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4415 return;
4416 }
4417 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4418#endif
4419}
4420
4421/* tlbie */
4422static void gen_tlbie(DisasContext *ctx)
4423{
4424#if defined(CONFIG_USER_ONLY)
4425 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4426#else
4427 if (unlikely(!ctx->mem_idx)) {
4428 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4429 return;
4430 }
4431#if defined(TARGET_PPC64)
4432 if (!ctx->sf_mode) {
4433 TCGv t0 = tcg_temp_new();
4434 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4435 gen_helper_tlbie(cpu_env, t0);
4436 tcg_temp_free(t0);
4437 } else
4438#endif
4439 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4440#endif
4441}
4442
4443/* tlbsync */
4444static void gen_tlbsync(DisasContext *ctx)
4445{
4446#if defined(CONFIG_USER_ONLY)
4447 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4448#else
4449 if (unlikely(!ctx->mem_idx)) {
4450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4451 return;
4452 }
4453 /* This has no effect: it should ensure that all previous
4454 * tlbie have completed
4455 */
4456 gen_stop_exception(ctx);
4457#endif
4458}
4459
4460#if defined(TARGET_PPC64)
4461/* slbia */
4462static void gen_slbia(DisasContext *ctx)
4463{
4464#if defined(CONFIG_USER_ONLY)
4465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4466#else
4467 if (unlikely(!ctx->mem_idx)) {
4468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4469 return;
4470 }
4471 gen_helper_slbia(cpu_env);
4472#endif
4473}
4474
4475/* slbie */
4476static void gen_slbie(DisasContext *ctx)
4477{
4478#if defined(CONFIG_USER_ONLY)
4479 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4480#else
4481 if (unlikely(!ctx->mem_idx)) {
4482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4483 return;
4484 }
4485 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4486#endif
4487}
4488#endif
4489
4490/*** External control ***/
4491/* Optional: */
4492
4493/* eciwx */
4494static void gen_eciwx(DisasContext *ctx)
4495{
4496 TCGv t0;
4497 /* Should check EAR[E] ! */
4498 gen_set_access_type(ctx, ACCESS_EXT);
4499 t0 = tcg_temp_new();
4500 gen_addr_reg_index(ctx, t0);
4501 gen_check_align(ctx, t0, 0x03);
4502 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4503 tcg_temp_free(t0);
4504}
4505
4506/* ecowx */
4507static void gen_ecowx(DisasContext *ctx)
4508{
4509 TCGv t0;
4510 /* Should check EAR[E] ! */
4511 gen_set_access_type(ctx, ACCESS_EXT);
4512 t0 = tcg_temp_new();
4513 gen_addr_reg_index(ctx, t0);
4514 gen_check_align(ctx, t0, 0x03);
4515 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4516 tcg_temp_free(t0);
4517}
4518
4519/* PowerPC 601 specific instructions */
4520
4521/* abs - abs. */
4522static void gen_abs(DisasContext *ctx)
4523{
4524 int l1 = gen_new_label();
4525 int l2 = gen_new_label();
4526 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4527 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4528 tcg_gen_br(l2);
4529 gen_set_label(l1);
4530 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4531 gen_set_label(l2);
4532 if (unlikely(Rc(ctx->opcode) != 0))
4533 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4534}
4535
4536/* abso - abso. */
4537static void gen_abso(DisasContext *ctx)
4538{
4539 int l1 = gen_new_label();
4540 int l2 = gen_new_label();
4541 int l3 = gen_new_label();
4542 /* Start with XER OV disabled, the most likely case */
4543 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4544 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4545 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4546 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4547 tcg_gen_br(l2);
4548 gen_set_label(l1);
4549 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4550 tcg_gen_br(l3);
4551 gen_set_label(l2);
4552 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4553 gen_set_label(l3);
4554 if (unlikely(Rc(ctx->opcode) != 0))
4555 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4556}
4557
4558/* clcs */
4559static void gen_clcs(DisasContext *ctx)
4560{
4561 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4562 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4563 tcg_temp_free_i32(t0);
4564 /* Rc=1 sets CR0 to an undefined state */
4565}
4566
4567/* div - div. */
4568static void gen_div(DisasContext *ctx)
4569{
4570 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4571 cpu_gpr[rB(ctx->opcode)]);
4572 if (unlikely(Rc(ctx->opcode) != 0))
4573 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4574}
4575
4576/* divo - divo. */
4577static void gen_divo(DisasContext *ctx)
4578{
4579 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4580 cpu_gpr[rB(ctx->opcode)]);
4581 if (unlikely(Rc(ctx->opcode) != 0))
4582 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4583}
4584
4585/* divs - divs. */
4586static void gen_divs(DisasContext *ctx)
4587{
4588 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4589 cpu_gpr[rB(ctx->opcode)]);
4590 if (unlikely(Rc(ctx->opcode) != 0))
4591 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4592}
4593
4594/* divso - divso. */
4595static void gen_divso(DisasContext *ctx)
4596{
4597 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4598 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4599 if (unlikely(Rc(ctx->opcode) != 0))
4600 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4601}
4602
4603/* doz - doz. */
4604static void gen_doz(DisasContext *ctx)
4605{
4606 int l1 = gen_new_label();
4607 int l2 = gen_new_label();
4608 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4609 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4610 tcg_gen_br(l2);
4611 gen_set_label(l1);
4612 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4613 gen_set_label(l2);
4614 if (unlikely(Rc(ctx->opcode) != 0))
4615 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4616}
4617
4618/* dozo - dozo. */
4619static void gen_dozo(DisasContext *ctx)
4620{
4621 int l1 = gen_new_label();
4622 int l2 = gen_new_label();
4623 TCGv t0 = tcg_temp_new();
4624 TCGv t1 = tcg_temp_new();
4625 TCGv t2 = tcg_temp_new();
4626 /* Start with XER OV disabled, the most likely case */
4627 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4628 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4629 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4630 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4631 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4632 tcg_gen_andc_tl(t1, t1, t2);
4633 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4634 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4635 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4636 tcg_gen_br(l2);
4637 gen_set_label(l1);
4638 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4639 gen_set_label(l2);
4640 tcg_temp_free(t0);
4641 tcg_temp_free(t1);
4642 tcg_temp_free(t2);
4643 if (unlikely(Rc(ctx->opcode) != 0))
4644 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4645}
4646
4647/* dozi */
4648static void gen_dozi(DisasContext *ctx)
4649{
4650 target_long simm = SIMM(ctx->opcode);
4651 int l1 = gen_new_label();
4652 int l2 = gen_new_label();
4653 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4654 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4655 tcg_gen_br(l2);
4656 gen_set_label(l1);
4657 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4658 gen_set_label(l2);
4659 if (unlikely(Rc(ctx->opcode) != 0))
4660 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4661}
4662
4663/* lscbx - lscbx. */
4664static void gen_lscbx(DisasContext *ctx)
4665{
4666 TCGv t0 = tcg_temp_new();
4667 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4668 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4669 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4670
4671 gen_addr_reg_index(ctx, t0);
4672 /* NIP cannot be restored if the memory exception comes from an helper */
4673 gen_update_nip(ctx, ctx->nip - 4);
4674 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4675 tcg_temp_free_i32(t1);
4676 tcg_temp_free_i32(t2);
4677 tcg_temp_free_i32(t3);
4678 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4679 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4680 if (unlikely(Rc(ctx->opcode) != 0))
4681 gen_set_Rc0(ctx, t0);
4682 tcg_temp_free(t0);
4683}
4684
4685/* maskg - maskg. */
4686static void gen_maskg(DisasContext *ctx)
4687{
4688 int l1 = gen_new_label();
4689 TCGv t0 = tcg_temp_new();
4690 TCGv t1 = tcg_temp_new();
4691 TCGv t2 = tcg_temp_new();
4692 TCGv t3 = tcg_temp_new();
4693 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4694 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4695 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4696 tcg_gen_addi_tl(t2, t0, 1);
4697 tcg_gen_shr_tl(t2, t3, t2);
4698 tcg_gen_shr_tl(t3, t3, t1);
4699 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4700 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4701 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4702 gen_set_label(l1);
4703 tcg_temp_free(t0);
4704 tcg_temp_free(t1);
4705 tcg_temp_free(t2);
4706 tcg_temp_free(t3);
4707 if (unlikely(Rc(ctx->opcode) != 0))
4708 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4709}
4710
4711/* maskir - maskir. */
4712static void gen_maskir(DisasContext *ctx)
4713{
4714 TCGv t0 = tcg_temp_new();
4715 TCGv t1 = tcg_temp_new();
4716 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4717 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4718 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4719 tcg_temp_free(t0);
4720 tcg_temp_free(t1);
4721 if (unlikely(Rc(ctx->opcode) != 0))
4722 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4723}
4724
4725/* mul - mul. */
4726static void gen_mul(DisasContext *ctx)
4727{
4728 TCGv_i64 t0 = tcg_temp_new_i64();
4729 TCGv_i64 t1 = tcg_temp_new_i64();
4730 TCGv t2 = tcg_temp_new();
4731 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4732 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4733 tcg_gen_mul_i64(t0, t0, t1);
4734 tcg_gen_trunc_i64_tl(t2, t0);
4735 gen_store_spr(SPR_MQ, t2);
4736 tcg_gen_shri_i64(t1, t0, 32);
4737 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4738 tcg_temp_free_i64(t0);
4739 tcg_temp_free_i64(t1);
4740 tcg_temp_free(t2);
4741 if (unlikely(Rc(ctx->opcode) != 0))
4742 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4743}
4744
4745/* mulo - mulo. */
4746static void gen_mulo(DisasContext *ctx)
4747{
4748 int l1 = gen_new_label();
4749 TCGv_i64 t0 = tcg_temp_new_i64();
4750 TCGv_i64 t1 = tcg_temp_new_i64();
4751 TCGv t2 = tcg_temp_new();
4752 /* Start with XER OV disabled, the most likely case */
4753 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4754 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4755 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4756 tcg_gen_mul_i64(t0, t0, t1);
4757 tcg_gen_trunc_i64_tl(t2, t0);
4758 gen_store_spr(SPR_MQ, t2);
4759 tcg_gen_shri_i64(t1, t0, 32);
4760 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4761 tcg_gen_ext32s_i64(t1, t0);
4762 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4763 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4764 gen_set_label(l1);
4765 tcg_temp_free_i64(t0);
4766 tcg_temp_free_i64(t1);
4767 tcg_temp_free(t2);
4768 if (unlikely(Rc(ctx->opcode) != 0))
4769 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4770}
4771
4772/* nabs - nabs. */
4773static void gen_nabs(DisasContext *ctx)
4774{
4775 int l1 = gen_new_label();
4776 int l2 = gen_new_label();
4777 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4778 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4779 tcg_gen_br(l2);
4780 gen_set_label(l1);
4781 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4782 gen_set_label(l2);
4783 if (unlikely(Rc(ctx->opcode) != 0))
4784 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4785}
4786
4787/* nabso - nabso. */
4788static void gen_nabso(DisasContext *ctx)
4789{
4790 int l1 = gen_new_label();
4791 int l2 = gen_new_label();
4792 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4793 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4794 tcg_gen_br(l2);
4795 gen_set_label(l1);
4796 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4797 gen_set_label(l2);
4798 /* nabs never overflows */
4799 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4800 if (unlikely(Rc(ctx->opcode) != 0))
4801 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4802}
4803
4804/* rlmi - rlmi. */
4805static void gen_rlmi(DisasContext *ctx)
4806{
4807 uint32_t mb = MB(ctx->opcode);
4808 uint32_t me = ME(ctx->opcode);
4809 TCGv t0 = tcg_temp_new();
4810 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4811 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4812 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4813 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4814 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4815 tcg_temp_free(t0);
4816 if (unlikely(Rc(ctx->opcode) != 0))
4817 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4818}
4819
4820/* rrib - rrib. */
4821static void gen_rrib(DisasContext *ctx)
4822{
4823 TCGv t0 = tcg_temp_new();
4824 TCGv t1 = tcg_temp_new();
4825 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4826 tcg_gen_movi_tl(t1, 0x80000000);
4827 tcg_gen_shr_tl(t1, t1, t0);
4828 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4829 tcg_gen_and_tl(t0, t0, t1);
4830 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4831 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4832 tcg_temp_free(t0);
4833 tcg_temp_free(t1);
4834 if (unlikely(Rc(ctx->opcode) != 0))
4835 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4836}
4837
4838/* sle - sle. */
4839static void gen_sle(DisasContext *ctx)
4840{
4841 TCGv t0 = tcg_temp_new();
4842 TCGv t1 = tcg_temp_new();
4843 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4844 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4845 tcg_gen_subfi_tl(t1, 32, t1);
4846 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4847 tcg_gen_or_tl(t1, t0, t1);
4848 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4849 gen_store_spr(SPR_MQ, t1);
4850 tcg_temp_free(t0);
4851 tcg_temp_free(t1);
4852 if (unlikely(Rc(ctx->opcode) != 0))
4853 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4854}
4855
4856/* sleq - sleq. */
4857static void gen_sleq(DisasContext *ctx)
4858{
4859 TCGv t0 = tcg_temp_new();
4860 TCGv t1 = tcg_temp_new();
4861 TCGv t2 = tcg_temp_new();
4862 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4863 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4864 tcg_gen_shl_tl(t2, t2, t0);
4865 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4866 gen_load_spr(t1, SPR_MQ);
4867 gen_store_spr(SPR_MQ, t0);
4868 tcg_gen_and_tl(t0, t0, t2);
4869 tcg_gen_andc_tl(t1, t1, t2);
4870 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4871 tcg_temp_free(t0);
4872 tcg_temp_free(t1);
4873 tcg_temp_free(t2);
4874 if (unlikely(Rc(ctx->opcode) != 0))
4875 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4876}
4877
4878/* sliq - sliq. */
4879static void gen_sliq(DisasContext *ctx)
4880{
4881 int sh = SH(ctx->opcode);
4882 TCGv t0 = tcg_temp_new();
4883 TCGv t1 = tcg_temp_new();
4884 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4885 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4886 tcg_gen_or_tl(t1, t0, t1);
4887 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4888 gen_store_spr(SPR_MQ, t1);
4889 tcg_temp_free(t0);
4890 tcg_temp_free(t1);
4891 if (unlikely(Rc(ctx->opcode) != 0))
4892 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4893}
4894
4895/* slliq - slliq. */
4896static void gen_slliq(DisasContext *ctx)
4897{
4898 int sh = SH(ctx->opcode);
4899 TCGv t0 = tcg_temp_new();
4900 TCGv t1 = tcg_temp_new();
4901 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4902 gen_load_spr(t1, SPR_MQ);
4903 gen_store_spr(SPR_MQ, t0);
4904 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4905 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4906 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4907 tcg_temp_free(t0);
4908 tcg_temp_free(t1);
4909 if (unlikely(Rc(ctx->opcode) != 0))
4910 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4911}
4912
4913/* sllq - sllq. */
4914static void gen_sllq(DisasContext *ctx)
4915{
4916 int l1 = gen_new_label();
4917 int l2 = gen_new_label();
4918 TCGv t0 = tcg_temp_local_new();
4919 TCGv t1 = tcg_temp_local_new();
4920 TCGv t2 = tcg_temp_local_new();
4921 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4922 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4923 tcg_gen_shl_tl(t1, t1, t2);
4924 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4925 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4926 gen_load_spr(t0, SPR_MQ);
4927 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4928 tcg_gen_br(l2);
4929 gen_set_label(l1);
4930 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4931 gen_load_spr(t2, SPR_MQ);
4932 tcg_gen_andc_tl(t1, t2, t1);
4933 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4934 gen_set_label(l2);
4935 tcg_temp_free(t0);
4936 tcg_temp_free(t1);
4937 tcg_temp_free(t2);
4938 if (unlikely(Rc(ctx->opcode) != 0))
4939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4940}
4941
4942/* slq - slq. */
4943static void gen_slq(DisasContext *ctx)
4944{
4945 int l1 = gen_new_label();
4946 TCGv t0 = tcg_temp_new();
4947 TCGv t1 = tcg_temp_new();
4948 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4949 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4950 tcg_gen_subfi_tl(t1, 32, t1);
4951 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4952 tcg_gen_or_tl(t1, t0, t1);
4953 gen_store_spr(SPR_MQ, t1);
4954 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4955 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4956 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4957 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4958 gen_set_label(l1);
4959 tcg_temp_free(t0);
4960 tcg_temp_free(t1);
4961 if (unlikely(Rc(ctx->opcode) != 0))
4962 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4963}
4964
4965/* sraiq - sraiq. */
4966static void gen_sraiq(DisasContext *ctx)
4967{
4968 int sh = SH(ctx->opcode);
4969 int l1 = gen_new_label();
4970 TCGv t0 = tcg_temp_new();
4971 TCGv t1 = tcg_temp_new();
4972 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4973 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4974 tcg_gen_or_tl(t0, t0, t1);
4975 gen_store_spr(SPR_MQ, t0);
4976 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4977 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4978 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4979 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4980 gen_set_label(l1);
4981 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4982 tcg_temp_free(t0);
4983 tcg_temp_free(t1);
4984 if (unlikely(Rc(ctx->opcode) != 0))
4985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4986}
4987
4988/* sraq - sraq. */
4989static void gen_sraq(DisasContext *ctx)
4990{
4991 int l1 = gen_new_label();
4992 int l2 = gen_new_label();
4993 TCGv t0 = tcg_temp_new();
4994 TCGv t1 = tcg_temp_local_new();
4995 TCGv t2 = tcg_temp_local_new();
4996 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4997 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4998 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4999 tcg_gen_subfi_tl(t2, 32, t2);
5000 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5001 tcg_gen_or_tl(t0, t0, t2);
5002 gen_store_spr(SPR_MQ, t0);
5003 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5004 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5005 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5006 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5007 gen_set_label(l1);
5008 tcg_temp_free(t0);
5009 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5010 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
5011 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5012 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5013 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
5014 gen_set_label(l2);
5015 tcg_temp_free(t1);
5016 tcg_temp_free(t2);
5017 if (unlikely(Rc(ctx->opcode) != 0))
5018 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5019}
5020
5021/* sre - sre. */
5022static void gen_sre(DisasContext *ctx)
5023{
5024 TCGv t0 = tcg_temp_new();
5025 TCGv t1 = tcg_temp_new();
5026 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5027 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5028 tcg_gen_subfi_tl(t1, 32, t1);
5029 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5030 tcg_gen_or_tl(t1, t0, t1);
5031 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5032 gen_store_spr(SPR_MQ, t1);
5033 tcg_temp_free(t0);
5034 tcg_temp_free(t1);
5035 if (unlikely(Rc(ctx->opcode) != 0))
5036 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5037}
5038
5039/* srea - srea. */
5040static void gen_srea(DisasContext *ctx)
5041{
5042 TCGv t0 = tcg_temp_new();
5043 TCGv t1 = tcg_temp_new();
5044 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5045 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5046 gen_store_spr(SPR_MQ, t0);
5047 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5048 tcg_temp_free(t0);
5049 tcg_temp_free(t1);
5050 if (unlikely(Rc(ctx->opcode) != 0))
5051 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5052}
5053
5054/* sreq */
5055static void gen_sreq(DisasContext *ctx)
5056{
5057 TCGv t0 = tcg_temp_new();
5058 TCGv t1 = tcg_temp_new();
5059 TCGv t2 = tcg_temp_new();
5060 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5061 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5062 tcg_gen_shr_tl(t1, t1, t0);
5063 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5064 gen_load_spr(t2, SPR_MQ);
5065 gen_store_spr(SPR_MQ, t0);
5066 tcg_gen_and_tl(t0, t0, t1);
5067 tcg_gen_andc_tl(t2, t2, t1);
5068 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5069 tcg_temp_free(t0);
5070 tcg_temp_free(t1);
5071 tcg_temp_free(t2);
5072 if (unlikely(Rc(ctx->opcode) != 0))
5073 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5074}
5075
5076/* sriq */
5077static void gen_sriq(DisasContext *ctx)
5078{
5079 int sh = SH(ctx->opcode);
5080 TCGv t0 = tcg_temp_new();
5081 TCGv t1 = tcg_temp_new();
5082 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5083 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5084 tcg_gen_or_tl(t1, t0, t1);
5085 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5086 gen_store_spr(SPR_MQ, t1);
5087 tcg_temp_free(t0);
5088 tcg_temp_free(t1);
5089 if (unlikely(Rc(ctx->opcode) != 0))
5090 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5091}
5092
5093/* srliq */
5094static void gen_srliq(DisasContext *ctx)
5095{
5096 int sh = SH(ctx->opcode);
5097 TCGv t0 = tcg_temp_new();
5098 TCGv t1 = tcg_temp_new();
5099 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5100 gen_load_spr(t1, SPR_MQ);
5101 gen_store_spr(SPR_MQ, t0);
5102 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5103 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5104 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5105 tcg_temp_free(t0);
5106 tcg_temp_free(t1);
5107 if (unlikely(Rc(ctx->opcode) != 0))
5108 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5109}
5110
5111/* srlq */
5112static void gen_srlq(DisasContext *ctx)
5113{
5114 int l1 = gen_new_label();
5115 int l2 = gen_new_label();
5116 TCGv t0 = tcg_temp_local_new();
5117 TCGv t1 = tcg_temp_local_new();
5118 TCGv t2 = tcg_temp_local_new();
5119 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5120 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5121 tcg_gen_shr_tl(t2, t1, t2);
5122 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5123 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5124 gen_load_spr(t0, SPR_MQ);
5125 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5126 tcg_gen_br(l2);
5127 gen_set_label(l1);
5128 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5129 tcg_gen_and_tl(t0, t0, t2);
5130 gen_load_spr(t1, SPR_MQ);
5131 tcg_gen_andc_tl(t1, t1, t2);
5132 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5133 gen_set_label(l2);
5134 tcg_temp_free(t0);
5135 tcg_temp_free(t1);
5136 tcg_temp_free(t2);
5137 if (unlikely(Rc(ctx->opcode) != 0))
5138 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5139}
5140
5141/* srq */
5142static void gen_srq(DisasContext *ctx)
5143{
5144 int l1 = gen_new_label();
5145 TCGv t0 = tcg_temp_new();
5146 TCGv t1 = tcg_temp_new();
5147 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5148 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5149 tcg_gen_subfi_tl(t1, 32, t1);
5150 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5151 tcg_gen_or_tl(t1, t0, t1);
5152 gen_store_spr(SPR_MQ, t1);
5153 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5154 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5155 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5156 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5157 gen_set_label(l1);
5158 tcg_temp_free(t0);
5159 tcg_temp_free(t1);
5160 if (unlikely(Rc(ctx->opcode) != 0))
5161 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5162}
5163
5164/* PowerPC 602 specific instructions */
5165
5166/* dsa */
5167static void gen_dsa(DisasContext *ctx)
5168{
5169 /* XXX: TODO */
5170 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5171}
5172
5173/* esa */
5174static void gen_esa(DisasContext *ctx)
5175{
5176 /* XXX: TODO */
5177 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5178}
5179
5180/* mfrom */
5181static void gen_mfrom(DisasContext *ctx)
5182{
5183#if defined(CONFIG_USER_ONLY)
5184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5185#else
5186 if (unlikely(!ctx->mem_idx)) {
5187 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5188 return;
5189 }
5190 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5191#endif
5192}
5193
5194/* 602 - 603 - G2 TLB management */
5195
5196/* tlbld */
5197static void gen_tlbld_6xx(DisasContext *ctx)
5198{
5199#if defined(CONFIG_USER_ONLY)
5200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5201#else
5202 if (unlikely(!ctx->mem_idx)) {
5203 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5204 return;
5205 }
5206 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5207#endif
5208}
5209
5210/* tlbli */
5211static void gen_tlbli_6xx(DisasContext *ctx)
5212{
5213#if defined(CONFIG_USER_ONLY)
5214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5215#else
5216 if (unlikely(!ctx->mem_idx)) {
5217 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5218 return;
5219 }
5220 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5221#endif
5222}
5223
5224/* 74xx TLB management */
5225
5226/* tlbld */
5227static void gen_tlbld_74xx(DisasContext *ctx)
5228{
5229#if defined(CONFIG_USER_ONLY)
5230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5231#else
5232 if (unlikely(!ctx->mem_idx)) {
5233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5234 return;
5235 }
5236 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5237#endif
5238}
5239
5240/* tlbli */
5241static void gen_tlbli_74xx(DisasContext *ctx)
5242{
5243#if defined(CONFIG_USER_ONLY)
5244 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5245#else
5246 if (unlikely(!ctx->mem_idx)) {
5247 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5248 return;
5249 }
5250 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5251#endif
5252}
5253
5254/* POWER instructions not in PowerPC 601 */
5255
5256/* clf */
5257static void gen_clf(DisasContext *ctx)
5258{
5259 /* Cache line flush: implemented as no-op */
5260}
5261
5262/* cli */
5263static void gen_cli(DisasContext *ctx)
5264{
5265 /* Cache line invalidate: privileged and treated as no-op */
5266#if defined(CONFIG_USER_ONLY)
5267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5268#else
5269 if (unlikely(!ctx->mem_idx)) {
5270 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5271 return;
5272 }
5273#endif
5274}
5275
5276/* dclst */
5277static void gen_dclst(DisasContext *ctx)
5278{
5279 /* Data cache line store: treated as no-op */
5280}
5281
5282static void gen_mfsri(DisasContext *ctx)
5283{
5284#if defined(CONFIG_USER_ONLY)
5285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5286#else
5287 int ra = rA(ctx->opcode);
5288 int rd = rD(ctx->opcode);
5289 TCGv t0;
5290 if (unlikely(!ctx->mem_idx)) {
5291 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5292 return;
5293 }
5294 t0 = tcg_temp_new();
5295 gen_addr_reg_index(ctx, t0);
5296 tcg_gen_shri_tl(t0, t0, 28);
5297 tcg_gen_andi_tl(t0, t0, 0xF);
5298 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5299 tcg_temp_free(t0);
5300 if (ra != 0 && ra != rd)
5301 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5302#endif
5303}
5304
5305static void gen_rac(DisasContext *ctx)
5306{
5307#if defined(CONFIG_USER_ONLY)
5308 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5309#else
5310 TCGv t0;
5311 if (unlikely(!ctx->mem_idx)) {
5312 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5313 return;
5314 }
5315 t0 = tcg_temp_new();
5316 gen_addr_reg_index(ctx, t0);
5317 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5318 tcg_temp_free(t0);
5319#endif
5320}
5321
5322static void gen_rfsvc(DisasContext *ctx)
5323{
5324#if defined(CONFIG_USER_ONLY)
5325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5326#else
5327 if (unlikely(!ctx->mem_idx)) {
5328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5329 return;
5330 }
5331 gen_helper_rfsvc(cpu_env);
5332 gen_sync_exception(ctx);
5333#endif
5334}
5335
5336/* svc is not implemented for now */
5337
5338/* POWER2 specific instructions */
5339/* Quad manipulation (load/store two floats at a time) */
5340
5341/* lfq */
5342static void gen_lfq(DisasContext *ctx)
5343{
5344 int rd = rD(ctx->opcode);
5345 TCGv t0;
5346 gen_set_access_type(ctx, ACCESS_FLOAT);
5347 t0 = tcg_temp_new();
5348 gen_addr_imm_index(ctx, t0, 0);
5349 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5350 gen_addr_add(ctx, t0, t0, 8);
5351 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5352 tcg_temp_free(t0);
5353}
5354
5355/* lfqu */
5356static void gen_lfqu(DisasContext *ctx)
5357{
5358 int ra = rA(ctx->opcode);
5359 int rd = rD(ctx->opcode);
5360 TCGv t0, t1;
5361 gen_set_access_type(ctx, ACCESS_FLOAT);
5362 t0 = tcg_temp_new();
5363 t1 = tcg_temp_new();
5364 gen_addr_imm_index(ctx, t0, 0);
5365 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5366 gen_addr_add(ctx, t1, t0, 8);
5367 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5368 if (ra != 0)
5369 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5370 tcg_temp_free(t0);
5371 tcg_temp_free(t1);
5372}
5373
5374/* lfqux */
5375static void gen_lfqux(DisasContext *ctx)
5376{
5377 int ra = rA(ctx->opcode);
5378 int rd = rD(ctx->opcode);
5379 gen_set_access_type(ctx, ACCESS_FLOAT);
5380 TCGv t0, t1;
5381 t0 = tcg_temp_new();
5382 gen_addr_reg_index(ctx, t0);
5383 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5384 t1 = tcg_temp_new();
5385 gen_addr_add(ctx, t1, t0, 8);
5386 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5387 tcg_temp_free(t1);
5388 if (ra != 0)
5389 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5390 tcg_temp_free(t0);
5391}
5392
5393/* lfqx */
5394static void gen_lfqx(DisasContext *ctx)
5395{
5396 int rd = rD(ctx->opcode);
5397 TCGv t0;
5398 gen_set_access_type(ctx, ACCESS_FLOAT);
5399 t0 = tcg_temp_new();
5400 gen_addr_reg_index(ctx, t0);
5401 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5402 gen_addr_add(ctx, t0, t0, 8);
5403 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5404 tcg_temp_free(t0);
5405}
5406
5407/* stfq */
5408static void gen_stfq(DisasContext *ctx)
5409{
5410 int rd = rD(ctx->opcode);
5411 TCGv t0;
5412 gen_set_access_type(ctx, ACCESS_FLOAT);
5413 t0 = tcg_temp_new();
5414 gen_addr_imm_index(ctx, t0, 0);
5415 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5416 gen_addr_add(ctx, t0, t0, 8);
5417 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5418 tcg_temp_free(t0);
5419}
5420
5421/* stfqu */
5422static void gen_stfqu(DisasContext *ctx)
5423{
5424 int ra = rA(ctx->opcode);
5425 int rd = rD(ctx->opcode);
5426 TCGv t0, t1;
5427 gen_set_access_type(ctx, ACCESS_FLOAT);
5428 t0 = tcg_temp_new();
5429 gen_addr_imm_index(ctx, t0, 0);
5430 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5431 t1 = tcg_temp_new();
5432 gen_addr_add(ctx, t1, t0, 8);
5433 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5434 tcg_temp_free(t1);
5435 if (ra != 0)
5436 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5437 tcg_temp_free(t0);
5438}
5439
5440/* stfqux */
5441static void gen_stfqux(DisasContext *ctx)
5442{
5443 int ra = rA(ctx->opcode);
5444 int rd = rD(ctx->opcode);
5445 TCGv t0, t1;
5446 gen_set_access_type(ctx, ACCESS_FLOAT);
5447 t0 = tcg_temp_new();
5448 gen_addr_reg_index(ctx, t0);
5449 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5450 t1 = tcg_temp_new();
5451 gen_addr_add(ctx, t1, t0, 8);
5452 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5453 tcg_temp_free(t1);
5454 if (ra != 0)
5455 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5456 tcg_temp_free(t0);
5457}
5458
5459/* stfqx */
5460static void gen_stfqx(DisasContext *ctx)
5461{
5462 int rd = rD(ctx->opcode);
5463 TCGv t0;
5464 gen_set_access_type(ctx, ACCESS_FLOAT);
5465 t0 = tcg_temp_new();
5466 gen_addr_reg_index(ctx, t0);
5467 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5468 gen_addr_add(ctx, t0, t0, 8);
5469 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5470 tcg_temp_free(t0);
5471}
5472
5473/* BookE specific instructions */
5474
5475/* XXX: not implemented on 440 ? */
5476static void gen_mfapidi(DisasContext *ctx)
5477{
5478 /* XXX: TODO */
5479 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5480}
5481
5482/* XXX: not implemented on 440 ? */
5483static void gen_tlbiva(DisasContext *ctx)
5484{
5485#if defined(CONFIG_USER_ONLY)
5486 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5487#else
5488 TCGv t0;
5489 if (unlikely(!ctx->mem_idx)) {
5490 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5491 return;
5492 }
5493 t0 = tcg_temp_new();
5494 gen_addr_reg_index(ctx, t0);
5495 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5496 tcg_temp_free(t0);
5497#endif
5498}
5499
5500/* All 405 MAC instructions are translated here */
5501static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5502 int ra, int rb, int rt, int Rc)
5503{
5504 TCGv t0, t1;
5505
5506 t0 = tcg_temp_local_new();
5507 t1 = tcg_temp_local_new();
5508
5509 switch (opc3 & 0x0D) {
5510 case 0x05:
5511 /* macchw - macchw. - macchwo - macchwo. */
5512 /* macchws - macchws. - macchwso - macchwso. */
5513 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5514 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5515 /* mulchw - mulchw. */
5516 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5517 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5518 tcg_gen_ext16s_tl(t1, t1);
5519 break;
5520 case 0x04:
5521 /* macchwu - macchwu. - macchwuo - macchwuo. */
5522 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5523 /* mulchwu - mulchwu. */
5524 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5525 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5526 tcg_gen_ext16u_tl(t1, t1);
5527 break;
5528 case 0x01:
5529 /* machhw - machhw. - machhwo - machhwo. */
5530 /* machhws - machhws. - machhwso - machhwso. */
5531 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5532 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5533 /* mulhhw - mulhhw. */
5534 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5535 tcg_gen_ext16s_tl(t0, t0);
5536 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5537 tcg_gen_ext16s_tl(t1, t1);
5538 break;
5539 case 0x00:
5540 /* machhwu - machhwu. - machhwuo - machhwuo. */
5541 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5542 /* mulhhwu - mulhhwu. */
5543 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5544 tcg_gen_ext16u_tl(t0, t0);
5545 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5546 tcg_gen_ext16u_tl(t1, t1);
5547 break;
5548 case 0x0D:
5549 /* maclhw - maclhw. - maclhwo - maclhwo. */
5550 /* maclhws - maclhws. - maclhwso - maclhwso. */
5551 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5552 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5553 /* mullhw - mullhw. */
5554 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5555 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5556 break;
5557 case 0x0C:
5558 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5559 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5560 /* mullhwu - mullhwu. */
5561 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5562 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5563 break;
5564 }
5565 if (opc2 & 0x04) {
5566 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5567 tcg_gen_mul_tl(t1, t0, t1);
5568 if (opc2 & 0x02) {
5569 /* nmultiply-and-accumulate (0x0E) */
5570 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5571 } else {
5572 /* multiply-and-accumulate (0x0C) */
5573 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5574 }
5575
5576 if (opc3 & 0x12) {
5577 /* Check overflow and/or saturate */
5578 int l1 = gen_new_label();
5579
5580 if (opc3 & 0x10) {
5581 /* Start with XER OV disabled, the most likely case */
5582 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5583 }
5584 if (opc3 & 0x01) {
5585 /* Signed */
5586 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5587 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5588 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5589 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5590 if (opc3 & 0x02) {
5591 /* Saturate */
5592 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5593 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5594 }
5595 } else {
5596 /* Unsigned */
5597 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5598 if (opc3 & 0x02) {
5599 /* Saturate */
5600 tcg_gen_movi_tl(t0, UINT32_MAX);
5601 }
5602 }
5603 if (opc3 & 0x10) {
5604 /* Check overflow */
5605 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5606 }
5607 gen_set_label(l1);
5608 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5609 }
5610 } else {
5611 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5612 }
5613 tcg_temp_free(t0);
5614 tcg_temp_free(t1);
5615 if (unlikely(Rc) != 0) {
5616 /* Update Rc0 */
5617 gen_set_Rc0(ctx, cpu_gpr[rt]);
5618 }
5619}
5620
5621#define GEN_MAC_HANDLER(name, opc2, opc3) \
5622static void glue(gen_, name)(DisasContext *ctx) \
5623{ \
5624 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5625 rD(ctx->opcode), Rc(ctx->opcode)); \
5626}
5627
5628/* macchw - macchw. */
5629GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5630/* macchwo - macchwo. */
5631GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5632/* macchws - macchws. */
5633GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5634/* macchwso - macchwso. */
5635GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5636/* macchwsu - macchwsu. */
5637GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5638/* macchwsuo - macchwsuo. */
5639GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5640/* macchwu - macchwu. */
5641GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5642/* macchwuo - macchwuo. */
5643GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5644/* machhw - machhw. */
5645GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5646/* machhwo - machhwo. */
5647GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5648/* machhws - machhws. */
5649GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5650/* machhwso - machhwso. */
5651GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5652/* machhwsu - machhwsu. */
5653GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5654/* machhwsuo - machhwsuo. */
5655GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5656/* machhwu - machhwu. */
5657GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5658/* machhwuo - machhwuo. */
5659GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5660/* maclhw - maclhw. */
5661GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5662/* maclhwo - maclhwo. */
5663GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5664/* maclhws - maclhws. */
5665GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5666/* maclhwso - maclhwso. */
5667GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5668/* maclhwu - maclhwu. */
5669GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5670/* maclhwuo - maclhwuo. */
5671GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5672/* maclhwsu - maclhwsu. */
5673GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5674/* maclhwsuo - maclhwsuo. */
5675GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5676/* nmacchw - nmacchw. */
5677GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5678/* nmacchwo - nmacchwo. */
5679GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5680/* nmacchws - nmacchws. */
5681GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5682/* nmacchwso - nmacchwso. */
5683GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5684/* nmachhw - nmachhw. */
5685GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5686/* nmachhwo - nmachhwo. */
5687GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5688/* nmachhws - nmachhws. */
5689GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5690/* nmachhwso - nmachhwso. */
5691GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5692/* nmaclhw - nmaclhw. */
5693GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5694/* nmaclhwo - nmaclhwo. */
5695GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5696/* nmaclhws - nmaclhws. */
5697GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5698/* nmaclhwso - nmaclhwso. */
5699GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5700
5701/* mulchw - mulchw. */
5702GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5703/* mulchwu - mulchwu. */
5704GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5705/* mulhhw - mulhhw. */
5706GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5707/* mulhhwu - mulhhwu. */
5708GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5709/* mullhw - mullhw. */
5710GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5711/* mullhwu - mullhwu. */
5712GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5713
5714/* mfdcr */
5715static void gen_mfdcr(DisasContext *ctx)
5716{
5717#if defined(CONFIG_USER_ONLY)
5718 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5719#else
5720 TCGv dcrn;
5721 if (unlikely(!ctx->mem_idx)) {
5722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5723 return;
5724 }
5725 /* NIP cannot be restored if the memory exception comes from an helper */
5726 gen_update_nip(ctx, ctx->nip - 4);
5727 dcrn = tcg_const_tl(SPR(ctx->opcode));
5728 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5729 tcg_temp_free(dcrn);
5730#endif
5731}
5732
5733/* mtdcr */
5734static void gen_mtdcr(DisasContext *ctx)
5735{
5736#if defined(CONFIG_USER_ONLY)
5737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5738#else
5739 TCGv dcrn;
5740 if (unlikely(!ctx->mem_idx)) {
5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5742 return;
5743 }
5744 /* NIP cannot be restored if the memory exception comes from an helper */
5745 gen_update_nip(ctx, ctx->nip - 4);
5746 dcrn = tcg_const_tl(SPR(ctx->opcode));
5747 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5748 tcg_temp_free(dcrn);
5749#endif
5750}
5751
5752/* mfdcrx */
5753/* XXX: not implemented on 440 ? */
5754static void gen_mfdcrx(DisasContext *ctx)
5755{
5756#if defined(CONFIG_USER_ONLY)
5757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5758#else
5759 if (unlikely(!ctx->mem_idx)) {
5760 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5761 return;
5762 }
5763 /* NIP cannot be restored if the memory exception comes from an helper */
5764 gen_update_nip(ctx, ctx->nip - 4);
5765 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5766 cpu_gpr[rA(ctx->opcode)]);
5767 /* Note: Rc update flag set leads to undefined state of Rc0 */
5768#endif
5769}
5770
5771/* mtdcrx */
5772/* XXX: not implemented on 440 ? */
5773static void gen_mtdcrx(DisasContext *ctx)
5774{
5775#if defined(CONFIG_USER_ONLY)
5776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5777#else
5778 if (unlikely(!ctx->mem_idx)) {
5779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5780 return;
5781 }
5782 /* NIP cannot be restored if the memory exception comes from an helper */
5783 gen_update_nip(ctx, ctx->nip - 4);
5784 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5785 cpu_gpr[rS(ctx->opcode)]);
5786 /* Note: Rc update flag set leads to undefined state of Rc0 */
5787#endif
5788}
5789
5790/* mfdcrux (PPC 460) : user-mode access to DCR */
5791static void gen_mfdcrux(DisasContext *ctx)
5792{
5793 /* NIP cannot be restored if the memory exception comes from an helper */
5794 gen_update_nip(ctx, ctx->nip - 4);
5795 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5796 cpu_gpr[rA(ctx->opcode)]);
5797 /* Note: Rc update flag set leads to undefined state of Rc0 */
5798}
5799
5800/* mtdcrux (PPC 460) : user-mode access to DCR */
5801static void gen_mtdcrux(DisasContext *ctx)
5802{
5803 /* NIP cannot be restored if the memory exception comes from an helper */
5804 gen_update_nip(ctx, ctx->nip - 4);
5805 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5806 cpu_gpr[rS(ctx->opcode)]);
5807 /* Note: Rc update flag set leads to undefined state of Rc0 */
5808}
5809
5810/* dccci */
5811static void gen_dccci(DisasContext *ctx)
5812{
5813#if defined(CONFIG_USER_ONLY)
5814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5815#else
5816 if (unlikely(!ctx->mem_idx)) {
5817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5818 return;
5819 }
5820 /* interpreted as no-op */
5821#endif
5822}
5823
5824/* dcread */
5825static void gen_dcread(DisasContext *ctx)
5826{
5827#if defined(CONFIG_USER_ONLY)
5828 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5829#else
5830 TCGv EA, val;
5831 if (unlikely(!ctx->mem_idx)) {
5832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5833 return;
5834 }
5835 gen_set_access_type(ctx, ACCESS_CACHE);
5836 EA = tcg_temp_new();
5837 gen_addr_reg_index(ctx, EA);
5838 val = tcg_temp_new();
5839 gen_qemu_ld32u(ctx, val, EA);
5840 tcg_temp_free(val);
5841 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5842 tcg_temp_free(EA);
5843#endif
5844}
5845
5846/* icbt */
5847static void gen_icbt_40x(DisasContext *ctx)
5848{
5849 /* interpreted as no-op */
5850 /* XXX: specification say this is treated as a load by the MMU
5851 * but does not generate any exception
5852 */
5853}
5854
5855/* iccci */
5856static void gen_iccci(DisasContext *ctx)
5857{
5858#if defined(CONFIG_USER_ONLY)
5859 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5860#else
5861 if (unlikely(!ctx->mem_idx)) {
5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5863 return;
5864 }
5865 /* interpreted as no-op */
5866#endif
5867}
5868
5869/* icread */
5870static void gen_icread(DisasContext *ctx)
5871{
5872#if defined(CONFIG_USER_ONLY)
5873 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5874#else
5875 if (unlikely(!ctx->mem_idx)) {
5876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5877 return;
5878 }
5879 /* interpreted as no-op */
5880#endif
5881}
5882
5883/* rfci (mem_idx only) */
5884static void gen_rfci_40x(DisasContext *ctx)
5885{
5886#if defined(CONFIG_USER_ONLY)
5887 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5888#else
5889 if (unlikely(!ctx->mem_idx)) {
5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5891 return;
5892 }
5893 /* Restore CPU state */
5894 gen_helper_40x_rfci(cpu_env);
5895 gen_sync_exception(ctx);
5896#endif
5897}
5898
5899static void gen_rfci(DisasContext *ctx)
5900{
5901#if defined(CONFIG_USER_ONLY)
5902 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5903#else
5904 if (unlikely(!ctx->mem_idx)) {
5905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5906 return;
5907 }
5908 /* Restore CPU state */
5909 gen_helper_rfci(cpu_env);
5910 gen_sync_exception(ctx);
5911#endif
5912}
5913
5914/* BookE specific */
5915
5916/* XXX: not implemented on 440 ? */
5917static void gen_rfdi(DisasContext *ctx)
5918{
5919#if defined(CONFIG_USER_ONLY)
5920 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5921#else
5922 if (unlikely(!ctx->mem_idx)) {
5923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5924 return;
5925 }
5926 /* Restore CPU state */
5927 gen_helper_rfdi(cpu_env);
5928 gen_sync_exception(ctx);
5929#endif
5930}
5931
5932/* XXX: not implemented on 440 ? */
5933static void gen_rfmci(DisasContext *ctx)
5934{
5935#if defined(CONFIG_USER_ONLY)
5936 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5937#else
5938 if (unlikely(!ctx->mem_idx)) {
5939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5940 return;
5941 }
5942 /* Restore CPU state */
5943 gen_helper_rfmci(cpu_env);
5944 gen_sync_exception(ctx);
5945#endif
5946}
5947
5948/* TLB management - PowerPC 405 implementation */
5949
5950/* tlbre */
5951static void gen_tlbre_40x(DisasContext *ctx)
5952{
5953#if defined(CONFIG_USER_ONLY)
5954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5955#else
5956 if (unlikely(!ctx->mem_idx)) {
5957 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5958 return;
5959 }
5960 switch (rB(ctx->opcode)) {
5961 case 0:
5962 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5963 cpu_gpr[rA(ctx->opcode)]);
5964 break;
5965 case 1:
5966 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5967 cpu_gpr[rA(ctx->opcode)]);
5968 break;
5969 default:
5970 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5971 break;
5972 }
5973#endif
5974}
5975
5976/* tlbsx - tlbsx. */
5977static void gen_tlbsx_40x(DisasContext *ctx)
5978{
5979#if defined(CONFIG_USER_ONLY)
5980 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5981#else
5982 TCGv t0;
5983 if (unlikely(!ctx->mem_idx)) {
5984 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5985 return;
5986 }
5987 t0 = tcg_temp_new();
5988 gen_addr_reg_index(ctx, t0);
5989 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5990 tcg_temp_free(t0);
5991 if (Rc(ctx->opcode)) {
5992 int l1 = gen_new_label();
5993 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5994 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5995 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5996 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5997 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5998 gen_set_label(l1);
5999 }
6000#endif
6001}
6002
6003/* tlbwe */
6004static void gen_tlbwe_40x(DisasContext *ctx)
6005{
6006#if defined(CONFIG_USER_ONLY)
6007 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6008#else
6009 if (unlikely(!ctx->mem_idx)) {
6010 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6011 return;
6012 }
6013 switch (rB(ctx->opcode)) {
6014 case 0:
6015 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6016 cpu_gpr[rS(ctx->opcode)]);
6017 break;
6018 case 1:
6019 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6020 cpu_gpr[rS(ctx->opcode)]);
6021 break;
6022 default:
6023 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6024 break;
6025 }
6026#endif
6027}
6028
6029/* TLB management - PowerPC 440 implementation */
6030
6031/* tlbre */
6032static void gen_tlbre_440(DisasContext *ctx)
6033{
6034#if defined(CONFIG_USER_ONLY)
6035 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6036#else
6037 if (unlikely(!ctx->mem_idx)) {
6038 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6039 return;
6040 }
6041 switch (rB(ctx->opcode)) {
6042 case 0:
6043 case 1:
6044 case 2:
6045 {
6046 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6047 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6048 t0, cpu_gpr[rA(ctx->opcode)]);
6049 tcg_temp_free_i32(t0);
6050 }
6051 break;
6052 default:
6053 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6054 break;
6055 }
6056#endif
6057}
6058
6059/* tlbsx - tlbsx. */
6060static void gen_tlbsx_440(DisasContext *ctx)
6061{
6062#if defined(CONFIG_USER_ONLY)
6063 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6064#else
6065 TCGv t0;
6066 if (unlikely(!ctx->mem_idx)) {
6067 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6068 return;
6069 }
6070 t0 = tcg_temp_new();
6071 gen_addr_reg_index(ctx, t0);
6072 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6073 tcg_temp_free(t0);
6074 if (Rc(ctx->opcode)) {
6075 int l1 = gen_new_label();
6076 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6077 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6078 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6079 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6080 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6081 gen_set_label(l1);
6082 }
6083#endif
6084}
6085
6086/* tlbwe */
6087static void gen_tlbwe_440(DisasContext *ctx)
6088{
6089#if defined(CONFIG_USER_ONLY)
6090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6091#else
6092 if (unlikely(!ctx->mem_idx)) {
6093 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6094 return;
6095 }
6096 switch (rB(ctx->opcode)) {
6097 case 0:
6098 case 1:
6099 case 2:
6100 {
6101 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6102 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6103 cpu_gpr[rS(ctx->opcode)]);
6104 tcg_temp_free_i32(t0);
6105 }
6106 break;
6107 default:
6108 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6109 break;
6110 }
6111#endif
6112}
6113
6114/* TLB management - PowerPC BookE 2.06 implementation */
6115
6116/* tlbre */
6117static void gen_tlbre_booke206(DisasContext *ctx)
6118{
6119#if defined(CONFIG_USER_ONLY)
6120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6121#else
6122 if (unlikely(!ctx->mem_idx)) {
6123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6124 return;
6125 }
6126
6127 gen_helper_booke206_tlbre(cpu_env);
6128#endif
6129}
6130
6131/* tlbsx - tlbsx. */
6132static void gen_tlbsx_booke206(DisasContext *ctx)
6133{
6134#if defined(CONFIG_USER_ONLY)
6135 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6136#else
6137 TCGv t0;
6138 if (unlikely(!ctx->mem_idx)) {
6139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6140 return;
6141 }
6142
6143 if (rA(ctx->opcode)) {
6144 t0 = tcg_temp_new();
6145 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6146 } else {
6147 t0 = tcg_const_tl(0);
6148 }
6149
6150 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6151 gen_helper_booke206_tlbsx(cpu_env, t0);
6152#endif
6153}
6154
6155/* tlbwe */
6156static void gen_tlbwe_booke206(DisasContext *ctx)
6157{
6158#if defined(CONFIG_USER_ONLY)
6159 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6160#else
6161 if (unlikely(!ctx->mem_idx)) {
6162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6163 return;
6164 }
6165 gen_update_nip(ctx, ctx->nip - 4);
6166 gen_helper_booke206_tlbwe(cpu_env);
6167#endif
6168}
6169
6170static void gen_tlbivax_booke206(DisasContext *ctx)
6171{
6172#if defined(CONFIG_USER_ONLY)
6173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6174#else
6175 TCGv t0;
6176 if (unlikely(!ctx->mem_idx)) {
6177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6178 return;
6179 }
6180
6181 t0 = tcg_temp_new();
6182 gen_addr_reg_index(ctx, t0);
6183
6184 gen_helper_booke206_tlbivax(cpu_env, t0);
6185#endif
6186}
6187
6188static void gen_tlbilx_booke206(DisasContext *ctx)
6189{
6190#if defined(CONFIG_USER_ONLY)
6191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6192#else
6193 TCGv t0;
6194 if (unlikely(!ctx->mem_idx)) {
6195 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6196 return;
6197 }
6198
6199 t0 = tcg_temp_new();
6200 gen_addr_reg_index(ctx, t0);
6201
6202 switch((ctx->opcode >> 21) & 0x3) {
6203 case 0:
6204 gen_helper_booke206_tlbilx0(cpu_env, t0);
6205 break;
6206 case 1:
6207 gen_helper_booke206_tlbilx1(cpu_env, t0);
6208 break;
6209 case 3:
6210 gen_helper_booke206_tlbilx3(cpu_env, t0);
6211 break;
6212 default:
6213 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6214 break;
6215 }
6216
6217 tcg_temp_free(t0);
6218#endif
6219}
6220
6221
6222/* wrtee */
6223static void gen_wrtee(DisasContext *ctx)
6224{
6225#if defined(CONFIG_USER_ONLY)
6226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6227#else
6228 TCGv t0;
6229 if (unlikely(!ctx->mem_idx)) {
6230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6231 return;
6232 }
6233 t0 = tcg_temp_new();
6234 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6235 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6236 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6237 tcg_temp_free(t0);
6238 /* Stop translation to have a chance to raise an exception
6239 * if we just set msr_ee to 1
6240 */
6241 gen_stop_exception(ctx);
6242#endif
6243}
6244
6245/* wrteei */
6246static void gen_wrteei(DisasContext *ctx)
6247{
6248#if defined(CONFIG_USER_ONLY)
6249 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6250#else
6251 if (unlikely(!ctx->mem_idx)) {
6252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6253 return;
6254 }
6255 if (ctx->opcode & 0x00008000) {
6256 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6257 /* Stop translation to have a chance to raise an exception */
6258 gen_stop_exception(ctx);
6259 } else {
6260 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6261 }
6262#endif
6263}
6264
6265/* PowerPC 440 specific instructions */
6266
6267/* dlmzb */
6268static void gen_dlmzb(DisasContext *ctx)
6269{
6270 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6271 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6272 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6273 tcg_temp_free_i32(t0);
6274}
6275
6276/* mbar replaces eieio on 440 */
6277static void gen_mbar(DisasContext *ctx)
6278{
6279 /* interpreted as no-op */
6280}
6281
6282/* msync replaces sync on 440 */
6283static void gen_msync_4xx(DisasContext *ctx)
6284{
6285 /* interpreted as no-op */
6286}
6287
6288/* icbt */
6289static void gen_icbt_440(DisasContext *ctx)
6290{
6291 /* interpreted as no-op */
6292 /* XXX: specification say this is treated as a load by the MMU
6293 * but does not generate any exception
6294 */
6295}
6296
6297/* Embedded.Processor Control */
6298
6299static void gen_msgclr(DisasContext *ctx)
6300{
6301#if defined(CONFIG_USER_ONLY)
6302 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6303#else
6304 if (unlikely(ctx->mem_idx == 0)) {
6305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6306 return;
6307 }
6308
6309 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6310#endif
6311}
6312
6313static void gen_msgsnd(DisasContext *ctx)
6314{
6315#if defined(CONFIG_USER_ONLY)
6316 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6317#else
6318 if (unlikely(ctx->mem_idx == 0)) {
6319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6320 return;
6321 }
6322
6323 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6324#endif
6325}
6326
6327/*** Altivec vector extension ***/
6328/* Altivec registers moves */
6329
6330static inline TCGv_ptr gen_avr_ptr(int reg)
6331{
6332 TCGv_ptr r = tcg_temp_new_ptr();
6333 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6334 return r;
6335}
6336
6337#define GEN_VR_LDX(name, opc2, opc3) \
6338static void glue(gen_, name)(DisasContext *ctx) \
6339{ \
6340 TCGv EA; \
6341 if (unlikely(!ctx->altivec_enabled)) { \
6342 gen_exception(ctx, POWERPC_EXCP_VPU); \
6343 return; \
6344 } \
6345 gen_set_access_type(ctx, ACCESS_INT); \
6346 EA = tcg_temp_new(); \
6347 gen_addr_reg_index(ctx, EA); \
6348 tcg_gen_andi_tl(EA, EA, ~0xf); \
6349 if (ctx->le_mode) { \
6350 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6351 tcg_gen_addi_tl(EA, EA, 8); \
6352 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6353 } else { \
6354 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6355 tcg_gen_addi_tl(EA, EA, 8); \
6356 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6357 } \
6358 tcg_temp_free(EA); \
6359}
6360
6361#define GEN_VR_STX(name, opc2, opc3) \
6362static void gen_st##name(DisasContext *ctx) \
6363{ \
6364 TCGv EA; \
6365 if (unlikely(!ctx->altivec_enabled)) { \
6366 gen_exception(ctx, POWERPC_EXCP_VPU); \
6367 return; \
6368 } \
6369 gen_set_access_type(ctx, ACCESS_INT); \
6370 EA = tcg_temp_new(); \
6371 gen_addr_reg_index(ctx, EA); \
6372 tcg_gen_andi_tl(EA, EA, ~0xf); \
6373 if (ctx->le_mode) { \
6374 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6375 tcg_gen_addi_tl(EA, EA, 8); \
6376 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6377 } else { \
6378 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6379 tcg_gen_addi_tl(EA, EA, 8); \
6380 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6381 } \
6382 tcg_temp_free(EA); \
6383}
6384
6385#define GEN_VR_LVE(name, opc2, opc3) \
6386static void gen_lve##name(DisasContext *ctx) \
6387 { \
6388 TCGv EA; \
6389 TCGv_ptr rs; \
6390 if (unlikely(!ctx->altivec_enabled)) { \
6391 gen_exception(ctx, POWERPC_EXCP_VPU); \
6392 return; \
6393 } \
6394 gen_set_access_type(ctx, ACCESS_INT); \
6395 EA = tcg_temp_new(); \
6396 gen_addr_reg_index(ctx, EA); \
6397 rs = gen_avr_ptr(rS(ctx->opcode)); \
6398 gen_helper_lve##name(cpu_env, rs, EA); \
6399 tcg_temp_free(EA); \
6400 tcg_temp_free_ptr(rs); \
6401 }
6402
6403#define GEN_VR_STVE(name, opc2, opc3) \
6404static void gen_stve##name(DisasContext *ctx) \
6405 { \
6406 TCGv EA; \
6407 TCGv_ptr rs; \
6408 if (unlikely(!ctx->altivec_enabled)) { \
6409 gen_exception(ctx, POWERPC_EXCP_VPU); \
6410 return; \
6411 } \
6412 gen_set_access_type(ctx, ACCESS_INT); \
6413 EA = tcg_temp_new(); \
6414 gen_addr_reg_index(ctx, EA); \
6415 rs = gen_avr_ptr(rS(ctx->opcode)); \
6416 gen_helper_stve##name(cpu_env, rs, EA); \
6417 tcg_temp_free(EA); \
6418 tcg_temp_free_ptr(rs); \
6419 }
6420
6421GEN_VR_LDX(lvx, 0x07, 0x03);
6422/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6423GEN_VR_LDX(lvxl, 0x07, 0x0B);
6424
6425GEN_VR_LVE(bx, 0x07, 0x00);
6426GEN_VR_LVE(hx, 0x07, 0x01);
6427GEN_VR_LVE(wx, 0x07, 0x02);
6428
6429GEN_VR_STX(svx, 0x07, 0x07);
6430/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6431GEN_VR_STX(svxl, 0x07, 0x0F);
6432
6433GEN_VR_STVE(bx, 0x07, 0x04);
6434GEN_VR_STVE(hx, 0x07, 0x05);
6435GEN_VR_STVE(wx, 0x07, 0x06);
6436
6437static void gen_lvsl(DisasContext *ctx)
6438{
6439 TCGv_ptr rd;
6440 TCGv EA;
6441 if (unlikely(!ctx->altivec_enabled)) {
6442 gen_exception(ctx, POWERPC_EXCP_VPU);
6443 return;
6444 }
6445 EA = tcg_temp_new();
6446 gen_addr_reg_index(ctx, EA);
6447 rd = gen_avr_ptr(rD(ctx->opcode));
6448 gen_helper_lvsl(rd, EA);
6449 tcg_temp_free(EA);
6450 tcg_temp_free_ptr(rd);
6451}
6452
6453static void gen_lvsr(DisasContext *ctx)
6454{
6455 TCGv_ptr rd;
6456 TCGv EA;
6457 if (unlikely(!ctx->altivec_enabled)) {
6458 gen_exception(ctx, POWERPC_EXCP_VPU);
6459 return;
6460 }
6461 EA = tcg_temp_new();
6462 gen_addr_reg_index(ctx, EA);
6463 rd = gen_avr_ptr(rD(ctx->opcode));
6464 gen_helper_lvsr(rd, EA);
6465 tcg_temp_free(EA);
6466 tcg_temp_free_ptr(rd);
6467}
6468
6469static void gen_mfvscr(DisasContext *ctx)
6470{
6471 TCGv_i32 t;
6472 if (unlikely(!ctx->altivec_enabled)) {
6473 gen_exception(ctx, POWERPC_EXCP_VPU);
6474 return;
6475 }
6476 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6477 t = tcg_temp_new_i32();
6478 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6479 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6480 tcg_temp_free_i32(t);
6481}
6482
6483static void gen_mtvscr(DisasContext *ctx)
6484{
6485 TCGv_ptr p;
6486 if (unlikely(!ctx->altivec_enabled)) {
6487 gen_exception(ctx, POWERPC_EXCP_VPU);
6488 return;
6489 }
6490 p = gen_avr_ptr(rD(ctx->opcode));
6491 gen_helper_mtvscr(cpu_env, p);
6492 tcg_temp_free_ptr(p);
6493}
6494
6495/* Logical operations */
6496#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6497static void glue(gen_, name)(DisasContext *ctx) \
6498{ \
6499 if (unlikely(!ctx->altivec_enabled)) { \
6500 gen_exception(ctx, POWERPC_EXCP_VPU); \
6501 return; \
6502 } \
6503 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6504 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6505}
6506
6507GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6508GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6509GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6510GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6511GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6512
6513#define GEN_VXFORM(name, opc2, opc3) \
6514static void glue(gen_, name)(DisasContext *ctx) \
6515{ \
6516 TCGv_ptr ra, rb, rd; \
6517 if (unlikely(!ctx->altivec_enabled)) { \
6518 gen_exception(ctx, POWERPC_EXCP_VPU); \
6519 return; \
6520 } \
6521 ra = gen_avr_ptr(rA(ctx->opcode)); \
6522 rb = gen_avr_ptr(rB(ctx->opcode)); \
6523 rd = gen_avr_ptr(rD(ctx->opcode)); \
6524 gen_helper_##name (rd, ra, rb); \
6525 tcg_temp_free_ptr(ra); \
6526 tcg_temp_free_ptr(rb); \
6527 tcg_temp_free_ptr(rd); \
6528}
6529
6530#define GEN_VXFORM_ENV(name, opc2, opc3) \
6531static void glue(gen_, name)(DisasContext *ctx) \
6532{ \
6533 TCGv_ptr ra, rb, rd; \
6534 if (unlikely(!ctx->altivec_enabled)) { \
6535 gen_exception(ctx, POWERPC_EXCP_VPU); \
6536 return; \
6537 } \
6538 ra = gen_avr_ptr(rA(ctx->opcode)); \
6539 rb = gen_avr_ptr(rB(ctx->opcode)); \
6540 rd = gen_avr_ptr(rD(ctx->opcode)); \
6541 gen_helper_##name(cpu_env, rd, ra, rb); \
6542 tcg_temp_free_ptr(ra); \
6543 tcg_temp_free_ptr(rb); \
6544 tcg_temp_free_ptr(rd); \
6545}
6546
6547GEN_VXFORM(vaddubm, 0, 0);
6548GEN_VXFORM(vadduhm, 0, 1);
6549GEN_VXFORM(vadduwm, 0, 2);
6550GEN_VXFORM(vsububm, 0, 16);
6551GEN_VXFORM(vsubuhm, 0, 17);
6552GEN_VXFORM(vsubuwm, 0, 18);
6553GEN_VXFORM(vmaxub, 1, 0);
6554GEN_VXFORM(vmaxuh, 1, 1);
6555GEN_VXFORM(vmaxuw, 1, 2);
6556GEN_VXFORM(vmaxsb, 1, 4);
6557GEN_VXFORM(vmaxsh, 1, 5);
6558GEN_VXFORM(vmaxsw, 1, 6);
6559GEN_VXFORM(vminub, 1, 8);
6560GEN_VXFORM(vminuh, 1, 9);
6561GEN_VXFORM(vminuw, 1, 10);
6562GEN_VXFORM(vminsb, 1, 12);
6563GEN_VXFORM(vminsh, 1, 13);
6564GEN_VXFORM(vminsw, 1, 14);
6565GEN_VXFORM(vavgub, 1, 16);
6566GEN_VXFORM(vavguh, 1, 17);
6567GEN_VXFORM(vavguw, 1, 18);
6568GEN_VXFORM(vavgsb, 1, 20);
6569GEN_VXFORM(vavgsh, 1, 21);
6570GEN_VXFORM(vavgsw, 1, 22);
6571GEN_VXFORM(vmrghb, 6, 0);
6572GEN_VXFORM(vmrghh, 6, 1);
6573GEN_VXFORM(vmrghw, 6, 2);
6574GEN_VXFORM(vmrglb, 6, 4);
6575GEN_VXFORM(vmrglh, 6, 5);
6576GEN_VXFORM(vmrglw, 6, 6);
6577GEN_VXFORM(vmuloub, 4, 0);
6578GEN_VXFORM(vmulouh, 4, 1);
6579GEN_VXFORM(vmulosb, 4, 4);
6580GEN_VXFORM(vmulosh, 4, 5);
6581GEN_VXFORM(vmuleub, 4, 8);
6582GEN_VXFORM(vmuleuh, 4, 9);
6583GEN_VXFORM(vmulesb, 4, 12);
6584GEN_VXFORM(vmulesh, 4, 13);
6585GEN_VXFORM(vslb, 2, 4);
6586GEN_VXFORM(vslh, 2, 5);
6587GEN_VXFORM(vslw, 2, 6);
6588GEN_VXFORM(vsrb, 2, 8);
6589GEN_VXFORM(vsrh, 2, 9);
6590GEN_VXFORM(vsrw, 2, 10);
6591GEN_VXFORM(vsrab, 2, 12);
6592GEN_VXFORM(vsrah, 2, 13);
6593GEN_VXFORM(vsraw, 2, 14);
6594GEN_VXFORM(vslo, 6, 16);
6595GEN_VXFORM(vsro, 6, 17);
6596GEN_VXFORM(vaddcuw, 0, 6);
6597GEN_VXFORM(vsubcuw, 0, 22);
6598GEN_VXFORM_ENV(vaddubs, 0, 8);
6599GEN_VXFORM_ENV(vadduhs, 0, 9);
6600GEN_VXFORM_ENV(vadduws, 0, 10);
6601GEN_VXFORM_ENV(vaddsbs, 0, 12);
6602GEN_VXFORM_ENV(vaddshs, 0, 13);
6603GEN_VXFORM_ENV(vaddsws, 0, 14);
6604GEN_VXFORM_ENV(vsububs, 0, 24);
6605GEN_VXFORM_ENV(vsubuhs, 0, 25);
6606GEN_VXFORM_ENV(vsubuws, 0, 26);
6607GEN_VXFORM_ENV(vsubsbs, 0, 28);
6608GEN_VXFORM_ENV(vsubshs, 0, 29);
6609GEN_VXFORM_ENV(vsubsws, 0, 30);
6610GEN_VXFORM(vrlb, 2, 0);
6611GEN_VXFORM(vrlh, 2, 1);
6612GEN_VXFORM(vrlw, 2, 2);
6613GEN_VXFORM(vsl, 2, 7);
6614GEN_VXFORM(vsr, 2, 11);
6615GEN_VXFORM_ENV(vpkuhum, 7, 0);
6616GEN_VXFORM_ENV(vpkuwum, 7, 1);
6617GEN_VXFORM_ENV(vpkuhus, 7, 2);
6618GEN_VXFORM_ENV(vpkuwus, 7, 3);
6619GEN_VXFORM_ENV(vpkshus, 7, 4);
6620GEN_VXFORM_ENV(vpkswus, 7, 5);
6621GEN_VXFORM_ENV(vpkshss, 7, 6);
6622GEN_VXFORM_ENV(vpkswss, 7, 7);
6623GEN_VXFORM(vpkpx, 7, 12);
6624GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6625GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6626GEN_VXFORM_ENV(vsum4shs, 4, 25);
6627GEN_VXFORM_ENV(vsum2sws, 4, 26);
6628GEN_VXFORM_ENV(vsumsws, 4, 30);
6629GEN_VXFORM_ENV(vaddfp, 5, 0);
6630GEN_VXFORM_ENV(vsubfp, 5, 1);
6631GEN_VXFORM_ENV(vmaxfp, 5, 16);
6632GEN_VXFORM_ENV(vminfp, 5, 17);
6633
6634#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6635static void glue(gen_, name)(DisasContext *ctx) \
6636 { \
6637 TCGv_ptr ra, rb, rd; \
6638 if (unlikely(!ctx->altivec_enabled)) { \
6639 gen_exception(ctx, POWERPC_EXCP_VPU); \
6640 return; \
6641 } \
6642 ra = gen_avr_ptr(rA(ctx->opcode)); \
6643 rb = gen_avr_ptr(rB(ctx->opcode)); \
6644 rd = gen_avr_ptr(rD(ctx->opcode)); \
6645 gen_helper_##opname(cpu_env, rd, ra, rb); \
6646 tcg_temp_free_ptr(ra); \
6647 tcg_temp_free_ptr(rb); \
6648 tcg_temp_free_ptr(rd); \
6649 }
6650
6651#define GEN_VXRFORM(name, opc2, opc3) \
6652 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6653 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6654
6655GEN_VXRFORM(vcmpequb, 3, 0)
6656GEN_VXRFORM(vcmpequh, 3, 1)
6657GEN_VXRFORM(vcmpequw, 3, 2)
6658GEN_VXRFORM(vcmpgtsb, 3, 12)
6659GEN_VXRFORM(vcmpgtsh, 3, 13)
6660GEN_VXRFORM(vcmpgtsw, 3, 14)
6661GEN_VXRFORM(vcmpgtub, 3, 8)
6662GEN_VXRFORM(vcmpgtuh, 3, 9)
6663GEN_VXRFORM(vcmpgtuw, 3, 10)
6664GEN_VXRFORM(vcmpeqfp, 3, 3)
6665GEN_VXRFORM(vcmpgefp, 3, 7)
6666GEN_VXRFORM(vcmpgtfp, 3, 11)
6667GEN_VXRFORM(vcmpbfp, 3, 15)
6668
6669#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6670static void glue(gen_, name)(DisasContext *ctx) \
6671 { \
6672 TCGv_ptr rd; \
6673 TCGv_i32 simm; \
6674 if (unlikely(!ctx->altivec_enabled)) { \
6675 gen_exception(ctx, POWERPC_EXCP_VPU); \
6676 return; \
6677 } \
6678 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6679 rd = gen_avr_ptr(rD(ctx->opcode)); \
6680 gen_helper_##name (rd, simm); \
6681 tcg_temp_free_i32(simm); \
6682 tcg_temp_free_ptr(rd); \
6683 }
6684
6685GEN_VXFORM_SIMM(vspltisb, 6, 12);
6686GEN_VXFORM_SIMM(vspltish, 6, 13);
6687GEN_VXFORM_SIMM(vspltisw, 6, 14);
6688
6689#define GEN_VXFORM_NOA(name, opc2, opc3) \
6690static void glue(gen_, name)(DisasContext *ctx) \
6691 { \
6692 TCGv_ptr rb, rd; \
6693 if (unlikely(!ctx->altivec_enabled)) { \
6694 gen_exception(ctx, POWERPC_EXCP_VPU); \
6695 return; \
6696 } \
6697 rb = gen_avr_ptr(rB(ctx->opcode)); \
6698 rd = gen_avr_ptr(rD(ctx->opcode)); \
6699 gen_helper_##name (rd, rb); \
6700 tcg_temp_free_ptr(rb); \
6701 tcg_temp_free_ptr(rd); \
6702 }
6703
6704#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6705static void glue(gen_, name)(DisasContext *ctx) \
6706 { \
6707 TCGv_ptr rb, rd; \
6708 \
6709 if (unlikely(!ctx->altivec_enabled)) { \
6710 gen_exception(ctx, POWERPC_EXCP_VPU); \
6711 return; \
6712 } \
6713 rb = gen_avr_ptr(rB(ctx->opcode)); \
6714 rd = gen_avr_ptr(rD(ctx->opcode)); \
6715 gen_helper_##name(cpu_env, rd, rb); \
6716 tcg_temp_free_ptr(rb); \
6717 tcg_temp_free_ptr(rd); \
6718 }
6719
6720GEN_VXFORM_NOA(vupkhsb, 7, 8);
6721GEN_VXFORM_NOA(vupkhsh, 7, 9);
6722GEN_VXFORM_NOA(vupklsb, 7, 10);
6723GEN_VXFORM_NOA(vupklsh, 7, 11);
6724GEN_VXFORM_NOA(vupkhpx, 7, 13);
6725GEN_VXFORM_NOA(vupklpx, 7, 15);
6726GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6727GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6728GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6729GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6730GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6731GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6732GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6733GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6734
6735#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6736static void glue(gen_, name)(DisasContext *ctx) \
6737 { \
6738 TCGv_ptr rd; \
6739 TCGv_i32 simm; \
6740 if (unlikely(!ctx->altivec_enabled)) { \
6741 gen_exception(ctx, POWERPC_EXCP_VPU); \
6742 return; \
6743 } \
6744 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6745 rd = gen_avr_ptr(rD(ctx->opcode)); \
6746 gen_helper_##name (rd, simm); \
6747 tcg_temp_free_i32(simm); \
6748 tcg_temp_free_ptr(rd); \
6749 }
6750
6751#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6752static void glue(gen_, name)(DisasContext *ctx) \
6753 { \
6754 TCGv_ptr rb, rd; \
6755 TCGv_i32 uimm; \
6756 if (unlikely(!ctx->altivec_enabled)) { \
6757 gen_exception(ctx, POWERPC_EXCP_VPU); \
6758 return; \
6759 } \
6760 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6761 rb = gen_avr_ptr(rB(ctx->opcode)); \
6762 rd = gen_avr_ptr(rD(ctx->opcode)); \
6763 gen_helper_##name (rd, rb, uimm); \
6764 tcg_temp_free_i32(uimm); \
6765 tcg_temp_free_ptr(rb); \
6766 tcg_temp_free_ptr(rd); \
6767 }
6768
6769#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6770static void glue(gen_, name)(DisasContext *ctx) \
6771 { \
6772 TCGv_ptr rb, rd; \
6773 TCGv_i32 uimm; \
6774 \
6775 if (unlikely(!ctx->altivec_enabled)) { \
6776 gen_exception(ctx, POWERPC_EXCP_VPU); \
6777 return; \
6778 } \
6779 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6780 rb = gen_avr_ptr(rB(ctx->opcode)); \
6781 rd = gen_avr_ptr(rD(ctx->opcode)); \
6782 gen_helper_##name(cpu_env, rd, rb, uimm); \
6783 tcg_temp_free_i32(uimm); \
6784 tcg_temp_free_ptr(rb); \
6785 tcg_temp_free_ptr(rd); \
6786 }
6787
6788GEN_VXFORM_UIMM(vspltb, 6, 8);
6789GEN_VXFORM_UIMM(vsplth, 6, 9);
6790GEN_VXFORM_UIMM(vspltw, 6, 10);
6791GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6792GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6793GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6794GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6795
6796static void gen_vsldoi(DisasContext *ctx)
6797{
6798 TCGv_ptr ra, rb, rd;
6799 TCGv_i32 sh;
6800 if (unlikely(!ctx->altivec_enabled)) {
6801 gen_exception(ctx, POWERPC_EXCP_VPU);
6802 return;
6803 }
6804 ra = gen_avr_ptr(rA(ctx->opcode));
6805 rb = gen_avr_ptr(rB(ctx->opcode));
6806 rd = gen_avr_ptr(rD(ctx->opcode));
6807 sh = tcg_const_i32(VSH(ctx->opcode));
6808 gen_helper_vsldoi (rd, ra, rb, sh);
6809 tcg_temp_free_ptr(ra);
6810 tcg_temp_free_ptr(rb);
6811 tcg_temp_free_ptr(rd);
6812 tcg_temp_free_i32(sh);
6813}
6814
6815#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6816static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6817 { \
6818 TCGv_ptr ra, rb, rc, rd; \
6819 if (unlikely(!ctx->altivec_enabled)) { \
6820 gen_exception(ctx, POWERPC_EXCP_VPU); \
6821 return; \
6822 } \
6823 ra = gen_avr_ptr(rA(ctx->opcode)); \
6824 rb = gen_avr_ptr(rB(ctx->opcode)); \
6825 rc = gen_avr_ptr(rC(ctx->opcode)); \
6826 rd = gen_avr_ptr(rD(ctx->opcode)); \
6827 if (Rc(ctx->opcode)) { \
6828 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6829 } else { \
6830 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6831 } \
6832 tcg_temp_free_ptr(ra); \
6833 tcg_temp_free_ptr(rb); \
6834 tcg_temp_free_ptr(rc); \
6835 tcg_temp_free_ptr(rd); \
6836 }
6837
6838GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6839
6840static void gen_vmladduhm(DisasContext *ctx)
6841{
6842 TCGv_ptr ra, rb, rc, rd;
6843 if (unlikely(!ctx->altivec_enabled)) {
6844 gen_exception(ctx, POWERPC_EXCP_VPU);
6845 return;
6846 }
6847 ra = gen_avr_ptr(rA(ctx->opcode));
6848 rb = gen_avr_ptr(rB(ctx->opcode));
6849 rc = gen_avr_ptr(rC(ctx->opcode));
6850 rd = gen_avr_ptr(rD(ctx->opcode));
6851 gen_helper_vmladduhm(rd, ra, rb, rc);
6852 tcg_temp_free_ptr(ra);
6853 tcg_temp_free_ptr(rb);
6854 tcg_temp_free_ptr(rc);
6855 tcg_temp_free_ptr(rd);
6856}
6857
6858GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6859GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6860GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6861GEN_VAFORM_PAIRED(vsel, vperm, 21)
6862GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6863
6864/*** SPE extension ***/
6865/* Register moves */
6866
6867
6868static inline void gen_evmra(DisasContext *ctx)
6869{
6870
6871 if (unlikely(!ctx->spe_enabled)) {
6872 gen_exception(ctx, POWERPC_EXCP_SPEU);
6873 return;
6874 }
6875
6876#if defined(TARGET_PPC64)
6877 /* rD := rA */
6878 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6879
6880 /* spe_acc := rA */
6881 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6882 cpu_env,
6883 offsetof(CPUPPCState, spe_acc));
6884#else
6885 TCGv_i64 tmp = tcg_temp_new_i64();
6886
6887 /* tmp := rA_lo + rA_hi << 32 */
6888 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6889
6890 /* spe_acc := tmp */
6891 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6892 tcg_temp_free_i64(tmp);
6893
6894 /* rD := rA */
6895 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6896 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6897#endif
6898}
6899
6900static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6901{
6902#if defined(TARGET_PPC64)
6903 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6904#else
6905 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6906#endif
6907}
6908
6909static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6910{
6911#if defined(TARGET_PPC64)
6912 tcg_gen_mov_i64(cpu_gpr[reg], t);
6913#else
6914 TCGv_i64 tmp = tcg_temp_new_i64();
6915 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6916 tcg_gen_shri_i64(tmp, t, 32);
6917 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6918 tcg_temp_free_i64(tmp);
6919#endif
6920}
6921
6922#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6923static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6924{ \
6925 if (Rc(ctx->opcode)) \
6926 gen_##name1(ctx); \
6927 else \
6928 gen_##name0(ctx); \
6929}
6930
6931/* Handler for undefined SPE opcodes */
6932static inline void gen_speundef(DisasContext *ctx)
6933{
6934 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6935}
6936
6937/* SPE logic */
6938#if defined(TARGET_PPC64)
6939#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6940static inline void gen_##name(DisasContext *ctx) \
6941{ \
6942 if (unlikely(!ctx->spe_enabled)) { \
6943 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6944 return; \
6945 } \
6946 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6947 cpu_gpr[rB(ctx->opcode)]); \
6948}
6949#else
6950#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6951static inline void gen_##name(DisasContext *ctx) \
6952{ \
6953 if (unlikely(!ctx->spe_enabled)) { \
6954 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6955 return; \
6956 } \
6957 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6958 cpu_gpr[rB(ctx->opcode)]); \
6959 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6960 cpu_gprh[rB(ctx->opcode)]); \
6961}
6962#endif
6963
6964GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6965GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6966GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6967GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6968GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6969GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6970GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6971GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6972
6973/* SPE logic immediate */
6974#if defined(TARGET_PPC64)
6975#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6976static inline void gen_##name(DisasContext *ctx) \
6977{ \
6978 if (unlikely(!ctx->spe_enabled)) { \
6979 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6980 return; \
6981 } \
6982 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6983 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6984 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6985 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6986 tcg_opi(t0, t0, rB(ctx->opcode)); \
6987 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6988 tcg_gen_trunc_i64_i32(t1, t2); \
6989 tcg_temp_free_i64(t2); \
6990 tcg_opi(t1, t1, rB(ctx->opcode)); \
6991 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6992 tcg_temp_free_i32(t0); \
6993 tcg_temp_free_i32(t1); \
6994}
6995#else
6996#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6997static inline void gen_##name(DisasContext *ctx) \
6998{ \
6999 if (unlikely(!ctx->spe_enabled)) { \
7000 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7001 return; \
7002 } \
7003 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7004 rB(ctx->opcode)); \
7005 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7006 rB(ctx->opcode)); \
7007}
7008#endif
7009GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7010GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7011GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7012GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7013
7014/* SPE arithmetic */
7015#if defined(TARGET_PPC64)
7016#define GEN_SPEOP_ARITH1(name, tcg_op) \
7017static inline void gen_##name(DisasContext *ctx) \
7018{ \
7019 if (unlikely(!ctx->spe_enabled)) { \
7020 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7021 return; \
7022 } \
7023 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7024 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7025 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7026 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7027 tcg_op(t0, t0); \
7028 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7029 tcg_gen_trunc_i64_i32(t1, t2); \
7030 tcg_temp_free_i64(t2); \
7031 tcg_op(t1, t1); \
7032 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7033 tcg_temp_free_i32(t0); \
7034 tcg_temp_free_i32(t1); \
7035}
7036#else
7037#define GEN_SPEOP_ARITH1(name, tcg_op) \
7038static inline void gen_##name(DisasContext *ctx) \
7039{ \
7040 if (unlikely(!ctx->spe_enabled)) { \
7041 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7042 return; \
7043 } \
7044 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
7045 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
7046}
7047#endif
7048
7049static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
7050{
7051 int l1 = gen_new_label();
7052 int l2 = gen_new_label();
7053
7054 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
7055 tcg_gen_neg_i32(ret, arg1);
7056 tcg_gen_br(l2);
7057 gen_set_label(l1);
7058 tcg_gen_mov_i32(ret, arg1);
7059 gen_set_label(l2);
7060}
7061GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
7062GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
7063GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
7064GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
7065static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
7066{
7067 tcg_gen_addi_i32(ret, arg1, 0x8000);
7068 tcg_gen_ext16u_i32(ret, ret);
7069}
7070GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
7071GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
7072GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
7073
7074#if defined(TARGET_PPC64)
7075#define GEN_SPEOP_ARITH2(name, tcg_op) \
7076static inline void gen_##name(DisasContext *ctx) \
7077{ \
7078 if (unlikely(!ctx->spe_enabled)) { \
7079 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7080 return; \
7081 } \
7082 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7083 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7084 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
7085 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
7086 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7087 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
7088 tcg_op(t0, t0, t2); \
7089 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
7090 tcg_gen_trunc_i64_i32(t1, t3); \
7091 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
7092 tcg_gen_trunc_i64_i32(t2, t3); \
7093 tcg_temp_free_i64(t3); \
7094 tcg_op(t1, t1, t2); \
7095 tcg_temp_free_i32(t2); \
7096 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7097 tcg_temp_free_i32(t0); \
7098 tcg_temp_free_i32(t1); \
7099}
7100#else
7101#define GEN_SPEOP_ARITH2(name, tcg_op) \
7102static inline void gen_##name(DisasContext *ctx) \
7103{ \
7104 if (unlikely(!ctx->spe_enabled)) { \
7105 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7106 return; \
7107 } \
7108 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7109 cpu_gpr[rB(ctx->opcode)]); \
7110 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7111 cpu_gprh[rB(ctx->opcode)]); \
7112}
7113#endif
7114
7115static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7116{
7117 TCGv_i32 t0;
7118 int l1, l2;
7119
7120 l1 = gen_new_label();
7121 l2 = gen_new_label();
7122 t0 = tcg_temp_local_new_i32();
7123 /* No error here: 6 bits are used */
7124 tcg_gen_andi_i32(t0, arg2, 0x3F);
7125 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7126 tcg_gen_shr_i32(ret, arg1, t0);
7127 tcg_gen_br(l2);
7128 gen_set_label(l1);
7129 tcg_gen_movi_i32(ret, 0);
7130 gen_set_label(l2);
7131 tcg_temp_free_i32(t0);
7132}
7133GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7134static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7135{
7136 TCGv_i32 t0;
7137 int l1, l2;
7138
7139 l1 = gen_new_label();
7140 l2 = gen_new_label();
7141 t0 = tcg_temp_local_new_i32();
7142 /* No error here: 6 bits are used */
7143 tcg_gen_andi_i32(t0, arg2, 0x3F);
7144 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7145 tcg_gen_sar_i32(ret, arg1, t0);
7146 tcg_gen_br(l2);
7147 gen_set_label(l1);
7148 tcg_gen_movi_i32(ret, 0);
7149 gen_set_label(l2);
7150 tcg_temp_free_i32(t0);
7151}
7152GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7153static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7154{
7155 TCGv_i32 t0;
7156 int l1, l2;
7157
7158 l1 = gen_new_label();
7159 l2 = gen_new_label();
7160 t0 = tcg_temp_local_new_i32();
7161 /* No error here: 6 bits are used */
7162 tcg_gen_andi_i32(t0, arg2, 0x3F);
7163 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7164 tcg_gen_shl_i32(ret, arg1, t0);
7165 tcg_gen_br(l2);
7166 gen_set_label(l1);
7167 tcg_gen_movi_i32(ret, 0);
7168 gen_set_label(l2);
7169 tcg_temp_free_i32(t0);
7170}
7171GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7172static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7173{
7174 TCGv_i32 t0 = tcg_temp_new_i32();
7175 tcg_gen_andi_i32(t0, arg2, 0x1F);
7176 tcg_gen_rotl_i32(ret, arg1, t0);
7177 tcg_temp_free_i32(t0);
7178}
7179GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7180static inline void gen_evmergehi(DisasContext *ctx)
7181{
7182 if (unlikely(!ctx->spe_enabled)) {
7183 gen_exception(ctx, POWERPC_EXCP_SPEU);
7184 return;
7185 }
7186#if defined(TARGET_PPC64)
7187 TCGv t0 = tcg_temp_new();
7188 TCGv t1 = tcg_temp_new();
7189 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7190 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7191 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7192 tcg_temp_free(t0);
7193 tcg_temp_free(t1);
7194#else
7195 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7196 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7197#endif
7198}
7199GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7200static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7201{
7202 tcg_gen_sub_i32(ret, arg2, arg1);
7203}
7204GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7205
7206/* SPE arithmetic immediate */
7207#if defined(TARGET_PPC64)
7208#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7209static inline void gen_##name(DisasContext *ctx) \
7210{ \
7211 if (unlikely(!ctx->spe_enabled)) { \
7212 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7213 return; \
7214 } \
7215 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7216 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7217 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7218 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7219 tcg_op(t0, t0, rA(ctx->opcode)); \
7220 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7221 tcg_gen_trunc_i64_i32(t1, t2); \
7222 tcg_temp_free_i64(t2); \
7223 tcg_op(t1, t1, rA(ctx->opcode)); \
7224 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7225 tcg_temp_free_i32(t0); \
7226 tcg_temp_free_i32(t1); \
7227}
7228#else
7229#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7230static inline void gen_##name(DisasContext *ctx) \
7231{ \
7232 if (unlikely(!ctx->spe_enabled)) { \
7233 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7234 return; \
7235 } \
7236 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7237 rA(ctx->opcode)); \
7238 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7239 rA(ctx->opcode)); \
7240}
7241#endif
7242GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7243GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7244
7245/* SPE comparison */
7246#if defined(TARGET_PPC64)
7247#define GEN_SPEOP_COMP(name, tcg_cond) \
7248static inline void gen_##name(DisasContext *ctx) \
7249{ \
7250 if (unlikely(!ctx->spe_enabled)) { \
7251 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7252 return; \
7253 } \
7254 int l1 = gen_new_label(); \
7255 int l2 = gen_new_label(); \
7256 int l3 = gen_new_label(); \
7257 int l4 = gen_new_label(); \
7258 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7259 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7260 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7261 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7262 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7263 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7264 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7265 tcg_gen_br(l2); \
7266 gen_set_label(l1); \
7267 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7268 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7269 gen_set_label(l2); \
7270 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7271 tcg_gen_trunc_i64_i32(t0, t2); \
7272 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7273 tcg_gen_trunc_i64_i32(t1, t2); \
7274 tcg_temp_free_i64(t2); \
7275 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7276 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7277 ~(CRF_CH | CRF_CH_AND_CL)); \
7278 tcg_gen_br(l4); \
7279 gen_set_label(l3); \
7280 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7281 CRF_CH | CRF_CH_OR_CL); \
7282 gen_set_label(l4); \
7283 tcg_temp_free_i32(t0); \
7284 tcg_temp_free_i32(t1); \
7285}
7286#else
7287#define GEN_SPEOP_COMP(name, tcg_cond) \
7288static inline void gen_##name(DisasContext *ctx) \
7289{ \
7290 if (unlikely(!ctx->spe_enabled)) { \
7291 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7292 return; \
7293 } \
7294 int l1 = gen_new_label(); \
7295 int l2 = gen_new_label(); \
7296 int l3 = gen_new_label(); \
7297 int l4 = gen_new_label(); \
7298 \
7299 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7300 cpu_gpr[rB(ctx->opcode)], l1); \
7301 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7302 tcg_gen_br(l2); \
7303 gen_set_label(l1); \
7304 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7305 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7306 gen_set_label(l2); \
7307 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7308 cpu_gprh[rB(ctx->opcode)], l3); \
7309 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7310 ~(CRF_CH | CRF_CH_AND_CL)); \
7311 tcg_gen_br(l4); \
7312 gen_set_label(l3); \
7313 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7314 CRF_CH | CRF_CH_OR_CL); \
7315 gen_set_label(l4); \
7316}
7317#endif
7318GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7319GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7320GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7321GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7322GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7323
7324/* SPE misc */
7325static inline void gen_brinc(DisasContext *ctx)
7326{
7327 /* Note: brinc is usable even if SPE is disabled */
7328 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7329 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7330}
7331static inline void gen_evmergelo(DisasContext *ctx)
7332{
7333 if (unlikely(!ctx->spe_enabled)) {
7334 gen_exception(ctx, POWERPC_EXCP_SPEU);
7335 return;
7336 }
7337#if defined(TARGET_PPC64)
7338 TCGv t0 = tcg_temp_new();
7339 TCGv t1 = tcg_temp_new();
7340 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7341 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7342 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7343 tcg_temp_free(t0);
7344 tcg_temp_free(t1);
7345#else
7346 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7347 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7348#endif
7349}
7350static inline void gen_evmergehilo(DisasContext *ctx)
7351{
7352 if (unlikely(!ctx->spe_enabled)) {
7353 gen_exception(ctx, POWERPC_EXCP_SPEU);
7354 return;
7355 }
7356#if defined(TARGET_PPC64)
7357 TCGv t0 = tcg_temp_new();
7358 TCGv t1 = tcg_temp_new();
7359 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7360 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7361 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7362 tcg_temp_free(t0);
7363 tcg_temp_free(t1);
7364#else
7365 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7366 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7367#endif
7368}
7369static inline void gen_evmergelohi(DisasContext *ctx)
7370{
7371 if (unlikely(!ctx->spe_enabled)) {
7372 gen_exception(ctx, POWERPC_EXCP_SPEU);
7373 return;
7374 }
7375#if defined(TARGET_PPC64)
7376 TCGv t0 = tcg_temp_new();
7377 TCGv t1 = tcg_temp_new();
7378 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7379 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7380 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7381 tcg_temp_free(t0);
7382 tcg_temp_free(t1);
7383#else
7384 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7385 TCGv_i32 tmp = tcg_temp_new_i32();
7386 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7387 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7388 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7389 tcg_temp_free_i32(tmp);
7390 } else {
7391 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7392 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7393 }
7394#endif
7395}
7396static inline void gen_evsplati(DisasContext *ctx)
7397{
7398 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7399
7400#if defined(TARGET_PPC64)
7401 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7402#else
7403 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7404 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7405#endif
7406}
7407static inline void gen_evsplatfi(DisasContext *ctx)
7408{
7409 uint64_t imm = rA(ctx->opcode) << 27;
7410
7411#if defined(TARGET_PPC64)
7412 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7413#else
7414 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7415 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7416#endif
7417}
7418
7419static inline void gen_evsel(DisasContext *ctx)
7420{
7421 int l1 = gen_new_label();
7422 int l2 = gen_new_label();
7423 int l3 = gen_new_label();
7424 int l4 = gen_new_label();
7425 TCGv_i32 t0 = tcg_temp_local_new_i32();
7426#if defined(TARGET_PPC64)
7427 TCGv t1 = tcg_temp_local_new();
7428 TCGv t2 = tcg_temp_local_new();
7429#endif
7430 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7431 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7432#if defined(TARGET_PPC64)
7433 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7434#else
7435 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7436#endif
7437 tcg_gen_br(l2);
7438 gen_set_label(l1);
7439#if defined(TARGET_PPC64)
7440 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7441#else
7442 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7443#endif
7444 gen_set_label(l2);
7445 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7446 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7447#if defined(TARGET_PPC64)
7448 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7449#else
7450 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7451#endif
7452 tcg_gen_br(l4);
7453 gen_set_label(l3);
7454#if defined(TARGET_PPC64)
7455 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7456#else
7457 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7458#endif
7459 gen_set_label(l4);
7460 tcg_temp_free_i32(t0);
7461#if defined(TARGET_PPC64)
7462 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7463 tcg_temp_free(t1);
7464 tcg_temp_free(t2);
7465#endif
7466}
7467
7468static void gen_evsel0(DisasContext *ctx)
7469{
7470 gen_evsel(ctx);
7471}
7472
7473static void gen_evsel1(DisasContext *ctx)
7474{
7475 gen_evsel(ctx);
7476}
7477
7478static void gen_evsel2(DisasContext *ctx)
7479{
7480 gen_evsel(ctx);
7481}
7482
7483static void gen_evsel3(DisasContext *ctx)
7484{
7485 gen_evsel(ctx);
7486}
7487
7488/* Multiply */
7489
7490static inline void gen_evmwumi(DisasContext *ctx)
7491{
7492 TCGv_i64 t0, t1;
7493
7494 if (unlikely(!ctx->spe_enabled)) {
7495 gen_exception(ctx, POWERPC_EXCP_SPEU);
7496 return;
7497 }
7498
7499 t0 = tcg_temp_new_i64();
7500 t1 = tcg_temp_new_i64();
7501
7502 /* t0 := rA; t1 := rB */
7503#if defined(TARGET_PPC64)
7504 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7505 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7506#else
7507 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7508 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7509#endif
7510
7511 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7512
7513 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7514
7515 tcg_temp_free_i64(t0);
7516 tcg_temp_free_i64(t1);
7517}
7518
7519static inline void gen_evmwumia(DisasContext *ctx)
7520{
7521 TCGv_i64 tmp;
7522
7523 if (unlikely(!ctx->spe_enabled)) {
7524 gen_exception(ctx, POWERPC_EXCP_SPEU);
7525 return;
7526 }
7527
7528 gen_evmwumi(ctx); /* rD := rA * rB */
7529
7530 tmp = tcg_temp_new_i64();
7531
7532 /* acc := rD */
7533 gen_load_gpr64(tmp, rD(ctx->opcode));
7534 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7535 tcg_temp_free_i64(tmp);
7536}
7537
7538static inline void gen_evmwumiaa(DisasContext *ctx)
7539{
7540 TCGv_i64 acc;
7541 TCGv_i64 tmp;
7542
7543 if (unlikely(!ctx->spe_enabled)) {
7544 gen_exception(ctx, POWERPC_EXCP_SPEU);
7545 return;
7546 }
7547
7548 gen_evmwumi(ctx); /* rD := rA * rB */
7549
7550 acc = tcg_temp_new_i64();
7551 tmp = tcg_temp_new_i64();
7552
7553 /* tmp := rD */
7554 gen_load_gpr64(tmp, rD(ctx->opcode));
7555
7556 /* Load acc */
7557 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7558
7559 /* acc := tmp + acc */
7560 tcg_gen_add_i64(acc, acc, tmp);
7561
7562 /* Store acc */
7563 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7564
7565 /* rD := acc */
7566 gen_store_gpr64(rD(ctx->opcode), acc);
7567
7568 tcg_temp_free_i64(acc);
7569 tcg_temp_free_i64(tmp);
7570}
7571
7572static inline void gen_evmwsmi(DisasContext *ctx)
7573{
7574 TCGv_i64 t0, t1;
7575
7576 if (unlikely(!ctx->spe_enabled)) {
7577 gen_exception(ctx, POWERPC_EXCP_SPEU);
7578 return;
7579 }
7580
7581 t0 = tcg_temp_new_i64();
7582 t1 = tcg_temp_new_i64();
7583
7584 /* t0 := rA; t1 := rB */
7585#if defined(TARGET_PPC64)
7586 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7587 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7588#else
7589 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7590 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7591#endif
7592
7593 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7594
7595 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7596
7597 tcg_temp_free_i64(t0);
7598 tcg_temp_free_i64(t1);
7599}
7600
7601static inline void gen_evmwsmia(DisasContext *ctx)
7602{
7603 TCGv_i64 tmp;
7604
7605 gen_evmwsmi(ctx); /* rD := rA * rB */
7606
7607 tmp = tcg_temp_new_i64();
7608
7609 /* acc := rD */
7610 gen_load_gpr64(tmp, rD(ctx->opcode));
7611 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7612
7613 tcg_temp_free_i64(tmp);
7614}
7615
7616static inline void gen_evmwsmiaa(DisasContext *ctx)
7617{
7618 TCGv_i64 acc = tcg_temp_new_i64();
7619 TCGv_i64 tmp = tcg_temp_new_i64();
7620
7621 gen_evmwsmi(ctx); /* rD := rA * rB */
7622
7623 acc = tcg_temp_new_i64();
7624 tmp = tcg_temp_new_i64();
7625
7626 /* tmp := rD */
7627 gen_load_gpr64(tmp, rD(ctx->opcode));
7628
7629 /* Load acc */
7630 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7631
7632 /* acc := tmp + acc */
7633 tcg_gen_add_i64(acc, acc, tmp);
7634
7635 /* Store acc */
7636 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7637
7638 /* rD := acc */
7639 gen_store_gpr64(rD(ctx->opcode), acc);
7640
7641 tcg_temp_free_i64(acc);
7642 tcg_temp_free_i64(tmp);
7643}
7644
7645GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7646GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7647GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7648GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7649GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7650GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7651GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7652GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7653GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7654GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7655GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7656GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7657GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7658GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7659GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7660GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7661GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7662GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7663GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7664GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7665GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7666GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7667GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7668GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7669GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7670GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7671GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7672GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7673GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7674
7675/* SPE load and stores */
7676static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7677{
7678 target_ulong uimm = rB(ctx->opcode);
7679
7680 if (rA(ctx->opcode) == 0) {
7681 tcg_gen_movi_tl(EA, uimm << sh);
7682 } else {
7683 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7684#if defined(TARGET_PPC64)
7685 if (!ctx->sf_mode) {
7686 tcg_gen_ext32u_tl(EA, EA);
7687 }
7688#endif
7689 }
7690}
7691
7692static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7693{
7694#if defined(TARGET_PPC64)
7695 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7696#else
7697 TCGv_i64 t0 = tcg_temp_new_i64();
7698 gen_qemu_ld64(ctx, t0, addr);
7699 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7700 tcg_gen_shri_i64(t0, t0, 32);
7701 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7702 tcg_temp_free_i64(t0);
7703#endif
7704}
7705
7706static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7707{
7708#if defined(TARGET_PPC64)
7709 TCGv t0 = tcg_temp_new();
7710 gen_qemu_ld32u(ctx, t0, addr);
7711 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7712 gen_addr_add(ctx, addr, addr, 4);
7713 gen_qemu_ld32u(ctx, t0, addr);
7714 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7715 tcg_temp_free(t0);
7716#else
7717 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7718 gen_addr_add(ctx, addr, addr, 4);
7719 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7720#endif
7721}
7722
7723static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7724{
7725 TCGv t0 = tcg_temp_new();
7726#if defined(TARGET_PPC64)
7727 gen_qemu_ld16u(ctx, t0, addr);
7728 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7729 gen_addr_add(ctx, addr, addr, 2);
7730 gen_qemu_ld16u(ctx, t0, addr);
7731 tcg_gen_shli_tl(t0, t0, 32);
7732 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7733 gen_addr_add(ctx, addr, addr, 2);
7734 gen_qemu_ld16u(ctx, t0, addr);
7735 tcg_gen_shli_tl(t0, t0, 16);
7736 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7737 gen_addr_add(ctx, addr, addr, 2);
7738 gen_qemu_ld16u(ctx, t0, addr);
7739 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7740#else
7741 gen_qemu_ld16u(ctx, t0, addr);
7742 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7743 gen_addr_add(ctx, addr, addr, 2);
7744 gen_qemu_ld16u(ctx, t0, addr);
7745 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7746 gen_addr_add(ctx, addr, addr, 2);
7747 gen_qemu_ld16u(ctx, t0, addr);
7748 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7749 gen_addr_add(ctx, addr, addr, 2);
7750 gen_qemu_ld16u(ctx, t0, addr);
7751 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7752#endif
7753 tcg_temp_free(t0);
7754}
7755
7756static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7757{
7758 TCGv t0 = tcg_temp_new();
7759 gen_qemu_ld16u(ctx, t0, addr);
7760#if defined(TARGET_PPC64)
7761 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7762 tcg_gen_shli_tl(t0, t0, 16);
7763 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7764#else
7765 tcg_gen_shli_tl(t0, t0, 16);
7766 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7767 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7768#endif
7769 tcg_temp_free(t0);
7770}
7771
7772static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7773{
7774 TCGv t0 = tcg_temp_new();
7775 gen_qemu_ld16u(ctx, t0, addr);
7776#if defined(TARGET_PPC64)
7777 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7778 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7779#else
7780 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7781 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7782#endif
7783 tcg_temp_free(t0);
7784}
7785
7786static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7787{
7788 TCGv t0 = tcg_temp_new();
7789 gen_qemu_ld16s(ctx, t0, addr);
7790#if defined(TARGET_PPC64)
7791 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7792 tcg_gen_ext32u_tl(t0, t0);
7793 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7794#else
7795 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7796 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7797#endif
7798 tcg_temp_free(t0);
7799}
7800
7801static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7802{
7803 TCGv t0 = tcg_temp_new();
7804#if defined(TARGET_PPC64)
7805 gen_qemu_ld16u(ctx, t0, addr);
7806 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7807 gen_addr_add(ctx, addr, addr, 2);
7808 gen_qemu_ld16u(ctx, t0, addr);
7809 tcg_gen_shli_tl(t0, t0, 16);
7810 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7811#else
7812 gen_qemu_ld16u(ctx, t0, addr);
7813 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7814 gen_addr_add(ctx, addr, addr, 2);
7815 gen_qemu_ld16u(ctx, t0, addr);
7816 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7817#endif
7818 tcg_temp_free(t0);
7819}
7820
7821static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7822{
7823#if defined(TARGET_PPC64)
7824 TCGv t0 = tcg_temp_new();
7825 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7826 gen_addr_add(ctx, addr, addr, 2);
7827 gen_qemu_ld16u(ctx, t0, addr);
7828 tcg_gen_shli_tl(t0, t0, 32);
7829 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7830 tcg_temp_free(t0);
7831#else
7832 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7833 gen_addr_add(ctx, addr, addr, 2);
7834 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7835#endif
7836}
7837
7838static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7839{
7840#if defined(TARGET_PPC64)
7841 TCGv t0 = tcg_temp_new();
7842 gen_qemu_ld16s(ctx, t0, addr);
7843 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7844 gen_addr_add(ctx, addr, addr, 2);
7845 gen_qemu_ld16s(ctx, t0, addr);
7846 tcg_gen_shli_tl(t0, t0, 32);
7847 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7848 tcg_temp_free(t0);
7849#else
7850 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7851 gen_addr_add(ctx, addr, addr, 2);
7852 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7853#endif
7854}
7855
7856static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7857{
7858 TCGv t0 = tcg_temp_new();
7859 gen_qemu_ld32u(ctx, t0, addr);
7860#if defined(TARGET_PPC64)
7861 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7862 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7863#else
7864 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7865 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7866#endif
7867 tcg_temp_free(t0);
7868}
7869
7870static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7871{
7872 TCGv t0 = tcg_temp_new();
7873#if defined(TARGET_PPC64)
7874 gen_qemu_ld16u(ctx, t0, addr);
7875 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7876 tcg_gen_shli_tl(t0, t0, 32);
7877 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7878 gen_addr_add(ctx, addr, addr, 2);
7879 gen_qemu_ld16u(ctx, t0, addr);
7880 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7881 tcg_gen_shli_tl(t0, t0, 16);
7882 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7883#else
7884 gen_qemu_ld16u(ctx, t0, addr);
7885 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7886 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7887 gen_addr_add(ctx, addr, addr, 2);
7888 gen_qemu_ld16u(ctx, t0, addr);
7889 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7890 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7891#endif
7892 tcg_temp_free(t0);
7893}
7894
7895static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7896{
7897#if defined(TARGET_PPC64)
7898 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7899#else
7900 TCGv_i64 t0 = tcg_temp_new_i64();
7901 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7902 gen_qemu_st64(ctx, t0, addr);
7903 tcg_temp_free_i64(t0);
7904#endif
7905}
7906
7907static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7908{
7909#if defined(TARGET_PPC64)
7910 TCGv t0 = tcg_temp_new();
7911 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7912 gen_qemu_st32(ctx, t0, addr);
7913 tcg_temp_free(t0);
7914#else
7915 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7916#endif
7917 gen_addr_add(ctx, addr, addr, 4);
7918 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7919}
7920
7921static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7922{
7923 TCGv t0 = tcg_temp_new();
7924#if defined(TARGET_PPC64)
7925 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7926#else
7927 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7928#endif
7929 gen_qemu_st16(ctx, t0, addr);
7930 gen_addr_add(ctx, addr, addr, 2);
7931#if defined(TARGET_PPC64)
7932 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7933 gen_qemu_st16(ctx, t0, addr);
7934#else
7935 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7936#endif
7937 gen_addr_add(ctx, addr, addr, 2);
7938 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7939 gen_qemu_st16(ctx, t0, addr);
7940 tcg_temp_free(t0);
7941 gen_addr_add(ctx, addr, addr, 2);
7942 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7943}
7944
7945static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7946{
7947 TCGv t0 = tcg_temp_new();
7948#if defined(TARGET_PPC64)
7949 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7950#else
7951 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7952#endif
7953 gen_qemu_st16(ctx, t0, addr);
7954 gen_addr_add(ctx, addr, addr, 2);
7955 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7956 gen_qemu_st16(ctx, t0, addr);
7957 tcg_temp_free(t0);
7958}
7959
7960static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7961{
7962#if defined(TARGET_PPC64)
7963 TCGv t0 = tcg_temp_new();
7964 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7965 gen_qemu_st16(ctx, t0, addr);
7966 tcg_temp_free(t0);
7967#else
7968 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7969#endif
7970 gen_addr_add(ctx, addr, addr, 2);
7971 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7972}
7973
7974static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7975{
7976#if defined(TARGET_PPC64)
7977 TCGv t0 = tcg_temp_new();
7978 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7979 gen_qemu_st32(ctx, t0, addr);
7980 tcg_temp_free(t0);
7981#else
7982 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7983#endif
7984}
7985
7986static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7987{
7988 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7989}
7990
7991#define GEN_SPEOP_LDST(name, opc2, sh) \
7992static void glue(gen_, name)(DisasContext *ctx) \
7993{ \
7994 TCGv t0; \
7995 if (unlikely(!ctx->spe_enabled)) { \
7996 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7997 return; \
7998 } \
7999 gen_set_access_type(ctx, ACCESS_INT); \
8000 t0 = tcg_temp_new(); \
8001 if (Rc(ctx->opcode)) { \
8002 gen_addr_spe_imm_index(ctx, t0, sh); \
8003 } else { \
8004 gen_addr_reg_index(ctx, t0); \
8005 } \
8006 gen_op_##name(ctx, t0); \
8007 tcg_temp_free(t0); \
8008}
8009
8010GEN_SPEOP_LDST(evldd, 0x00, 3);
8011GEN_SPEOP_LDST(evldw, 0x01, 3);
8012GEN_SPEOP_LDST(evldh, 0x02, 3);
8013GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8014GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8015GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8016GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8017GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8018GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8019GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8020GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8021
8022GEN_SPEOP_LDST(evstdd, 0x10, 3);
8023GEN_SPEOP_LDST(evstdw, 0x11, 3);
8024GEN_SPEOP_LDST(evstdh, 0x12, 3);
8025GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8026GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8027GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8028GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8029
8030/* Multiply and add - TODO */
8031#if 0
8032GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8033GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8034GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8035GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8036GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8037GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8038GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8039GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8040GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8041GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8042GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8043GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8044
8045GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8046GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8047GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8048GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8049GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8050GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8051GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8052GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8053GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8054GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8055GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8056GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8057
8058GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8059GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8060GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8061GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
8062GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
8063
8064GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8065GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8066GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8067GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8068GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8069GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8070GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8071GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8072GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8073GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8074GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
8075GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8076
8077GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8078GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8079GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8080GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8081
8082GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8083GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8084GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8085GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8086GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8087GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8088GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8089GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8090GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8091GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8092GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
8093GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8094
8095GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8096GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8097GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8098GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
8099GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8100#endif
8101
8102/*** SPE floating-point extension ***/
8103#if defined(TARGET_PPC64)
8104#define GEN_SPEFPUOP_CONV_32_32(name) \
8105static inline void gen_##name(DisasContext *ctx) \
8106{ \
8107 TCGv_i32 t0; \
8108 TCGv t1; \
8109 t0 = tcg_temp_new_i32(); \
8110 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8111 gen_helper_##name(t0, cpu_env, t0); \
8112 t1 = tcg_temp_new(); \
8113 tcg_gen_extu_i32_tl(t1, t0); \
8114 tcg_temp_free_i32(t0); \
8115 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8116 0xFFFFFFFF00000000ULL); \
8117 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8118 tcg_temp_free(t1); \
8119}
8120#define GEN_SPEFPUOP_CONV_32_64(name) \
8121static inline void gen_##name(DisasContext *ctx) \
8122{ \
8123 TCGv_i32 t0; \
8124 TCGv t1; \
8125 t0 = tcg_temp_new_i32(); \
8126 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8127 t1 = tcg_temp_new(); \
8128 tcg_gen_extu_i32_tl(t1, t0); \
8129 tcg_temp_free_i32(t0); \
8130 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8131 0xFFFFFFFF00000000ULL); \
8132 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8133 tcg_temp_free(t1); \
8134}
8135#define GEN_SPEFPUOP_CONV_64_32(name) \
8136static inline void gen_##name(DisasContext *ctx) \
8137{ \
8138 TCGv_i32 t0 = tcg_temp_new_i32(); \
8139 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8140 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8141 tcg_temp_free_i32(t0); \
8142}
8143#define GEN_SPEFPUOP_CONV_64_64(name) \
8144static inline void gen_##name(DisasContext *ctx) \
8145{ \
8146 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8147 cpu_gpr[rB(ctx->opcode)]); \
8148}
8149#define GEN_SPEFPUOP_ARITH2_32_32(name) \
8150static inline void gen_##name(DisasContext *ctx) \
8151{ \
8152 TCGv_i32 t0, t1; \
8153 TCGv_i64 t2; \
8154 if (unlikely(!ctx->spe_enabled)) { \
8155 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8156 return; \
8157 } \
8158 t0 = tcg_temp_new_i32(); \
8159 t1 = tcg_temp_new_i32(); \
8160 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8161 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8162 gen_helper_##name(t0, cpu_env, t0, t1); \
8163 tcg_temp_free_i32(t1); \
8164 t2 = tcg_temp_new(); \
8165 tcg_gen_extu_i32_tl(t2, t0); \
8166 tcg_temp_free_i32(t0); \
8167 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8168 0xFFFFFFFF00000000ULL); \
8169 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8170 tcg_temp_free(t2); \
8171}
8172#define GEN_SPEFPUOP_ARITH2_64_64(name) \
8173static inline void gen_##name(DisasContext *ctx) \
8174{ \
8175 if (unlikely(!ctx->spe_enabled)) { \
8176 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8177 return; \
8178 } \
8179 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8180 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8181}
8182#define GEN_SPEFPUOP_COMP_32(name) \
8183static inline void gen_##name(DisasContext *ctx) \
8184{ \
8185 TCGv_i32 t0, t1; \
8186 if (unlikely(!ctx->spe_enabled)) { \
8187 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8188 return; \
8189 } \
8190 t0 = tcg_temp_new_i32(); \
8191 t1 = tcg_temp_new_i32(); \
8192 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8193 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8194 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8195 tcg_temp_free_i32(t0); \
8196 tcg_temp_free_i32(t1); \
8197}
8198#define GEN_SPEFPUOP_COMP_64(name) \
8199static inline void gen_##name(DisasContext *ctx) \
8200{ \
8201 if (unlikely(!ctx->spe_enabled)) { \
8202 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8203 return; \
8204 } \
8205 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8206 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8207}
8208#else
8209#define GEN_SPEFPUOP_CONV_32_32(name) \
8210static inline void gen_##name(DisasContext *ctx) \
8211{ \
8212 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8213 cpu_gpr[rB(ctx->opcode)]); \
8214}
8215#define GEN_SPEFPUOP_CONV_32_64(name) \
8216static inline void gen_##name(DisasContext *ctx) \
8217{ \
8218 TCGv_i64 t0 = tcg_temp_new_i64(); \
8219 gen_load_gpr64(t0, rB(ctx->opcode)); \
8220 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8221 tcg_temp_free_i64(t0); \
8222}
8223#define GEN_SPEFPUOP_CONV_64_32(name) \
8224static inline void gen_##name(DisasContext *ctx) \
8225{ \
8226 TCGv_i64 t0 = tcg_temp_new_i64(); \
8227 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8228 gen_store_gpr64(rD(ctx->opcode), t0); \
8229 tcg_temp_free_i64(t0); \
8230}
8231#define GEN_SPEFPUOP_CONV_64_64(name) \
8232static inline void gen_##name(DisasContext *ctx) \
8233{ \
8234 TCGv_i64 t0 = tcg_temp_new_i64(); \
8235 gen_load_gpr64(t0, rB(ctx->opcode)); \
8236 gen_helper_##name(t0, cpu_env, t0); \
8237 gen_store_gpr64(rD(ctx->opcode), t0); \
8238 tcg_temp_free_i64(t0); \
8239}
8240#define GEN_SPEFPUOP_ARITH2_32_32(name) \
8241static inline void gen_##name(DisasContext *ctx) \
8242{ \
8243 if (unlikely(!ctx->spe_enabled)) { \
8244 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8245 return; \
8246 } \
8247 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8248 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8249}
8250#define GEN_SPEFPUOP_ARITH2_64_64(name) \
8251static inline void gen_##name(DisasContext *ctx) \
8252{ \
8253 TCGv_i64 t0, t1; \
8254 if (unlikely(!ctx->spe_enabled)) { \
8255 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8256 return; \
8257 } \
8258 t0 = tcg_temp_new_i64(); \
8259 t1 = tcg_temp_new_i64(); \
8260 gen_load_gpr64(t0, rA(ctx->opcode)); \
8261 gen_load_gpr64(t1, rB(ctx->opcode)); \
8262 gen_helper_##name(t0, cpu_env, t0, t1); \
8263 gen_store_gpr64(rD(ctx->opcode), t0); \
8264 tcg_temp_free_i64(t0); \
8265 tcg_temp_free_i64(t1); \
8266}
8267#define GEN_SPEFPUOP_COMP_32(name) \
8268static inline void gen_##name(DisasContext *ctx) \
8269{ \
8270 if (unlikely(!ctx->spe_enabled)) { \
8271 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8272 return; \
8273 } \
8274 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8275 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8276}
8277#define GEN_SPEFPUOP_COMP_64(name) \
8278static inline void gen_##name(DisasContext *ctx) \
8279{ \
8280 TCGv_i64 t0, t1; \
8281 if (unlikely(!ctx->spe_enabled)) { \
8282 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8283 return; \
8284 } \
8285 t0 = tcg_temp_new_i64(); \
8286 t1 = tcg_temp_new_i64(); \
8287 gen_load_gpr64(t0, rA(ctx->opcode)); \
8288 gen_load_gpr64(t1, rB(ctx->opcode)); \
8289 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8290 tcg_temp_free_i64(t0); \
8291 tcg_temp_free_i64(t1); \
8292}
8293#endif
8294
8295/* Single precision floating-point vectors operations */
8296/* Arithmetic */
8297GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8298GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8299GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8300GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8301static inline void gen_evfsabs(DisasContext *ctx)
8302{
8303 if (unlikely(!ctx->spe_enabled)) {
8304 gen_exception(ctx, POWERPC_EXCP_SPEU);
8305 return;
8306 }
8307#if defined(TARGET_PPC64)
8308 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8309#else
8310 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8311 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8312#endif
8313}
8314static inline void gen_evfsnabs(DisasContext *ctx)
8315{
8316 if (unlikely(!ctx->spe_enabled)) {
8317 gen_exception(ctx, POWERPC_EXCP_SPEU);
8318 return;
8319 }
8320#if defined(TARGET_PPC64)
8321 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8322#else
8323 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8324 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8325#endif
8326}
8327static inline void gen_evfsneg(DisasContext *ctx)
8328{
8329 if (unlikely(!ctx->spe_enabled)) {
8330 gen_exception(ctx, POWERPC_EXCP_SPEU);
8331 return;
8332 }
8333#if defined(TARGET_PPC64)
8334 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8335#else
8336 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8337 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8338#endif
8339}
8340
8341/* Conversion */
8342GEN_SPEFPUOP_CONV_64_64(evfscfui);
8343GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8344GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8345GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8346GEN_SPEFPUOP_CONV_64_64(evfsctui);
8347GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8348GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8349GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8350GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8351GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8352
8353/* Comparison */
8354GEN_SPEFPUOP_COMP_64(evfscmpgt);
8355GEN_SPEFPUOP_COMP_64(evfscmplt);
8356GEN_SPEFPUOP_COMP_64(evfscmpeq);
8357GEN_SPEFPUOP_COMP_64(evfststgt);
8358GEN_SPEFPUOP_COMP_64(evfststlt);
8359GEN_SPEFPUOP_COMP_64(evfststeq);
8360
8361/* Opcodes definitions */
8362GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8363GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8364GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8365GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8366GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8367GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8368GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8369GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8370GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8371GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8372GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8373GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8374GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8375GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8376
8377/* Single precision floating-point operations */
8378/* Arithmetic */
8379GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8380GEN_SPEFPUOP_ARITH2_32_32(efssub);
8381GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8382GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8383static inline void gen_efsabs(DisasContext *ctx)
8384{
8385 if (unlikely(!ctx->spe_enabled)) {
8386 gen_exception(ctx, POWERPC_EXCP_SPEU);
8387 return;
8388 }
8389 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8390}
8391static inline void gen_efsnabs(DisasContext *ctx)
8392{
8393 if (unlikely(!ctx->spe_enabled)) {
8394 gen_exception(ctx, POWERPC_EXCP_SPEU);
8395 return;
8396 }
8397 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8398}
8399static inline void gen_efsneg(DisasContext *ctx)
8400{
8401 if (unlikely(!ctx->spe_enabled)) {
8402 gen_exception(ctx, POWERPC_EXCP_SPEU);
8403 return;
8404 }
8405 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8406}
8407
8408/* Conversion */
8409GEN_SPEFPUOP_CONV_32_32(efscfui);
8410GEN_SPEFPUOP_CONV_32_32(efscfsi);
8411GEN_SPEFPUOP_CONV_32_32(efscfuf);
8412GEN_SPEFPUOP_CONV_32_32(efscfsf);
8413GEN_SPEFPUOP_CONV_32_32(efsctui);
8414GEN_SPEFPUOP_CONV_32_32(efsctsi);
8415GEN_SPEFPUOP_CONV_32_32(efsctuf);
8416GEN_SPEFPUOP_CONV_32_32(efsctsf);
8417GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8418GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8419GEN_SPEFPUOP_CONV_32_64(efscfd);
8420
8421/* Comparison */
8422GEN_SPEFPUOP_COMP_32(efscmpgt);
8423GEN_SPEFPUOP_COMP_32(efscmplt);
8424GEN_SPEFPUOP_COMP_32(efscmpeq);
8425GEN_SPEFPUOP_COMP_32(efststgt);
8426GEN_SPEFPUOP_COMP_32(efststlt);
8427GEN_SPEFPUOP_COMP_32(efststeq);
8428
8429/* Opcodes definitions */
8430GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8431GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8432GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8433GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8434GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8435GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8436GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8437GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8438GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8439GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8440GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8441GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8442GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8443GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8444
8445/* Double precision floating-point operations */
8446/* Arithmetic */
8447GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8448GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8449GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8450GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8451static inline void gen_efdabs(DisasContext *ctx)
8452{
8453 if (unlikely(!ctx->spe_enabled)) {
8454 gen_exception(ctx, POWERPC_EXCP_SPEU);
8455 return;
8456 }
8457#if defined(TARGET_PPC64)
8458 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8459#else
8460 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8461 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8462#endif
8463}
8464static inline void gen_efdnabs(DisasContext *ctx)
8465{
8466 if (unlikely(!ctx->spe_enabled)) {
8467 gen_exception(ctx, POWERPC_EXCP_SPEU);
8468 return;
8469 }
8470#if defined(TARGET_PPC64)
8471 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8472#else
8473 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8474 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8475#endif
8476}
8477static inline void gen_efdneg(DisasContext *ctx)
8478{
8479 if (unlikely(!ctx->spe_enabled)) {
8480 gen_exception(ctx, POWERPC_EXCP_SPEU);
8481 return;
8482 }
8483#if defined(TARGET_PPC64)
8484 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8485#else
8486 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8487 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8488#endif
8489}
8490
8491/* Conversion */
8492GEN_SPEFPUOP_CONV_64_32(efdcfui);
8493GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8494GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8495GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8496GEN_SPEFPUOP_CONV_32_64(efdctui);
8497GEN_SPEFPUOP_CONV_32_64(efdctsi);
8498GEN_SPEFPUOP_CONV_32_64(efdctuf);
8499GEN_SPEFPUOP_CONV_32_64(efdctsf);
8500GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8501GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8502GEN_SPEFPUOP_CONV_64_32(efdcfs);
8503GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8504GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8505GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8506GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8507
8508/* Comparison */
8509GEN_SPEFPUOP_COMP_64(efdcmpgt);
8510GEN_SPEFPUOP_COMP_64(efdcmplt);
8511GEN_SPEFPUOP_COMP_64(efdcmpeq);
8512GEN_SPEFPUOP_COMP_64(efdtstgt);
8513GEN_SPEFPUOP_COMP_64(efdtstlt);
8514GEN_SPEFPUOP_COMP_64(efdtsteq);
8515
8516/* Opcodes definitions */
8517GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8518GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8519GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8520GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8521GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8522GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8523GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8524GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8525GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8526GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8527GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8528GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8529GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8530GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8531GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8532GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8533
8534static opcode_t opcodes[] = {
8535GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8536GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8537GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8538GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8539GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8540GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8541GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8542GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8543GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8544GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8545GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8546GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8547GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8548GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8549GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8550#if defined(TARGET_PPC64)
8551GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8552#endif
8553GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8554GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8555GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8556GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8557GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8558GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8559GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8560GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8561GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8562GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8563GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8564GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8565GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8566GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8567#if defined(TARGET_PPC64)
8568GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8569GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8570#endif
8571GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8572GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8573GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8574GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8575GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8576GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8577GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8578#if defined(TARGET_PPC64)
8579GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8580GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8581GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8582GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8583GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8584#endif
8585GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8586GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8587GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8588GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8589GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8590GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8591GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8592GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8593GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8594GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8595GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8596GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8597#if defined(TARGET_PPC64)
8598GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8599GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8600GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8601#endif
8602GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8603GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8604GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8605GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8606GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8607GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8608GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8609GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8610GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8611GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8612#if defined(TARGET_PPC64)
8613GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8614GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8615#endif
8616GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8617GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8618GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8619GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8620GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8621GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8622GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8623GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8624#if defined(TARGET_PPC64)
8625GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8626GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8627#endif
8628GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8629GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8630GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8631#if defined(TARGET_PPC64)
8632GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8633GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8634#endif
8635GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8636GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8637GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8638GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8639GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8640GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8641#if defined(TARGET_PPC64)
8642GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8643#endif
8644GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8645GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8646GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8647GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8648GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8649GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8650GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8651GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
8652GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
8653GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8654GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8655GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8656GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8657GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8658GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8659GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8660GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8661GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8662#if defined(TARGET_PPC64)
8663GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8664GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8665 PPC_SEGMENT_64B),
8666GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8667GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8668 PPC_SEGMENT_64B),
8669GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8670GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8671GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8672#endif
8673GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8674GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8675GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8676GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8677#if defined(TARGET_PPC64)
8678GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8679GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8680#endif
8681GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8682GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8683GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8684GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8685GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8686GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8687GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8688GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8689GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8690GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8691GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8692GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8693GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8694GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8695GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8696GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8697GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8698GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8699GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8700GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8701GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8702GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8703GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8704GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8705GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8706GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8707GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8708GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8709GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8710GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8711GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8712GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8713GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8714GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8715GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8716GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8717GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8718GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8719GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8720GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8721GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8722GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8723GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8724GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8725GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8726GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8727GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8728GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8729GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8730GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8731GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8732GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8733GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8734GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8735GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8736GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8737GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8738GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8739GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8740GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8741GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8742GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8743GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8744GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8745GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8746GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8747GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8748GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8749GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8750GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8751GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8752GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8753GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8754GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8755GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8756GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8757GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8758GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8759GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8760GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8761GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8762 PPC_NONE, PPC2_BOOKE206),
8763GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8764 PPC_NONE, PPC2_BOOKE206),
8765GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8766 PPC_NONE, PPC2_BOOKE206),
8767GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8768 PPC_NONE, PPC2_BOOKE206),
8769GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8770 PPC_NONE, PPC2_BOOKE206),
8771GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8772 PPC_NONE, PPC2_PRCNTL),
8773GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8774 PPC_NONE, PPC2_PRCNTL),
8775GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8776GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8777GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8778GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8779 PPC_BOOKE, PPC2_BOOKE206),
8780GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8781GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8782 PPC_BOOKE, PPC2_BOOKE206),
8783GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8784GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8785GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8786GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8787GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8788GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8789GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8790GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8791GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8792GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8793
8794#undef GEN_INT_ARITH_ADD
8795#undef GEN_INT_ARITH_ADD_CONST
8796#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8797GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8798#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8799 add_ca, compute_ca, compute_ov) \
8800GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8801GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8802GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8803GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8804GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8805GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8806GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8807GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8808GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8809GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8810GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8811
8812#undef GEN_INT_ARITH_DIVW
8813#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8814GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8815GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8816GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8817GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8818GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8819
8820#if defined(TARGET_PPC64)
8821#undef GEN_INT_ARITH_DIVD
8822#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8823GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8824GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8825GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8826GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8827GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8828
8829#undef GEN_INT_ARITH_MUL_HELPER
8830#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8831GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8832GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8833GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8834GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8835#endif
8836
8837#undef GEN_INT_ARITH_SUBF
8838#undef GEN_INT_ARITH_SUBF_CONST
8839#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8840GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8841#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8842 add_ca, compute_ca, compute_ov) \
8843GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8844GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8845GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8846GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8847GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8848GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8849GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8850GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8851GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8852GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8853GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8854
8855#undef GEN_LOGICAL1
8856#undef GEN_LOGICAL2
8857#define GEN_LOGICAL2(name, tcg_op, opc, type) \
8858GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8859#define GEN_LOGICAL1(name, tcg_op, opc, type) \
8860GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8861GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8862GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8863GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8864GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8865GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8866GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8867GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8868GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8869#if defined(TARGET_PPC64)
8870GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8871#endif
8872
8873#if defined(TARGET_PPC64)
8874#undef GEN_PPC64_R2
8875#undef GEN_PPC64_R4
8876#define GEN_PPC64_R2(name, opc1, opc2) \
8877GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8878GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8879 PPC_64B)
8880#define GEN_PPC64_R4(name, opc1, opc2) \
8881GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8882GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8883 PPC_64B), \
8884GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8885 PPC_64B), \
8886GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8887 PPC_64B)
8888GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8889GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8890GEN_PPC64_R4(rldic, 0x1E, 0x04),
8891GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8892GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8893GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8894#endif
8895
8896#undef _GEN_FLOAT_ACB
8897#undef GEN_FLOAT_ACB
8898#undef _GEN_FLOAT_AB
8899#undef GEN_FLOAT_AB
8900#undef _GEN_FLOAT_AC
8901#undef GEN_FLOAT_AC
8902#undef GEN_FLOAT_B
8903#undef GEN_FLOAT_BS
8904#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8905GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8906#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8907_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8908_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8909#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8910GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8911#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8912_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8913_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8914#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8915GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8916#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8917_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8918_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8919#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8920GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8921#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8922GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8923
8924GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8925GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8926GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8927GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8928GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8929GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8930_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8931GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8932GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8933GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8934GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8935GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8936GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8937GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8938GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8939#if defined(TARGET_PPC64)
8940GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8941GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8942GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8943#endif
8944GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8945GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8946GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8947GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8948GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8949GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8950GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8951
8952#undef GEN_LD
8953#undef GEN_LDU
8954#undef GEN_LDUX
8955#undef GEN_LDX_E
8956#undef GEN_LDS
8957#define GEN_LD(name, ldop, opc, type) \
8958GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8959#define GEN_LDU(name, ldop, opc, type) \
8960GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8961#define GEN_LDUX(name, ldop, opc2, opc3, type) \
8962GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8963#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8964GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8965#define GEN_LDS(name, ldop, op, type) \
8966GEN_LD(name, ldop, op | 0x20, type) \
8967GEN_LDU(name, ldop, op | 0x21, type) \
8968GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8969GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8970
8971GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8972GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8973GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8974GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8975#if defined(TARGET_PPC64)
8976GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8977GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8978GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8979GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8980GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8981#endif
8982GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8983GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8984
8985#undef GEN_ST
8986#undef GEN_STU
8987#undef GEN_STUX
8988#undef GEN_STX_E
8989#undef GEN_STS
8990#define GEN_ST(name, stop, opc, type) \
8991GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8992#define GEN_STU(name, stop, opc, type) \
8993GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8994#define GEN_STUX(name, stop, opc2, opc3, type) \
8995GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8996#define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8997GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8998#define GEN_STS(name, stop, op, type) \
8999GEN_ST(name, stop, op | 0x20, type) \
9000GEN_STU(name, stop, op | 0x21, type) \
9001GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9002GEN_STX(name, stop, 0x17, op | 0x00, type)
9003
9004GEN_STS(stb, st8, 0x06, PPC_INTEGER)
9005GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
9006GEN_STS(stw, st32, 0x04, PPC_INTEGER)
9007#if defined(TARGET_PPC64)
9008GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9009GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9010GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
9011#endif
9012GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
9013GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
9014
9015#undef GEN_LDF
9016#undef GEN_LDUF
9017#undef GEN_LDUXF
9018#undef GEN_LDXF
9019#undef GEN_LDFS
9020#define GEN_LDF(name, ldop, opc, type) \
9021GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9022#define GEN_LDUF(name, ldop, opc, type) \
9023GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9024#define GEN_LDUXF(name, ldop, opc, type) \
9025GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9026#define GEN_LDXF(name, ldop, opc2, opc3, type) \
9027GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9028#define GEN_LDFS(name, ldop, op, type) \
9029GEN_LDF(name, ldop, op | 0x20, type) \
9030GEN_LDUF(name, ldop, op | 0x21, type) \
9031GEN_LDUXF(name, ldop, op | 0x01, type) \
9032GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
9033
9034GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
9035GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
9036
9037#undef GEN_STF
9038#undef GEN_STUF
9039#undef GEN_STUXF
9040#undef GEN_STXF
9041#undef GEN_STFS
9042#define GEN_STF(name, stop, opc, type) \
9043GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9044#define GEN_STUF(name, stop, opc, type) \
9045GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9046#define GEN_STUXF(name, stop, opc, type) \
9047GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
9048#define GEN_STXF(name, stop, opc2, opc3, type) \
9049GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
9050#define GEN_STFS(name, stop, op, type) \
9051GEN_STF(name, stop, op | 0x20, type) \
9052GEN_STUF(name, stop, op | 0x21, type) \
9053GEN_STUXF(name, stop, op | 0x01, type) \
9054GEN_STXF(name, stop, 0x17, op | 0x00, type)
9055
9056GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
9057GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
9058GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
9059
9060#undef GEN_CRLOGIC
9061#define GEN_CRLOGIC(name, tcg_op, opc) \
9062GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
9063GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
9064GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
9065GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
9066GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
9067GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
9068GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
9069GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
9070GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
9071
9072#undef GEN_MAC_HANDLER
9073#define GEN_MAC_HANDLER(name, opc2, opc3) \
9074GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
9075GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
9076GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
9077GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
9078GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
9079GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
9080GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
9081GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
9082GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
9083GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
9084GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
9085GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
9086GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
9087GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
9088GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
9089GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
9090GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
9091GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
9092GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
9093GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
9094GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
9095GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
9096GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
9097GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
9098GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
9099GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
9100GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
9101GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
9102GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
9103GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
9104GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
9105GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9106GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9107GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9108GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9109GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9110GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9111GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9112GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9113GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9114GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9115GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9116GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9117
9118#undef GEN_VR_LDX
9119#undef GEN_VR_STX
9120#undef GEN_VR_LVE
9121#undef GEN_VR_STVE
9122#define GEN_VR_LDX(name, opc2, opc3) \
9123GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9124#define GEN_VR_STX(name, opc2, opc3) \
9125GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9126#define GEN_VR_LVE(name, opc2, opc3) \
9127 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9128#define GEN_VR_STVE(name, opc2, opc3) \
9129 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9130GEN_VR_LDX(lvx, 0x07, 0x03),
9131GEN_VR_LDX(lvxl, 0x07, 0x0B),
9132GEN_VR_LVE(bx, 0x07, 0x00),
9133GEN_VR_LVE(hx, 0x07, 0x01),
9134GEN_VR_LVE(wx, 0x07, 0x02),
9135GEN_VR_STX(svx, 0x07, 0x07),
9136GEN_VR_STX(svxl, 0x07, 0x0F),
9137GEN_VR_STVE(bx, 0x07, 0x04),
9138GEN_VR_STVE(hx, 0x07, 0x05),
9139GEN_VR_STVE(wx, 0x07, 0x06),
9140
9141#undef GEN_VX_LOGICAL
9142#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9143GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9144GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9145GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9146GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9147GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9148GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9149
9150#undef GEN_VXFORM
9151#define GEN_VXFORM(name, opc2, opc3) \
9152GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9153GEN_VXFORM(vaddubm, 0, 0),
9154GEN_VXFORM(vadduhm, 0, 1),
9155GEN_VXFORM(vadduwm, 0, 2),
9156GEN_VXFORM(vsububm, 0, 16),
9157GEN_VXFORM(vsubuhm, 0, 17),
9158GEN_VXFORM(vsubuwm, 0, 18),
9159GEN_VXFORM(vmaxub, 1, 0),
9160GEN_VXFORM(vmaxuh, 1, 1),
9161GEN_VXFORM(vmaxuw, 1, 2),
9162GEN_VXFORM(vmaxsb, 1, 4),
9163GEN_VXFORM(vmaxsh, 1, 5),
9164GEN_VXFORM(vmaxsw, 1, 6),
9165GEN_VXFORM(vminub, 1, 8),
9166GEN_VXFORM(vminuh, 1, 9),
9167GEN_VXFORM(vminuw, 1, 10),
9168GEN_VXFORM(vminsb, 1, 12),
9169GEN_VXFORM(vminsh, 1, 13),
9170GEN_VXFORM(vminsw, 1, 14),
9171GEN_VXFORM(vavgub, 1, 16),
9172GEN_VXFORM(vavguh, 1, 17),
9173GEN_VXFORM(vavguw, 1, 18),
9174GEN_VXFORM(vavgsb, 1, 20),
9175GEN_VXFORM(vavgsh, 1, 21),
9176GEN_VXFORM(vavgsw, 1, 22),
9177GEN_VXFORM(vmrghb, 6, 0),
9178GEN_VXFORM(vmrghh, 6, 1),
9179GEN_VXFORM(vmrghw, 6, 2),
9180GEN_VXFORM(vmrglb, 6, 4),
9181GEN_VXFORM(vmrglh, 6, 5),
9182GEN_VXFORM(vmrglw, 6, 6),
9183GEN_VXFORM(vmuloub, 4, 0),
9184GEN_VXFORM(vmulouh, 4, 1),
9185GEN_VXFORM(vmulosb, 4, 4),
9186GEN_VXFORM(vmulosh, 4, 5),
9187GEN_VXFORM(vmuleub, 4, 8),
9188GEN_VXFORM(vmuleuh, 4, 9),
9189GEN_VXFORM(vmulesb, 4, 12),
9190GEN_VXFORM(vmulesh, 4, 13),
9191GEN_VXFORM(vslb, 2, 4),
9192GEN_VXFORM(vslh, 2, 5),
9193GEN_VXFORM(vslw, 2, 6),
9194GEN_VXFORM(vsrb, 2, 8),
9195GEN_VXFORM(vsrh, 2, 9),
9196GEN_VXFORM(vsrw, 2, 10),
9197GEN_VXFORM(vsrab, 2, 12),
9198GEN_VXFORM(vsrah, 2, 13),
9199GEN_VXFORM(vsraw, 2, 14),
9200GEN_VXFORM(vslo, 6, 16),
9201GEN_VXFORM(vsro, 6, 17),
9202GEN_VXFORM(vaddcuw, 0, 6),
9203GEN_VXFORM(vsubcuw, 0, 22),
9204GEN_VXFORM(vaddubs, 0, 8),
9205GEN_VXFORM(vadduhs, 0, 9),
9206GEN_VXFORM(vadduws, 0, 10),
9207GEN_VXFORM(vaddsbs, 0, 12),
9208GEN_VXFORM(vaddshs, 0, 13),
9209GEN_VXFORM(vaddsws, 0, 14),
9210GEN_VXFORM(vsububs, 0, 24),
9211GEN_VXFORM(vsubuhs, 0, 25),
9212GEN_VXFORM(vsubuws, 0, 26),
9213GEN_VXFORM(vsubsbs, 0, 28),
9214GEN_VXFORM(vsubshs, 0, 29),
9215GEN_VXFORM(vsubsws, 0, 30),
9216GEN_VXFORM(vrlb, 2, 0),
9217GEN_VXFORM(vrlh, 2, 1),
9218GEN_VXFORM(vrlw, 2, 2),
9219GEN_VXFORM(vsl, 2, 7),
9220GEN_VXFORM(vsr, 2, 11),
9221GEN_VXFORM(vpkuhum, 7, 0),
9222GEN_VXFORM(vpkuwum, 7, 1),
9223GEN_VXFORM(vpkuhus, 7, 2),
9224GEN_VXFORM(vpkuwus, 7, 3),
9225GEN_VXFORM(vpkshus, 7, 4),
9226GEN_VXFORM(vpkswus, 7, 5),
9227GEN_VXFORM(vpkshss, 7, 6),
9228GEN_VXFORM(vpkswss, 7, 7),
9229GEN_VXFORM(vpkpx, 7, 12),
9230GEN_VXFORM(vsum4ubs, 4, 24),
9231GEN_VXFORM(vsum4sbs, 4, 28),
9232GEN_VXFORM(vsum4shs, 4, 25),
9233GEN_VXFORM(vsum2sws, 4, 26),
9234GEN_VXFORM(vsumsws, 4, 30),
9235GEN_VXFORM(vaddfp, 5, 0),
9236GEN_VXFORM(vsubfp, 5, 1),
9237GEN_VXFORM(vmaxfp, 5, 16),
9238GEN_VXFORM(vminfp, 5, 17),
9239
9240#undef GEN_VXRFORM1
9241#undef GEN_VXRFORM
9242#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9243 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9244#define GEN_VXRFORM(name, opc2, opc3) \
9245 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9246 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9247GEN_VXRFORM(vcmpequb, 3, 0)
9248GEN_VXRFORM(vcmpequh, 3, 1)
9249GEN_VXRFORM(vcmpequw, 3, 2)
9250GEN_VXRFORM(vcmpgtsb, 3, 12)
9251GEN_VXRFORM(vcmpgtsh, 3, 13)
9252GEN_VXRFORM(vcmpgtsw, 3, 14)
9253GEN_VXRFORM(vcmpgtub, 3, 8)
9254GEN_VXRFORM(vcmpgtuh, 3, 9)
9255GEN_VXRFORM(vcmpgtuw, 3, 10)
9256GEN_VXRFORM(vcmpeqfp, 3, 3)
9257GEN_VXRFORM(vcmpgefp, 3, 7)
9258GEN_VXRFORM(vcmpgtfp, 3, 11)
9259GEN_VXRFORM(vcmpbfp, 3, 15)
9260
9261#undef GEN_VXFORM_SIMM
9262#define GEN_VXFORM_SIMM(name, opc2, opc3) \
9263 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9264GEN_VXFORM_SIMM(vspltisb, 6, 12),
9265GEN_VXFORM_SIMM(vspltish, 6, 13),
9266GEN_VXFORM_SIMM(vspltisw, 6, 14),
9267
9268#undef GEN_VXFORM_NOA
9269#define GEN_VXFORM_NOA(name, opc2, opc3) \
9270 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9271GEN_VXFORM_NOA(vupkhsb, 7, 8),
9272GEN_VXFORM_NOA(vupkhsh, 7, 9),
9273GEN_VXFORM_NOA(vupklsb, 7, 10),
9274GEN_VXFORM_NOA(vupklsh, 7, 11),
9275GEN_VXFORM_NOA(vupkhpx, 7, 13),
9276GEN_VXFORM_NOA(vupklpx, 7, 15),
9277GEN_VXFORM_NOA(vrefp, 5, 4),
9278GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9279GEN_VXFORM_NOA(vexptefp, 5, 6),
9280GEN_VXFORM_NOA(vlogefp, 5, 7),
9281GEN_VXFORM_NOA(vrfim, 5, 8),
9282GEN_VXFORM_NOA(vrfin, 5, 9),
9283GEN_VXFORM_NOA(vrfip, 5, 10),
9284GEN_VXFORM_NOA(vrfiz, 5, 11),
9285
9286#undef GEN_VXFORM_UIMM
9287#define GEN_VXFORM_UIMM(name, opc2, opc3) \
9288 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9289GEN_VXFORM_UIMM(vspltb, 6, 8),
9290GEN_VXFORM_UIMM(vsplth, 6, 9),
9291GEN_VXFORM_UIMM(vspltw, 6, 10),
9292GEN_VXFORM_UIMM(vcfux, 5, 12),
9293GEN_VXFORM_UIMM(vcfsx, 5, 13),
9294GEN_VXFORM_UIMM(vctuxs, 5, 14),
9295GEN_VXFORM_UIMM(vctsxs, 5, 15),
9296
9297#undef GEN_VAFORM_PAIRED
9298#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9299 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9300GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9301GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9302GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9303GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9304GEN_VAFORM_PAIRED(vsel, vperm, 21),
9305GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9306
9307#undef GEN_SPE
9308#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9309 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9310GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9311GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9312GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9313GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9314GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9315GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9316GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9317GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9318GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9319GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9320GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9321GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9322GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9323GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9324GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9325GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9326GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9327GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9328GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9329GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9330GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9331GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9332GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9333GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9334GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9335GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9336GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9337GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9338GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9339
9340GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9341GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9342GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9343GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9344GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9345GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9346GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9347GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9348GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9349GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9350GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9351GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9352GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9353GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9354
9355GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9356GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9357GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9358GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9359GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9360GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9361GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9362GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9363GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9364GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9365GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9366GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9367GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9368GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9369
9370GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9371GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9372GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9373GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9374GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9375GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9376GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9377GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9378GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9379GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9380GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9381GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9382GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9383GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9384GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9385GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9386
9387#undef GEN_SPEOP_LDST
9388#define GEN_SPEOP_LDST(name, opc2, sh) \
9389GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9390GEN_SPEOP_LDST(evldd, 0x00, 3),
9391GEN_SPEOP_LDST(evldw, 0x01, 3),
9392GEN_SPEOP_LDST(evldh, 0x02, 3),
9393GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9394GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9395GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9396GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9397GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9398GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9399GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9400GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9401
9402GEN_SPEOP_LDST(evstdd, 0x10, 3),
9403GEN_SPEOP_LDST(evstdw, 0x11, 3),
9404GEN_SPEOP_LDST(evstdh, 0x12, 3),
9405GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9406GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9407GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9408GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9409};
9410
9411#include "helper_regs.h"
9412#include "translate_init.c"
9413
9414/*****************************************************************************/
9415/* Misc PowerPC helpers */
9416void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9417 int flags)
9418{
9419#define RGPL 4
9420#define RFPL 4
9421
9422 int i;
9423
9424 cpu_synchronize_state(env);
9425
9426 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9427 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9428 env->nip, env->lr, env->ctr, env->xer);
9429 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9430 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9431 env->hflags, env->mmu_idx);
9432#if !defined(NO_TIMER_DUMP)
9433 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9434#if !defined(CONFIG_USER_ONLY)
9435 " DECR %08" PRIu32
9436#endif
9437 "\n",
9438 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9439#if !defined(CONFIG_USER_ONLY)
9440 , cpu_ppc_load_decr(env)
9441#endif
9442 );
9443#endif
9444 for (i = 0; i < 32; i++) {
9445 if ((i & (RGPL - 1)) == 0)
9446 cpu_fprintf(f, "GPR%02d", i);
9447 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9448 if ((i & (RGPL - 1)) == (RGPL - 1))
9449 cpu_fprintf(f, "\n");
9450 }
9451 cpu_fprintf(f, "CR ");
9452 for (i = 0; i < 8; i++)
9453 cpu_fprintf(f, "%01x", env->crf[i]);
9454 cpu_fprintf(f, " [");
9455 for (i = 0; i < 8; i++) {
9456 char a = '-';
9457 if (env->crf[i] & 0x08)
9458 a = 'L';
9459 else if (env->crf[i] & 0x04)
9460 a = 'G';
9461 else if (env->crf[i] & 0x02)
9462 a = 'E';
9463 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9464 }
9465 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9466 env->reserve_addr);
9467 for (i = 0; i < 32; i++) {
9468 if ((i & (RFPL - 1)) == 0)
9469 cpu_fprintf(f, "FPR%02d", i);
9470 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9471 if ((i & (RFPL - 1)) == (RFPL - 1))
9472 cpu_fprintf(f, "\n");
9473 }
9474 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9475#if !defined(CONFIG_USER_ONLY)
9476 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9477 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9478 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9479 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9480
9481 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9482 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9483 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9484 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9485
9486 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9487 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9488 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9489 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9490
9491 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9492 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9493 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9494 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9495 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9496
9497 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9498 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9499 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9500 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9501
9502 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9503 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9504 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9505 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9506
9507 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9508 " EPR " TARGET_FMT_lx "\n",
9509 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9510 env->spr[SPR_BOOKE_EPR]);
9511
9512 /* FSL-specific */
9513 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9514 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9515 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9516 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9517
9518 /*
9519 * IVORs are left out as they are large and do not change often --
9520 * they can be read with "p $ivor0", "p $ivor1", etc.
9521 */
9522 }
9523
9524#if defined(TARGET_PPC64)
9525 if (env->flags & POWERPC_FLAG_CFAR) {
9526 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9527 }
9528#endif
9529
9530 switch (env->mmu_model) {
9531 case POWERPC_MMU_32B:
9532 case POWERPC_MMU_601:
9533 case POWERPC_MMU_SOFT_6xx:
9534 case POWERPC_MMU_SOFT_74xx:
9535#if defined(TARGET_PPC64)
9536 case POWERPC_MMU_620:
9537 case POWERPC_MMU_64B:
9538#endif
9539 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9540 break;
9541 case POWERPC_MMU_BOOKE206:
9542 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9543 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9544 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9545 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9546
9547 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9548 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9549 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9550 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9551
9552 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9553 " TLB1CFG " TARGET_FMT_lx "\n",
9554 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9555 env->spr[SPR_BOOKE_TLB1CFG]);
9556 break;
9557 default:
9558 break;
9559 }
9560#endif
9561
9562#undef RGPL
9563#undef RFPL
9564}
9565
9566void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9567 int flags)
9568{
9569#if defined(DO_PPC_STATISTICS)
9570 opc_handler_t **t1, **t2, **t3, *handler;
9571 int op1, op2, op3;
9572
9573 t1 = env->opcodes;
9574 for (op1 = 0; op1 < 64; op1++) {
9575 handler = t1[op1];
9576 if (is_indirect_opcode(handler)) {
9577 t2 = ind_table(handler);
9578 for (op2 = 0; op2 < 32; op2++) {
9579 handler = t2[op2];
9580 if (is_indirect_opcode(handler)) {
9581 t3 = ind_table(handler);
9582 for (op3 = 0; op3 < 32; op3++) {
9583 handler = t3[op3];
9584 if (handler->count == 0)
9585 continue;
9586 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9587 "%016" PRIx64 " %" PRId64 "\n",
9588 op1, op2, op3, op1, (op3 << 5) | op2,
9589 handler->oname,
9590 handler->count, handler->count);
9591 }
9592 } else {
9593 if (handler->count == 0)
9594 continue;
9595 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9596 "%016" PRIx64 " %" PRId64 "\n",
9597 op1, op2, op1, op2, handler->oname,
9598 handler->count, handler->count);
9599 }
9600 }
9601 } else {
9602 if (handler->count == 0)
9603 continue;
9604 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9605 " %" PRId64 "\n",
9606 op1, op1, handler->oname,
9607 handler->count, handler->count);
9608 }
9609 }
9610#endif
9611}
9612
9613/*****************************************************************************/
9614static inline void gen_intermediate_code_internal(CPUPPCState *env,
9615 TranslationBlock *tb,
9616 int search_pc)
9617{
9618 DisasContext ctx, *ctxp = &ctx;
9619 opc_handler_t **table, *handler;
9620 target_ulong pc_start;
9621 uint16_t *gen_opc_end;
9622 CPUBreakpoint *bp;
9623 int j, lj = -1;
9624 int num_insns;
9625 int max_insns;
9626
9627 pc_start = tb->pc;
9628 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9629 ctx.nip = pc_start;
9630 ctx.tb = tb;
9631 ctx.exception = POWERPC_EXCP_NONE;
9632 ctx.spr_cb = env->spr_cb;
9633 ctx.mem_idx = env->mmu_idx;
9634 ctx.access_type = -1;
9635 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9636#if defined(TARGET_PPC64)
9637 ctx.sf_mode = msr_is_64bit(env, env->msr);
9638 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9639#endif
9640 ctx.fpu_enabled = msr_fp;
9641 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9642 ctx.spe_enabled = msr_spe;
9643 else
9644 ctx.spe_enabled = 0;
9645 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9646 ctx.altivec_enabled = msr_vr;
9647 else
9648 ctx.altivec_enabled = 0;
9649 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9650 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9651 else
9652 ctx.singlestep_enabled = 0;
9653 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9654 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9655 if (unlikely(env->singlestep_enabled))
9656 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9657#if defined (DO_SINGLE_STEP) && 0
9658 /* Single step trace mode */
9659 msr_se = 1;
9660#endif
9661 num_insns = 0;
9662 max_insns = tb->cflags & CF_COUNT_MASK;
9663 if (max_insns == 0)
9664 max_insns = CF_COUNT_MASK;
9665
9666 gen_icount_start();
9667 /* Set env in case of segfault during code fetch */
9668 while (ctx.exception == POWERPC_EXCP_NONE
9669 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9670 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9671 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9672 if (bp->pc == ctx.nip) {
9673 gen_debug_exception(ctxp);
9674 break;
9675 }
9676 }
9677 }
9678 if (unlikely(search_pc)) {
9679 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9680 if (lj < j) {
9681 lj++;
9682 while (lj < j)
9683 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9684 }
9685 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9686 tcg_ctx.gen_opc_instr_start[lj] = 1;
9687 tcg_ctx.gen_opc_icount[lj] = num_insns;
9688 }
9689 LOG_DISAS("----------------\n");
9690 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9691 ctx.nip, ctx.mem_idx, (int)msr_ir);
9692 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9693 gen_io_start();
9694 if (unlikely(ctx.le_mode)) {
9695 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9696 } else {
9697 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9698 }
9699 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9700 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9701 opc3(ctx.opcode), little_endian ? "little" : "big");
9702 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9703 tcg_gen_debug_insn_start(ctx.nip);
9704 }
9705 ctx.nip += 4;
9706 table = env->opcodes;
9707 num_insns++;
9708 handler = table[opc1(ctx.opcode)];
9709 if (is_indirect_opcode(handler)) {
9710 table = ind_table(handler);
9711 handler = table[opc2(ctx.opcode)];
9712 if (is_indirect_opcode(handler)) {
9713 table = ind_table(handler);
9714 handler = table[opc3(ctx.opcode)];
9715 }
9716 }
9717 /* Is opcode *REALLY* valid ? */
9718 if (unlikely(handler->handler == &gen_invalid)) {
9719 if (qemu_log_enabled()) {
9720 qemu_log("invalid/unsupported opcode: "
9721 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9722 opc1(ctx.opcode), opc2(ctx.opcode),
9723 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9724 }
9725 } else {
9726 uint32_t inval;
9727
9728 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9729 inval = handler->inval2;
9730 } else {
9731 inval = handler->inval1;
9732 }
9733
9734 if (unlikely((ctx.opcode & inval) != 0)) {
9735 if (qemu_log_enabled()) {
9736 qemu_log("invalid bits: %08x for opcode: "
9737 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9738 ctx.opcode & inval, opc1(ctx.opcode),
9739 opc2(ctx.opcode), opc3(ctx.opcode),
9740 ctx.opcode, ctx.nip - 4);
9741 }
9742 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9743 break;
9744 }
9745 }
9746 (*(handler->handler))(&ctx);
9747#if defined(DO_PPC_STATISTICS)
9748 handler->count++;
9749#endif
9750 /* Check trace mode exceptions */
9751 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9752 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9753 ctx.exception != POWERPC_SYSCALL &&
9754 ctx.exception != POWERPC_EXCP_TRAP &&
9755 ctx.exception != POWERPC_EXCP_BRANCH)) {
9756 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9757 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9758 (env->singlestep_enabled) ||
9759 singlestep ||
9760 num_insns >= max_insns)) {
9761 /* if we reach a page boundary or are single stepping, stop
9762 * generation
9763 */
9764 break;
9765 }
9766 }
9767 if (tb->cflags & CF_LAST_IO)
9768 gen_io_end();
9769 if (ctx.exception == POWERPC_EXCP_NONE) {
9770 gen_goto_tb(&ctx, 0, ctx.nip);
9771 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9772 if (unlikely(env->singlestep_enabled)) {
9773 gen_debug_exception(ctxp);
9774 }
9775 /* Generate the return instruction */
9776 tcg_gen_exit_tb(0);
9777 }
9778 gen_icount_end(tb, num_insns);
9779 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9780 if (unlikely(search_pc)) {
9781 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9782 lj++;
9783 while (lj <= j)
9784 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9785 } else {
9786 tb->size = ctx.nip - pc_start;
9787 tb->icount = num_insns;
9788 }
9789#if defined(DEBUG_DISAS)
9790 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9791 int flags;
9792 flags = env->bfd_mach;
9793 flags |= ctx.le_mode << 16;
9794 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9795 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9796 qemu_log("\n");
9797 }
9798#endif
9799}
9800
9801void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9802{
9803 gen_intermediate_code_internal(env, tb, 0);
9804}
9805
9806void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9807{
9808 gen_intermediate_code_internal(env, tb, 1);
9809}
9810
9811void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9812{
9813 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9814}
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