]>
Commit | Line | Data |
---|---|---|
1 | /* | |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
28 | #ifndef CPU_XTENSA_H | |
29 | #define CPU_XTENSA_H | |
30 | ||
31 | #define ALIGNED_ONLY | |
32 | #define TARGET_LONG_BITS 32 | |
33 | ||
34 | #define CPUArchState struct CPUXtensaState | |
35 | ||
36 | #include "qemu-common.h" | |
37 | #include "exec/cpu-defs.h" | |
38 | #include "fpu/softfloat.h" | |
39 | ||
40 | #define NB_MMU_MODES 4 | |
41 | ||
42 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 | |
43 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
44 | #define TARGET_PAGE_BITS 12 | |
45 | ||
46 | enum { | |
47 | /* Additional instructions */ | |
48 | XTENSA_OPTION_CODE_DENSITY, | |
49 | XTENSA_OPTION_LOOP, | |
50 | XTENSA_OPTION_EXTENDED_L32R, | |
51 | XTENSA_OPTION_16_BIT_IMUL, | |
52 | XTENSA_OPTION_32_BIT_IMUL, | |
53 | XTENSA_OPTION_32_BIT_IMUL_HIGH, | |
54 | XTENSA_OPTION_32_BIT_IDIV, | |
55 | XTENSA_OPTION_MAC16, | |
56 | XTENSA_OPTION_MISC_OP_NSA, | |
57 | XTENSA_OPTION_MISC_OP_MINMAX, | |
58 | XTENSA_OPTION_MISC_OP_SEXT, | |
59 | XTENSA_OPTION_MISC_OP_CLAMPS, | |
60 | XTENSA_OPTION_COPROCESSOR, | |
61 | XTENSA_OPTION_BOOLEAN, | |
62 | XTENSA_OPTION_FP_COPROCESSOR, | |
63 | XTENSA_OPTION_MP_SYNCHRO, | |
64 | XTENSA_OPTION_CONDITIONAL_STORE, | |
65 | XTENSA_OPTION_ATOMCTL, | |
66 | XTENSA_OPTION_DEPBITS, | |
67 | ||
68 | /* Interrupts and exceptions */ | |
69 | XTENSA_OPTION_EXCEPTION, | |
70 | XTENSA_OPTION_RELOCATABLE_VECTOR, | |
71 | XTENSA_OPTION_UNALIGNED_EXCEPTION, | |
72 | XTENSA_OPTION_INTERRUPT, | |
73 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, | |
74 | XTENSA_OPTION_TIMER_INTERRUPT, | |
75 | ||
76 | /* Local memory */ | |
77 | XTENSA_OPTION_ICACHE, | |
78 | XTENSA_OPTION_ICACHE_TEST, | |
79 | XTENSA_OPTION_ICACHE_INDEX_LOCK, | |
80 | XTENSA_OPTION_DCACHE, | |
81 | XTENSA_OPTION_DCACHE_TEST, | |
82 | XTENSA_OPTION_DCACHE_INDEX_LOCK, | |
83 | XTENSA_OPTION_IRAM, | |
84 | XTENSA_OPTION_IROM, | |
85 | XTENSA_OPTION_DRAM, | |
86 | XTENSA_OPTION_DROM, | |
87 | XTENSA_OPTION_XLMI, | |
88 | XTENSA_OPTION_HW_ALIGNMENT, | |
89 | XTENSA_OPTION_MEMORY_ECC_PARITY, | |
90 | ||
91 | /* Memory protection and translation */ | |
92 | XTENSA_OPTION_REGION_PROTECTION, | |
93 | XTENSA_OPTION_REGION_TRANSLATION, | |
94 | XTENSA_OPTION_MMU, | |
95 | XTENSA_OPTION_CACHEATTR, | |
96 | ||
97 | /* Other */ | |
98 | XTENSA_OPTION_WINDOWED_REGISTER, | |
99 | XTENSA_OPTION_PROCESSOR_INTERFACE, | |
100 | XTENSA_OPTION_MISC_SR, | |
101 | XTENSA_OPTION_THREAD_POINTER, | |
102 | XTENSA_OPTION_PROCESSOR_ID, | |
103 | XTENSA_OPTION_DEBUG, | |
104 | XTENSA_OPTION_TRACE_PORT, | |
105 | }; | |
106 | ||
107 | enum { | |
108 | THREADPTR = 231, | |
109 | FCR = 232, | |
110 | FSR = 233, | |
111 | }; | |
112 | ||
113 | enum { | |
114 | LBEG = 0, | |
115 | LEND = 1, | |
116 | LCOUNT = 2, | |
117 | SAR = 3, | |
118 | BR = 4, | |
119 | LITBASE = 5, | |
120 | SCOMPARE1 = 12, | |
121 | ACCLO = 16, | |
122 | ACCHI = 17, | |
123 | MR = 32, | |
124 | WINDOW_BASE = 72, | |
125 | WINDOW_START = 73, | |
126 | PTEVADDR = 83, | |
127 | RASID = 90, | |
128 | ITLBCFG = 91, | |
129 | DTLBCFG = 92, | |
130 | IBREAKENABLE = 96, | |
131 | CACHEATTR = 98, | |
132 | ATOMCTL = 99, | |
133 | IBREAKA = 128, | |
134 | DBREAKA = 144, | |
135 | DBREAKC = 160, | |
136 | CONFIGID0 = 176, | |
137 | EPC1 = 177, | |
138 | DEPC = 192, | |
139 | EPS2 = 194, | |
140 | CONFIGID1 = 208, | |
141 | EXCSAVE1 = 209, | |
142 | CPENABLE = 224, | |
143 | INTSET = 226, | |
144 | INTCLEAR = 227, | |
145 | INTENABLE = 228, | |
146 | PS = 230, | |
147 | VECBASE = 231, | |
148 | EXCCAUSE = 232, | |
149 | DEBUGCAUSE = 233, | |
150 | CCOUNT = 234, | |
151 | PRID = 235, | |
152 | ICOUNT = 236, | |
153 | ICOUNTLEVEL = 237, | |
154 | EXCVADDR = 238, | |
155 | CCOMPARE = 240, | |
156 | MISC = 244, | |
157 | }; | |
158 | ||
159 | #define PS_INTLEVEL 0xf | |
160 | #define PS_INTLEVEL_SHIFT 0 | |
161 | ||
162 | #define PS_EXCM 0x10 | |
163 | #define PS_UM 0x20 | |
164 | ||
165 | #define PS_RING 0xc0 | |
166 | #define PS_RING_SHIFT 6 | |
167 | ||
168 | #define PS_OWB 0xf00 | |
169 | #define PS_OWB_SHIFT 8 | |
170 | ||
171 | #define PS_CALLINC 0x30000 | |
172 | #define PS_CALLINC_SHIFT 16 | |
173 | #define PS_CALLINC_LEN 2 | |
174 | ||
175 | #define PS_WOE 0x40000 | |
176 | ||
177 | #define DEBUGCAUSE_IC 0x1 | |
178 | #define DEBUGCAUSE_IB 0x2 | |
179 | #define DEBUGCAUSE_DB 0x4 | |
180 | #define DEBUGCAUSE_BI 0x8 | |
181 | #define DEBUGCAUSE_BN 0x10 | |
182 | #define DEBUGCAUSE_DI 0x20 | |
183 | #define DEBUGCAUSE_DBNUM 0xf00 | |
184 | #define DEBUGCAUSE_DBNUM_SHIFT 8 | |
185 | ||
186 | #define DBREAKC_SB 0x80000000 | |
187 | #define DBREAKC_LB 0x40000000 | |
188 | #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) | |
189 | #define DBREAKC_MASK 0x3f | |
190 | ||
191 | #define MAX_NAREG 64 | |
192 | #define MAX_NINTERRUPT 32 | |
193 | #define MAX_NLEVEL 6 | |
194 | #define MAX_NNMI 1 | |
195 | #define MAX_NCCOMPARE 3 | |
196 | #define MAX_TLB_WAY_SIZE 8 | |
197 | #define MAX_NDBREAK 2 | |
198 | ||
199 | #define REGION_PAGE_MASK 0xe0000000 | |
200 | ||
201 | #define PAGE_CACHE_MASK 0x700 | |
202 | #define PAGE_CACHE_SHIFT 8 | |
203 | #define PAGE_CACHE_INVALID 0x000 | |
204 | #define PAGE_CACHE_BYPASS 0x100 | |
205 | #define PAGE_CACHE_WT 0x200 | |
206 | #define PAGE_CACHE_WB 0x400 | |
207 | #define PAGE_CACHE_ISOLATE 0x600 | |
208 | ||
209 | enum { | |
210 | /* Static vectors */ | |
211 | EXC_RESET, | |
212 | EXC_MEMORY_ERROR, | |
213 | ||
214 | /* Dynamic vectors */ | |
215 | EXC_WINDOW_OVERFLOW4, | |
216 | EXC_WINDOW_UNDERFLOW4, | |
217 | EXC_WINDOW_OVERFLOW8, | |
218 | EXC_WINDOW_UNDERFLOW8, | |
219 | EXC_WINDOW_OVERFLOW12, | |
220 | EXC_WINDOW_UNDERFLOW12, | |
221 | EXC_IRQ, | |
222 | EXC_KERNEL, | |
223 | EXC_USER, | |
224 | EXC_DOUBLE, | |
225 | EXC_DEBUG, | |
226 | EXC_MAX | |
227 | }; | |
228 | ||
229 | enum { | |
230 | ILLEGAL_INSTRUCTION_CAUSE = 0, | |
231 | SYSCALL_CAUSE, | |
232 | INSTRUCTION_FETCH_ERROR_CAUSE, | |
233 | LOAD_STORE_ERROR_CAUSE, | |
234 | LEVEL1_INTERRUPT_CAUSE, | |
235 | ALLOCA_CAUSE, | |
236 | INTEGER_DIVIDE_BY_ZERO_CAUSE, | |
237 | PRIVILEGED_CAUSE = 8, | |
238 | LOAD_STORE_ALIGNMENT_CAUSE, | |
239 | ||
240 | INSTR_PIF_DATA_ERROR_CAUSE = 12, | |
241 | LOAD_STORE_PIF_DATA_ERROR_CAUSE, | |
242 | INSTR_PIF_ADDR_ERROR_CAUSE, | |
243 | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, | |
244 | ||
245 | INST_TLB_MISS_CAUSE, | |
246 | INST_TLB_MULTI_HIT_CAUSE, | |
247 | INST_FETCH_PRIVILEGE_CAUSE, | |
248 | INST_FETCH_PROHIBITED_CAUSE = 20, | |
249 | LOAD_STORE_TLB_MISS_CAUSE = 24, | |
250 | LOAD_STORE_TLB_MULTI_HIT_CAUSE, | |
251 | LOAD_STORE_PRIVILEGE_CAUSE, | |
252 | LOAD_PROHIBITED_CAUSE = 28, | |
253 | STORE_PROHIBITED_CAUSE, | |
254 | ||
255 | COPROCESSOR0_DISABLED = 32, | |
256 | }; | |
257 | ||
258 | typedef enum { | |
259 | INTTYPE_LEVEL, | |
260 | INTTYPE_EDGE, | |
261 | INTTYPE_NMI, | |
262 | INTTYPE_SOFTWARE, | |
263 | INTTYPE_TIMER, | |
264 | INTTYPE_DEBUG, | |
265 | INTTYPE_WRITE_ERR, | |
266 | INTTYPE_PROFILING, | |
267 | INTTYPE_MAX | |
268 | } interrupt_type; | |
269 | ||
270 | typedef struct xtensa_tlb_entry { | |
271 | uint32_t vaddr; | |
272 | uint32_t paddr; | |
273 | uint8_t asid; | |
274 | uint8_t attr; | |
275 | bool variable; | |
276 | } xtensa_tlb_entry; | |
277 | ||
278 | typedef struct xtensa_tlb { | |
279 | unsigned nways; | |
280 | const unsigned way_size[10]; | |
281 | bool varway56; | |
282 | unsigned nrefillentries; | |
283 | } xtensa_tlb; | |
284 | ||
285 | typedef struct XtensaGdbReg { | |
286 | int targno; | |
287 | int type; | |
288 | int group; | |
289 | unsigned size; | |
290 | } XtensaGdbReg; | |
291 | ||
292 | typedef struct XtensaGdbRegmap { | |
293 | int num_regs; | |
294 | int num_core_regs; | |
295 | /* PC + a + ar + sr + ur */ | |
296 | XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; | |
297 | } XtensaGdbRegmap; | |
298 | ||
299 | typedef struct XtensaConfig { | |
300 | const char *name; | |
301 | uint64_t options; | |
302 | XtensaGdbRegmap gdb_regmap; | |
303 | unsigned nareg; | |
304 | int excm_level; | |
305 | int ndepc; | |
306 | uint32_t vecbase; | |
307 | uint32_t exception_vector[EXC_MAX]; | |
308 | unsigned ninterrupt; | |
309 | unsigned nlevel; | |
310 | uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; | |
311 | uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; | |
312 | uint32_t inttype_mask[INTTYPE_MAX]; | |
313 | struct { | |
314 | uint32_t level; | |
315 | interrupt_type inttype; | |
316 | } interrupt[MAX_NINTERRUPT]; | |
317 | unsigned nccompare; | |
318 | uint32_t timerint[MAX_NCCOMPARE]; | |
319 | unsigned nextint; | |
320 | unsigned extint[MAX_NINTERRUPT]; | |
321 | ||
322 | unsigned debug_level; | |
323 | unsigned nibreak; | |
324 | unsigned ndbreak; | |
325 | ||
326 | uint32_t configid[2]; | |
327 | ||
328 | uint32_t clock_freq_khz; | |
329 | ||
330 | xtensa_tlb itlb; | |
331 | xtensa_tlb dtlb; | |
332 | } XtensaConfig; | |
333 | ||
334 | typedef struct XtensaConfigList { | |
335 | const XtensaConfig *config; | |
336 | struct XtensaConfigList *next; | |
337 | } XtensaConfigList; | |
338 | ||
339 | #ifdef HOST_WORDS_BIGENDIAN | |
340 | enum { | |
341 | FP_F32_HIGH, | |
342 | FP_F32_LOW, | |
343 | }; | |
344 | #else | |
345 | enum { | |
346 | FP_F32_LOW, | |
347 | FP_F32_HIGH, | |
348 | }; | |
349 | #endif | |
350 | ||
351 | typedef struct CPUXtensaState { | |
352 | const XtensaConfig *config; | |
353 | uint32_t regs[16]; | |
354 | uint32_t pc; | |
355 | uint32_t sregs[256]; | |
356 | uint32_t uregs[256]; | |
357 | uint32_t phys_regs[MAX_NAREG]; | |
358 | union { | |
359 | float32 f32[2]; | |
360 | float64 f64; | |
361 | } fregs[16]; | |
362 | float_status fp_status; | |
363 | ||
364 | xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; | |
365 | xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; | |
366 | unsigned autorefill_idx; | |
367 | ||
368 | int pending_irq_level; /* level of last raised IRQ */ | |
369 | void **irq_inputs; | |
370 | QEMUTimer *ccompare_timer; | |
371 | uint32_t wake_ccount; | |
372 | int64_t halt_clock; | |
373 | ||
374 | int exception_taken; | |
375 | ||
376 | /* Watchpoints for DBREAK registers */ | |
377 | struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; | |
378 | ||
379 | CPU_COMMON | |
380 | } CPUXtensaState; | |
381 | ||
382 | #include "cpu-qom.h" | |
383 | ||
384 | #define cpu_exec cpu_xtensa_exec | |
385 | #define cpu_signal_handler cpu_xtensa_signal_handler | |
386 | #define cpu_list xtensa_cpu_list | |
387 | ||
388 | #ifdef TARGET_WORDS_BIGENDIAN | |
389 | #define XTENSA_DEFAULT_CPU_MODEL "fsf" | |
390 | #else | |
391 | #define XTENSA_DEFAULT_CPU_MODEL "dc232b" | |
392 | #endif | |
393 | ||
394 | XtensaCPU *cpu_xtensa_init(const char *cpu_model); | |
395 | ||
396 | #define cpu_init(cpu_model) CPU(cpu_xtensa_init(cpu_model)) | |
397 | ||
398 | void xtensa_translate_init(void); | |
399 | void xtensa_breakpoint_handler(CPUState *cs); | |
400 | int cpu_xtensa_exec(CPUState *cpu); | |
401 | void xtensa_finalize_config(XtensaConfig *config); | |
402 | void xtensa_register_core(XtensaConfigList *node); | |
403 | void check_interrupts(CPUXtensaState *s); | |
404 | void xtensa_irq_init(CPUXtensaState *env); | |
405 | void *xtensa_get_extint(CPUXtensaState *env, unsigned extint); | |
406 | void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d); | |
407 | void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active); | |
408 | void xtensa_rearm_ccompare_timer(CPUXtensaState *env); | |
409 | int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); | |
410 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); | |
411 | void xtensa_sync_window_from_phys(CPUXtensaState *env); | |
412 | void xtensa_sync_phys_from_window(CPUXtensaState *env); | |
413 | uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way); | |
414 | void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, | |
415 | uint32_t *vpn, uint32_t wi, uint32_t *ei); | |
416 | int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, | |
417 | uint32_t *pwi, uint32_t *pei, uint8_t *pring); | |
418 | void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, | |
419 | xtensa_tlb_entry *entry, bool dtlb, | |
420 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); | |
421 | void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, | |
422 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); | |
423 | int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, | |
424 | uint32_t vaddr, int is_write, int mmu_idx, | |
425 | uint32_t *paddr, uint32_t *page_size, unsigned *access); | |
426 | void reset_mmu(CPUXtensaState *env); | |
427 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env); | |
428 | void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); | |
429 | ||
430 | ||
431 | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) | |
432 | #define XTENSA_OPTION_ALL (~(uint64_t)0) | |
433 | ||
434 | static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, | |
435 | uint64_t opt) | |
436 | { | |
437 | return (config->options & opt) != 0; | |
438 | } | |
439 | ||
440 | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) | |
441 | { | |
442 | return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); | |
443 | } | |
444 | ||
445 | static inline int xtensa_get_cintlevel(const CPUXtensaState *env) | |
446 | { | |
447 | int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; | |
448 | if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { | |
449 | level = env->config->excm_level; | |
450 | } | |
451 | return level; | |
452 | } | |
453 | ||
454 | static inline int xtensa_get_ring(const CPUXtensaState *env) | |
455 | { | |
456 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { | |
457 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
458 | } else { | |
459 | return 0; | |
460 | } | |
461 | } | |
462 | ||
463 | static inline int xtensa_get_cring(const CPUXtensaState *env) | |
464 | { | |
465 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && | |
466 | (env->sregs[PS] & PS_EXCM) == 0) { | |
467 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; | |
468 | } else { | |
469 | return 0; | |
470 | } | |
471 | } | |
472 | ||
473 | static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, | |
474 | bool dtlb, unsigned wi, unsigned ei) | |
475 | { | |
476 | return dtlb ? | |
477 | env->dtlb[wi] + ei : | |
478 | env->itlb[wi] + ei; | |
479 | } | |
480 | ||
481 | static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) | |
482 | { | |
483 | return env->sregs[WINDOW_START] | | |
484 | (env->sregs[WINDOW_START] << env->config->nareg / 4); | |
485 | } | |
486 | ||
487 | /* MMU modes definitions */ | |
488 | #define MMU_MODE0_SUFFIX _ring0 | |
489 | #define MMU_MODE1_SUFFIX _ring1 | |
490 | #define MMU_MODE2_SUFFIX _ring2 | |
491 | #define MMU_MODE3_SUFFIX _ring3 | |
492 | ||
493 | static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) | |
494 | { | |
495 | return xtensa_get_cring(env); | |
496 | } | |
497 | ||
498 | #define XTENSA_TBFLAG_RING_MASK 0x3 | |
499 | #define XTENSA_TBFLAG_EXCM 0x4 | |
500 | #define XTENSA_TBFLAG_LITBASE 0x8 | |
501 | #define XTENSA_TBFLAG_DEBUG 0x10 | |
502 | #define XTENSA_TBFLAG_ICOUNT 0x20 | |
503 | #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 | |
504 | #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 | |
505 | #define XTENSA_TBFLAG_EXCEPTION 0x4000 | |
506 | #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 | |
507 | #define XTENSA_TBFLAG_WINDOW_SHIFT 15 | |
508 | ||
509 | static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, | |
510 | target_ulong *cs_base, int *flags) | |
511 | { | |
512 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); | |
513 | ||
514 | *pc = env->pc; | |
515 | *cs_base = 0; | |
516 | *flags = 0; | |
517 | *flags |= xtensa_get_ring(env); | |
518 | if (env->sregs[PS] & PS_EXCM) { | |
519 | *flags |= XTENSA_TBFLAG_EXCM; | |
520 | } | |
521 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && | |
522 | (env->sregs[LITBASE] & 1)) { | |
523 | *flags |= XTENSA_TBFLAG_LITBASE; | |
524 | } | |
525 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { | |
526 | if (xtensa_get_cintlevel(env) < env->config->debug_level) { | |
527 | *flags |= XTENSA_TBFLAG_DEBUG; | |
528 | } | |
529 | if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { | |
530 | *flags |= XTENSA_TBFLAG_ICOUNT; | |
531 | } | |
532 | } | |
533 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { | |
534 | *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; | |
535 | } | |
536 | if (cs->singlestep_enabled && env->exception_taken) { | |
537 | *flags |= XTENSA_TBFLAG_EXCEPTION; | |
538 | } | |
539 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && | |
540 | (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { | |
541 | uint32_t windowstart = xtensa_replicate_windowstart(env) >> | |
542 | (env->sregs[WINDOW_BASE] + 1); | |
543 | uint32_t w = ctz32(windowstart | 0x8); | |
544 | ||
545 | *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT; | |
546 | } else { | |
547 | *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; | |
548 | } | |
549 | } | |
550 | ||
551 | #include "exec/cpu-all.h" | |
552 | #include "exec/exec-all.h" | |
553 | ||
554 | #endif |