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Commit | Line | Data |
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1 | .include "macros.inc" | |
2 | ||
3 | test_suite timer | |
4 | ||
5 | test ccount | |
6 | rsr a3, ccount | |
7 | rsr a4, ccount | |
8 | sub a3, a4, a3 | |
9 | assert eqi, a3, 1 | |
10 | test_end | |
11 | ||
12 | test ccompare | |
13 | movi a2, 0 | |
14 | wsr a2, intenable | |
15 | rsr a2, interrupt | |
16 | wsr a2, intclear | |
17 | wsr a2, ccompare1 | |
18 | wsr a2, ccompare2 | |
19 | ||
20 | movi a3, 20 | |
21 | rsr a2, ccount | |
22 | addi a2, a2, 20 | |
23 | wsr a2, ccompare0 | |
24 | rsr a2, interrupt | |
25 | assert eqi, a2, 0 | |
26 | loop a3, 1f | |
27 | rsr a3, interrupt | |
28 | bnez a3, 2f | |
29 | 1: | |
30 | test_fail | |
31 | 2: | |
32 | test_end | |
33 | ||
34 | test ccompare0_interrupt | |
35 | set_vector kernel, 2f | |
36 | movi a2, 0 | |
37 | wsr a2, intenable | |
38 | rsr a2, interrupt | |
39 | wsr a2, intclear | |
40 | wsr a2, ccompare1 | |
41 | wsr a2, ccompare2 | |
42 | ||
43 | movi a3, 20 | |
44 | rsr a2, ccount | |
45 | addi a2, a2, 20 | |
46 | wsr a2, ccompare0 | |
47 | rsync | |
48 | rsr a2, interrupt | |
49 | assert eqi, a2, 0 | |
50 | ||
51 | movi a2, 0x40 | |
52 | wsr a2, intenable | |
53 | rsil a2, 0 | |
54 | loop a3, 1f | |
55 | nop | |
56 | 1: | |
57 | test_fail | |
58 | 2: | |
59 | rsr a2, exccause | |
60 | assert eqi, a2, 4 /* LEVEL1_INTERRUPT_CAUSE */ | |
61 | test_end | |
62 | ||
63 | test ccompare1_interrupt | |
64 | set_vector level3, 2f | |
65 | movi a2, 0 | |
66 | wsr a2, intenable | |
67 | rsr a2, interrupt | |
68 | wsr a2, intclear | |
69 | wsr a2, ccompare0 | |
70 | wsr a2, ccompare2 | |
71 | ||
72 | movi a3, 20 | |
73 | rsr a2, ccount | |
74 | addi a2, a2, 20 | |
75 | wsr a2, ccompare1 | |
76 | rsync | |
77 | rsr a2, interrupt | |
78 | assert eqi, a2, 0 | |
79 | movi a2, 0x400 | |
80 | wsr a2, intenable | |
81 | rsil a2, 2 | |
82 | loop a3, 1f | |
83 | nop | |
84 | 1: | |
85 | test_fail | |
86 | 2: | |
87 | test_end | |
88 | ||
89 | test ccompare2_interrupt | |
90 | set_vector level5, 2f | |
91 | movi a2, 0 | |
92 | wsr a2, intenable | |
93 | rsr a2, interrupt | |
94 | wsr a2, intclear | |
95 | wsr a2, ccompare0 | |
96 | wsr a2, ccompare1 | |
97 | ||
98 | movi a3, 20 | |
99 | rsr a2, ccount | |
100 | addi a2, a2, 20 | |
101 | wsr a2, ccompare2 | |
102 | rsync | |
103 | rsr a2, interrupt | |
104 | assert eqi, a2, 0 | |
105 | movi a2, 0x2000 | |
106 | wsr a2, intenable | |
107 | rsil a2, 4 | |
108 | loop a3, 1f | |
109 | nop | |
110 | 1: | |
111 | test_fail | |
112 | 2: | |
113 | test_end | |
114 | ||
115 | test_suite_end |