[mirror_ubuntu-artful-kernel.git] / virt / kvm / arm / vgic / vgic.h

/*
 * Copyright (C) 2015, 2016 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __KVM_ARM_VGIC_NEW_H__
#define __KVM_ARM_VGIC_NEW_H__

#include <linux/irqchip/arm-gic-common.h>

#define PRODUCT_ID_KVM		0x4b	/* ASCII code K */
#define IMPLEMENTER_ARM		0x43b

#define VGIC_ADDR_UNDEF		(-1)
#define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)

#define INTERRUPT_ID_BITS_SPIS	10
#define INTERRUPT_ID_BITS_ITS	16
#define VGIC_PRI_BITS		5

#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)

#define VGIC_AFFINITY_0_SHIFT 0
#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
#define VGIC_AFFINITY_1_SHIFT 8
#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
#define VGIC_AFFINITY_2_SHIFT 16
#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
#define VGIC_AFFINITY_3_SHIFT 24
#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)

#define VGIC_AFFINITY_LEVEL(reg, level) \
	((((reg) & VGIC_AFFINITY_## level ##_MASK) \
	>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))

/*
 * The Userspace encodes the affinity differently from the MPIDR,
 * Below macro converts vgic userspace format to MPIDR reg format.
 */
#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
			    VGIC_AFFINITY_LEVEL(val, 1) | \
			    VGIC_AFFINITY_LEVEL(val, 2) | \
			    VGIC_AFFINITY_LEVEL(val, 3))

/*
 * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
 * below macros are defined for CPUREG encoding.
 */
#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK   0x000000000000c000
#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT  14
#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK   0x0000000000003800
#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT  11
#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK   0x0000000000000780
#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT  7
#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK   0x0000000000000078
#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT  3
#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK   0x0000000000000007
#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT  0

#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
				      KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)

/*
 * As per Documentation/virtual/kvm/devices/arm-vgic-its.txt,
 * below macros are defined for ITS table entry encoding.
 */
#define KVM_ITS_CTE_VALID_SHIFT		63
#define KVM_ITS_CTE_VALID_MASK		BIT_ULL(63)
#define KVM_ITS_CTE_RDBASE_SHIFT	16
#define KVM_ITS_CTE_ICID_MASK		GENMASK_ULL(15, 0)
#define KVM_ITS_ITE_NEXT_SHIFT		48
#define KVM_ITS_ITE_PINTID_SHIFT	16
#define KVM_ITS_ITE_PINTID_MASK		GENMASK_ULL(47, 16)
#define KVM_ITS_ITE_ICID_MASK		GENMASK_ULL(15, 0)
#define KVM_ITS_DTE_VALID_SHIFT		63
#define KVM_ITS_DTE_VALID_MASK		BIT_ULL(63)
#define KVM_ITS_DTE_NEXT_SHIFT		49
#define KVM_ITS_DTE_NEXT_MASK		GENMASK_ULL(62, 49)
#define KVM_ITS_DTE_ITTADDR_SHIFT	5
#define KVM_ITS_DTE_ITTADDR_MASK	GENMASK_ULL(48, 5)
#define KVM_ITS_DTE_SIZE_MASK		GENMASK_ULL(4, 0)
#define KVM_ITS_L1E_VALID_MASK		BIT_ULL(63)
/* we only support 64 kB translation table page size */
#define KVM_ITS_L1E_ADDR_MASK		GENMASK_ULL(51, 16)

static inline bool irq_is_pending(struct vgic_irq *irq)
{
	if (irq->config == VGIC_CONFIG_EDGE)
		return irq->pending_latch;
	else
		return irq->pending_latch || irq->line_level;
}

/*
 * This struct provides an intermediate representation of the fields contained
 * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
 * state to userspace can generate either GICv2 or GICv3 CPU interface
 * registers regardless of the hardware backed GIC used.
 */
struct vgic_vmcr {
	u32	grpen0;
	u32	grpen1;

	u32	ackctl;
	u32	fiqen;
	u32	cbpr;
	u32	eoim;

	u32	abpr;
	u32	bpr;
	u32	pmr;  /* Priority mask field in the GICC_PMR and
		       * ICC_PMR_EL1 priority field format */
};

struct vgic_reg_attr {
	struct kvm_vcpu *vcpu;
	gpa_t addr;
};

int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
		       struct vgic_reg_attr *reg_attr);
int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
		       struct vgic_reg_attr *reg_attr);
const struct vgic_register_region *
vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
		     gpa_t addr, int len);
struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
			      u32 intid);
void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq);
void vgic_kick_vcpus(struct kvm *kvm);

int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
		      phys_addr_t addr, phys_addr_t alignment);

void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val);
int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			  int offset, u32 *val);
void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v2_enable(struct kvm_vcpu *vcpu);
int vgic_v2_probe(const struct gic_kvm_info *info);
int vgic_v2_map_resources(struct kvm *kvm);
int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
			     enum vgic_type);

void vgic_v2_init_lrs(void);
void vgic_v2_load(struct kvm_vcpu *vcpu);
void vgic_v2_put(struct kvm_vcpu *vcpu);

static inline void vgic_get_irq_kref(struct vgic_irq *irq)
{
	if (irq->intid < VGIC_MIN_LPI)
		return;

	kref_get(&irq->refcount);
}

void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_v3_enable(struct kvm_vcpu *vcpu);
int vgic_v3_probe(const struct gic_kvm_info *info);
int vgic_v3_map_resources(struct kvm *kvm);
int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
int vgic_v3_save_pending_tables(struct kvm *kvm);
int vgic_v3_set_redist_base(struct kvm *kvm, u64 addr);
int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
bool vgic_v3_check_base(struct kvm *kvm);

void vgic_v3_load(struct kvm_vcpu *vcpu);
void vgic_v3_put(struct kvm_vcpu *vcpu);

bool vgic_has_its(struct kvm *kvm);
int kvm_vgic_register_its_device(void);
void vgic_enable_lpis(struct kvm_vcpu *vcpu);
int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val);
int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 int offset, u32 *val);
int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
			 u64 id, u64 *val);
int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
				u64 *reg);
int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
				    u32 intid, u64 *val);
int kvm_register_vgic_device(unsigned long type);
void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
int vgic_lazy_init(struct kvm *kvm);
int vgic_init(struct kvm *kvm);

int vgic_debug_init(struct kvm *kvm);
int vgic_debug_destroy(struct kvm *kvm);

bool lock_all_vcpus(struct kvm *kvm);
void unlock_all_vcpus(struct kvm *kvm);

#endif
Commit	Line	Data
	1	/*
	2	* Copyright (C) 2015, 2016 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#ifndef __KVM_ARM_VGIC_NEW_H__
	17	#define __KVM_ARM_VGIC_NEW_H__
	18
	19	#include <linux/irqchip/arm-gic-common.h>
	20
	21	#define PRODUCT_ID_KVM 0x4b /* ASCII code K */
	22	#define IMPLEMENTER_ARM 0x43b
	23
	24	#define VGIC_ADDR_UNDEF (-1)
	25	#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
	26
	27	#define INTERRUPT_ID_BITS_SPIS 10
	28	#define INTERRUPT_ID_BITS_ITS 16
	29	#define VGIC_PRI_BITS 5
	30
	31	#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
	32
	33	#define VGIC_AFFINITY_0_SHIFT 0
	34	#define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
	35	#define VGIC_AFFINITY_1_SHIFT 8
	36	#define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
	37	#define VGIC_AFFINITY_2_SHIFT 16
	38	#define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
	39	#define VGIC_AFFINITY_3_SHIFT 24
	40	#define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
	41
	42	#define VGIC_AFFINITY_LEVEL(reg, level) \
	43	((((reg) & VGIC_AFFINITY_## level ##_MASK) \
	44	>> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
	45
	46	/*
	47	* The Userspace encodes the affinity differently from the MPIDR,
	48	* Below macro converts vgic userspace format to MPIDR reg format.
	49	*/
	50	#define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) \| \
	51	VGIC_AFFINITY_LEVEL(val, 1) \| \
	52	VGIC_AFFINITY_LEVEL(val, 2) \| \
	53	VGIC_AFFINITY_LEVEL(val, 3))
	54
	55	/*
	56	* As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
	57	* below macros are defined for CPUREG encoding.
	58	*/
	59	#define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK 0x000000000000c000
	60	#define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT 14
	61	#define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK 0x0000000000003800
	62	#define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT 11
	63	#define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK 0x0000000000000780
	64	#define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT 7
	65	#define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK 0x0000000000000078
	66	#define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT 3
	67	#define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK 0x0000000000000007
	68	#define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT 0
	69
	70	#define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK \| \
	71	KVM_REG_ARM_VGIC_SYSREG_OP1_MASK \| \
	72	KVM_REG_ARM_VGIC_SYSREG_CRN_MASK \| \
	73	KVM_REG_ARM_VGIC_SYSREG_CRM_MASK \| \
	74	KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
	75
	76	/*
	77	* As per Documentation/virtual/kvm/devices/arm-vgic-its.txt,
	78	* below macros are defined for ITS table entry encoding.
	79	*/
	80	#define KVM_ITS_CTE_VALID_SHIFT 63
	81	#define KVM_ITS_CTE_VALID_MASK BIT_ULL(63)
	82	#define KVM_ITS_CTE_RDBASE_SHIFT 16
	83	#define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
	84	#define KVM_ITS_ITE_NEXT_SHIFT 48
	85	#define KVM_ITS_ITE_PINTID_SHIFT 16
	86	#define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
	87	#define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
	88	#define KVM_ITS_DTE_VALID_SHIFT 63
	89	#define KVM_ITS_DTE_VALID_MASK BIT_ULL(63)
	90	#define KVM_ITS_DTE_NEXT_SHIFT 49
	91	#define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
	92	#define KVM_ITS_DTE_ITTADDR_SHIFT 5
	93	#define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
	94	#define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
	95	#define KVM_ITS_L1E_VALID_MASK BIT_ULL(63)
	96	/* we only support 64 kB translation table page size */
	97	#define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
	98
	99	static inline bool irq_is_pending(struct vgic_irq *irq)
	100	{
	101	if (irq->config == VGIC_CONFIG_EDGE)
	102	return irq->pending_latch;
	103	else
	104	return irq->pending_latch \|\| irq->line_level;
	105	}
	106
	107	/*
	108	* This struct provides an intermediate representation of the fields contained
	109	* in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
	110	* state to userspace can generate either GICv2 or GICv3 CPU interface
	111	* registers regardless of the hardware backed GIC used.
	112	*/
	113	struct vgic_vmcr {
	114	u32 grpen0;
	115	u32 grpen1;
	116
	117	u32 ackctl;
	118	u32 fiqen;
	119	u32 cbpr;
	120	u32 eoim;
	121
	122	u32 abpr;
	123	u32 bpr;
	124	u32 pmr; /* Priority mask field in the GICC_PMR and
	125	* ICC_PMR_EL1 priority field format */
	126	};
	127
	128	struct vgic_reg_attr {
	129	struct kvm_vcpu *vcpu;
	130	gpa_t addr;
	131	};
	132
	133	int vgic_v3_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
	134	struct vgic_reg_attr *reg_attr);
	135	int vgic_v2_parse_attr(struct kvm_device dev, struct kvm_device_attr attr,
	136	struct vgic_reg_attr *reg_attr);
	137	const struct vgic_register_region *
	138	vgic_get_mmio_region(struct kvm_vcpu vcpu, struct vgic_io_device iodev,
	139	gpa_t addr, int len);
	140	struct vgic_irq vgic_get_irq(struct kvm kvm, struct kvm_vcpu *vcpu,
	141	u32 intid);
	142	void vgic_put_irq(struct kvm kvm, struct vgic_irq irq);
	143	bool vgic_queue_irq_unlock(struct kvm kvm, struct vgic_irq irq);
	144	void vgic_kick_vcpus(struct kvm *kvm);
	145
	146	int vgic_check_ioaddr(struct kvm kvm, phys_addr_t ioaddr,
	147	phys_addr_t addr, phys_addr_t alignment);
	148
	149	void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
	150	void vgic_v2_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr);
	151	void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
	152	void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
	153	int vgic_v2_has_attr_regs(struct kvm_device dev, struct kvm_device_attr attr);
	154	int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	155	int offset, u32 *val);
	156	int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	157	int offset, u32 *val);
	158	void vgic_v2_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
	159	void vgic_v2_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
	160	void vgic_v2_enable(struct kvm_vcpu *vcpu);
	161	int vgic_v2_probe(const struct gic_kvm_info *info);
	162	int vgic_v2_map_resources(struct kvm *kvm);
	163	int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
	164	enum vgic_type);
	165
	166	void vgic_v2_init_lrs(void);
	167	void vgic_v2_load(struct kvm_vcpu *vcpu);
	168	void vgic_v2_put(struct kvm_vcpu *vcpu);
	169
	170	static inline void vgic_get_irq_kref(struct vgic_irq *irq)
	171	{
	172	if (irq->intid < VGIC_MIN_LPI)
	173	return;
	174
	175	kref_get(&irq->refcount);
	176	}
	177
	178	void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
	179	void vgic_v3_populate_lr(struct kvm_vcpu vcpu, struct vgic_irq irq, int lr);
	180	void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
	181	void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
	182	void vgic_v3_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
	183	void vgic_v3_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
	184	void vgic_v3_enable(struct kvm_vcpu *vcpu);
	185	int vgic_v3_probe(const struct gic_kvm_info *info);
	186	int vgic_v3_map_resources(struct kvm *kvm);
	187	int vgic_v3_lpi_sync_pending_status(struct kvm kvm, struct vgic_irq irq);
	188	int vgic_v3_save_pending_tables(struct kvm *kvm);
	189	int vgic_v3_set_redist_base(struct kvm *kvm, u64 addr);
	190	int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
	191	bool vgic_v3_check_base(struct kvm *kvm);
	192
	193	void vgic_v3_load(struct kvm_vcpu *vcpu);
	194	void vgic_v3_put(struct kvm_vcpu *vcpu);
	195
	196	bool vgic_has_its(struct kvm *kvm);
	197	int kvm_vgic_register_its_device(void);
	198	void vgic_enable_lpis(struct kvm_vcpu *vcpu);
	199	int vgic_its_inject_msi(struct kvm kvm, struct kvm_msi msi);
	200	int vgic_v3_has_attr_regs(struct kvm_device dev, struct kvm_device_attr attr);
	201	int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	202	int offset, u32 *val);
	203	int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	204	int offset, u32 *val);
	205	int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	206	u64 id, u64 *val);
	207	int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
	208	u64 *reg);
	209	int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
	210	u32 intid, u64 *val);
	211	int kvm_register_vgic_device(unsigned long type);
	212	void vgic_set_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
	213	void vgic_get_vmcr(struct kvm_vcpu vcpu, struct vgic_vmcr vmcr);
	214	int vgic_lazy_init(struct kvm *kvm);
	215	int vgic_init(struct kvm *kvm);
	216
	217	int vgic_debug_init(struct kvm *kvm);
	218	int vgic_debug_destroy(struct kvm *kvm);
	219
	220	bool lock_all_vcpus(struct kvm *kvm);
	221	void unlock_all_vcpus(struct kvm *kvm);
	222
	223	#endif