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1 | /* | |
2 | * QEMU PC System Emulator | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include <stdlib.h> | |
25 | #include <stdio.h> | |
26 | #include <stdarg.h> | |
27 | #include <string.h> | |
28 | #include <getopt.h> | |
29 | #include <inttypes.h> | |
30 | #include <unistd.h> | |
31 | #include <sys/mman.h> | |
32 | #include <fcntl.h> | |
33 | #include <signal.h> | |
34 | #include <time.h> | |
35 | #include <sys/time.h> | |
36 | #include <malloc.h> | |
37 | #include <termios.h> | |
38 | #include <sys/poll.h> | |
39 | #include <errno.h> | |
40 | #include <sys/wait.h> | |
41 | ||
42 | #include <sys/ioctl.h> | |
43 | #include <sys/socket.h> | |
44 | #include <linux/if.h> | |
45 | #include <linux/if_tun.h> | |
46 | ||
47 | #include "cpu-i386.h" | |
48 | #include "disas.h" | |
49 | ||
50 | #define DEBUG_LOGFILE "/tmp/vl.log" | |
51 | #define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup" | |
52 | ||
53 | //#define DEBUG_UNUSED_IOPORT | |
54 | ||
55 | #define PHYS_RAM_BASE 0xa8000000 | |
56 | #define KERNEL_LOAD_ADDR 0x00100000 | |
57 | #define INITRD_LOAD_ADDR 0x00400000 | |
58 | #define KERNEL_PARAMS_ADDR 0x00090000 | |
59 | ||
60 | /* from plex86 (BSD license) */ | |
61 | struct __attribute__ ((packed)) linux_params { | |
62 | // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h. | |
63 | // I just padded out the VESA parts, rather than define them. | |
64 | ||
65 | /* 0x000 */ uint8_t orig_x; | |
66 | /* 0x001 */ uint8_t orig_y; | |
67 | /* 0x002 */ uint16_t ext_mem_k; | |
68 | /* 0x004 */ uint16_t orig_video_page; | |
69 | /* 0x006 */ uint8_t orig_video_mode; | |
70 | /* 0x007 */ uint8_t orig_video_cols; | |
71 | /* 0x008 */ uint16_t unused1; | |
72 | /* 0x00a */ uint16_t orig_video_ega_bx; | |
73 | /* 0x00c */ uint16_t unused2; | |
74 | /* 0x00e */ uint8_t orig_video_lines; | |
75 | /* 0x00f */ uint8_t orig_video_isVGA; | |
76 | /* 0x010 */ uint16_t orig_video_points; | |
77 | /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info. | |
78 | /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F) | |
79 | /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline | |
80 | // is calculated as 0x90000 + cl_offset, bu | |
81 | // only if cl_magic == 0xA33F. | |
82 | /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info. | |
83 | ||
84 | /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info | |
85 | /* 0x054 */ uint8_t pad2[0x80 - 0x54]; | |
86 | ||
87 | // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h. | |
88 | // Might be truncated? | |
89 | /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41 | |
90 | /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46 | |
91 | ||
92 | // System description table truncated to 16 bytes | |
93 | // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c. | |
94 | /* 0x0a0 */ uint16_t sys_description_len; | |
95 | /* 0x0a2 */ uint8_t sys_description_table[14]; | |
96 | // [0] machine id | |
97 | // [1] machine submodel id | |
98 | // [2] BIOS revision | |
99 | // [3] bit1: MCA bus | |
100 | ||
101 | /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0]; | |
102 | /* 0x1e0 */ uint32_t alt_mem_k; | |
103 | /* 0x1e4 */ uint8_t pad4[4]; | |
104 | /* 0x1e8 */ uint8_t e820map_entries; | |
105 | /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR | |
106 | /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea]; | |
107 | /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors | |
108 | /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0) | |
109 | /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the | |
110 | // (b)zImage-file (in 16 byte units, rounded up) | |
111 | /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK) | |
112 | /* 0x1f8 */ uint16_t ramdisk_flags; | |
113 | /* 0x1fa */ uint16_t vga_mode; // (old one) | |
114 | /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor) | |
115 | /* 0x1fe */ uint8_t pad6[1]; | |
116 | /* 0x1ff */ uint8_t aux_device_info; | |
117 | /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code, | |
118 | // aka "reserved" field. | |
119 | /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS" | |
120 | /* 0x206 */ uint16_t header_format_version; // Version number of header format; | |
121 | /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with | |
122 | // boot loaders, look there. | |
123 | /* 0x210 */ uint8_t loader_type; | |
124 | // 0 for old one. | |
125 | // else 0xTV: | |
126 | // T=0: LILO | |
127 | // T=1: Loadlin | |
128 | // T=2: bootsect-loader | |
129 | // T=3: SYSLINUX | |
130 | // T=4: ETHERBOOT | |
131 | // V=version | |
132 | /* 0x211 */ uint8_t loadflags; | |
133 | // bit0 = 1: kernel is loaded high (bzImage) | |
134 | // bit7 = 1: Heap and pointer (see below) set by boot | |
135 | // loader. | |
136 | /* 0x212 */ uint16_t setup_S_temp1; | |
137 | /* 0x214 */ uint32_t kernel_start; | |
138 | /* 0x218 */ uint32_t initrd_start; | |
139 | /* 0x21c */ uint32_t initrd_size; | |
140 | /* 0x220 */ uint8_t setup_S_temp2[4]; | |
141 | /* 0x224 */ uint16_t setup_S_heap_end_pointer; | |
142 | /* 0x226 */ uint8_t pad7[0x2d0 - 0x226]; | |
143 | ||
144 | /* 0x2d0 : Int 15, ax=e820 memory map. */ | |
145 | // (linux/include/asm-i386/e820.h, 'struct e820entry') | |
146 | #define E820MAX 32 | |
147 | #define E820_RAM 1 | |
148 | #define E820_RESERVED 2 | |
149 | #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */ | |
150 | #define E820_NVS 4 | |
151 | struct { | |
152 | uint64_t addr; | |
153 | uint64_t size; | |
154 | uint32_t type; | |
155 | } e820map[E820MAX]; | |
156 | ||
157 | /* 0x550 */ uint8_t pad8[0x600 - 0x550]; | |
158 | ||
159 | // BIOS Enhanced Disk Drive Services. | |
160 | // (From linux/include/asm-i386/edd.h, 'struct edd_info') | |
161 | // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array. | |
162 | /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600]; | |
163 | ||
164 | /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4]; | |
165 | /* 0x800 */ uint8_t commandline[0x800]; | |
166 | ||
167 | /* 0x1000 */ | |
168 | uint64_t gdt_table[256]; | |
169 | uint64_t idt_table[48]; | |
170 | }; | |
171 | ||
172 | #define KERNEL_CS 0x10 | |
173 | #define KERNEL_DS 0x18 | |
174 | ||
175 | typedef void (IOPortWriteFunc)(CPUX86State *env, uint32_t address, uint32_t data); | |
176 | typedef uint32_t (IOPortReadFunc)(CPUX86State *env, uint32_t address); | |
177 | ||
178 | #define MAX_IOPORTS 1024 | |
179 | ||
180 | char phys_ram_file[1024]; | |
181 | CPUX86State *global_env; | |
182 | CPUX86State *cpu_single_env; | |
183 | FILE *logfile = NULL; | |
184 | int loglevel; | |
185 | IOPortReadFunc *ioport_readb_table[MAX_IOPORTS]; | |
186 | IOPortWriteFunc *ioport_writeb_table[MAX_IOPORTS]; | |
187 | IOPortReadFunc *ioport_readw_table[MAX_IOPORTS]; | |
188 | IOPortWriteFunc *ioport_writew_table[MAX_IOPORTS]; | |
189 | ||
190 | /***********************************************************/ | |
191 | /* x86 io ports */ | |
192 | ||
193 | uint32_t default_ioport_readb(CPUX86State *env, uint32_t address) | |
194 | { | |
195 | #ifdef DEBUG_UNUSED_IOPORT | |
196 | fprintf(stderr, "inb: port=0x%04x\n", address); | |
197 | #endif | |
198 | return 0; | |
199 | } | |
200 | ||
201 | void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data) | |
202 | { | |
203 | #ifdef DEBUG_UNUSED_IOPORT | |
204 | fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data); | |
205 | #endif | |
206 | } | |
207 | ||
208 | /* default is to make two byte accesses */ | |
209 | uint32_t default_ioport_readw(CPUX86State *env, uint32_t address) | |
210 | { | |
211 | uint32_t data; | |
212 | data = ioport_readb_table[address](env, address); | |
213 | data |= ioport_readb_table[address + 1](env, address + 1) << 8; | |
214 | return data; | |
215 | } | |
216 | ||
217 | void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data) | |
218 | { | |
219 | ioport_writeb_table[address](env, address, data & 0xff); | |
220 | ioport_writeb_table[address + 1](env, address + 1, (data >> 8) & 0xff); | |
221 | } | |
222 | ||
223 | void init_ioports(void) | |
224 | { | |
225 | int i; | |
226 | ||
227 | for(i = 0; i < MAX_IOPORTS; i++) { | |
228 | ioport_readb_table[i] = default_ioport_readb; | |
229 | ioport_writeb_table[i] = default_ioport_writeb; | |
230 | ioport_readw_table[i] = default_ioport_readw; | |
231 | ioport_writew_table[i] = default_ioport_writew; | |
232 | } | |
233 | } | |
234 | ||
235 | int register_ioport_readb(int start, int length, IOPortReadFunc *func) | |
236 | { | |
237 | int i; | |
238 | ||
239 | for(i = start; i < start + length; i++) | |
240 | ioport_readb_table[i] = func; | |
241 | return 0; | |
242 | } | |
243 | ||
244 | int register_ioport_writeb(int start, int length, IOPortWriteFunc *func) | |
245 | { | |
246 | int i; | |
247 | ||
248 | for(i = start; i < start + length; i++) | |
249 | ioport_writeb_table[i] = func; | |
250 | return 0; | |
251 | } | |
252 | ||
253 | int register_ioport_readw(int start, int length, IOPortReadFunc *func) | |
254 | { | |
255 | int i; | |
256 | ||
257 | for(i = start; i < start + length; i += 2) | |
258 | ioport_readw_table[i] = func; | |
259 | return 0; | |
260 | } | |
261 | ||
262 | int register_ioport_writew(int start, int length, IOPortWriteFunc *func) | |
263 | { | |
264 | int i; | |
265 | ||
266 | for(i = start; i < start + length; i += 2) | |
267 | ioport_writew_table[i] = func; | |
268 | return 0; | |
269 | } | |
270 | ||
271 | void pstrcpy(char *buf, int buf_size, const char *str) | |
272 | { | |
273 | int c; | |
274 | char *q = buf; | |
275 | ||
276 | if (buf_size <= 0) | |
277 | return; | |
278 | ||
279 | for(;;) { | |
280 | c = *str++; | |
281 | if (c == 0 || q >= buf + buf_size - 1) | |
282 | break; | |
283 | *q++ = c; | |
284 | } | |
285 | *q = '\0'; | |
286 | } | |
287 | ||
288 | /* strcat and truncate. */ | |
289 | char *pstrcat(char *buf, int buf_size, const char *s) | |
290 | { | |
291 | int len; | |
292 | len = strlen(buf); | |
293 | if (len < buf_size) | |
294 | pstrcpy(buf + len, buf_size - len, s); | |
295 | return buf; | |
296 | } | |
297 | ||
298 | int load_kernel(const char *filename, uint8_t *addr) | |
299 | { | |
300 | int fd, size, setup_sects; | |
301 | uint8_t bootsect[512]; | |
302 | ||
303 | fd = open(filename, O_RDONLY); | |
304 | if (fd < 0) | |
305 | return -1; | |
306 | if (read(fd, bootsect, 512) != 512) | |
307 | goto fail; | |
308 | setup_sects = bootsect[0x1F1]; | |
309 | if (!setup_sects) | |
310 | setup_sects = 4; | |
311 | /* skip 16 bit setup code */ | |
312 | lseek(fd, (setup_sects + 1) * 512, SEEK_SET); | |
313 | size = read(fd, addr, 16 * 1024 * 1024); | |
314 | if (size < 0) | |
315 | goto fail; | |
316 | close(fd); | |
317 | return size; | |
318 | fail: | |
319 | close(fd); | |
320 | return -1; | |
321 | } | |
322 | ||
323 | /* return the size or -1 if error */ | |
324 | int load_image(const char *filename, uint8_t *addr) | |
325 | { | |
326 | int fd, size; | |
327 | fd = open(filename, O_RDONLY); | |
328 | if (fd < 0) | |
329 | return -1; | |
330 | size = lseek(fd, 0, SEEK_END); | |
331 | lseek(fd, 0, SEEK_SET); | |
332 | if (read(fd, addr, size) != size) { | |
333 | close(fd); | |
334 | return -1; | |
335 | } | |
336 | close(fd); | |
337 | return size; | |
338 | } | |
339 | ||
340 | void cpu_x86_outb(CPUX86State *env, int addr, int val) | |
341 | { | |
342 | ioport_writeb_table[addr & (MAX_IOPORTS - 1)](env, addr, val); | |
343 | } | |
344 | ||
345 | void cpu_x86_outw(CPUX86State *env, int addr, int val) | |
346 | { | |
347 | ioport_writew_table[addr & (MAX_IOPORTS - 1)](env, addr, val); | |
348 | } | |
349 | ||
350 | void cpu_x86_outl(CPUX86State *env, int addr, int val) | |
351 | { | |
352 | fprintf(stderr, "outl: port=0x%04x, data=%08x\n", addr, val); | |
353 | } | |
354 | ||
355 | int cpu_x86_inb(CPUX86State *env, int addr) | |
356 | { | |
357 | return ioport_readb_table[addr & (MAX_IOPORTS - 1)](env, addr); | |
358 | } | |
359 | ||
360 | int cpu_x86_inw(CPUX86State *env, int addr) | |
361 | { | |
362 | return ioport_readw_table[addr & (MAX_IOPORTS - 1)](env, addr); | |
363 | } | |
364 | ||
365 | int cpu_x86_inl(CPUX86State *env, int addr) | |
366 | { | |
367 | fprintf(stderr, "inl: port=0x%04x\n", addr); | |
368 | return 0; | |
369 | } | |
370 | ||
371 | /***********************************************************/ | |
372 | void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data) | |
373 | { | |
374 | } | |
375 | ||
376 | void hw_error(const char *fmt, ...) | |
377 | { | |
378 | va_list ap; | |
379 | ||
380 | va_start(ap, fmt); | |
381 | fprintf(stderr, "qemu: hardware error: "); | |
382 | vfprintf(stderr, fmt, ap); | |
383 | fprintf(stderr, "\n"); | |
384 | #ifdef TARGET_I386 | |
385 | cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP); | |
386 | #endif | |
387 | va_end(ap); | |
388 | abort(); | |
389 | } | |
390 | ||
391 | /***********************************************************/ | |
392 | /* vga emulation */ | |
393 | static uint8_t vga_index; | |
394 | static uint8_t vga_regs[256]; | |
395 | static int last_cursor_pos; | |
396 | ||
397 | void update_console_messages(void) | |
398 | { | |
399 | int c, i, cursor_pos, eol; | |
400 | ||
401 | cursor_pos = vga_regs[0x0f] | (vga_regs[0x0e] << 8); | |
402 | eol = 0; | |
403 | for(i = last_cursor_pos; i < cursor_pos; i++) { | |
404 | c = phys_ram_base[0xb8000 + (i) * 2]; | |
405 | if (c >= ' ') { | |
406 | putchar(c); | |
407 | eol = 0; | |
408 | } else { | |
409 | if (!eol) | |
410 | putchar('\n'); | |
411 | eol = 1; | |
412 | } | |
413 | } | |
414 | fflush(stdout); | |
415 | last_cursor_pos = cursor_pos; | |
416 | } | |
417 | ||
418 | /* just to see first Linux console messages, we intercept cursor position */ | |
419 | void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data) | |
420 | { | |
421 | switch(addr) { | |
422 | case 0x3d4: | |
423 | vga_index = data; | |
424 | break; | |
425 | case 0x3d5: | |
426 | vga_regs[vga_index] = data; | |
427 | if (vga_index == 0x0f) | |
428 | update_console_messages(); | |
429 | break; | |
430 | } | |
431 | ||
432 | } | |
433 | ||
434 | /***********************************************************/ | |
435 | /* cmos emulation */ | |
436 | ||
437 | #define RTC_SECONDS 0 | |
438 | #define RTC_SECONDS_ALARM 1 | |
439 | #define RTC_MINUTES 2 | |
440 | #define RTC_MINUTES_ALARM 3 | |
441 | #define RTC_HOURS 4 | |
442 | #define RTC_HOURS_ALARM 5 | |
443 | #define RTC_ALARM_DONT_CARE 0xC0 | |
444 | ||
445 | #define RTC_DAY_OF_WEEK 6 | |
446 | #define RTC_DAY_OF_MONTH 7 | |
447 | #define RTC_MONTH 8 | |
448 | #define RTC_YEAR 9 | |
449 | ||
450 | #define RTC_REG_A 10 | |
451 | #define RTC_REG_B 11 | |
452 | #define RTC_REG_C 12 | |
453 | #define RTC_REG_D 13 | |
454 | ||
455 | /* PC cmos mappings */ | |
456 | #define REG_EQUIPMENT_BYTE 0x14 | |
457 | ||
458 | uint8_t cmos_data[128]; | |
459 | uint8_t cmos_index; | |
460 | ||
461 | void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data) | |
462 | { | |
463 | if (addr == 0x70) { | |
464 | cmos_index = data & 0x7f; | |
465 | } | |
466 | } | |
467 | ||
468 | uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr) | |
469 | { | |
470 | int ret; | |
471 | ||
472 | if (addr == 0x70) { | |
473 | return 0xff; | |
474 | } else { | |
475 | /* toggle update-in-progress bit for Linux (same hack as | |
476 | plex86) */ | |
477 | ret = cmos_data[cmos_index]; | |
478 | if (cmos_index == RTC_REG_A) | |
479 | cmos_data[RTC_REG_A] ^= 0x80; | |
480 | else if (cmos_index == RTC_REG_C) | |
481 | cmos_data[RTC_REG_C] = 0x00; | |
482 | return ret; | |
483 | } | |
484 | } | |
485 | ||
486 | ||
487 | static inline int to_bcd(int a) | |
488 | { | |
489 | return ((a / 10) << 4) | (a % 10); | |
490 | } | |
491 | ||
492 | void cmos_init(void) | |
493 | { | |
494 | struct tm *tm; | |
495 | time_t ti; | |
496 | ||
497 | ti = time(NULL); | |
498 | tm = gmtime(&ti); | |
499 | cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec); | |
500 | cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min); | |
501 | cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour); | |
502 | cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday); | |
503 | cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday); | |
504 | cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon); | |
505 | cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100); | |
506 | ||
507 | cmos_data[RTC_REG_A] = 0x26; | |
508 | cmos_data[RTC_REG_B] = 0x02; | |
509 | cmos_data[RTC_REG_C] = 0x00; | |
510 | cmos_data[RTC_REG_D] = 0x80; | |
511 | ||
512 | cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */ | |
513 | ||
514 | register_ioport_writeb(0x70, 2, cmos_ioport_write); | |
515 | register_ioport_readb(0x70, 2, cmos_ioport_read); | |
516 | } | |
517 | ||
518 | /***********************************************************/ | |
519 | /* 8259 pic emulation */ | |
520 | ||
521 | typedef struct PicState { | |
522 | uint8_t last_irr; /* edge detection */ | |
523 | uint8_t irr; /* interrupt request register */ | |
524 | uint8_t imr; /* interrupt mask register */ | |
525 | uint8_t isr; /* interrupt service register */ | |
526 | uint8_t priority_add; /* used to compute irq priority */ | |
527 | uint8_t irq_base; | |
528 | uint8_t read_reg_select; | |
529 | uint8_t special_mask; | |
530 | uint8_t init_state; | |
531 | uint8_t auto_eoi; | |
532 | uint8_t rotate_on_autoeoi; | |
533 | uint8_t init4; /* true if 4 byte init */ | |
534 | } PicState; | |
535 | ||
536 | /* 0 is master pic, 1 is slave pic */ | |
537 | PicState pics[2]; | |
538 | int pic_irq_requested; | |
539 | ||
540 | /* set irq level. If an edge is detected, then the IRR is set to 1 */ | |
541 | static inline void pic_set_irq1(PicState *s, int irq, int level) | |
542 | { | |
543 | int mask; | |
544 | mask = 1 << irq; | |
545 | if (level) { | |
546 | if ((s->last_irr & mask) == 0) | |
547 | s->irr |= mask; | |
548 | s->last_irr |= mask; | |
549 | } else { | |
550 | s->last_irr &= ~mask; | |
551 | } | |
552 | } | |
553 | ||
554 | static inline int get_priority(PicState *s, int mask) | |
555 | { | |
556 | int priority; | |
557 | if (mask == 0) | |
558 | return -1; | |
559 | priority = 7; | |
560 | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) | |
561 | priority--; | |
562 | return priority; | |
563 | } | |
564 | ||
565 | /* return the pic wanted interrupt. return -1 if none */ | |
566 | static int pic_get_irq(PicState *s) | |
567 | { | |
568 | int mask, cur_priority, priority; | |
569 | ||
570 | mask = s->irr & ~s->imr; | |
571 | priority = get_priority(s, mask); | |
572 | if (priority < 0) | |
573 | return -1; | |
574 | /* compute current priority */ | |
575 | cur_priority = get_priority(s, s->isr); | |
576 | if (priority > cur_priority) { | |
577 | /* higher priority found: an irq should be generated */ | |
578 | return priority; | |
579 | } else { | |
580 | return -1; | |
581 | } | |
582 | } | |
583 | ||
584 | void pic_set_irq(int irq, int level) | |
585 | { | |
586 | pic_set_irq1(&pics[irq >> 3], irq & 7, level); | |
587 | } | |
588 | ||
589 | /* can be called at any time outside cpu_exec() to raise irqs if | |
590 | necessary */ | |
591 | void pic_handle_irq(void) | |
592 | { | |
593 | int irq2, irq; | |
594 | ||
595 | /* first look at slave pic */ | |
596 | irq2 = pic_get_irq(&pics[1]); | |
597 | if (irq2 >= 0) { | |
598 | /* if irq request by slave pic, signal master PIC */ | |
599 | pic_set_irq1(&pics[0], 2, 1); | |
600 | pic_set_irq1(&pics[0], 2, 0); | |
601 | } | |
602 | /* look at requested irq */ | |
603 | irq = pic_get_irq(&pics[0]); | |
604 | if (irq >= 0) { | |
605 | if (irq == 2) { | |
606 | /* from slave pic */ | |
607 | pic_irq_requested = 8 + irq2; | |
608 | } else { | |
609 | /* from master pic */ | |
610 | pic_irq_requested = irq; | |
611 | } | |
612 | global_env->hard_interrupt_request = 1; | |
613 | } | |
614 | } | |
615 | ||
616 | int cpu_x86_get_pic_interrupt(CPUX86State *env) | |
617 | { | |
618 | int irq, irq2, intno; | |
619 | ||
620 | /* signal the pic that the irq was acked by the CPU */ | |
621 | irq = pic_irq_requested; | |
622 | if (irq >= 8) { | |
623 | irq2 = irq & 7; | |
624 | pics[1].isr |= (1 << irq2); | |
625 | pics[1].irr &= ~(1 << irq2); | |
626 | irq = 2; | |
627 | intno = pics[1].irq_base + irq2; | |
628 | } else { | |
629 | intno = pics[0].irq_base + irq; | |
630 | } | |
631 | pics[0].isr |= (1 << irq); | |
632 | pics[0].irr &= ~(1 << irq); | |
633 | return intno; | |
634 | } | |
635 | ||
636 | void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
637 | { | |
638 | PicState *s; | |
639 | int priority; | |
640 | ||
641 | s = &pics[addr >> 7]; | |
642 | addr &= 1; | |
643 | if (addr == 0) { | |
644 | if (val & 0x10) { | |
645 | /* init */ | |
646 | memset(s, 0, sizeof(PicState)); | |
647 | s->init_state = 1; | |
648 | s->init4 = val & 1; | |
649 | if (val & 0x02) | |
650 | hw_error("single mode not supported"); | |
651 | if (val & 0x08) | |
652 | hw_error("level sensitive irq not supported"); | |
653 | } else if (val & 0x08) { | |
654 | if (val & 0x02) | |
655 | s->read_reg_select = val & 1; | |
656 | if (val & 0x40) | |
657 | s->special_mask = (val >> 5) & 1; | |
658 | } else { | |
659 | switch(val) { | |
660 | case 0x00: | |
661 | case 0x80: | |
662 | s->rotate_on_autoeoi = val >> 7; | |
663 | break; | |
664 | case 0x20: /* end of interrupt */ | |
665 | case 0xa0: | |
666 | priority = get_priority(s, s->isr); | |
667 | if (priority >= 0) { | |
668 | s->isr &= ~(1 << ((priority + s->priority_add) & 7)); | |
669 | } | |
670 | if (val == 0xa0) | |
671 | s->priority_add = (s->priority_add + 1) & 7; | |
672 | break; | |
673 | case 0x60 ... 0x67: | |
674 | priority = val & 7; | |
675 | s->isr &= ~(1 << priority); | |
676 | break; | |
677 | case 0xc0 ... 0xc7: | |
678 | s->priority_add = (val + 1) & 7; | |
679 | break; | |
680 | case 0xe0 ... 0xe7: | |
681 | priority = val & 7; | |
682 | s->isr &= ~(1 << priority); | |
683 | s->priority_add = (priority + 1) & 7; | |
684 | break; | |
685 | } | |
686 | } | |
687 | } else { | |
688 | switch(s->init_state) { | |
689 | case 0: | |
690 | /* normal mode */ | |
691 | s->imr = val; | |
692 | break; | |
693 | case 1: | |
694 | s->irq_base = val & 0xf8; | |
695 | s->init_state = 2; | |
696 | break; | |
697 | case 2: | |
698 | if (s->init4) { | |
699 | s->init_state = 3; | |
700 | } else { | |
701 | s->init_state = 0; | |
702 | } | |
703 | break; | |
704 | case 3: | |
705 | s->auto_eoi = (val >> 1) & 1; | |
706 | s->init_state = 0; | |
707 | break; | |
708 | } | |
709 | } | |
710 | } | |
711 | ||
712 | uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr) | |
713 | { | |
714 | PicState *s; | |
715 | s = &pics[addr >> 7]; | |
716 | addr &= 1; | |
717 | if (addr == 0) { | |
718 | if (s->read_reg_select) | |
719 | return s->isr; | |
720 | else | |
721 | return s->irr; | |
722 | } else { | |
723 | return s->imr; | |
724 | } | |
725 | } | |
726 | ||
727 | void pic_init(void) | |
728 | { | |
729 | register_ioport_writeb(0x20, 2, pic_ioport_write); | |
730 | register_ioport_readb(0x20, 2, pic_ioport_read); | |
731 | register_ioport_writeb(0xa0, 2, pic_ioport_write); | |
732 | register_ioport_readb(0xa0, 2, pic_ioport_read); | |
733 | } | |
734 | ||
735 | /***********************************************************/ | |
736 | /* 8253 PIT emulation */ | |
737 | ||
738 | #define PIT_FREQ 1193182 | |
739 | ||
740 | #define RW_STATE_LSB 0 | |
741 | #define RW_STATE_MSB 1 | |
742 | #define RW_STATE_WORD0 2 | |
743 | #define RW_STATE_WORD1 3 | |
744 | #define RW_STATE_LATCHED_WORD0 4 | |
745 | #define RW_STATE_LATCHED_WORD1 5 | |
746 | ||
747 | typedef struct PITChannelState { | |
748 | int count; /* can be 65536 */ | |
749 | uint16_t latched_count; | |
750 | uint8_t rw_state; | |
751 | uint8_t mode; | |
752 | uint8_t bcd; /* not supported */ | |
753 | uint8_t gate; /* timer start */ | |
754 | int64_t count_load_time; | |
755 | int64_t count_last_edge_check_time; | |
756 | } PITChannelState; | |
757 | ||
758 | PITChannelState pit_channels[3]; | |
759 | int speaker_data_on; | |
760 | int pit_min_timer_count = 0; | |
761 | ||
762 | int64_t ticks_per_sec; | |
763 | ||
764 | int64_t get_clock(void) | |
765 | { | |
766 | struct timeval tv; | |
767 | gettimeofday(&tv, NULL); | |
768 | return tv.tv_sec * 1000000LL + tv.tv_usec; | |
769 | } | |
770 | ||
771 | int64_t cpu_get_ticks(void) | |
772 | { | |
773 | int64_t val; | |
774 | asm("rdtsc" : "=A" (val)); | |
775 | return val; | |
776 | } | |
777 | ||
778 | void cpu_calibrate_ticks(void) | |
779 | { | |
780 | int64_t usec, ticks; | |
781 | ||
782 | usec = get_clock(); | |
783 | ticks = cpu_get_ticks(); | |
784 | usleep(50 * 1000); | |
785 | usec = get_clock() - usec; | |
786 | ticks = cpu_get_ticks() - ticks; | |
787 | ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec; | |
788 | } | |
789 | ||
790 | /* compute with 96 bit intermediate result: (a*b)/c */ | |
791 | static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) | |
792 | { | |
793 | union { | |
794 | uint64_t ll; | |
795 | struct { | |
796 | #ifdef WORDS_BIGENDIAN | |
797 | uint32_t high, low; | |
798 | #else | |
799 | uint32_t low, high; | |
800 | #endif | |
801 | } l; | |
802 | } u, res; | |
803 | uint64_t rl, rh; | |
804 | ||
805 | u.ll = a; | |
806 | rl = (uint64_t)u.l.low * (uint64_t)b; | |
807 | rh = (uint64_t)u.l.high * (uint64_t)b; | |
808 | rh += (rl >> 32); | |
809 | res.l.high = rh / c; | |
810 | res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; | |
811 | return res.ll; | |
812 | } | |
813 | ||
814 | static int pit_get_count(PITChannelState *s) | |
815 | { | |
816 | uint64_t d; | |
817 | int counter; | |
818 | ||
819 | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); | |
820 | switch(s->mode) { | |
821 | case 0: | |
822 | case 1: | |
823 | case 4: | |
824 | case 5: | |
825 | counter = (s->count - d) & 0xffff; | |
826 | break; | |
827 | default: | |
828 | counter = s->count - (d % s->count); | |
829 | break; | |
830 | } | |
831 | return counter; | |
832 | } | |
833 | ||
834 | /* get pit output bit */ | |
835 | static int pit_get_out(PITChannelState *s) | |
836 | { | |
837 | uint64_t d; | |
838 | int out; | |
839 | ||
840 | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); | |
841 | switch(s->mode) { | |
842 | default: | |
843 | case 0: | |
844 | out = (d >= s->count); | |
845 | break; | |
846 | case 1: | |
847 | out = (d < s->count); | |
848 | break; | |
849 | case 2: | |
850 | if ((d % s->count) == 0 && d != 0) | |
851 | out = 1; | |
852 | else | |
853 | out = 0; | |
854 | break; | |
855 | case 3: | |
856 | out = (d % s->count) < (s->count >> 1); | |
857 | break; | |
858 | case 4: | |
859 | case 5: | |
860 | out = (d == s->count); | |
861 | break; | |
862 | } | |
863 | return out; | |
864 | } | |
865 | ||
866 | /* get the number of 0 to 1 transitions we had since we call this | |
867 | function */ | |
868 | /* XXX: maybe better to use ticks precision to avoid getting edges | |
869 | twice if checks are done at very small intervals */ | |
870 | static int pit_get_out_edges(PITChannelState *s) | |
871 | { | |
872 | uint64_t d1, d2; | |
873 | int64_t ticks; | |
874 | int ret, v; | |
875 | ||
876 | ticks = cpu_get_ticks(); | |
877 | d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time, | |
878 | PIT_FREQ, ticks_per_sec); | |
879 | d2 = muldiv64(ticks - s->count_load_time, | |
880 | PIT_FREQ, ticks_per_sec); | |
881 | s->count_last_edge_check_time = ticks; | |
882 | switch(s->mode) { | |
883 | default: | |
884 | case 0: | |
885 | if (d1 < s->count && d2 >= s->count) | |
886 | ret = 1; | |
887 | else | |
888 | ret = 0; | |
889 | break; | |
890 | case 1: | |
891 | ret = 0; | |
892 | break; | |
893 | case 2: | |
894 | d1 /= s->count; | |
895 | d2 /= s->count; | |
896 | ret = d2 - d1; | |
897 | break; | |
898 | case 3: | |
899 | v = s->count - (s->count >> 1); | |
900 | d1 = (d1 + v) / s->count; | |
901 | d2 = (d2 + v) / s->count; | |
902 | ret = d2 - d1; | |
903 | break; | |
904 | case 4: | |
905 | case 5: | |
906 | if (d1 < s->count && d2 >= s->count) | |
907 | ret = 1; | |
908 | else | |
909 | ret = 0; | |
910 | break; | |
911 | } | |
912 | return ret; | |
913 | } | |
914 | ||
915 | static inline void pit_load_count(PITChannelState *s, int val) | |
916 | { | |
917 | if (val == 0) | |
918 | val = 0x10000; | |
919 | s->count_load_time = cpu_get_ticks(); | |
920 | s->count_last_edge_check_time = s->count_load_time; | |
921 | s->count = val; | |
922 | if (s == &pit_channels[0] && val <= pit_min_timer_count) { | |
923 | fprintf(stderr, | |
924 | "\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n", | |
925 | PIT_FREQ / pit_min_timer_count); | |
926 | } | |
927 | } | |
928 | ||
929 | void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
930 | { | |
931 | int channel, access; | |
932 | PITChannelState *s; | |
933 | ||
934 | addr &= 3; | |
935 | if (addr == 3) { | |
936 | channel = val >> 6; | |
937 | if (channel == 3) | |
938 | return; | |
939 | s = &pit_channels[channel]; | |
940 | access = (val >> 4) & 3; | |
941 | switch(access) { | |
942 | case 0: | |
943 | s->latched_count = pit_get_count(s); | |
944 | s->rw_state = RW_STATE_LATCHED_WORD0; | |
945 | break; | |
946 | default: | |
947 | s->mode = (val >> 1) & 7; | |
948 | s->bcd = val & 1; | |
949 | s->rw_state = access - 1 + RW_STATE_LSB; | |
950 | break; | |
951 | } | |
952 | } else { | |
953 | s = &pit_channels[addr]; | |
954 | switch(s->rw_state) { | |
955 | case RW_STATE_LSB: | |
956 | pit_load_count(s, val); | |
957 | break; | |
958 | case RW_STATE_MSB: | |
959 | pit_load_count(s, val << 8); | |
960 | break; | |
961 | case RW_STATE_WORD0: | |
962 | case RW_STATE_WORD1: | |
963 | if (s->rw_state & 1) { | |
964 | pit_load_count(s, (s->latched_count & 0xff) | (val << 8)); | |
965 | } else { | |
966 | s->latched_count = val; | |
967 | } | |
968 | s->rw_state ^= 1; | |
969 | break; | |
970 | } | |
971 | } | |
972 | } | |
973 | ||
974 | uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr) | |
975 | { | |
976 | int ret, count; | |
977 | PITChannelState *s; | |
978 | ||
979 | addr &= 3; | |
980 | s = &pit_channels[addr]; | |
981 | switch(s->rw_state) { | |
982 | case RW_STATE_LSB: | |
983 | case RW_STATE_MSB: | |
984 | case RW_STATE_WORD0: | |
985 | case RW_STATE_WORD1: | |
986 | count = pit_get_count(s); | |
987 | if (s->rw_state & 1) | |
988 | ret = (count >> 8) & 0xff; | |
989 | else | |
990 | ret = count & 0xff; | |
991 | if (s->rw_state & 2) | |
992 | s->rw_state ^= 1; | |
993 | break; | |
994 | default: | |
995 | case RW_STATE_LATCHED_WORD0: | |
996 | case RW_STATE_LATCHED_WORD1: | |
997 | if (s->rw_state & 1) | |
998 | ret = s->latched_count >> 8; | |
999 | else | |
1000 | ret = s->latched_count & 0xff; | |
1001 | s->rw_state ^= 1; | |
1002 | break; | |
1003 | } | |
1004 | return ret; | |
1005 | } | |
1006 | ||
1007 | void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1008 | { | |
1009 | speaker_data_on = (val >> 1) & 1; | |
1010 | pit_channels[2].gate = val & 1; | |
1011 | } | |
1012 | ||
1013 | uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr) | |
1014 | { | |
1015 | int out; | |
1016 | out = pit_get_out(&pit_channels[2]); | |
1017 | return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5); | |
1018 | } | |
1019 | ||
1020 | void pit_init(void) | |
1021 | { | |
1022 | PITChannelState *s; | |
1023 | int i; | |
1024 | ||
1025 | cpu_calibrate_ticks(); | |
1026 | ||
1027 | for(i = 0;i < 3; i++) { | |
1028 | s = &pit_channels[i]; | |
1029 | s->mode = 3; | |
1030 | s->gate = (i != 2); | |
1031 | pit_load_count(s, 0); | |
1032 | } | |
1033 | ||
1034 | register_ioport_writeb(0x40, 4, pit_ioport_write); | |
1035 | register_ioport_readb(0x40, 3, pit_ioport_read); | |
1036 | ||
1037 | register_ioport_readb(0x61, 1, speaker_ioport_read); | |
1038 | register_ioport_writeb(0x61, 1, speaker_ioport_write); | |
1039 | } | |
1040 | ||
1041 | /***********************************************************/ | |
1042 | /* serial port emulation */ | |
1043 | ||
1044 | #define UART_IRQ 4 | |
1045 | ||
1046 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
1047 | ||
1048 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
1049 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
1050 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
1051 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
1052 | ||
1053 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
1054 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
1055 | ||
1056 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
1057 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
1058 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
1059 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
1060 | ||
1061 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
1062 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
1063 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
1064 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
1065 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
1066 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
1067 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
1068 | ||
1069 | typedef struct SerialState { | |
1070 | uint8_t divider; | |
1071 | uint8_t rbr; /* receive register */ | |
1072 | uint8_t ier; | |
1073 | uint8_t iir; /* read only */ | |
1074 | uint8_t lcr; | |
1075 | uint8_t mcr; | |
1076 | uint8_t lsr; /* read only */ | |
1077 | uint8_t msr; | |
1078 | uint8_t scr; | |
1079 | } SerialState; | |
1080 | ||
1081 | SerialState serial_ports[1]; | |
1082 | ||
1083 | void serial_update_irq(void) | |
1084 | { | |
1085 | SerialState *s = &serial_ports[0]; | |
1086 | ||
1087 | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) { | |
1088 | s->iir = UART_IIR_RDI; | |
1089 | } else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) { | |
1090 | s->iir = UART_IIR_THRI; | |
1091 | } else { | |
1092 | s->iir = UART_IIR_NO_INT; | |
1093 | } | |
1094 | if (s->iir != UART_IIR_NO_INT) { | |
1095 | pic_set_irq(UART_IRQ, 1); | |
1096 | } else { | |
1097 | pic_set_irq(UART_IRQ, 0); | |
1098 | } | |
1099 | } | |
1100 | ||
1101 | void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1102 | { | |
1103 | SerialState *s = &serial_ports[0]; | |
1104 | unsigned char ch; | |
1105 | int ret; | |
1106 | ||
1107 | addr &= 7; | |
1108 | switch(addr) { | |
1109 | default: | |
1110 | case 0: | |
1111 | if (s->lcr & UART_LCR_DLAB) { | |
1112 | s->divider = (s->divider & 0xff00) | val; | |
1113 | } else { | |
1114 | s->lsr &= ~UART_LSR_THRE; | |
1115 | serial_update_irq(); | |
1116 | ||
1117 | ch = val; | |
1118 | do { | |
1119 | ret = write(1, &ch, 1); | |
1120 | } while (ret != 1); | |
1121 | s->lsr |= UART_LSR_THRE; | |
1122 | s->lsr |= UART_LSR_TEMT; | |
1123 | serial_update_irq(); | |
1124 | } | |
1125 | break; | |
1126 | case 1: | |
1127 | if (s->lcr & UART_LCR_DLAB) { | |
1128 | s->divider = (s->divider & 0x00ff) | (val << 8); | |
1129 | } else { | |
1130 | s->ier = val; | |
1131 | serial_update_irq(); | |
1132 | } | |
1133 | break; | |
1134 | case 2: | |
1135 | break; | |
1136 | case 3: | |
1137 | s->lcr = val; | |
1138 | break; | |
1139 | case 4: | |
1140 | s->mcr = val; | |
1141 | break; | |
1142 | case 5: | |
1143 | break; | |
1144 | case 6: | |
1145 | s->msr = val; | |
1146 | break; | |
1147 | case 7: | |
1148 | s->scr = val; | |
1149 | break; | |
1150 | } | |
1151 | } | |
1152 | ||
1153 | uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr) | |
1154 | { | |
1155 | SerialState *s = &serial_ports[0]; | |
1156 | uint32_t ret; | |
1157 | ||
1158 | addr &= 7; | |
1159 | switch(addr) { | |
1160 | default: | |
1161 | case 0: | |
1162 | if (s->lcr & UART_LCR_DLAB) { | |
1163 | ret = s->divider & 0xff; | |
1164 | } else { | |
1165 | ret = s->rbr; | |
1166 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
1167 | serial_update_irq(); | |
1168 | } | |
1169 | break; | |
1170 | case 1: | |
1171 | if (s->lcr & UART_LCR_DLAB) { | |
1172 | ret = (s->divider >> 8) & 0xff; | |
1173 | } else { | |
1174 | ret = s->ier; | |
1175 | } | |
1176 | break; | |
1177 | case 2: | |
1178 | ret = s->iir; | |
1179 | break; | |
1180 | case 3: | |
1181 | ret = s->lcr; | |
1182 | break; | |
1183 | case 4: | |
1184 | ret = s->mcr; | |
1185 | break; | |
1186 | case 5: | |
1187 | ret = s->lsr; | |
1188 | break; | |
1189 | case 6: | |
1190 | ret = s->msr; | |
1191 | break; | |
1192 | case 7: | |
1193 | ret = s->scr; | |
1194 | break; | |
1195 | } | |
1196 | return ret; | |
1197 | } | |
1198 | ||
1199 | #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */ | |
1200 | static int term_got_escape; | |
1201 | ||
1202 | void term_print_help(void) | |
1203 | { | |
1204 | printf("\n" | |
1205 | "C-a h print this help\n" | |
1206 | "C-a x exit emulatior\n" | |
1207 | "C-a b send break (magic sysrq)\n" | |
1208 | "C-a C-a send C-a\n" | |
1209 | ); | |
1210 | } | |
1211 | ||
1212 | /* called when a char is received */ | |
1213 | void serial_received_byte(SerialState *s, int ch) | |
1214 | { | |
1215 | if (term_got_escape) { | |
1216 | term_got_escape = 0; | |
1217 | switch(ch) { | |
1218 | case 'h': | |
1219 | term_print_help(); | |
1220 | break; | |
1221 | case 'x': | |
1222 | exit(0); | |
1223 | break; | |
1224 | case 'b': | |
1225 | /* send break */ | |
1226 | s->rbr = 0; | |
1227 | s->lsr |= UART_LSR_BI | UART_LSR_DR; | |
1228 | serial_update_irq(); | |
1229 | break; | |
1230 | case TERM_ESCAPE: | |
1231 | goto send_char; | |
1232 | } | |
1233 | } else if (ch == TERM_ESCAPE) { | |
1234 | term_got_escape = 1; | |
1235 | } else { | |
1236 | send_char: | |
1237 | s->rbr = ch; | |
1238 | s->lsr |= UART_LSR_DR; | |
1239 | serial_update_irq(); | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | /* init terminal so that we can grab keys */ | |
1244 | static struct termios oldtty; | |
1245 | ||
1246 | static void term_exit(void) | |
1247 | { | |
1248 | tcsetattr (0, TCSANOW, &oldtty); | |
1249 | } | |
1250 | ||
1251 | static void term_init(void) | |
1252 | { | |
1253 | struct termios tty; | |
1254 | ||
1255 | tcgetattr (0, &tty); | |
1256 | oldtty = tty; | |
1257 | ||
1258 | tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP | |
1259 | |INLCR|IGNCR|ICRNL|IXON); | |
1260 | tty.c_oflag |= OPOST; | |
1261 | tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG); | |
1262 | tty.c_cflag &= ~(CSIZE|PARENB); | |
1263 | tty.c_cflag |= CS8; | |
1264 | tty.c_cc[VMIN] = 1; | |
1265 | tty.c_cc[VTIME] = 0; | |
1266 | ||
1267 | tcsetattr (0, TCSANOW, &tty); | |
1268 | ||
1269 | atexit(term_exit); | |
1270 | ||
1271 | fcntl(0, F_SETFL, O_NONBLOCK); | |
1272 | } | |
1273 | ||
1274 | void serial_init(void) | |
1275 | { | |
1276 | SerialState *s = &serial_ports[0]; | |
1277 | ||
1278 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; | |
1279 | ||
1280 | register_ioport_writeb(0x3f8, 8, serial_ioport_write); | |
1281 | register_ioport_readb(0x3f8, 8, serial_ioport_read); | |
1282 | ||
1283 | term_init(); | |
1284 | } | |
1285 | ||
1286 | /***********************************************************/ | |
1287 | /* ne2000 emulation */ | |
1288 | ||
1289 | //#define DEBUG_NE2000 | |
1290 | ||
1291 | #define NE2000_IOPORT 0x300 | |
1292 | #define NE2000_IRQ 9 | |
1293 | ||
1294 | #define MAX_ETH_FRAME_SIZE 1514 | |
1295 | ||
1296 | #define E8390_CMD 0x00 /* The command register (for all pages) */ | |
1297 | /* Page 0 register offsets. */ | |
1298 | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ | |
1299 | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ | |
1300 | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ | |
1301 | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ | |
1302 | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ | |
1303 | #define EN0_TSR 0x04 /* Transmit status reg RD */ | |
1304 | #define EN0_TPSR 0x04 /* Transmit starting page WR */ | |
1305 | #define EN0_NCR 0x05 /* Number of collision reg RD */ | |
1306 | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ | |
1307 | #define EN0_FIFO 0x06 /* FIFO RD */ | |
1308 | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ | |
1309 | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ | |
1310 | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ | |
1311 | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ | |
1312 | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ | |
1313 | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ | |
1314 | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ | |
1315 | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ | |
1316 | #define EN0_RSR 0x0c /* rx status reg RD */ | |
1317 | #define EN0_RXCR 0x0c /* RX configuration reg WR */ | |
1318 | #define EN0_TXCR 0x0d /* TX configuration reg WR */ | |
1319 | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ | |
1320 | #define EN0_DCFG 0x0e /* Data configuration reg WR */ | |
1321 | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ | |
1322 | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ | |
1323 | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ | |
1324 | ||
1325 | #define EN1_PHYS 0x11 | |
1326 | #define EN1_CURPAG 0x17 | |
1327 | #define EN1_MULT 0x18 | |
1328 | ||
1329 | /* Register accessed at EN_CMD, the 8390 base addr. */ | |
1330 | #define E8390_STOP 0x01 /* Stop and reset the chip */ | |
1331 | #define E8390_START 0x02 /* Start the chip, clear reset */ | |
1332 | #define E8390_TRANS 0x04 /* Transmit a frame */ | |
1333 | #define E8390_RREAD 0x08 /* Remote read */ | |
1334 | #define E8390_RWRITE 0x10 /* Remote write */ | |
1335 | #define E8390_NODMA 0x20 /* Remote DMA */ | |
1336 | #define E8390_PAGE0 0x00 /* Select page chip registers */ | |
1337 | #define E8390_PAGE1 0x40 /* using the two high-order bits */ | |
1338 | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ | |
1339 | ||
1340 | /* Bits in EN0_ISR - Interrupt status register */ | |
1341 | #define ENISR_RX 0x01 /* Receiver, no error */ | |
1342 | #define ENISR_TX 0x02 /* Transmitter, no error */ | |
1343 | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ | |
1344 | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ | |
1345 | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ | |
1346 | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ | |
1347 | #define ENISR_RDC 0x40 /* remote dma complete */ | |
1348 | #define ENISR_RESET 0x80 /* Reset completed */ | |
1349 | #define ENISR_ALL 0x3f /* Interrupts we will enable */ | |
1350 | ||
1351 | /* Bits in received packet status byte and EN0_RSR*/ | |
1352 | #define ENRSR_RXOK 0x01 /* Received a good packet */ | |
1353 | #define ENRSR_CRC 0x02 /* CRC error */ | |
1354 | #define ENRSR_FAE 0x04 /* frame alignment error */ | |
1355 | #define ENRSR_FO 0x08 /* FIFO overrun */ | |
1356 | #define ENRSR_MPA 0x10 /* missed pkt */ | |
1357 | #define ENRSR_PHY 0x20 /* physical/multicast address */ | |
1358 | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ | |
1359 | #define ENRSR_DEF 0x80 /* deferring */ | |
1360 | ||
1361 | /* Transmitted packet status, EN0_TSR. */ | |
1362 | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ | |
1363 | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ | |
1364 | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ | |
1365 | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ | |
1366 | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ | |
1367 | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ | |
1368 | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ | |
1369 | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ | |
1370 | ||
1371 | #define NE2000_MEM_SIZE 32768 | |
1372 | ||
1373 | typedef struct NE2000State { | |
1374 | uint8_t cmd; | |
1375 | uint32_t start; | |
1376 | uint32_t stop; | |
1377 | uint8_t boundary; | |
1378 | uint8_t tsr; | |
1379 | uint8_t tpsr; | |
1380 | uint16_t tcnt; | |
1381 | uint16_t rcnt; | |
1382 | uint32_t rsar; | |
1383 | uint8_t isr; | |
1384 | uint8_t dcfg; | |
1385 | uint8_t imr; | |
1386 | uint8_t phys[6]; /* mac address */ | |
1387 | uint8_t curpag; | |
1388 | uint8_t mult[8]; /* multicast mask array */ | |
1389 | uint8_t mem[NE2000_MEM_SIZE]; | |
1390 | } NE2000State; | |
1391 | ||
1392 | NE2000State ne2000_state; | |
1393 | int net_fd = -1; | |
1394 | char network_script[1024]; | |
1395 | ||
1396 | void ne2000_reset(void) | |
1397 | { | |
1398 | NE2000State *s = &ne2000_state; | |
1399 | int i; | |
1400 | ||
1401 | s->isr = ENISR_RESET; | |
1402 | s->mem[0] = 0x52; | |
1403 | s->mem[1] = 0x54; | |
1404 | s->mem[2] = 0x00; | |
1405 | s->mem[3] = 0x12; | |
1406 | s->mem[4] = 0x34; | |
1407 | s->mem[5] = 0x56; | |
1408 | s->mem[14] = 0x57; | |
1409 | s->mem[15] = 0x57; | |
1410 | ||
1411 | /* duplicate prom data */ | |
1412 | for(i = 15;i >= 0; i--) { | |
1413 | s->mem[2 * i] = s->mem[i]; | |
1414 | s->mem[2 * i + 1] = s->mem[i]; | |
1415 | } | |
1416 | } | |
1417 | ||
1418 | void ne2000_update_irq(NE2000State *s) | |
1419 | { | |
1420 | int isr; | |
1421 | isr = s->isr & s->imr; | |
1422 | if (isr) | |
1423 | pic_set_irq(NE2000_IRQ, 1); | |
1424 | else | |
1425 | pic_set_irq(NE2000_IRQ, 0); | |
1426 | } | |
1427 | ||
1428 | int net_init(void) | |
1429 | { | |
1430 | struct ifreq ifr; | |
1431 | int fd, ret, pid, status; | |
1432 | ||
1433 | fd = open("/dev/net/tun", O_RDWR); | |
1434 | if (fd < 0) { | |
1435 | fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n"); | |
1436 | return -1; | |
1437 | } | |
1438 | memset(&ifr, 0, sizeof(ifr)); | |
1439 | ifr.ifr_flags = IFF_TAP | IFF_NO_PI; | |
1440 | pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d"); | |
1441 | ret = ioctl(fd, TUNSETIFF, (void *) &ifr); | |
1442 | if (ret != 0) { | |
1443 | fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n"); | |
1444 | close(fd); | |
1445 | return -1; | |
1446 | } | |
1447 | printf("connected to host network interface: %s\n", ifr.ifr_name); | |
1448 | fcntl(fd, F_SETFL, O_NONBLOCK); | |
1449 | net_fd = fd; | |
1450 | ||
1451 | /* try to launch network init script */ | |
1452 | pid = fork(); | |
1453 | if (pid >= 0) { | |
1454 | if (pid == 0) { | |
1455 | execl(network_script, network_script, ifr.ifr_name, NULL); | |
1456 | exit(1); | |
1457 | } | |
1458 | while (waitpid(pid, &status, 0) != pid); | |
1459 | if (!WIFEXITED(status) || | |
1460 | WEXITSTATUS(status) != 0) { | |
1461 | fprintf(stderr, "%s: could not launch network script for '%s'\n", | |
1462 | network_script, ifr.ifr_name); | |
1463 | } | |
1464 | } | |
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | void net_send_packet(NE2000State *s, const uint8_t *buf, int size) | |
1469 | { | |
1470 | #ifdef DEBUG_NE2000 | |
1471 | printf("NE2000: sending packet size=%d\n", size); | |
1472 | #endif | |
1473 | write(net_fd, buf, size); | |
1474 | } | |
1475 | ||
1476 | /* return true if the NE2000 can receive more data */ | |
1477 | int ne2000_can_receive(NE2000State *s) | |
1478 | { | |
1479 | int avail, index, boundary; | |
1480 | ||
1481 | if (s->cmd & E8390_STOP) | |
1482 | return 0; | |
1483 | index = s->curpag << 8; | |
1484 | boundary = s->boundary << 8; | |
1485 | if (index < boundary) | |
1486 | avail = boundary - index; | |
1487 | else | |
1488 | avail = (s->stop - s->start) - (index - boundary); | |
1489 | if (avail < (MAX_ETH_FRAME_SIZE + 4)) | |
1490 | return 0; | |
1491 | return 1; | |
1492 | } | |
1493 | ||
1494 | void ne2000_receive(NE2000State *s, uint8_t *buf, int size) | |
1495 | { | |
1496 | uint8_t *p; | |
1497 | int total_len, next, avail, len, index; | |
1498 | ||
1499 | #if defined(DEBUG_NE2000) | |
1500 | printf("NE2000: received len=%d\n", size); | |
1501 | #endif | |
1502 | ||
1503 | index = s->curpag << 8; | |
1504 | /* 4 bytes for header */ | |
1505 | total_len = size + 4; | |
1506 | /* address for next packet (4 bytes for CRC) */ | |
1507 | next = index + ((total_len + 4 + 255) & ~0xff); | |
1508 | if (next >= s->stop) | |
1509 | next -= (s->stop - s->start); | |
1510 | /* prepare packet header */ | |
1511 | p = s->mem + index; | |
1512 | p[0] = ENRSR_RXOK; /* receive status */ | |
1513 | p[1] = next >> 8; | |
1514 | p[2] = total_len; | |
1515 | p[3] = total_len >> 8; | |
1516 | index += 4; | |
1517 | ||
1518 | /* write packet data */ | |
1519 | while (size > 0) { | |
1520 | avail = s->stop - index; | |
1521 | len = size; | |
1522 | if (len > avail) | |
1523 | len = avail; | |
1524 | memcpy(s->mem + index, buf, len); | |
1525 | buf += len; | |
1526 | index += len; | |
1527 | if (index == s->stop) | |
1528 | index = s->start; | |
1529 | size -= len; | |
1530 | } | |
1531 | s->curpag = next >> 8; | |
1532 | ||
1533 | /* now we can signal we have receive something */ | |
1534 | s->isr |= ENISR_RX; | |
1535 | ne2000_update_irq(s); | |
1536 | } | |
1537 | ||
1538 | void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1539 | { | |
1540 | NE2000State *s = &ne2000_state; | |
1541 | int offset, page; | |
1542 | ||
1543 | addr &= 0xf; | |
1544 | #ifdef DEBUG_NE2000 | |
1545 | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val); | |
1546 | #endif | |
1547 | if (addr == E8390_CMD) { | |
1548 | /* control register */ | |
1549 | s->cmd = val; | |
1550 | if (val & E8390_START) { | |
1551 | /* test specific case: zero length transfert */ | |
1552 | if ((val & (E8390_RREAD | E8390_RWRITE)) && | |
1553 | s->rcnt == 0) { | |
1554 | s->isr |= ENISR_RDC; | |
1555 | ne2000_update_irq(s); | |
1556 | /* XXX: find a better solution for irqs */ | |
1557 | cpu_x86_interrupt(global_env); | |
1558 | } | |
1559 | if (val & E8390_TRANS) { | |
1560 | net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt); | |
1561 | /* signal end of transfert */ | |
1562 | s->tsr = ENTSR_PTX; | |
1563 | s->isr |= ENISR_TX; | |
1564 | ne2000_update_irq(s); | |
1565 | } | |
1566 | } | |
1567 | } else { | |
1568 | page = s->cmd >> 6; | |
1569 | offset = addr | (page << 4); | |
1570 | switch(offset) { | |
1571 | case EN0_STARTPG: | |
1572 | s->start = val << 8; | |
1573 | break; | |
1574 | case EN0_STOPPG: | |
1575 | s->stop = val << 8; | |
1576 | break; | |
1577 | case EN0_BOUNDARY: | |
1578 | s->boundary = val; | |
1579 | break; | |
1580 | case EN0_IMR: | |
1581 | s->imr = val; | |
1582 | ne2000_update_irq(s); | |
1583 | break; | |
1584 | case EN0_TPSR: | |
1585 | s->tpsr = val; | |
1586 | break; | |
1587 | case EN0_TCNTLO: | |
1588 | s->tcnt = (s->tcnt & 0xff00) | val; | |
1589 | break; | |
1590 | case EN0_TCNTHI: | |
1591 | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); | |
1592 | break; | |
1593 | case EN0_RSARLO: | |
1594 | s->rsar = (s->rsar & 0xff00) | val; | |
1595 | break; | |
1596 | case EN0_RSARHI: | |
1597 | s->rsar = (s->rsar & 0x00ff) | (val << 8); | |
1598 | break; | |
1599 | case EN0_RCNTLO: | |
1600 | s->rcnt = (s->rcnt & 0xff00) | val; | |
1601 | break; | |
1602 | case EN0_RCNTHI: | |
1603 | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); | |
1604 | break; | |
1605 | case EN0_DCFG: | |
1606 | s->dcfg = val; | |
1607 | break; | |
1608 | case EN0_ISR: | |
1609 | s->isr &= ~val; | |
1610 | ne2000_update_irq(s); | |
1611 | break; | |
1612 | case EN1_PHYS ... EN1_PHYS + 5: | |
1613 | s->phys[offset - EN1_PHYS] = val; | |
1614 | break; | |
1615 | case EN1_CURPAG: | |
1616 | s->curpag = val; | |
1617 | break; | |
1618 | case EN1_MULT ... EN1_MULT + 7: | |
1619 | s->mult[offset - EN1_MULT] = val; | |
1620 | break; | |
1621 | } | |
1622 | } | |
1623 | } | |
1624 | ||
1625 | uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr) | |
1626 | { | |
1627 | NE2000State *s = &ne2000_state; | |
1628 | int offset, page, ret; | |
1629 | ||
1630 | addr &= 0xf; | |
1631 | if (addr == E8390_CMD) { | |
1632 | ret = s->cmd; | |
1633 | } else { | |
1634 | page = s->cmd >> 6; | |
1635 | offset = addr | (page << 4); | |
1636 | switch(offset) { | |
1637 | case EN0_TSR: | |
1638 | ret = s->tsr; | |
1639 | break; | |
1640 | case EN0_BOUNDARY: | |
1641 | ret = s->boundary; | |
1642 | break; | |
1643 | case EN0_ISR: | |
1644 | ret = s->isr; | |
1645 | break; | |
1646 | case EN1_PHYS ... EN1_PHYS + 5: | |
1647 | ret = s->phys[offset - EN1_PHYS]; | |
1648 | break; | |
1649 | case EN1_CURPAG: | |
1650 | ret = s->curpag; | |
1651 | break; | |
1652 | case EN1_MULT ... EN1_MULT + 7: | |
1653 | ret = s->mult[offset - EN1_MULT]; | |
1654 | break; | |
1655 | default: | |
1656 | ret = 0x00; | |
1657 | break; | |
1658 | } | |
1659 | } | |
1660 | #ifdef DEBUG_NE2000 | |
1661 | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret); | |
1662 | #endif | |
1663 | return ret; | |
1664 | } | |
1665 | ||
1666 | void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1667 | { | |
1668 | NE2000State *s = &ne2000_state; | |
1669 | uint8_t *p; | |
1670 | ||
1671 | #ifdef DEBUG_NE2000 | |
1672 | printf("NE2000: asic write val=0x%04x\n", val); | |
1673 | #endif | |
1674 | p = s->mem + s->rsar; | |
1675 | if (s->dcfg & 0x01) { | |
1676 | /* 16 bit access */ | |
1677 | p[0] = val; | |
1678 | p[1] = val >> 8; | |
1679 | s->rsar += 2; | |
1680 | s->rcnt -= 2; | |
1681 | } else { | |
1682 | /* 8 bit access */ | |
1683 | p[0] = val; | |
1684 | s->rsar++; | |
1685 | s->rcnt--; | |
1686 | } | |
1687 | /* wrap */ | |
1688 | if (s->rsar == s->stop) | |
1689 | s->rsar = s->start; | |
1690 | if (s->rcnt == 0) { | |
1691 | /* signal end of transfert */ | |
1692 | s->isr |= ENISR_RDC; | |
1693 | ne2000_update_irq(s); | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr) | |
1698 | { | |
1699 | NE2000State *s = &ne2000_state; | |
1700 | uint8_t *p; | |
1701 | int ret; | |
1702 | ||
1703 | p = s->mem + s->rsar; | |
1704 | if (s->dcfg & 0x01) { | |
1705 | /* 16 bit access */ | |
1706 | ret = p[0] | (p[1] << 8); | |
1707 | s->rsar += 2; | |
1708 | s->rcnt -= 2; | |
1709 | } else { | |
1710 | /* 8 bit access */ | |
1711 | ret = p[0]; | |
1712 | s->rsar++; | |
1713 | s->rcnt--; | |
1714 | } | |
1715 | /* wrap */ | |
1716 | if (s->rsar == s->stop) | |
1717 | s->rsar = s->start; | |
1718 | if (s->rcnt == 0) { | |
1719 | /* signal end of transfert */ | |
1720 | s->isr |= ENISR_RDC; | |
1721 | ne2000_update_irq(s); | |
1722 | } | |
1723 | #ifdef DEBUG_NE2000 | |
1724 | printf("NE2000: asic read val=0x%04x\n", ret); | |
1725 | #endif | |
1726 | return ret; | |
1727 | } | |
1728 | ||
1729 | void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val) | |
1730 | { | |
1731 | /* nothing to do (end of reset pulse) */ | |
1732 | } | |
1733 | ||
1734 | uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr) | |
1735 | { | |
1736 | ne2000_reset(); | |
1737 | return 0; | |
1738 | } | |
1739 | ||
1740 | void ne2000_init(void) | |
1741 | { | |
1742 | register_ioport_writeb(NE2000_IOPORT, 16, ne2000_ioport_write); | |
1743 | register_ioport_readb(NE2000_IOPORT, 16, ne2000_ioport_read); | |
1744 | ||
1745 | register_ioport_writeb(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write); | |
1746 | register_ioport_readb(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read); | |
1747 | register_ioport_writew(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write); | |
1748 | register_ioport_readw(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read); | |
1749 | ||
1750 | register_ioport_writeb(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write); | |
1751 | register_ioport_readb(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read); | |
1752 | ne2000_reset(); | |
1753 | } | |
1754 | ||
1755 | /***********************************************************/ | |
1756 | /* cpu signal handler */ | |
1757 | static void host_segv_handler(int host_signum, siginfo_t *info, | |
1758 | void *puc) | |
1759 | { | |
1760 | if (cpu_signal_handler(host_signum, info, puc)) | |
1761 | return; | |
1762 | term_exit(); | |
1763 | abort(); | |
1764 | } | |
1765 | ||
1766 | static int timer_irq_pending; | |
1767 | static int timer_irq_count; | |
1768 | ||
1769 | static void host_alarm_handler(int host_signum, siginfo_t *info, | |
1770 | void *puc) | |
1771 | { | |
1772 | /* NOTE: since usually the OS asks a 100 Hz clock, there can be | |
1773 | some drift between cpu_get_ticks() and the interrupt time. So | |
1774 | we queue some interrupts to avoid missing some */ | |
1775 | timer_irq_count += pit_get_out_edges(&pit_channels[0]); | |
1776 | if (timer_irq_count) { | |
1777 | if (timer_irq_count > 2) | |
1778 | timer_irq_count = 2; | |
1779 | timer_irq_count--; | |
1780 | /* just exit from the cpu to have a chance to handle timers */ | |
1781 | cpu_x86_interrupt(global_env); | |
1782 | timer_irq_pending = 1; | |
1783 | } | |
1784 | } | |
1785 | ||
1786 | void help(void) | |
1787 | { | |
1788 | printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n" | |
1789 | "usage: vl [-h] bzImage initrd [kernel parameters...]\n" | |
1790 | "\n" | |
1791 | "'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n" | |
1792 | "to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n" | |
1793 | "'initrd' is an initrd image\n" | |
1794 | "-m megs set virtual RAM size to megs MB\n" | |
1795 | "-n script set network init script [default=%s]\n" | |
1796 | "-d output log in /tmp/vl.log\n" | |
1797 | "\n" | |
1798 | "During emulation, use C-a h to get terminal commands:\n", | |
1799 | DEFAULT_NETWORK_SCRIPT); | |
1800 | term_print_help(); | |
1801 | exit(1); | |
1802 | } | |
1803 | ||
1804 | int main(int argc, char **argv) | |
1805 | { | |
1806 | int c, ret, initrd_size, i; | |
1807 | struct linux_params *params; | |
1808 | struct sigaction act; | |
1809 | struct itimerval itv; | |
1810 | CPUX86State *env; | |
1811 | const char *tmpdir; | |
1812 | ||
1813 | /* we never want that malloc() uses mmap() */ | |
1814 | mallopt(M_MMAP_THRESHOLD, 4096 * 1024); | |
1815 | ||
1816 | phys_ram_size = 32 * 1024 * 1024; | |
1817 | pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT); | |
1818 | for(;;) { | |
1819 | c = getopt(argc, argv, "hm:dn:"); | |
1820 | if (c == -1) | |
1821 | break; | |
1822 | switch(c) { | |
1823 | case 'h': | |
1824 | help(); | |
1825 | break; | |
1826 | case 'm': | |
1827 | phys_ram_size = atoi(optarg) * 1024 * 1024; | |
1828 | if (phys_ram_size <= 0) | |
1829 | help(); | |
1830 | break; | |
1831 | case 'd': | |
1832 | loglevel = 1; | |
1833 | break; | |
1834 | case 'n': | |
1835 | pstrcpy(network_script, sizeof(network_script), optarg); | |
1836 | break; | |
1837 | } | |
1838 | } | |
1839 | if (optind + 1 >= argc) | |
1840 | help(); | |
1841 | ||
1842 | /* init debug */ | |
1843 | if (loglevel) { | |
1844 | logfile = fopen(DEBUG_LOGFILE, "w"); | |
1845 | if (!logfile) { | |
1846 | perror(DEBUG_LOGFILE); | |
1847 | _exit(1); | |
1848 | } | |
1849 | setvbuf(logfile, NULL, _IOLBF, 0); | |
1850 | } | |
1851 | ||
1852 | /* init network tun interface */ | |
1853 | net_init(); | |
1854 | ||
1855 | /* init the memory */ | |
1856 | tmpdir = getenv("VLTMPDIR"); | |
1857 | if (!tmpdir) | |
1858 | tmpdir = "/tmp"; | |
1859 | snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir); | |
1860 | if (mkstemp(phys_ram_file) < 0) { | |
1861 | fprintf(stderr, "Could not create temporary memory file '%s'\n", | |
1862 | phys_ram_file); | |
1863 | exit(1); | |
1864 | } | |
1865 | phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600); | |
1866 | if (phys_ram_fd < 0) { | |
1867 | fprintf(stderr, "Could not open temporary memory file '%s'\n", | |
1868 | phys_ram_file); | |
1869 | exit(1); | |
1870 | } | |
1871 | ftruncate(phys_ram_fd, phys_ram_size); | |
1872 | unlink(phys_ram_file); | |
1873 | phys_ram_base = mmap((void *)PHYS_RAM_BASE, phys_ram_size, | |
1874 | PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED, | |
1875 | phys_ram_fd, 0); | |
1876 | if (phys_ram_base == MAP_FAILED) { | |
1877 | fprintf(stderr, "Could not map physical memory\n"); | |
1878 | exit(1); | |
1879 | } | |
1880 | ||
1881 | /* now we can load the kernel */ | |
1882 | ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR); | |
1883 | if (ret < 0) { | |
1884 | fprintf(stderr, "%s: could not load kernel\n", argv[optind]); | |
1885 | exit(1); | |
1886 | } | |
1887 | ||
1888 | /* load initrd */ | |
1889 | initrd_size = load_image(argv[optind + 1], phys_ram_base + INITRD_LOAD_ADDR); | |
1890 | if (initrd_size < 0) { | |
1891 | fprintf(stderr, "%s: could not load initrd\n", argv[optind + 1]); | |
1892 | exit(1); | |
1893 | } | |
1894 | ||
1895 | /* init kernel params */ | |
1896 | params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR); | |
1897 | memset(params, 0, sizeof(struct linux_params)); | |
1898 | params->mount_root_rdonly = 0; | |
1899 | params->cl_magic = 0xA33F; | |
1900 | params->cl_offset = params->commandline - (uint8_t *)params; | |
1901 | params->ext_mem_k = (phys_ram_size / 1024) - 1024; | |
1902 | for(i = optind + 2; i < argc; i++) { | |
1903 | if (i != optind + 2) | |
1904 | pstrcat(params->commandline, sizeof(params->commandline), " "); | |
1905 | pstrcat(params->commandline, sizeof(params->commandline), argv[i]); | |
1906 | } | |
1907 | params->loader_type = 0x01; | |
1908 | if (initrd_size > 0) { | |
1909 | params->initrd_start = INITRD_LOAD_ADDR; | |
1910 | params->initrd_size = initrd_size; | |
1911 | } | |
1912 | params->orig_video_lines = 25; | |
1913 | params->orig_video_cols = 80; | |
1914 | ||
1915 | /* init basic PC hardware */ | |
1916 | init_ioports(); | |
1917 | register_ioport_writeb(0x80, 1, ioport80_write); | |
1918 | ||
1919 | register_ioport_writeb(0x3d4, 2, vga_ioport_write); | |
1920 | ||
1921 | cmos_init(); | |
1922 | pic_init(); | |
1923 | pit_init(); | |
1924 | serial_init(); | |
1925 | ne2000_init(); | |
1926 | ||
1927 | /* setup cpu signal handlers for MMU / self modifying code handling */ | |
1928 | sigfillset(&act.sa_mask); | |
1929 | act.sa_flags = SA_SIGINFO; | |
1930 | act.sa_sigaction = host_segv_handler; | |
1931 | sigaction(SIGSEGV, &act, NULL); | |
1932 | sigaction(SIGBUS, &act, NULL); | |
1933 | ||
1934 | act.sa_sigaction = host_alarm_handler; | |
1935 | sigaction(SIGALRM, &act, NULL); | |
1936 | ||
1937 | /* init CPU state */ | |
1938 | env = cpu_init(); | |
1939 | global_env = env; | |
1940 | cpu_single_env = env; | |
1941 | ||
1942 | /* setup basic memory access */ | |
1943 | env->cr[0] = 0x00000033; | |
1944 | cpu_x86_init_mmu(env); | |
1945 | ||
1946 | memset(params->idt_table, 0, sizeof(params->idt_table)); | |
1947 | ||
1948 | params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */ | |
1949 | params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */ | |
1950 | ||
1951 | env->idt.base = (void *)params->idt_table; | |
1952 | env->idt.limit = sizeof(params->idt_table) - 1; | |
1953 | env->gdt.base = (void *)params->gdt_table; | |
1954 | env->gdt.limit = sizeof(params->gdt_table) - 1; | |
1955 | ||
1956 | cpu_x86_load_seg(env, R_CS, KERNEL_CS); | |
1957 | cpu_x86_load_seg(env, R_DS, KERNEL_DS); | |
1958 | cpu_x86_load_seg(env, R_ES, KERNEL_DS); | |
1959 | cpu_x86_load_seg(env, R_SS, KERNEL_DS); | |
1960 | cpu_x86_load_seg(env, R_FS, KERNEL_DS); | |
1961 | cpu_x86_load_seg(env, R_GS, KERNEL_DS); | |
1962 | ||
1963 | env->eip = KERNEL_LOAD_ADDR; | |
1964 | env->regs[R_ESI] = KERNEL_PARAMS_ADDR; | |
1965 | env->eflags = 0x2; | |
1966 | ||
1967 | itv.it_interval.tv_sec = 0; | |
1968 | itv.it_interval.tv_usec = 1000; | |
1969 | itv.it_value.tv_sec = 0; | |
1970 | itv.it_value.tv_usec = 10 * 1000; | |
1971 | setitimer(ITIMER_REAL, &itv, NULL); | |
1972 | /* we probe the tick duration of the kernel to inform the user if | |
1973 | the emulated kernel requested a too high timer frequency */ | |
1974 | getitimer(ITIMER_REAL, &itv); | |
1975 | pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) / | |
1976 | 1000000; | |
1977 | ||
1978 | for(;;) { | |
1979 | struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd; | |
1980 | int ret, n, timeout; | |
1981 | uint8_t ch; | |
1982 | ||
1983 | ret = cpu_x86_exec(env); | |
1984 | ||
1985 | /* if hlt instruction, we wait until the next IRQ */ | |
1986 | if (ret == EXCP_HLT) | |
1987 | timeout = 10; | |
1988 | else | |
1989 | timeout = 0; | |
1990 | /* poll any events */ | |
1991 | serial_ufd = NULL; | |
1992 | net_ufd = NULL; | |
1993 | pf = ufds; | |
1994 | if (!(serial_ports[0].lsr & UART_LSR_DR)) { | |
1995 | serial_ufd = pf; | |
1996 | pf->fd = 0; | |
1997 | pf->events = POLLIN; | |
1998 | pf++; | |
1999 | } | |
2000 | if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) { | |
2001 | net_ufd = pf; | |
2002 | pf->fd = net_fd; | |
2003 | pf->events = POLLIN; | |
2004 | pf++; | |
2005 | } | |
2006 | ret = poll(ufds, pf - ufds, timeout); | |
2007 | if (ret > 0) { | |
2008 | if (serial_ufd && (serial_ufd->revents & POLLIN)) { | |
2009 | n = read(0, &ch, 1); | |
2010 | if (n == 1) { | |
2011 | serial_received_byte(&serial_ports[0], ch); | |
2012 | } | |
2013 | } | |
2014 | if (net_ufd && (net_ufd->revents & POLLIN)) { | |
2015 | uint8_t buf[MAX_ETH_FRAME_SIZE]; | |
2016 | ||
2017 | n = read(net_fd, buf, MAX_ETH_FRAME_SIZE); | |
2018 | if (n > 0) { | |
2019 | if (n < 60) { | |
2020 | memset(buf + n, 0, 60 - n); | |
2021 | n = 60; | |
2022 | } | |
2023 | ne2000_receive(&ne2000_state, buf, n); | |
2024 | } | |
2025 | } | |
2026 | } | |
2027 | ||
2028 | /* timer IRQ */ | |
2029 | if (timer_irq_pending) { | |
2030 | pic_set_irq(0, 1); | |
2031 | pic_set_irq(0, 0); | |
2032 | timer_irq_pending = 0; | |
2033 | } | |
2034 | ||
2035 | pic_handle_irq(); | |
2036 | } | |
2037 | ||
2038 | return 0; | |
2039 | } |