Documentation/arm64/booting.rst

   1 =====================
   2 Booting AArch64 Linux
   3 =====================
   4
   5 Author: Will Deacon <will.deacon@arm.com>
   6
   7 Date  : 07 September 2012
   8
   9 This document is based on the ARM booting document by Russell King and
  10 is relevant to all public releases of the AArch64 Linux kernel.
  11
  12 The AArch64 exception model is made up of a number of exception levels
  13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
  14 counterpart.  EL2 is the hypervisor level and exists only in non-secure
  15 mode. EL3 is the highest priority level and exists only in secure mode.
  16
  17 For the purposes of this document, we will use the term `boot loader`
  18 simply to define all software that executes on the CPU(s) before control
  19 is passed to the Linux kernel.  This may include secure monitor and
  20 hypervisor code, or it may just be a handful of instructions for
  21 preparing a minimal boot environment.
  22
  23 Essentially, the boot loader should provide (as a minimum) the
  24 following:
  25
  26 1. Setup and initialise the RAM
  27 2. Setup the device tree
  28 3. Decompress the kernel image
  29 4. Call the kernel image
  30
  31
  32 1. Setup and initialise RAM
  33 ---------------------------
  34
  35 Requirement: MANDATORY
  36
  37 The boot loader is expected to find and initialise all RAM that the
  38 kernel will use for volatile data storage in the system.  It performs
  39 this in a machine dependent manner.  (It may use internal algorithms
  40 to automatically locate and size all RAM, or it may use knowledge of
  41 the RAM in the machine, or any other method the boot loader designer
  42 sees fit.)
  43
  44
  45 2. Setup the device tree
  46 -------------------------
  47
  48 Requirement: MANDATORY
  49
  50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
  51 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
  52 using blocks of up to 2 megabytes in size, it must not be placed within
  53 any 2M region which must be mapped with any specific attributes.
  54
  55 NOTE: versions prior to v4.2 also require that the DTB be placed within
  56 the 512 MB region starting at text_offset bytes below the kernel Image.
  57
  58 3. Decompress the kernel image
  59 ------------------------------
  60
  61 Requirement: OPTIONAL
  62
  63 The AArch64 kernel does not currently provide a decompressor and
  64 therefore requires decompression (gzip etc.) to be performed by the boot
  65 loader if a compressed Image target (e.g. Image.gz) is used.  For
  66 bootloaders that do not implement this requirement, the uncompressed
  67 Image target is available instead.
  68
  69
  70 4. Call the kernel image
  71 ------------------------
  72
  73 Requirement: MANDATORY
  74
  75 The decompressed kernel image contains a 64-byte header as follows::
  76
  77   u32 code0;                    /* Executable code */
  78   u32 code1;                    /* Executable code */
  79   u64 text_offset;              /* Image load offset, little endian */
  80   u64 image_size;               /* Effective Image size, little endian */
  81   u64 flags;                    /* kernel flags, little endian */
  82   u64 res2      = 0;            /* reserved */
  83   u64 res3      = 0;            /* reserved */
  84   u64 res4      = 0;            /* reserved */
  85   u32 magic     = 0x644d5241;   /* Magic number, little endian, "ARM\x64" */
  86   u32 res5;                     /* reserved (used for PE COFF offset) */
  87
  88
  89 Header notes:
  90
  91 - As of v3.17, all fields are little endian unless stated otherwise.
  92
  93 - code0/code1 are responsible for branching to stext.
  94
  95 - when booting through EFI, code0/code1 are initially skipped.
  96   res5 is an offset to the PE header and the PE header has the EFI
  97   entry point (efi_stub_entry).  When the stub has done its work, it
  98   jumps to code0 to resume the normal boot process.
  99
 100 - Prior to v3.17, the endianness of text_offset was not specified.  In
 101   these cases image_size is zero and text_offset is 0x80000 in the
 102   endianness of the kernel.  Where image_size is non-zero image_size is
 103   little-endian and must be respected.  Where image_size is zero,
 104   text_offset can be assumed to be 0x80000.
 105
 106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
 107   composed as follows:
 108
 109   ============= ===============================================================
 110   Bit 0         Kernel endianness.  1 if BE, 0 if LE.
 111   Bit 1-2       Kernel Page size.
 112
 113                         * 0 - Unspecified.
 114                         * 1 - 4K
 115                         * 2 - 16K
 116                         * 3 - 64K
 117   Bit 3         Kernel physical placement
 118
 119                         0
 120                           2MB aligned base should be as close as possible
 121                           to the base of DRAM, since memory below it is not
 122                           accessible via the linear mapping
 123                         1
 124                           2MB aligned base may be anywhere in physical
 125                           memory
 126   Bits 4-63     Reserved.
 127   ============= ===============================================================
 128
 129 - When image_size is zero, a bootloader should attempt to keep as much
 130   memory as possible free for use by the kernel immediately after the
 131   end of the kernel image. The amount of space required will vary
 132   depending on selected features, and is effectively unbound.
 133
 134 The Image must be placed text_offset bytes from a 2MB aligned base
 135 address anywhere in usable system RAM and called there. The region
 136 between the 2 MB aligned base address and the start of the image has no
 137 special significance to the kernel, and may be used for other purposes.
 138 At least image_size bytes from the start of the image must be free for
 139 use by the kernel.
 140 NOTE: versions prior to v4.6 cannot make use of memory below the
 141 physical offset of the Image so it is recommended that the Image be
 142 placed as close as possible to the start of system RAM.
 143
 144 If an initrd/initramfs is passed to the kernel at boot, it must reside
 145 entirely within a 1 GB aligned physical memory window of up to 32 GB in
 146 size that fully covers the kernel Image as well.
 147
 148 Any memory described to the kernel (even that below the start of the
 149 image) which is not marked as reserved from the kernel (e.g., with a
 150 memreserve region in the device tree) will be considered as available to
 151 the kernel.
 152
 153 Before jumping into the kernel, the following conditions must be met:
 154
 155 - Quiesce all DMA capable devices so that memory does not get
 156   corrupted by bogus network packets or disk data.  This will save
 157   you many hours of debug.
 158
 159 - Primary CPU general-purpose register settings:
 160
 161     - x0 = physical address of device tree blob (dtb) in system RAM.
 162     - x1 = 0 (reserved for future use)
 163     - x2 = 0 (reserved for future use)
 164     - x3 = 0 (reserved for future use)
 165
 166 - CPU mode
 167
 168   All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
 169   IRQ and FIQ).
 170   The CPU must be in either EL2 (RECOMMENDED in order to have access to
 171   the virtualisation extensions) or non-secure EL1.
 172
 173 - Caches, MMUs
 174
 175   The MMU must be off.
 176   Instruction cache may be on or off.
 177   The address range corresponding to the loaded kernel image must be
 178   cleaned to the PoC. In the presence of a system cache or other
 179   coherent masters with caches enabled, this will typically require
 180   cache maintenance by VA rather than set/way operations.
 181   System caches which respect the architected cache maintenance by VA
 182   operations must be configured and may be enabled.
 183   System caches which do not respect architected cache maintenance by VA
 184   operations (not recommended) must be configured and disabled.
 185
 186 - Architected timers
 187
 188   CNTFRQ must be programmed with the timer frequency and CNTVOFF must
 189   be programmed with a consistent value on all CPUs.  If entering the
 190   kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
 191   available.
 192
 193 - Coherency
 194
 195   All CPUs to be booted by the kernel must be part of the same coherency
 196   domain on entry to the kernel.  This may require IMPLEMENTATION DEFINED
 197   initialisation to enable the receiving of maintenance operations on
 198   each CPU.
 199
 200 - System registers
 201
 202   All writable architected system registers at the exception level where
 203   the kernel image will be entered must be initialised by software at a
 204   higher exception level to prevent execution in an UNKNOWN state.
 205
 206   - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
 207     executing on.
 208   - The value of SCR_EL3.FIQ must be the same as the one present at boot
 209     time whenever the kernel is executing.
 210
 211   For systems with a GICv3 interrupt controller to be used in v3 mode:
 212   - If EL3 is present:
 213
 214       - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
 215       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
 216
 217   - If the kernel is entered at EL1:
 218
 219       - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
 220       - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
 221
 222   - The DT or ACPI tables must describe a GICv3 interrupt controller.
 223
 224   For systems with a GICv3 interrupt controller to be used in
 225   compatibility (v2) mode:
 226
 227   - If EL3 is present:
 228
 229       ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
 230
 231   - If the kernel is entered at EL1:
 232
 233       ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
 234
 235   - The DT or ACPI tables must describe a GICv2 interrupt controller.
 236
 237   For CPUs with pointer authentication functionality:
 238   - If EL3 is present:
 239
 240     - SCR_EL3.APK (bit 16) must be initialised to 0b1
 241     - SCR_EL3.API (bit 17) must be initialised to 0b1
 242
 243   - If the kernel is entered at EL1:
 244
 245     - HCR_EL2.APK (bit 40) must be initialised to 0b1
 246     - HCR_EL2.API (bit 41) must be initialised to 0b1
 247
 248 The requirements described above for CPU mode, caches, MMUs, architected
 249 timers, coherency and system registers apply to all CPUs.  All CPUs must
 250 enter the kernel in the same exception level.
 251
 252 The boot loader is expected to enter the kernel on each CPU in the
 253 following manner:
 254
 255 - The primary CPU must jump directly to the first instruction of the
 256   kernel image.  The device tree blob passed by this CPU must contain
 257   an 'enable-method' property for each cpu node.  The supported
 258   enable-methods are described below.
 259
 260   It is expected that the bootloader will generate these device tree
 261   properties and insert them into the blob prior to kernel entry.
 262
 263 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
 264   property in their cpu node.  This property identifies a
 265   naturally-aligned 64-bit zero-initalised memory location.
 266
 267   These CPUs should spin outside of the kernel in a reserved area of
 268   memory (communicated to the kernel by a /memreserve/ region in the
 269   device tree) polling their cpu-release-addr location, which must be
 270   contained in the reserved region.  A wfe instruction may be inserted
 271   to reduce the overhead of the busy-loop and a sev will be issued by
 272   the primary CPU.  When a read of the location pointed to by the
 273   cpu-release-addr returns a non-zero value, the CPU must jump to this
 274   value.  The value will be written as a single 64-bit little-endian
 275   value, so CPUs must convert the read value to their native endianness
 276   before jumping to it.
 277
 278 - CPUs with a "psci" enable method should remain outside of
 279   the kernel (i.e. outside of the regions of memory described to the
 280   kernel in the memory node, or in a reserved area of memory described
 281   to the kernel by a /memreserve/ region in the device tree).  The
 282   kernel will issue CPU_ON calls as described in ARM document number ARM
 283   DEN 0022A ("Power State Coordination Interface System Software on ARM
 284   processors") to bring CPUs into the kernel.
 285
 286   The device tree should contain a 'psci' node, as described in
 287   Documentation/devicetree/bindings/arm/psci.txt.
 288
 289 - Secondary CPU general-purpose register settings
 290   x0 = 0 (reserved for future use)
 291   x1 = 0 (reserved for future use)
 292   x2 = 0 (reserved for future use)
 293   x3 = 0 (reserved for future use)