5 The device tree allows to describe the layout of CPUs in a system through
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
9 Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:
11 https://www.power.org/documentation/epapr-version-1-1/
13 with updates for 32-bit and 64-bit ARM systems provided in this document.
15 ================================
16 Convention used in this document
17 ================================
19 This document follows the conventions described in the ePAPR v1.1, with
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
23 the reg property contained in bits 7 down to 0
25 =====================================
26 cpus and cpu node bindings definition
27 =====================================
29 The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu
30 nodes to be present and contain the properties described below.
34 Description: Container of cpu nodes
36 The node name must be "cpus".
38 A cpus node must define the following properties:
44 Definition depends on ARM architecture version and
47 # On uniprocessor ARM architectures previous to v7
48 value must be 1, to enable a simple enumeration
49 scheme for processors that do not have a HW CPU
50 identification register.
51 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
52 value must be 1, that corresponds to CPUID/MPIDR
54 # On ARM v8 64-bit systems value should be set to 2,
55 that corresponds to the MPIDR_EL1 register size.
56 If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
57 in the system, #address-cells can be set to 1, since
58 MPIDR_EL1[63:32] bits are not used for CPUs
63 Definition: must be set to 0
67 Description: Describes a CPU in an ARM based system
74 Definition: must be "cpu"
76 Usage and definition depend on ARM architecture version and
79 # On uniprocessor ARM architectures previous to v7
80 this property is required and must be set to 0.
82 # On ARM 11 MPcore based systems this property is
83 required and matches the CPUID[11:0] register bits.
85 Bits [11:0] in the reg cell must be set to
86 bits [11:0] in CPU ID register.
88 All other bits in the reg cell must be set to 0.
90 # On 32-bit ARM v7 or later systems this property is
91 required and matches the CPU MPIDR[23:0] register
94 Bits [23:0] in the reg cell must be set to
97 All other bits in the reg cell must be set to 0.
99 # On ARM v8 64-bit systems this property is required
100 and matches the MPIDR_EL1 register affinity bits.
102 * If cpus node's #address-cells property is set to 2
104 The first reg cell bits [7:0] must be set to
105 bits [39:32] of MPIDR_EL1.
107 The second reg cell bits [23:0] must be set to
108 bits [23:0] of MPIDR_EL1.
110 * If cpus node's #address-cells property is set to 1
112 The reg cell bits [23:0] must be set to bits [23:0]
115 All other bits in the reg cells must be set to 0.
120 Definition: should be one of:
179 "nvidia,tegra132-denver"
183 Value type: <stringlist>
184 Usage and definition depend on ARM architecture version.
185 # On ARM v8 64-bit this property is required and must
189 # On ARM 32-bit systems this property is optional and
191 "allwinner,sun6i-a31"
192 "allwinner,sun8i-a23"
197 "marvell,armada-375-smp"
198 "marvell,armada-380-smp"
199 "marvell,armada-390-smp"
200 "marvell,armada-xp-smp"
201 "mediatek,mt6589-smp"
202 "mediatek,mt81xx-tz-smp"
206 "rockchip,rk3036-smp"
207 "rockchip,rk3066-smp"
211 Usage: required for systems that have an "enable-method"
212 property value of "spin-table".
213 Value type: <prop-encoded-array>
215 # On ARM v8 64-bit systems must be a two cell
216 property identifying a 64-bit zero-initialised
220 Usage: required for systems that have an "enable-method"
221 property value of "qcom,kpss-acc-v1" or
223 Value type: <phandle>
224 Definition: Specifies the SAW[1] node associated with this CPU.
227 Usage: required for systems that have an "enable-method"
228 property value of "qcom,kpss-acc-v1" or
230 Value type: <phandle>
231 Definition: Specifies the ACC[2] node associated with this CPU.
235 Value type: <prop-encoded-array>
237 # List of phandles to idle state nodes supported
241 Usage: optional for systems that have an "enable-method"
242 property value of "rockchip,rk3066-smp"
243 While optional, it is the preferred way to get access to
244 the cpu-core power-domains.
245 Value type: <phandle>
246 Definition: Specifies the syscon node controlling the cpu core
249 - dynamic-power-coefficient
251 Value type: <prop-encoded-array>
252 Definition: A u32 value that represents the running time dynamic
253 power coefficient in units of mW/MHz/uVolt^2. The
254 coefficient can either be calculated from power
255 measurements or derived by analysis.
257 The dynamic power consumption of the CPU is
258 proportional to the square of the Voltage (V) and
259 the clock frequency (f). The coefficient is used to
260 calculate the dynamic power as below -
262 Pdyn = dynamic-power-coefficient * V^2 * f
264 where voltage is in uV, frequency is in MHz.
266 Example 1 (dual-cluster big.LITTLE system 32-bit):
270 #address-cells = <1>;
274 compatible = "arm,cortex-a15";
280 compatible = "arm,cortex-a15";
286 compatible = "arm,cortex-a7";
292 compatible = "arm,cortex-a7";
297 Example 2 (Cortex-A8 uniprocessor 32-bit system):
301 #address-cells = <1>;
305 compatible = "arm,cortex-a8";
310 Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
314 #address-cells = <1>;
318 compatible = "arm,arm926ej-s";
323 Example 4 (ARM Cortex-A57 64-bit system):
327 #address-cells = <2>;
331 compatible = "arm,cortex-a57";
333 enable-method = "spin-table";
334 cpu-release-addr = <0 0x20000000>;
339 compatible = "arm,cortex-a57";
341 enable-method = "spin-table";
342 cpu-release-addr = <0 0x20000000>;
347 compatible = "arm,cortex-a57";
349 enable-method = "spin-table";
350 cpu-release-addr = <0 0x20000000>;
355 compatible = "arm,cortex-a57";
357 enable-method = "spin-table";
358 cpu-release-addr = <0 0x20000000>;
363 compatible = "arm,cortex-a57";
365 enable-method = "spin-table";
366 cpu-release-addr = <0 0x20000000>;
371 compatible = "arm,cortex-a57";
373 enable-method = "spin-table";
374 cpu-release-addr = <0 0x20000000>;
379 compatible = "arm,cortex-a57";
381 enable-method = "spin-table";
382 cpu-release-addr = <0 0x20000000>;
387 compatible = "arm,cortex-a57";
389 enable-method = "spin-table";
390 cpu-release-addr = <0 0x20000000>;
395 compatible = "arm,cortex-a57";
397 enable-method = "spin-table";
398 cpu-release-addr = <0 0x20000000>;
403 compatible = "arm,cortex-a57";
405 enable-method = "spin-table";
406 cpu-release-addr = <0 0x20000000>;
411 compatible = "arm,cortex-a57";
413 enable-method = "spin-table";
414 cpu-release-addr = <0 0x20000000>;
419 compatible = "arm,cortex-a57";
421 enable-method = "spin-table";
422 cpu-release-addr = <0 0x20000000>;
427 compatible = "arm,cortex-a57";
429 enable-method = "spin-table";
430 cpu-release-addr = <0 0x20000000>;
435 compatible = "arm,cortex-a57";
437 enable-method = "spin-table";
438 cpu-release-addr = <0 0x20000000>;
443 compatible = "arm,cortex-a57";
445 enable-method = "spin-table";
446 cpu-release-addr = <0 0x20000000>;
451 compatible = "arm,cortex-a57";
453 enable-method = "spin-table";
454 cpu-release-addr = <0 0x20000000>;
459 [1] arm/msm/qcom,saw2.txt
460 [2] arm/msm/qcom,kpss-acc.txt
461 [3] ARM Linux kernel documentation - idle states bindings
462 Documentation/devicetree/bindings/arm/idle-states.txt