Documentation/devicetree/bindings/arm/cpus.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/arm/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: ARM CPUs bindings
   8
   9 maintainers:
  10   - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  11
  12 description: |+
  13   The device tree allows to describe the layout of CPUs in a system through
  14   the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
  15   defining properties for every cpu.
  16
  17   Bindings for CPU nodes follow the Devicetree Specification, available from:
  18
  19   https://www.devicetree.org/specifications/
  20
  21   with updates for 32-bit and 64-bit ARM systems provided in this document.
  22
  23   ================================
  24   Convention used in this document
  25   ================================
  26
  27   This document follows the conventions described in the Devicetree
  28   Specification, with the addition:
  29
  30   - square brackets define bitfields, eg reg[7:0] value of the bitfield in
  31     the reg property contained in bits 7 down to 0
  32
  33   =====================================
  34   cpus and cpu node bindings definition
  35   =====================================
  36
  37   The ARM architecture, in accordance with the Devicetree Specification,
  38   requires the cpus and cpu nodes to be present and contain the properties
  39   described below.
  40
  41 properties:
  42   reg:
  43     maxItems: 1
  44     description: |
  45       Usage and definition depend on ARM architecture version and
  46       configuration:
  47
  48       On uniprocessor ARM architectures previous to v7
  49       this property is required and must be set to 0.
  50
  51       On ARM 11 MPcore based systems this property is
  52         required and matches the CPUID[11:0] register bits.
  53
  54         Bits [11:0] in the reg cell must be set to
  55         bits [11:0] in CPU ID register.
  56
  57         All other bits in the reg cell must be set to 0.
  58
  59       On 32-bit ARM v7 or later systems this property is
  60         required and matches the CPU MPIDR[23:0] register
  61         bits.
  62
  63         Bits [23:0] in the reg cell must be set to
  64         bits [23:0] in MPIDR.
  65
  66         All other bits in the reg cell must be set to 0.
  67
  68       On ARM v8 64-bit systems this property is required
  69         and matches the MPIDR_EL1 register affinity bits.
  70
  71         * If cpus node's #address-cells property is set to 2
  72
  73           The first reg cell bits [7:0] must be set to
  74           bits [39:32] of MPIDR_EL1.
  75
  76           The second reg cell bits [23:0] must be set to
  77           bits [23:0] of MPIDR_EL1.
  78
  79         * If cpus node's #address-cells property is set to 1
  80
  81           The reg cell bits [23:0] must be set to bits [23:0]
  82           of MPIDR_EL1.
  83
  84       All other bits in the reg cells must be set to 0.
  85
  86   compatible:
  87     enum:
  88       - apple,icestorm
  89       - apple,firestorm
  90       - arm,arm710t
  91       - arm,arm720t
  92       - arm,arm740t
  93       - arm,arm7ej-s
  94       - arm,arm7tdmi
  95       - arm,arm7tdmi-s
  96       - arm,arm9es
  97       - arm,arm9ej-s
  98       - arm,arm920t
  99       - arm,arm922t
 100       - arm,arm925
 101       - arm,arm926e-s
 102       - arm,arm926ej-s
 103       - arm,arm940t
 104       - arm,arm946e-s
 105       - arm,arm966e-s
 106       - arm,arm968e-s
 107       - arm,arm9tdmi
 108       - arm,arm1020e
 109       - arm,arm1020t
 110       - arm,arm1022e
 111       - arm,arm1026ej-s
 112       - arm,arm1136j-s
 113       - arm,arm1136jf-s
 114       - arm,arm1156t2-s
 115       - arm,arm1156t2f-s
 116       - arm,arm1176jzf
 117       - arm,arm1176jz-s
 118       - arm,arm1176jzf-s
 119       - arm,arm11mpcore
 120       - arm,armv8 # Only for s/w models
 121       - arm,cortex-a5
 122       - arm,cortex-a7
 123       - arm,cortex-a8
 124       - arm,cortex-a9
 125       - arm,cortex-a12
 126       - arm,cortex-a15
 127       - arm,cortex-a17
 128       - arm,cortex-a32
 129       - arm,cortex-a34
 130       - arm,cortex-a35
 131       - arm,cortex-a53
 132       - arm,cortex-a55
 133       - arm,cortex-a57
 134       - arm,cortex-a65
 135       - arm,cortex-a72
 136       - arm,cortex-a73
 137       - arm,cortex-a75
 138       - arm,cortex-a76
 139       - arm,cortex-a77
 140       - arm,cortex-m0
 141       - arm,cortex-m0+
 142       - arm,cortex-m1
 143       - arm,cortex-m3
 144       - arm,cortex-m4
 145       - arm,cortex-r4
 146       - arm,cortex-r5
 147       - arm,cortex-r7
 148       - arm,neoverse-e1
 149       - arm,neoverse-n1
 150       - brcm,brahma-b15
 151       - brcm,brahma-b53
 152       - brcm,vulcan
 153       - cavium,thunder
 154       - cavium,thunder2
 155       - faraday,fa526
 156       - intel,sa110
 157       - intel,sa1100
 158       - marvell,feroceon
 159       - marvell,mohawk
 160       - marvell,pj4a
 161       - marvell,pj4b
 162       - marvell,sheeva-v5
 163       - marvell,sheeva-v7
 164       - nvidia,tegra132-denver
 165       - nvidia,tegra186-denver
 166       - nvidia,tegra194-carmel
 167       - qcom,krait
 168       - qcom,kryo
 169       - qcom,kryo260
 170       - qcom,kryo280
 171       - qcom,kryo385
 172       - qcom,kryo468
 173       - qcom,kryo485
 174       - qcom,kryo685
 175       - qcom,scorpion
 176
 177   enable-method:
 178     $ref: '/schemas/types.yaml#/definitions/string'
 179     oneOf:
 180       # On ARM v8 64-bit this property is required
 181       - enum:
 182           - psci
 183           - spin-table
 184       # On ARM 32-bit systems this property is optional
 185       - enum:
 186           - actions,s500-smp
 187           - allwinner,sun6i-a31
 188           - allwinner,sun8i-a23
 189           - allwinner,sun9i-a80-smp
 190           - allwinner,sun8i-a83t-smp
 191           - amlogic,meson8-smp
 192           - amlogic,meson8b-smp
 193           - arm,realview-smp
 194           - aspeed,ast2600-smp
 195           - brcm,bcm11351-cpu-method
 196           - brcm,bcm23550
 197           - brcm,bcm2836-smp
 198           - brcm,bcm63138
 199           - brcm,bcm-nsp-smp
 200           - brcm,brahma-b15
 201           - marvell,armada-375-smp
 202           - marvell,armada-380-smp
 203           - marvell,armada-390-smp
 204           - marvell,armada-xp-smp
 205           - marvell,98dx3236-smp
 206           - marvell,mmp3-smp
 207           - mediatek,mt6589-smp
 208           - mediatek,mt81xx-tz-smp
 209           - qcom,gcc-msm8660
 210           - qcom,kpss-acc-v1
 211           - qcom,kpss-acc-v2
 212           - renesas,apmu
 213           - renesas,r9a06g032-smp
 214           - rockchip,rk3036-smp
 215           - rockchip,rk3066-smp
 216           - socionext,milbeaut-m10v-smp
 217           - ste,dbx500-smp
 218           - ti,am3352
 219           - ti,am4372
 220
 221   cpu-release-addr:
 222     $ref: '/schemas/types.yaml#/definitions/uint64'
 223
 224     description:
 225       Required for systems that have an "enable-method"
 226         property value of "spin-table".
 227       On ARM v8 64-bit systems must be a two cell
 228         property identifying a 64-bit zero-initialised
 229         memory location.
 230
 231   cpu-idle-states:
 232     $ref: '/schemas/types.yaml#/definitions/phandle-array'
 233     description: |
 234       List of phandles to idle state nodes supported
 235       by this cpu (see ./idle-states.yaml).
 236
 237   capacity-dmips-mhz:
 238     description:
 239       u32 value representing CPU capacity (see ./cpu-capacity.txt) in
 240       DMIPS/MHz, relative to highest capacity-dmips-mhz
 241       in the system.
 242
 243   dynamic-power-coefficient:
 244     $ref: '/schemas/types.yaml#/definitions/uint32'
 245     description:
 246       A u32 value that represents the running time dynamic
 247       power coefficient in units of uW/MHz/V^2. The
 248       coefficient can either be calculated from power
 249       measurements or derived by analysis.
 250
 251       The dynamic power consumption of the CPU  is
 252       proportional to the square of the Voltage (V) and
 253       the clock frequency (f). The coefficient is used to
 254       calculate the dynamic power as below -
 255
 256       Pdyn = dynamic-power-coefficient * V^2 * f
 257
 258       where voltage is in V, frequency is in MHz.
 259
 260   power-domains:
 261     description:
 262       List of phandles and PM domain specifiers, as defined by bindings of the
 263       PM domain provider (see also ../power_domain.txt).
 264
 265   power-domain-names:
 266     description:
 267       A list of power domain name strings sorted in the same order as the
 268       power-domains property.
 269
 270       For PSCI based platforms, the name corresponding to the index of the PSCI
 271       PM domain provider, must be "psci".
 272
 273   qcom,saw:
 274     $ref: '/schemas/types.yaml#/definitions/phandle'
 275     description: |
 276       Specifies the SAW* node associated with this CPU.
 277
 278       Required for systems that have an "enable-method" property
 279       value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
 280
 281       * arm/msm/qcom,saw2.txt
 282
 283   qcom,acc:
 284     $ref: '/schemas/types.yaml#/definitions/phandle'
 285     description: |
 286       Specifies the ACC* node associated with this CPU.
 287
 288       Required for systems that have an "enable-method" property
 289       value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
 290
 291       * arm/msm/qcom,kpss-acc.txt
 292
 293   rockchip,pmu:
 294     $ref: '/schemas/types.yaml#/definitions/phandle'
 295     description: |
 296       Specifies the syscon node controlling the cpu core power domains.
 297
 298       Optional for systems that have an "enable-method"
 299       property value of "rockchip,rk3066-smp"
 300       While optional, it is the preferred way to get access to
 301       the cpu-core power-domains.
 302
 303   secondary-boot-reg:
 304     $ref: '/schemas/types.yaml#/definitions/uint32'
 305     description: |
 306       Required for systems that have an "enable-method" property value of
 307       "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
 308
 309       This includes the following SoCs: |
 310       BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
 311       BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
 312
 313       The secondary-boot-reg property is a u32 value that specifies the
 314       physical address of the register used to request the ROM holding pen
 315       code release a secondary CPU. The value written to the register is
 316       formed by encoding the target CPU id into the low bits of the
 317       physical start address it should jump to.
 318
 319 if:
 320   # If the enable-method property contains one of those values
 321   properties:
 322     enable-method:
 323       contains:
 324         enum:
 325           - brcm,bcm11351-cpu-method
 326           - brcm,bcm23550
 327           - brcm,bcm-nsp-smp
 328   # and if enable-method is present
 329   required:
 330     - enable-method
 331
 332 then:
 333   required:
 334     - secondary-boot-reg
 335
 336 required:
 337   - device_type
 338   - reg
 339   - compatible
 340
 341 dependencies:
 342   rockchip,pmu: [enable-method]
 343
 344 additionalProperties: true
 345
 346 examples:
 347   - |
 348     cpus {
 349       #size-cells = <0>;
 350       #address-cells = <1>;
 351
 352       cpu@0 {
 353         device_type = "cpu";
 354         compatible = "arm,cortex-a15";
 355         reg = <0x0>;
 356       };
 357
 358       cpu@1 {
 359         device_type = "cpu";
 360         compatible = "arm,cortex-a15";
 361         reg = <0x1>;
 362       };
 363
 364       cpu@100 {
 365         device_type = "cpu";
 366         compatible = "arm,cortex-a7";
 367         reg = <0x100>;
 368       };
 369
 370       cpu@101 {
 371         device_type = "cpu";
 372         compatible = "arm,cortex-a7";
 373         reg = <0x101>;
 374       };
 375     };
 376
 377   - |
 378     // Example 2 (Cortex-A8 uniprocessor 32-bit system):
 379     cpus {
 380       #size-cells = <0>;
 381       #address-cells = <1>;
 382
 383       cpu@0 {
 384         device_type = "cpu";
 385         compatible = "arm,cortex-a8";
 386         reg = <0x0>;
 387       };
 388     };
 389
 390   - |
 391     // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
 392     cpus {
 393       #size-cells = <0>;
 394       #address-cells = <1>;
 395
 396       cpu@0 {
 397         device_type = "cpu";
 398         compatible = "arm,arm926ej-s";
 399         reg = <0x0>;
 400       };
 401     };
 402
 403   - |
 404     //  Example 4 (ARM Cortex-A57 64-bit system):
 405     cpus {
 406       #size-cells = <0>;
 407       #address-cells = <2>;
 408
 409       cpu@0 {
 410         device_type = "cpu";
 411         compatible = "arm,cortex-a57";
 412         reg = <0x0 0x0>;
 413         enable-method = "spin-table";
 414         cpu-release-addr = <0 0x20000000>;
 415       };
 416
 417       cpu@1 {
 418         device_type = "cpu";
 419         compatible = "arm,cortex-a57";
 420         reg = <0x0 0x1>;
 421         enable-method = "spin-table";
 422         cpu-release-addr = <0 0x20000000>;
 423       };
 424
 425       cpu@100 {
 426         device_type = "cpu";
 427         compatible = "arm,cortex-a57";
 428         reg = <0x0 0x100>;
 429         enable-method = "spin-table";
 430         cpu-release-addr = <0 0x20000000>;
 431       };
 432
 433       cpu@101 {
 434         device_type = "cpu";
 435         compatible = "arm,cortex-a57";
 436         reg = <0x0 0x101>;
 437         enable-method = "spin-table";
 438         cpu-release-addr = <0 0x20000000>;
 439       };
 440
 441       cpu@10000 {
 442         device_type = "cpu";
 443         compatible = "arm,cortex-a57";
 444         reg = <0x0 0x10000>;
 445         enable-method = "spin-table";
 446         cpu-release-addr = <0 0x20000000>;
 447       };
 448
 449       cpu@10001 {
 450         device_type = "cpu";
 451         compatible = "arm,cortex-a57";
 452         reg = <0x0 0x10001>;
 453         enable-method = "spin-table";
 454         cpu-release-addr = <0 0x20000000>;
 455       };
 456
 457       cpu@10100 {
 458         device_type = "cpu";
 459         compatible = "arm,cortex-a57";
 460         reg = <0x0 0x10100>;
 461         enable-method = "spin-table";
 462         cpu-release-addr = <0 0x20000000>;
 463       };
 464
 465       cpu@10101 {
 466         device_type = "cpu";
 467         compatible = "arm,cortex-a57";
 468         reg = <0x0 0x10101>;
 469         enable-method = "spin-table";
 470         cpu-release-addr = <0 0x20000000>;
 471       };
 472
 473       cpu@100000000 {
 474         device_type = "cpu";
 475         compatible = "arm,cortex-a57";
 476         reg = <0x1 0x0>;
 477         enable-method = "spin-table";
 478         cpu-release-addr = <0 0x20000000>;
 479       };
 480
 481       cpu@100000001 {
 482         device_type = "cpu";
 483         compatible = "arm,cortex-a57";
 484         reg = <0x1 0x1>;
 485         enable-method = "spin-table";
 486         cpu-release-addr = <0 0x20000000>;
 487       };
 488
 489       cpu@100000100 {
 490         device_type = "cpu";
 491         compatible = "arm,cortex-a57";
 492         reg = <0x1 0x100>;
 493         enable-method = "spin-table";
 494         cpu-release-addr = <0 0x20000000>;
 495       };
 496
 497       cpu@100000101 {
 498         device_type = "cpu";
 499         compatible = "arm,cortex-a57";
 500         reg = <0x1 0x101>;
 501         enable-method = "spin-table";
 502         cpu-release-addr = <0 0x20000000>;
 503       };
 504
 505       cpu@100010000 {
 506         device_type = "cpu";
 507         compatible = "arm,cortex-a57";
 508         reg = <0x1 0x10000>;
 509         enable-method = "spin-table";
 510         cpu-release-addr = <0 0x20000000>;
 511       };
 512
 513       cpu@100010001 {
 514         device_type = "cpu";
 515         compatible = "arm,cortex-a57";
 516         reg = <0x1 0x10001>;
 517         enable-method = "spin-table";
 518         cpu-release-addr = <0 0x20000000>;
 519       };
 520
 521       cpu@100010100 {
 522         device_type = "cpu";
 523         compatible = "arm,cortex-a57";
 524         reg = <0x1 0x10100>;
 525         enable-method = "spin-table";
 526         cpu-release-addr = <0 0x20000000>;
 527       };
 528
 529       cpu@100010101 {
 530         device_type = "cpu";
 531         compatible = "arm,cortex-a57";
 532         reg = <0x1 0x10101>;
 533         enable-method = "spin-table";
 534         cpu-release-addr = <0 0x20000000>;
 535       };
 536     };
 537 ...