Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

   1 NXP i.MX System Controller Firmware (SCFW)
   2 --------------------------------------------------------------------
   3
   4 The System Controller Firmware (SCFW) is a low-level system function
   5 which runs on a dedicated Cortex-M core to provide power, clock, and
   6 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
   7 (QM, QP), and i.MX8QX (QXP, DX).
   8
   9 The AP communicates with the SC using a multi-ported MU module found
  10 in the LSIO subsystem. The current definition of this MU module provides
  11 5 remote AP connections to the SC to support up to 5 execution environments
  12 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
  13 with the LSIO DSC IP bus. The SC firmware will communicate with this MU
  14 using the MSI bus.
  15
  16 System Controller Device Node:
  17 ============================================================
  18
  19 The scu node with the following properties shall be under the /firmware/ node.
  20
  21 Required properties:
  22 -------------------
  23 - compatible:   should be "fsl,imx-scu".
  24 - mbox-names:   should include "tx0", "tx1", "tx2", "tx3",
  25                                "rx0", "rx1", "rx2", "rx3".
  26 - mboxes:       List of phandle of 4 MU channels for tx and 4 MU channels
  27                 for rx. All 8 MU channels must be in the same MU instance.
  28                 Cross instances are not allowed. The MU instance can only
  29                 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
  30                 to make sure use the one which is not conflict with other
  31                 execution environments. e.g. ATF.
  32                 Note:
  33                 Channel 0 must be "tx0" or "rx0".
  34                 Channel 1 must be "tx1" or "rx1".
  35                 Channel 2 must be "tx2" or "rx2".
  36                 Channel 3 must be "tx3" or "rx3".
  37                 e.g.
  38                 mboxes = <&lsio_mu1 0 0
  39                           &lsio_mu1 0 1
  40                           &lsio_mu1 0 2
  41                           &lsio_mu1 0 3
  42                           &lsio_mu1 1 0
  43                           &lsio_mu1 1 1
  44                           &lsio_mu1 1 2
  45                           &lsio_mu1 1 3>;
  46                 See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
  47                 for detailed mailbox binding.
  48
  49 i.MX SCU Client Device Node:
  50 ============================================================
  51
  52 Client nodes are maintained as children of the relevant IMX-SCU device node.
  53
  54 Power domain bindings based on SCU Message Protocol
  55 ------------------------------------------------------------
  56
  57 This binding for the SCU power domain providers uses the generic power
  58 domain binding[2].
  59
  60 Required properties:
  61 - compatible:           Should be "fsl,scu-pd".
  62 - #address-cells:       Should be 1.
  63 - #size-cells:          Should be 0.
  64
  65 Required properties for power domain sub nodes:
  66 - #power-domain-cells:  Must be 0.
  67
  68 Optional Properties:
  69 - reg:                  Resource ID of this power domain.
  70                         No exist means uncontrollable by user.
  71                         See detailed Resource ID list from:
  72                         include/dt-bindings/power/imx-rsrc.h
  73 - power-domains:        phandle pointing to the parent power domain.
  74
  75 Clock bindings based on SCU Message Protocol
  76 ------------------------------------------------------------
  77
  78 This binding uses the common clock binding[1].
  79
  80 Required properties:
  81 - compatible:           Should be "fsl,imx8qxp-clock".
  82 - #clock-cells:         Should be 1. Contains the Clock ID value.
  83 - clocks:               List of clock specifiers, must contain an entry for
  84                         each required entry in clock-names
  85 - clock-names:          Should include entries "xtal_32KHz", "xtal_24MHz"
  86
  87 The clock consumer should specify the desired clock by having the clock
  88 ID in its "clocks" phandle cell.
  89
  90 See the full list of clock IDs from:
  91 include/dt-bindings/clock/imx8qxp-clock.h
  92
  93 Pinctrl bindings based on SCU Message Protocol
  94 ------------------------------------------------------------
  95
  96 This binding uses the i.MX common pinctrl binding[3].
  97
  98 Required properties:
  99 - compatible:           Should be "fsl,imx8qxp-iomuxc".
 100
 101 Required properties for Pinctrl sub nodes:
 102 - fsl,pins:             Each entry consists of 3 integers which represents
 103                         the mux and config setting for one pin. The first 2
 104                         integers <pin_id mux_mode> are specified using a
 105                         PIN_FUNC_ID macro, which can be found in
 106                         <dt-bindings/pinctrl/pads-imx8qxp.h>.
 107                         The last integer CONFIG is the pad setting value like
 108                         pull-up on this pin.
 109
 110                         Please refer to i.MX8QXP Reference Manual for detailed
 111                         CONFIG settings.
 112
 113 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 114 [2] Documentation/devicetree/bindings/power/power_domain.txt
 115 [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
 116
 117 Example (imx8qxp):
 118 -------------
 119 lsio_mu1: mailbox@5d1c0000 {
 120         ...
 121         #mbox-cells = <2>;
 122 };
 123
 124 firmware {
 125         scu {
 126                 compatible = "fsl,imx-scu";
 127                 mbox-names = "tx0", "tx1", "tx2", "tx3",
 128                              "rx0", "rx1", "rx2", "rx3";
 129                 mboxes = <&lsio_mu1 0 0
 130                           &lsio_mu1 0 1
 131                           &lsio_mu1 0 2
 132                           &lsio_mu1 0 3
 133                           &lsio_mu1 1 0
 134                           &lsio_mu1 1 1
 135                           &lsio_mu1 1 2
 136                           &lsio_mu1 1 3>;
 137
 138                 clk: clk {
 139                         compatible = "fsl,imx8qxp-clk";
 140                         #clock-cells = <1>;
 141                 };
 142
 143                 iomuxc {
 144                         compatible = "fsl,imx8qxp-iomuxc";
 145
 146                         pinctrl_lpuart0: lpuart0grp {
 147                                 fsl,pins = <
 148                                         SC_P_UART0_RX_ADMA_UART0_RX     0x06000020
 149                                         SC_P_UART0_TX_ADMA_UART0_TX     0x06000020
 150                                 >;
 151                         };
 152                         ...
 153                 };
 154
 155                 imx8qx-pm {
 156                         compatible = "fsl,scu-pd";
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159
 160                         pd_dma: dma-power-domain {
 161                                 #power-domain-cells = <0>;
 162
 163                                 pd_dma_lpuart0: dma-lpuart0@57 {
 164                                         reg = <SC_R_UART_0>;
 165                                         #power-domain-cells = <0>;
 166                                         power-domains = <&pd_dma>;
 167                                 };
 168                                 ...
 169                         };
 170                         ...
 171                 };
 172         };
 173 };
 174
 175 serial@5a060000 {
 176         ...
 177         pinctrl-names = "default";
 178         pinctrl-0 = <&pinctrl_lpuart0>;
 179         clocks = <&clk IMX8QXP_UART0_CLK>,
 180                  <&clk IMX8QXP_UART0_IPG_CLK>;
 181         clock-names = "per", "ipg";
 182         power-domains = <&pd_dma_lpuart0>;
 183 };