Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

   1 NXP i.MX System Controller Firmware (SCFW)
   2 --------------------------------------------------------------------
   3
   4 The System Controller Firmware (SCFW) is a low-level system function
   5 which runs on a dedicated Cortex-M core to provide power, clock, and
   6 resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
   7 (QM, QP), and i.MX8QX (QXP, DX).
   8
   9 The AP communicates with the SC using a multi-ported MU module found
  10 in the LSIO subsystem. The current definition of this MU module provides
  11 5 remote AP connections to the SC to support up to 5 execution environments
  12 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
  13 with the LSIO DSC IP bus. The SC firmware will communicate with this MU
  14 using the MSI bus.
  15
  16 System Controller Device Node:
  17 ============================================================
  18
  19 The scu node with the following properties shall be under the /firmware/ node.
  20
  21 Required properties:
  22 -------------------
  23 - compatible:   should be "fsl,imx-scu".
  24 - mbox-names:   should include "tx0", "tx1", "tx2", "tx3",
  25                                "rx0", "rx1", "rx2", "rx3".
  26 - mboxes:       List of phandle of 4 MU channels for tx and 4 MU channels
  27                 for rx. All 8 MU channels must be in the same MU instance.
  28                 Cross instances are not allowed. The MU instance can only
  29                 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
  30                 to make sure use the one which is not conflict with other
  31                 execution environments. e.g. ATF.
  32                 Note:
  33                 Channel 0 must be "tx0" or "rx0".
  34                 Channel 1 must be "tx1" or "rx1".
  35                 Channel 2 must be "tx2" or "rx2".
  36                 Channel 3 must be "tx3" or "rx3".
  37                 e.g.
  38                 mboxes = <&lsio_mu1 0 0
  39                           &lsio_mu1 0 1
  40                           &lsio_mu1 0 2
  41                           &lsio_mu1 0 3
  42                           &lsio_mu1 1 0
  43                           &lsio_mu1 1 1
  44                           &lsio_mu1 1 2
  45                           &lsio_mu1 1 3>;
  46                 See Documentation/devicetree/bindings/mailbox/fsl,mu.txt
  47                 for detailed mailbox binding.
  48
  49 i.MX SCU Client Device Node:
  50 ============================================================
  51
  52 Client nodes are maintained as children of the relevant IMX-SCU device node.
  53
  54 Power domain bindings based on SCU Message Protocol
  55 ------------------------------------------------------------
  56
  57 This binding for the SCU power domain providers uses the generic power
  58 domain binding[2].
  59
  60 Required properties:
  61 - compatible:           Should be "fsl,imx8qxp-scu-pd".
  62 - #power-domain-cells:  Must be 1. Contains the Resource ID used by
  63                         SCU commands.
  64                         See detailed Resource ID list from:
  65                         include/dt-bindings/firmware/imx/rsrc.h
  66
  67 Clock bindings based on SCU Message Protocol
  68 ------------------------------------------------------------
  69
  70 This binding uses the common clock binding[1].
  71
  72 Required properties:
  73 - compatible:           Should be "fsl,imx8qxp-clock".
  74 - #clock-cells:         Should be 1. Contains the Clock ID value.
  75 - clocks:               List of clock specifiers, must contain an entry for
  76                         each required entry in clock-names
  77 - clock-names:          Should include entries "xtal_32KHz", "xtal_24MHz"
  78
  79 The clock consumer should specify the desired clock by having the clock
  80 ID in its "clocks" phandle cell.
  81
  82 See the full list of clock IDs from:
  83 include/dt-bindings/clock/imx8qxp-clock.h
  84
  85 Pinctrl bindings based on SCU Message Protocol
  86 ------------------------------------------------------------
  87
  88 This binding uses the i.MX common pinctrl binding[3].
  89
  90 Required properties:
  91 - compatible:           Should be "fsl,imx8qxp-iomuxc".
  92
  93 Required properties for Pinctrl sub nodes:
  94 - fsl,pins:             Each entry consists of 3 integers which represents
  95                         the mux and config setting for one pin. The first 2
  96                         integers <pin_id mux_mode> are specified using a
  97                         PIN_FUNC_ID macro, which can be found in
  98                         <dt-bindings/pinctrl/pads-imx8qxp.h>.
  99                         The last integer CONFIG is the pad setting value like
 100                         pull-up on this pin.
 101
 102                         Please refer to i.MX8QXP Reference Manual for detailed
 103                         CONFIG settings.
 104
 105 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 106 [2] Documentation/devicetree/bindings/power/power_domain.txt
 107 [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
 108
 109 Example (imx8qxp):
 110 -------------
 111 lsio_mu1: mailbox@5d1c0000 {
 112         ...
 113         #mbox-cells = <2>;
 114 };
 115
 116 firmware {
 117         scu {
 118                 compatible = "fsl,imx-scu";
 119                 mbox-names = "tx0", "tx1", "tx2", "tx3",
 120                              "rx0", "rx1", "rx2", "rx3";
 121                 mboxes = <&lsio_mu1 0 0
 122                           &lsio_mu1 0 1
 123                           &lsio_mu1 0 2
 124                           &lsio_mu1 0 3
 125                           &lsio_mu1 1 0
 126                           &lsio_mu1 1 1
 127                           &lsio_mu1 1 2
 128                           &lsio_mu1 1 3>;
 129
 130                 clk: clk {
 131                         compatible = "fsl,imx8qxp-clk";
 132                         #clock-cells = <1>;
 133                 };
 134
 135                 iomuxc {
 136                         compatible = "fsl,imx8qxp-iomuxc";
 137
 138                         pinctrl_lpuart0: lpuart0grp {
 139                                 fsl,pins = <
 140                                         SC_P_UART0_RX_ADMA_UART0_RX     0x06000020
 141                                         SC_P_UART0_TX_ADMA_UART0_TX     0x06000020
 142                                 >;
 143                         };
 144                         ...
 145                 };
 146
 147                 pd: imx8qx-pd {
 148                         compatible = "fsl,imx8qxp-scu-pd";
 149                         #power-domain-cells = <1>;
 150                 };
 151         };
 152 };
 153
 154 serial@5a060000 {
 155         ...
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_lpuart0>;
 158         clocks = <&clk IMX8QXP_UART0_CLK>,
 159                  <&clk IMX8QXP_UART0_IPG_CLK>;
 160         clock-names = "per", "ipg";
 161         power-domains = <&pd IMX_SC_R_UART_0>;
 162 };