Documentation/devicetree/bindings/arm/gic.txt

   1 * ARM Generic Interrupt Controller
   2
   3 ARM SMP cores are often associated with a GIC, providing per processor
   4 interrupts (PPI), shared processor interrupts (SPI) and software
   5 generated interrupts (SGI).
   6
   7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
   8 Secondary GICs are cascaded into the upward interrupt controller and do not
   9 have PPIs or SGIs.
  10
  11 Main node required properties:
  12
  13 - compatible : should be one of:
  14         "arm,gic-400"
  15         "arm,cortex-a15-gic"
  16         "arm,cortex-a9-gic"
  17         "arm,cortex-a7-gic"
  18         "arm,arm11mp-gic"
  19         "brcm,brahma-b15-gic"
  20         "arm,arm1176jzf-devchip-gic"
  21 - interrupt-controller : Identifies the node as an interrupt controller
  22 - #interrupt-cells : Specifies the number of cells needed to encode an
  23   interrupt source.  The type shall be a <u32> and the value shall be 3.
  24
  25   The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
  26   interrupts.
  27
  28   The 2nd cell contains the interrupt number for the interrupt type.
  29   SPI interrupts are in the range [0-987].  PPI interrupts are in the
  30   range [0-15].
  31
  32   The 3rd cell is the flags, encoded as follows:
  33         bits[3:0] trigger type and level flags.
  34                 1 = low-to-high edge triggered
  35                 2 = high-to-low edge triggered (invalid for SPIs)
  36                 4 = active high level-sensitive
  37                 8 = active low level-sensitive (invalid for SPIs).
  38         bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
  39         the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
  40         the interrupt is wired to that CPU.  Only valid for PPI interrupts.
  41         Also note that the configurability of PPI interrupts is IMPLEMENTATION
  42         DEFINED and as such not guaranteed to be present (most SoC available
  43         in 2014 seem to ignore the setting of this flag and use the hardware
  44         default value).
  45
  46 - reg : Specifies base physical address(s) and size of the GIC registers. The
  47   first region is the GIC distributor register base and size. The 2nd region is
  48   the GIC cpu interface register base and size.
  49
  50 Optional
  51 - interrupts    : Interrupt source of the parent interrupt controller on
  52   secondary GICs, or VGIC maintenance interrupt on primary GIC (see
  53   below).
  54
  55 - cpu-offset    : per-cpu offset within the distributor and cpu interface
  56   regions, used when the GIC doesn't have banked registers. The offset is
  57   cpu-offset * cpu-nr.
  58
  59 Example:
  60
  61         intc: interrupt-controller@fff11000 {
  62                 compatible = "arm,cortex-a9-gic";
  63                 #interrupt-cells = <3>;
  64                 #address-cells = <1>;
  65                 interrupt-controller;
  66                 reg = <0xfff11000 0x1000>,
  67                       <0xfff10100 0x100>;
  68         };
  69
  70
  71 * GIC virtualization extensions (VGIC)
  72
  73 For ARM cores that support the virtualization extensions, additional
  74 properties must be described (they only exist if the GIC is the
  75 primary interrupt controller).
  76
  77 Required properties:
  78
  79 - reg : Additional regions specifying the base physical address and
  80   size of the VGIC registers. The first additional region is the GIC
  81   virtual interface control register base and size. The 2nd additional
  82   region is the GIC virtual cpu interface register base and size.
  83
  84 - interrupts : VGIC maintenance interrupt.
  85
  86 Example:
  87
  88         interrupt-controller@2c001000 {
  89                 compatible = "arm,cortex-a15-gic";
  90                 #interrupt-cells = <3>;
  91                 interrupt-controller;
  92                 reg = <0x2c001000 0x1000>,
  93                       <0x2c002000 0x1000>,
  94                       <0x2c004000 0x2000>,
  95                       <0x2c006000 0x2000>;
  96                 interrupts = <1 9 0xf04>;
  97         };
  98
  99
 100 * GICv2m extension for MSI/MSI-x support (Optional)
 101
 102 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
 103 This is enabled by specifying v2m sub-node(s).
 104
 105 Required properties:
 106
 107 - compatible        : The value here should contain "arm,gic-v2m-frame".
 108
 109 - msi-controller    : Identifies the node as an MSI controller.
 110
 111 - reg               : GICv2m MSI interface register base and size
 112
 113 Optional properties:
 114
 115 - arm,msi-base-spi  : When the MSI_TYPER register contains an incorrect
 116                       value, this property should contain the SPI base of
 117                       the MSI frame, overriding the HW value.
 118
 119 - arm,msi-num-spis  : When the MSI_TYPER register contains an incorrect
 120                       value, this property should contain the number of
 121                       SPIs assigned to the frame, overriding the HW value.
 122
 123 Example:
 124
 125         interrupt-controller@e1101000 {
 126                 compatible = "arm,gic-400";
 127                 #interrupt-cells = <3>;
 128                 #address-cells = <2>;
 129                 #size-cells = <2>;
 130                 interrupt-controller;
 131                 interrupts = <1 8 0xf04>;
 132                 ranges = <0 0 0 0xe1100000 0 0x100000>;
 133                 reg = <0x0 0xe1110000 0 0x01000>,
 134                       <0x0 0xe112f000 0 0x02000>,
 135                       <0x0 0xe1140000 0 0x10000>,
 136                       <0x0 0xe1160000 0 0x10000>;
 137                 v2m0: v2m@0x8000 {
 138                         compatible = "arm,gic-v2m-frame";
 139                         msi-controller;
 140                         reg = <0x0 0x80000 0 0x1000>;
 141                 };
 142
 143                 ....
 144
 145                 v2mN: v2m@0x9000 {
 146                         compatible = "arm,gic-v2m-frame";
 147                         msi-controller;
 148                         reg = <0x0 0x90000 0 0x1000>;
 149                 };
 150         };