1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/ata/sata_highbank.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda AHCI SATA Controller
10 The Calxeda SATA controller mostly conforms to the AHCI interface
11 with some special extensions to add functionality, to map GPIOs for
12 activity LEDs and for mapping the ComboPHYs.
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
30 $ref: /schemas/types.yaml#/definitions/uint32
32 Indicates the number of additional clock cycles to transmit before
33 sending an SGPIO pattern.
36 $ref: /schemas/types.yaml#/definitions/uint32
38 Indicates the number of additional clock cycles to transmit after
39 sending an SGPIO pattern.
42 description: Maps port numbers to offsets within the SGPIO bitstream.
43 $ref: /schemas/types.yaml#/definitions/uint32-array
49 phandle-combophy and lane assignment, which maps each SATA port to a
50 combophy and a lane within that combophy
51 $ref: /schemas/types.yaml#/definitions/phandle-array
57 Contains TX attenuation override codes, one per port.
58 The upper 24 bits of each entry are always 0 and thus ignored.
59 $ref: /schemas/types.yaml#/definitions/uint32-array
66 phandle-gpio bank, bit offset, and default on or off, which indicates
67 that the driver supports SGPIO indicator lights using the indicated
75 additionalProperties: false
80 compatible = "calxeda,hb-ahci";
81 reg = <0xffe08000 0x1000>;
84 calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>,
85 <&combophy0 2>, <&combophy0 3>;
86 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>;
87 calxeda,led-order = <4 0 1 2 3>;
88 calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
89 calxeda,pre-clocks = <10>;
90 calxeda,post-clocks = <0>;