Documentation/devicetree/bindings/clock/exynos4-clock.txt

   1 * Samsung Exynos4 Clock Controller
   2
   3 The Exynos4 clock controller generates and supplies clock to various controllers
   4 within the Exynos4 SoC. The clock binding described here is applicable to all
   5 SoC's in the Exynos4 family.
   6
   7 Required Properties:
   8
   9 - comptible: should be one of the following.
  10   - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
  11   - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
  12
  13 - reg: physical base address of the controller and length of memory mapped
  14   region.
  15
  16 - #clock-cells: should be 1.
  17
  18 The following is the list of clocks generated by the controller. Each clock is
  19 assigned an identifier and client nodes use this identifier to specify the
  20 clock which they consume. Some of the clocks are available only on a particular
  21 Exynos4 SoC and this is specified where applicable.
  22
  23
  24                  [Core Clocks]
  25
  26   Clock               ID      SoC (if specific)
  27   -----------------------------------------------
  28
  29   xxti                1
  30   xusbxti             2
  31   fin_pll             3
  32   fout_apll           4
  33   fout_mpll           5
  34   fout_epll           6
  35   fout_vpll           7
  36   sclk_apll           8
  37   sclk_mpll           9
  38   sclk_epll           10
  39   sclk_vpll           11
  40   arm_clk             12
  41   aclk200             13
  42   aclk100             14
  43   aclk160             15
  44   aclk133             16
  45   mout_mpll_user_t    17      Exynos4x12
  46   mout_mpll_user_c    18      Exynos4x12
  47   mout_core           19
  48   mout_apll           20
  49
  50
  51             [Clock Gate for Special Clocks]
  52
  53   Clock               ID      SoC (if specific)
  54   -----------------------------------------------
  55
  56   sclk_fimc0          128
  57   sclk_fimc1          129
  58   sclk_fimc2          130
  59   sclk_fimc3          131
  60   sclk_cam0           132
  61   sclk_cam1           133
  62   sclk_csis0          134
  63   sclk_csis1          135
  64   sclk_hdmi           136
  65   sclk_mixer          137
  66   sclk_dac            138
  67   sclk_pixel          139
  68   sclk_fimd0          140
  69   sclk_mdnie0         141     Exynos4412
  70   sclk_mdnie_pwm0 12  142     Exynos4412
  71   sclk_mipi0          143
  72   sclk_audio0         144
  73   sclk_mmc0           145
  74   sclk_mmc1           146
  75   sclk_mmc2           147
  76   sclk_mmc3           148
  77   sclk_mmc4           149
  78   sclk_sata           150     Exynos4210
  79   sclk_uart0          151
  80   sclk_uart1          152
  81   sclk_uart2          153
  82   sclk_uart3          154
  83   sclk_uart4          155
  84   sclk_audio1         156
  85   sclk_audio2         157
  86   sclk_spdif          158
  87   sclk_spi0           159
  88   sclk_spi1           160
  89   sclk_spi2           161
  90   sclk_slimbus        162
  91   sclk_fimd1          163     Exynos4210
  92   sclk_mipi1          164     Exynos4210
  93   sclk_pcm1           165
  94   sclk_pcm2           166
  95   sclk_i2s1           167
  96   sclk_i2s2           168
  97   sclk_mipihsi        169     Exynos4412
  98   sclk_mfc            170
  99   sclk_pcm0           171
 100   sclk_g3d            172
 101   sclk_pwm_isp        173     Exynos4x12
 102   sclk_spi0_isp       174     Exynos4x12
 103   sclk_spi1_isp       175     Exynos4x12
 104   sclk_uart_isp       176     Exynos4x12
 105
 106               [Peripheral Clock Gates]
 107
 108   Clock               ID      SoC (if specific)
 109   -----------------------------------------------
 110
 111   fimc0               256
 112   fimc1               257
 113   fimc2               258
 114   fimc3               259
 115   csis0               260
 116   csis1               261
 117   jpeg                262
 118   smmu_fimc0          263
 119   smmu_fimc1          264
 120   smmu_fimc2          265
 121   smmu_fimc3          266
 122   smmu_jpeg           267
 123   vp                  268
 124   mixer               269
 125   tvenc               270     Exynos4210
 126   hdmi                271
 127   smmu_tv             272
 128   mfc                 273
 129   smmu_mfcl           274
 130   smmu_mfcr           275
 131   g3d                 276
 132   g2d                 277     Exynos4210
 133   rotator             278     Exynos4210
 134   mdma                279     Exynos4210
 135   smmu_g2d            280     Exynos4210
 136   smmu_rotator        281     Exynos4210
 137   smmu_mdma           282     Exynos4210
 138   fimd0               283
 139   mie0                284
 140   mdnie0              285     Exynos4412
 141   dsim0               286
 142   smmu_fimd0          287
 143   fimd1               288     Exynos4210
 144   mie1                289     Exynos4210
 145   dsim1               290     Exynos4210
 146   smmu_fimd1          291     Exynos4210
 147   pdma0               292
 148   pdma1               293
 149   pcie_phy            294
 150   sata_phy            295     Exynos4210
 151   tsi                 296
 152   sdmmc0              297
 153   sdmmc1              298
 154   sdmmc2              299
 155   sdmmc3              300
 156   sdmmc4              301
 157   sata                302     Exynos4210
 158   sromc               303
 159   usb_host            304
 160   usb_device          305
 161   pcie                306
 162   onenand             307
 163   nfcon               308
 164   smmu_pcie           309
 165   gps                 310
 166   smmu_gps            311
 167   uart0               312
 168   uart1               313
 169   uart2               314
 170   uart3               315
 171   uart4               316
 172   i2c0                317
 173   i2c1                318
 174   i2c2                319
 175   i2c3                320
 176   i2c4                321
 177   i2c5                322
 178   i2c6                323
 179   i2c7                324
 180   i2c_hdmi            325
 181   tsadc               326
 182   spi0                327
 183   spi1                328
 184   spi2                329
 185   i2s1                330
 186   i2s2                331
 187   pcm0                332
 188   i2s0                333
 189   pcm1                334
 190   pcm2                335
 191   pwm                 336
 192   slimbus             337
 193   spdif               338
 194   ac97                339
 195   modemif             340
 196   chipid              341
 197   sysreg              342
 198   hdmi_cec            343
 199   mct                 344
 200   wdt                 345
 201   rtc                 346
 202   keyif               347
 203   audss               348
 204   mipi_hsi            349     Exynos4210
 205   mdma2               350     Exynos4210
 206   pixelasyncm0        351
 207   pixelasyncm1        352
 208   fimc_lite0          353     Exynos4x12
 209   fimc_lite1          354     Exynos4x12
 210   ppmuispx            355     Exynos4x12
 211   ppmuispmx           356     Exynos4x12
 212   fimc_isp            357     Exynos4x12
 213   fimc_drc            358     Exynos4x12
 214   fimc_fd             359     Exynos4x12
 215   mcuisp              360     Exynos4x12
 216   gicisp              361     Exynos4x12
 217   smmu_isp            362     Exynos4x12
 218   smmu_drc            363     Exynos4x12
 219   smmu_fd             364     Exynos4x12
 220   smmu_lite0          365     Exynos4x12
 221   smmu_lite1          366     Exynos4x12
 222   mcuctl_isp          367     Exynos4x12
 223   mpwm_isp            368     Exynos4x12
 224   i2c0_isp            369     Exynos4x12
 225   i2c1_isp            370     Exynos4x12
 226   mtcadc_isp          371     Exynos4x12
 227   pwm_isp             372     Exynos4x12
 228   wdt_isp             373     Exynos4x12
 229   uart_isp            374     Exynos4x12
 230   asyncaxim           375     Exynos4x12
 231   smmu_ispcx          376     Exynos4x12
 232   spi0_isp            377     Exynos4x12
 233   spi1_isp            378     Exynos4x12
 234   pwm_isp_sclk        379     Exynos4x12
 235   spi0_isp_sclk       380     Exynos4x12
 236   spi1_isp_sclk       381     Exynos4x12
 237   uart_isp_sclk       382     Exynos4x12
 238
 239                 [Mux Clocks]
 240
 241   Clock                 ID      SoC (if specific)
 242   -----------------------------------------------
 243
 244   mout_fimc0            384
 245   mout_fimc1            385
 246   mout_fimc2            386
 247   mout_fimc3            387
 248   mout_cam0             388
 249   mout_cam1             389
 250   mout_csis0            390
 251   mout_csis1            391
 252   mout_g3d0             392
 253   mout_g3d1             393
 254   mout_g3d              394
 255   aclk400_mcuisp        395     Exynos4x12
 256
 257                 [Div Clocks]
 258
 259   Clock                 ID      SoC (if specific)
 260   -----------------------------------------------
 261
 262   div_isp0              450     Exynos4x12
 263   div_isp1              451     Exynos4x12
 264   div_mcuisp0           452     Exynos4x12
 265   div_mcuisp1           453     Exynos4x12
 266   div_aclk200           454     Exynos4x12
 267   div_aclk400_mcuisp    455     Exynos4x12
 268
 269
 270 Example 1: An example of a clock controller node is listed below.
 271
 272         clock: clock-controller@0x10030000 {
 273                 compatible = "samsung,exynos4210-clock";
 274                 reg = <0x10030000 0x20000>;
 275                 #clock-cells = <1>;
 276         };
 277
 278 Example 2: UART controller node that consumes the clock generated by the clock
 279            controller. Refer to the standard clock bindings for information
 280            about 'clocks' and 'clock-names' property.
 281
 282         serial@13820000 {
 283                 compatible = "samsung,exynos4210-uart";
 284                 reg = <0x13820000 0x100>;
 285                 interrupts = <0 54 0>;
 286                 clocks = <&clock 314>, <&clock 153>;
 287                 clock-names = "uart", "clk_uart_baud0";
 288         };