1 Device Tree Clock bindings for arch-sunxi
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "allwinner,sun4i-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-pll1-clk" - for the main PLL clock
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
13 "allwinner,sun4i-axi-clk" - for the AXI clock
14 "allwinner,sun4i-axi-gates-clk" - for the AXI gates
15 "allwinner,sun4i-ahb-clk" - for the AHB clock
16 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
17 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
18 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
19 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
20 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
21 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
22 "allwinner,sun4i-apb0-clk" - for the APB0 clock
23 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
24 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
25 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
26 "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
27 "allwinner,sun4i-apb1-clk" - for the APB1 clock
28 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
29 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
30 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
31 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
32 "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
33 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
34 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
35 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
37 Required properties for all clocks:
38 - reg : shall be the control register address for the clock.
39 - clocks : shall be the input parent clock(s) phandle for the clock
40 - #clock-cells : from common clock binding; shall be set to 0 except for
41 "allwinner,*-gates-clk" where it shall be set to 1
43 Additionally, "allwinner,*-gates-clk" clocks require:
44 - clock-output-names : the corresponding gate names that the clock controls
46 Clock consumers should specify the desired clocks they use with a
47 "clocks" phandle cell. Consumers that are using a gated clock should
48 provide an additional ID in their clock property. This ID is the
49 offset of the bit controlling this particular gate in the register.
53 osc24M: osc24M@01c20050 {
55 compatible = "allwinner,sun4i-osc-clk";
56 reg = <0x01c20050 0x4>;
57 clocks = <&osc24M_fixed>;
62 compatible = "allwinner,sun4i-pll1-clk";
63 reg = <0x01c20000 0x4>;
69 compatible = "allwinner,sun4i-cpu-clk";
70 reg = <0x01c20054 0x4>;
71 clocks = <&osc32k>, <&osc24M>, <&pll1>;