Documentation/devicetree/bindings/clock/sunxi.txt

   1 Device Tree Clock bindings for arch-sunxi
   2
   3 This binding uses the common clock binding[1].
   4
   5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
   6
   7 Required properties:
   8 - compatible : shall be one of the following:
   9         "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
  10         "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
  11         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
  12         "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
  13         "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
  14         "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
  15         "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
  16         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
  17         "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
  18         "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
  19         "allwinner,sun4i-a10-axi-clk" - for the AXI clock
  20         "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
  21         "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
  22         "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
  23         "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
  24         "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
  25         "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
  26         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
  27         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
  28         "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
  29         "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
  30         "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
  31         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
  32         "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
  33         "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
  34         "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
  35         "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
  36         "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
  37         "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
  38         "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
  39         "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
  40         "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
  41         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
  42         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
  43         "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
  44         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
  45         "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
  46         "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
  47         "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
  48         "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
  49         "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
  50         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
  51         "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
  52         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
  53         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
  54         "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
  55         "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
  56         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  57         "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
  58         "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
  59         "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
  60         "allwinner,sun4i-a10-mmc-clk" - for the MMC clock
  61         "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
  62         "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80
  63         "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
  64         "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80
  65         "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
  66         "allwinner,sun7i-a20-out-clk" - for the external output clocks
  67         "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
  68         "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
  69         "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
  70         "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
  71         "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
  72         "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
  73         "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
  74         "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
  75
  76 Required properties for all clocks:
  77 - reg : shall be the control register address for the clock.
  78 - clocks : shall be the input parent clock(s) phandle for the clock. For
  79         multiplexed clocks, the list order must match the hardware
  80         programming order.
  81 - #clock-cells : from common clock binding; shall be set to 0 except for
  82         the following compatibles where it shall be set to 1:
  83         "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
  84         "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
  85         "allwinner,*-usb-clk", "allwinner,*-mmc-clk",
  86         "allwinner,*-mmc-config-clk"
  87 - clock-output-names : shall be the corresponding names of the outputs.
  88         If the clock module only has one output, the name shall be the
  89         module name.
  90
  91 And "allwinner,*-usb-clk" clocks also require:
  92 - reset-cells : shall be set to 1
  93
  94 The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
  95 - #reset-cells : shall be set to 1
  96 - resets : shall be the reset control phandle for the mmc block.
  97
  98 For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
  99 dummy clocks at 25 MHz and 125 MHz, respectively. See example.
 100
 101 Clock consumers should specify the desired clocks they use with a
 102 "clocks" phandle cell. Consumers that are using a gated clock should
 103 provide an additional ID in their clock property. This ID is the
 104 offset of the bit controlling this particular gate in the register.
 105 For the other clocks with "#clock-cells" = 1, the additional ID shall
 106 refer to the index of the output.
 107
 108 For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
 109 is the normal PLL6 output, or "pll6". The second output is rate doubled
 110 PLL6, or "pll6x2".
 111
 112 The "allwinner,*-mmc-clk" clocks have three different outputs: the
 113 main clock, with the ID 0, and the output and sample clocks, with the
 114 IDs 1 and 2, respectively.
 115
 116 The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output
 117 per mmc controller. The number of outputs is determined by the size of
 118 the address block, which is related to the overall mmc block.
 119
 120 For example:
 121
 122 osc24M: clk@01c20050 {
 123         #clock-cells = <0>;
 124         compatible = "allwinner,sun4i-a10-osc-clk";
 125         reg = <0x01c20050 0x4>;
 126         clocks = <&osc24M_fixed>;
 127         clock-output-names = "osc24M";
 128 };
 129
 130 pll1: clk@01c20000 {
 131         #clock-cells = <0>;
 132         compatible = "allwinner,sun4i-a10-pll1-clk";
 133         reg = <0x01c20000 0x4>;
 134         clocks = <&osc24M>;
 135         clock-output-names = "pll1";
 136 };
 137
 138 pll5: clk@01c20020 {
 139         #clock-cells = <1>;
 140         compatible = "allwinner,sun4i-pll5-clk";
 141         reg = <0x01c20020 0x4>;
 142         clocks = <&osc24M>;
 143         clock-output-names = "pll5_ddr", "pll5_other";
 144 };
 145
 146 pll6: clk@01c20028 {
 147         #clock-cells = <1>;
 148         compatible = "allwinner,sun6i-a31-pll6-clk";
 149         reg = <0x01c20028 0x4>;
 150         clocks = <&osc24M>;
 151         clock-output-names = "pll6", "pll6x2";
 152 };
 153
 154 cpu: cpu@01c20054 {
 155         #clock-cells = <0>;
 156         compatible = "allwinner,sun4i-a10-cpu-clk";
 157         reg = <0x01c20054 0x4>;
 158         clocks = <&osc32k>, <&osc24M>, <&pll1>;
 159         clock-output-names = "cpu";
 160 };
 161
 162 mmc0_clk: clk@01c20088 {
 163         #clock-cells = <1>;
 164         compatible = "allwinner,sun4i-a10-mmc-clk";
 165         reg = <0x01c20088 0x4>;
 166         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 167         clock-output-names = "mmc0", "mmc0_output", "mmc0_sample";
 168 };
 169
 170 mii_phy_tx_clk: clk@2 {
 171         #clock-cells = <0>;
 172         compatible = "fixed-clock";
 173         clock-frequency = <25000000>;
 174         clock-output-names = "mii_phy_tx";
 175 };
 176
 177 gmac_int_tx_clk: clk@3 {
 178         #clock-cells = <0>;
 179         compatible = "fixed-clock";
 180         clock-frequency = <125000000>;
 181         clock-output-names = "gmac_int_tx";
 182 };
 183
 184 gmac_clk: clk@01c20164 {
 185         #clock-cells = <0>;
 186         compatible = "allwinner,sun7i-a20-gmac-clk";
 187         reg = <0x01c20164 0x4>;
 188         /*
 189          * The first clock must be fixed at 25MHz;
 190          * the second clock must be fixed at 125MHz
 191          */
 192         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 193         clock-output-names = "gmac";
 194 };
 195
 196 mmc_config_clk: clk@01c13000 {
 197         compatible = "allwinner,sun9i-a80-mmc-config-clk";
 198         reg = <0x01c13000 0x10>;
 199         clocks = <&ahb0_gates 8>;
 200         clock-names = "ahb";
 201         resets = <&ahb0_resets 8>;
 202         reset-names = "ahb";
 203         #clock-cells = <1>;
 204         #reset-cells = <1>;
 205         clock-output-names = "mmc0_config", "mmc1_config",
 206                              "mmc2_config", "mmc3_config";
 207 };