Documentation/devicetree/bindings/display/msm/dsi.txt

   1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
   2
   3 DSI Controller:
   4 Required properties:
   5 - compatible:
   6   * "qcom,mdss-dsi-ctrl"
   7 - reg: Physical base address and length of the registers of controller
   8 - reg-names: The names of register regions. The following regions are required:
   9   * "dsi_ctrl"
  10 - qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
  11   be 0 or 1, since we have 2 DSI controllers at most for now.
  12 - interrupts: The interrupt signal from the DSI block.
  13 - power-domains: Should be <&mmcc MDSS_GDSC>.
  14 - clocks: Phandles to device clocks.
  15 - clock-names: the following clocks are required:
  16   * "mdp_core"
  17   * "iface"
  18   * "bus"
  19   * "core_mmss"
  20   * "byte"
  21   * "pixel"
  22   * "core"
  23   For DSIv2, we need an additional clock:
  24    * "src"
  25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
  26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
  27   by a DSI PHY block. See [1] for details on clock bindings.
  28 - vdd-supply: phandle to vdd regulator device node
  29 - vddio-supply: phandle to vdd-io regulator device node
  30 - vdda-supply: phandle to vdda regulator device node
  31 - phys: phandle to DSI PHY device node
  32 - phy-names: the name of the corresponding PHY device
  33 - syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
  34 - ports: Contains 2 DSI controller ports as child nodes. Each port contains
  35   an endpoint subnode as defined in [2] and [3].
  36
  37 Optional properties:
  38 - panel@0: Node of panel connected to this DSI controller.
  39   See files in [4] for each supported panel.
  40 - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
  41   driving a panel which needs 2 DSI links.
  42 - qcom,master-dsi: Boolean value indicating if the DSI controller is driving
  43   the master link of the 2-DSI panel.
  44 - qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
  45   driving a 2-DSI panel whose 2 links need receive command simultaneously.
  46 - interrupt-parent: phandle to the MDP block if the interrupt signal is routed
  47   through MDP block
  48 - pinctrl-names: the pin control state names; should contain "default"
  49 - pinctrl-0: the default pinctrl state (active)
  50 - pinctrl-n: the "sleep" pinctrl state
  51 - ports: contains DSI controller input and output ports as children, each
  52   containing one endpoint subnode.
  53
  54   DSI Endpoint properties:
  55   - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
  56     input endpoint. For port@1, set to the MDP interface output. See [2] for
  57     device graph info.
  58
  59   - data-lanes: this describes how the physical DSI data lanes are mapped
  60     to the logical lanes on the given platform. The value contained in
  61     index n describes what physical lane is mapped to the logical lane n
  62     (DATAn, where n lies between 0 and 3). The clock lane position is fixed
  63     and can't be changed. Hence, they aren't a part of the DT bindings. See
  64     [3] for more info on the data-lanes property.
  65
  66     For example:
  67
  68     data-lanes = <3 0 1 2>;
  69
  70     The above mapping describes that the logical data lane DATA0 is mapped to
  71     the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
  72     to phys DATA1 and logic DATA3 to phys DATA2.
  73
  74     There are only a limited number of physical to logical mappings possible:
  75     <0 1 2 3>
  76     <1 2 3 0>
  77     <2 3 0 1>
  78     <3 0 1 2>
  79     <0 3 2 1>
  80     <1 0 3 2>
  81     <2 1 0 3>
  82     <3 2 1 0>
  83
  84 DSI PHY:
  85 Required properties:
  86 - compatible: Could be the following
  87   * "qcom,dsi-phy-28nm-hpm"
  88   * "qcom,dsi-phy-28nm-lp"
  89   * "qcom,dsi-phy-20nm"
  90   * "qcom,dsi-phy-28nm-8960"
  91 - reg: Physical base address and length of the registers of PLL, PHY and PHY
  92   regulator
  93 - reg-names: The names of register regions. The following regions are required:
  94   * "dsi_pll"
  95   * "dsi_phy"
  96   * "dsi_phy_regulator"
  97 - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
  98   2 clocks: A byte clock (index 0), and a pixel clock (index 1).
  99 - qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
 100   be 0 or 1, since we have 2 DSI PHYs at most for now.
 101 - power-domains: Should be <&mmcc MDSS_GDSC>.
 102 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
 103 - clock-names: the following clocks are required:
 104   * "iface"
 105   For 28nm HPM/LP, 28nm 8960 PHYs:
 106 - vddio-supply: phandle to vdd-io regulator device node
 107   For 20nm PHY:
 108 - vddio-supply: phandle to vdd-io regulator device node
 109 - vcca-supply: phandle to vcca regulator device node
 110
 111 Optional properties:
 112 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
 113   regulator is wanted.
 114
 115 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 116 [2] Documentation/devicetree/bindings/graph.txt
 117 [3] Documentation/devicetree/bindings/media/video-interfaces.txt
 118 [4] Documentation/devicetree/bindings/display/panel/
 119
 120 Example:
 121         dsi0: dsi@fd922800 {
 122                 compatible = "qcom,mdss-dsi-ctrl";
 123                 qcom,dsi-host-index = <0>;
 124                 interrupt-parent = <&mdp>;
 125                 interrupts = <4 0>;
 126                 reg-names = "dsi_ctrl";
 127                 reg = <0xfd922800 0x200>;
 128                 power-domains = <&mmcc MDSS_GDSC>;
 129                 clock-names =
 130                         "bus",
 131                         "byte",
 132                         "core",
 133                         "core_mmss",
 134                         "iface",
 135                         "mdp_core",
 136                         "pixel";
 137                 clocks =
 138                         <&mmcc MDSS_AXI_CLK>,
 139                         <&mmcc MDSS_BYTE0_CLK>,
 140                         <&mmcc MDSS_ESC0_CLK>,
 141                         <&mmcc MMSS_MISC_AHB_CLK>,
 142                         <&mmcc MDSS_AHB_CLK>,
 143                         <&mmcc MDSS_MDP_CLK>,
 144                         <&mmcc MDSS_PCLK0_CLK>;
 145
 146                 assigned-clocks =
 147                                  <&mmcc BYTE0_CLK_SRC>,
 148                                  <&mmcc PCLK0_CLK_SRC>;
 149                 assigned-clock-parents =
 150                                  <&dsi_phy0 0>,
 151                                  <&dsi_phy0 1>;
 152
 153                 vdda-supply = <&pma8084_l2>;
 154                 vdd-supply = <&pma8084_l22>;
 155                 vddio-supply = <&pma8084_l12>;
 156
 157                 phys = <&dsi_phy0>;
 158                 phy-names ="dsi-phy";
 159
 160                 qcom,dual-dsi-mode;
 161                 qcom,master-dsi;
 162                 qcom,sync-dual-dsi;
 163
 164                 pinctrl-names = "default", "sleep";
 165                 pinctrl-0 = <&dsi_active>;
 166                 pinctrl-1 = <&dsi_suspend>;
 167
 168                 ports {
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171
 172                         port@0 {
 173                                 reg = <0>;
 174                                 dsi0_in: endpoint {
 175                                         remote-endpoint = <&mdp_intf1_out>;
 176                                 };
 177                         };
 178
 179                         port@1 {
 180                                 reg = <1>;
 181                                 dsi0_out: endpoint {
 182                                         remote-endpoint = <&panel_in>;
 183                                         data-lanes = <0 1 2 3>;
 184                                 };
 185                         };
 186                 };
 187
 188                 panel: panel@0 {
 189                         compatible = "sharp,lq101r1sx01";
 190                         reg = <0>;
 191                         link2 = <&secondary>;
 192
 193                         power-supply = <...>;
 194                         backlight = <...>;
 195
 196                         port {
 197                                 panel_in: endpoint {
 198                                         remote-endpoint = <&dsi0_out>;
 199                                 };
 200                         };
 201                 };
 202         };
 203
 204         dsi_phy0: dsi-phy@fd922a00 {
 205                 compatible = "qcom,dsi-phy-28nm-hpm";
 206                 qcom,dsi-phy-index = <0>;
 207                 reg-names =
 208                         "dsi_pll",
 209                         "dsi_phy",
 210                         "dsi_phy_regulator";
 211                 reg =   <0xfd922a00 0xd4>,
 212                         <0xfd922b00 0x2b0>,
 213                         <0xfd922d80 0x7b>;
 214                 clock-names = "iface";
 215                 clocks = <&mmcc MDSS_AHB_CLK>;
 216                 #clock-cells = <1>;
 217                 vddio-supply = <&pma8084_l12>;
 218
 219                 qcom,dsi-phy-regulator-ldo-mode;
 220         };