Documentation/devicetree/bindings/dma/stm32-dma.txt

   1 * STMicroelectronics STM32 DMA controller
   2
   3 The STM32 DMA is a general-purpose direct memory access controller capable of
   4 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
   5
   6 Required properties:
   7 - compatible: Should be "st,stm32-dma"
   8 - reg: Should contain DMA registers location and length. This should include
   9   all of the per-channel registers.
  10 - interrupts: Should contain all of the per-channel DMA interrupts in
  11   ascending order with respect to the DMA channel index.
  12 - clocks: Should contain the input clock of the DMA instance.
  13 - #dma-cells : Must be <4>. See DMA client paragraph for more details.
  14
  15 Optional properties:
  16 - resets: Reference to a reset controller asserting the DMA controller
  17 - st,mem2mem: boolean; if defined, it indicates that the controller supports
  18   memory-to-memory transfer
  19
  20 Example:
  21
  22         dma2: dma-controller@40026400 {
  23                 compatible = "st,stm32-dma";
  24                 reg = <0x40026400 0x400>;
  25                 interrupts = <56>,
  26                              <57>,
  27                              <58>,
  28                              <59>,
  29                              <60>,
  30                              <68>,
  31                              <69>,
  32                              <70>;
  33                 clocks = <&clk_hclk>;
  34                 #dma-cells = <4>;
  35                 st,mem2mem;
  36                 resets = <&rcc 150>;
  37         };
  38
  39 * DMA client
  40
  41 DMA clients connected to the STM32 DMA controller must use the format
  42 described in the dma.txt file, using a five-cell specifier for each
  43 channel: a phandle to the DMA controller plus the following four integer cells:
  44
  45 1. The channel id
  46 2. The request line number
  47 3. A 32bit mask specifying the DMA channel configuration which are device
  48    dependent:
  49   -bit 9: Peripheral Increment Address
  50         0x0: no address increment between transfers
  51         0x1: increment address between transfers
  52  -bit 10: Memory Increment Address
  53         0x0: no address increment between transfers
  54         0x1: increment address between transfers
  55  -bit 15: Peripheral Increment Offset Size
  56         0x0: offset size is linked to the peripheral bus width
  57         0x1: offset size is fixed to 4 (32-bit alignment)
  58  -bit 16-17: Priority level
  59         0x0: low
  60         0x1: medium
  61         0x2: high
  62         0x3: very high
  63 4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
  64    dependent:
  65  -bit 0-1: Fifo threshold
  66         0x0: 1/4 full FIFO
  67         0x1: 1/2 full FIFO
  68         0x2: 3/4 full FIFO
  69         0x3: full FIFO
  70
  71 Example:
  72
  73         usart1: serial@40011000 {
  74                 compatible = "st,stm32-usart", "st,stm32-uart";
  75                 reg = <0x40011000 0x400>;
  76                 interrupts = <37>;
  77                 clocks = <&clk_pclk2>;
  78                 dmas = <&dma2 2 4 0x10400 0x3>,
  79                        <&dma2 7 5 0x10200 0x3>;
  80                 dma-names = "rx", "tx";
  81         };