Documentation/devicetree/bindings/gpio/mrvl-gpio.txt

   1 * Marvell PXA GPIO controller
   2
   3 Required properties:
   4 - compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio",
   5                 "intel,pxa27x-gpio", "intel,pxa3xx-gpio",
   6                 "marvell,pxa93x-gpio", "marvell,mmp-gpio" or
   7                 "marvell,mmp2-gpio".
   8 - reg : Address and length of the register set for the device
   9 - interrupts : Should be the port interrupt shared by all gpio pins.
  10   There're three gpio interrupts in arch-pxa, and they're gpio0,
  11   gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
  12   gpio_mux.
  13 - interrupt-names : Should be the names of irq resources. Each interrupt
  14   uses its own interrupt name, so there should be as many interrupt names
  15   as referenced interrups.
  16 - interrupt-controller : Identifies the node as an interrupt controller.
  17 - #interrupt-cells: Specifies the number of cells needed to encode an
  18   interrupt source.
  19 - gpio-controller : Marks the device node as a gpio controller.
  20 - #gpio-cells : Should be one.  It is the pin number.
  21
  22 Example:
  23
  24         gpio: gpio@d4019000 {
  25                 compatible = "marvell,mmp-gpio";
  26                 reg = <0xd4019000 0x1000>;
  27                 interrupts = <49>;
  28                 interrupt-names = "gpio_mux";
  29                 gpio-controller;
  30                 #gpio-cells = <1>;
  31                 interrupt-controller;
  32                 #interrupt-cells = <1>;
  33       };
  34
  35 * Marvell Orion GPIO Controller
  36
  37 Required properties:
  38 - compatible         : Should be "marvell,orion-gpio"
  39 - reg                : Address and length of the register set for controller.
  40 - gpio-controller    : So we know this is a gpio controller.
  41 - ngpio              : How many gpios this controller has.
  42 - interrupts         : Up to 4 Interrupts for the controller.
  43
  44 Optional properties:
  45 - mask-offset        : For SMP Orions, offset for Nth CPU
  46
  47 Example:
  48
  49                 gpio0: gpio@10100 {
  50                         compatible = "marvell,orion-gpio";
  51                         #gpio-cells = <2>;
  52                         gpio-controller;
  53                         reg = <0x10100 0x40>;
  54                         ngpio = <32>;
  55                         interrupts = <35>, <36>, <37>, <38>;
  56                 };