6 * Must be one of the following:
10 * And, optionally, one of the vendor specific compatible:
11 + allwinner,sun4i-a10-mali
12 + allwinner,sun7i-a20-mali
13 + amlogic,meson-gxbb-mali
14 + amlogic,meson-gxl-mali
15 + stericsson,db8500-mali
17 - reg: Physical base address and length of the GPU registers
19 - interrupts: an entry for each entry in interrupt-names.
20 See ../interrupt-controller/interrupts.txt for details.
23 * ppX: Pixel Processor X interrupt (X from 0 to 7)
24 * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
25 * pp: Pixel Processor broadcast interrupt (mali-450 only)
26 * gp: Geometry Processor interrupt
27 * gpmmu: Geometry Processor MMU interrupt
29 - clocks: an entry for each entry in clock-names
31 * bus: bus clock for the GPU
32 * core: clock driving the GPU itself
35 - interrupt-names and interrupts:
36 * pmu: Power Management Unit interrupt, if implemented in hardware
39 Memory region to allocate from, as defined in
40 Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
42 - operating-points-v2:
43 Operating Points for the GPU, as defined in
44 Documentation/devicetree/bindings/opp/opp.txt
46 Vendor-specific bindings
47 ------------------------
49 The Mali GPU is integrated very differently from one SoC to
50 another. In order to accomodate those differences, you have the option
51 to specify one more vendor-specific compatible, among:
53 - allwinner,sun4i-a10-mali
55 * resets: phandle to the reset line for the GPU
57 - allwinner,sun7i-a20-mali
59 * resets: phandle to the reset line for the GPU
61 - stericsson,db8500-mali
63 * interrupt-names and interrupts:
64 + combined: combined interrupt of all of the above lines
69 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
70 reg = <0x01c40000 0x10000>;
71 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-names = "gp",
85 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
86 clock-names = "bus", "core";
87 resets = <&ccu RST_BUS_GPU>;