Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt

   1 * Tegra keyboard controller
   2 The key controller has maximum 24 pins to make matrix keypad. Any pin
   3 can be configured as row or column. The maximum column pin can be 8
   4 and maximum row pins can be 16 for Tegra20/Tegra30.
   5
   6 Required properties:
   7 - compatible: "nvidia,tegra20-kbc"
   8 - reg: Register base address of KBC.
   9 - interrupts: Interrupt number for the KBC.
  10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
  11   array of pin numbers which is used as rows.
  12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
  13   array of pin numbers which is used as column.
  14 - linux,keymap: The keymap for keys as described in the binding document
  15   devicetree/bindings/input/matrix-keymap.txt.
  16
  17 Optional properties, in addition to those specified by the shared
  18 matrix-keyboard bindings:
  19
  20 - linux,fn-keymap: a second keymap, same specification as the
  21   matrix-keyboard-controller spec but to be used when the KEY_FN modifier
  22   key is pressed.
  23 - nvidia,debounce-delay-ms: delay in milliseconds per row scan for debouncing
  24 - nvidia,repeat-delay-ms: delay in milliseconds before repeat starts
  25 - nvidia,ghost-filter: enable ghost filtering for this device
  26 - nvidia,wakeup-source: configure keyboard as a wakeup source for suspend/resume
  27
  28 Example:
  29
  30 keyboard: keyboard {
  31         compatible = "nvidia,tegra20-kbc";
  32         reg = <0x7000e200 0x100>;
  33         interrupts = <0 85 0x04>;
  34         nvidia,ghost-filter;
  35         nvidia,debounce-delay-ms = <640>;
  36         nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
  37         nvidia,kbc-col-pins = <11 12 13>; /* pin 11, 12, 13 as columns */
  38         linux,keymap = <0x00000074
  39                         0x00010067
  40                         0x00020066
  41                         0x01010068
  42                         0x02000069
  43                         0x02010070
  44                         0x02020071>;
  45 };