Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

   1 * ARM Generic Interrupt Controller, version 3
   2
   3 AArch64 SMP cores are often associated with a GICv3, providing Private
   4 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
   5 Software Generated Interrupts (SGI), and Locality-specific Peripheral
   6 Interrupts (LPI).
   7
   8 Main node required properties:
   9
  10 - compatible : should at least contain  "arm,gic-v3".
  11 - interrupt-controller : Identifies the node as an interrupt controller
  12 - #interrupt-cells : Specifies the number of cells needed to encode an
  13   interrupt source. Must be a single cell with a value of at least 3.
  14   If the system requires describing PPI affinity, then the value must
  15   be at least 4.
  16
  17   The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
  18   interrupts. Other values are reserved for future use.
  19
  20   The 2nd cell contains the interrupt number for the interrupt type.
  21   SPI interrupts are in the range [0-987]. PPI interrupts are in the
  22   range [0-15].
  23
  24   The 3rd cell is the flags, encoded as follows:
  25         bits[3:0] trigger type and level flags.
  26                 1 = edge triggered
  27                 4 = level triggered
  28
  29   The 4th cell is a phandle to a node describing a set of CPUs this
  30   interrupt is affine to. The interrupt must be a PPI, and the node
  31   pointed must be a subnode of the "ppi-partitions" subnode. For
  32   interrupt types other than PPI or PPIs that are not partitionned,
  33   this cell must be zero. See the "ppi-partitions" node description
  34   below.
  35
  36   Cells 5 and beyond are reserved for future use and must have a value
  37   of 0 if present.
  38
  39 - reg : Specifies base physical address(s) and size of the GIC
  40   registers, in the following order:
  41   - GIC Distributor interface (GICD)
  42   - GIC Redistributors (GICR), one range per redistributor region
  43   - GIC CPU interface (GICC)
  44   - GIC Hypervisor interface (GICH)
  45   - GIC Virtual CPU interface (GICV)
  46
  47   GICC, GICH and GICV are optional.
  48
  49 - interrupts : Interrupt source of the VGIC maintenance interrupt.
  50
  51 Optional
  52
  53 - redistributor-stride : If using padding pages, specifies the stride
  54   of consecutive redistributors. Must be a multiple of 64kB.
  55
  56 - #redistributor-regions: The number of independent contiguous regions
  57   occupied by the redistributors. Required if more than one such
  58   region is present.
  59
  60 Sub-nodes:
  61
  62 PPI affinity can be expressed as a single "ppi-partitions" node,
  63 containing a set of sub-nodes, each with the following property:
  64 - affinity: Should be a list of phandles to CPU nodes (as described in
  65 Documentation/devicetree/bindings/arm/cpus.txt).
  66
  67 GICv3 has one or more Interrupt Translation Services (ITS) that are
  68 used to route Message Signalled Interrupts (MSI) to the CPUs.
  69
  70 These nodes must have the following properties:
  71 - compatible : Should at least contain  "arm,gic-v3-its".
  72 - msi-controller : Boolean property. Identifies the node as an MSI controller
  73 - #msi-cells: Must be <1>. The single msi-cell is the DeviceID of the device
  74   which will generate the MSI.
  75 - reg: Specifies the base physical address and size of the ITS
  76   registers.
  77
  78 The main GIC node must contain the appropriate #address-cells,
  79 #size-cells and ranges properties for the reg property of all ITS
  80 nodes.
  81
  82 Examples:
  83
  84         gic: interrupt-controller@2cf00000 {
  85                 compatible = "arm,gic-v3";
  86                 #interrupt-cells = <3>;
  87                 #address-cells = <2>;
  88                 #size-cells = <2>;
  89                 ranges;
  90                 interrupt-controller;
  91                 reg = <0x0 0x2f000000 0 0x10000>,       // GICD
  92                       <0x0 0x2f100000 0 0x200000>,      // GICR
  93                       <0x0 0x2c000000 0 0x2000>,        // GICC
  94                       <0x0 0x2c010000 0 0x2000>,        // GICH
  95                       <0x0 0x2c020000 0 0x2000>;        // GICV
  96                 interrupts = <1 9 4>;
  97
  98                 gic-its@2c200000 {
  99                         compatible = "arm,gic-v3-its";
 100                         msi-controller;
 101                         #msi-cells = <1>;
 102                         reg = <0x0 0x2c200000 0 0x200000>;
 103                 };
 104         };
 105
 106         gic: interrupt-controller@2c010000 {
 107                 compatible = "arm,gic-v3";
 108                 #interrupt-cells = <4>;
 109                 #address-cells = <2>;
 110                 #size-cells = <2>;
 111                 ranges;
 112                 interrupt-controller;
 113                 redistributor-stride = <0x0 0x40000>;   // 256kB stride
 114                 #redistributor-regions = <2>;
 115                 reg = <0x0 0x2c010000 0 0x10000>,       // GICD
 116                       <0x0 0x2d000000 0 0x800000>,      // GICR 1: CPUs 0-31
 117                       <0x0 0x2e000000 0 0x800000>;      // GICR 2: CPUs 32-63
 118                       <0x0 0x2c040000 0 0x2000>,        // GICC
 119                       <0x0 0x2c060000 0 0x2000>,        // GICH
 120                       <0x0 0x2c080000 0 0x2000>;        // GICV
 121                 interrupts = <1 9 4>;
 122
 123                 gic-its@2c200000 {
 124                         compatible = "arm,gic-v3-its";
 125                         msi-controller;
 126                         #msi-cells = <1>;
 127                         reg = <0x0 0x2c200000 0 0x200000>;
 128                 };
 129
 130                 gic-its@2c400000 {
 131                         compatible = "arm,gic-v3-its";
 132                         msi-controller;
 133                         #msi-cells = <1>;
 134                         reg = <0x0 0x2c400000 0 0x200000>;
 135                 };
 136
 137                 ppi-partitions {
 138                         part0: interrupt-partition-0 {
 139                                 affinity = <&cpu0 &cpu2>;
 140                         };
 141
 142                         part1: interrupt-partition-1 {
 143                                 affinity = <&cpu1 &cpu3>;
 144                         };
 145                 };
 146         };
 147
 148
 149         device@0 {
 150                 reg = <0 0 0 4>;
 151                 interrupts = <1 1 4 &part0>;
 152         };