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1 Device tree bindings for ARM PL353 static memory controller
2
3 PL353 Static Memory Controller is a bus where you can connect two kinds
4 of memory interfaces: NAND and memory mapped interfaces (such as SRAM or NOR).
5
6 Required properties:
7 - compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell".
8 - reg : Controller registers map and length.
9 - clock-names : List of input clock names - "memclk", "apb_pclk"
10 (See clock bindings for details).
11 - clocks : Clock phandles (see clock bindings for details).
12 - address-cells : Must be 2.
13 - size-cells : Must be 1.
14 - ranges : Memory bus areas for interacting with the devices.
15 Encodes CS to memory region association.
16
17 The child device node represents the controller connected to the SMC
18 bus. Only one between: NAND controller, NOR controller and SRAM controller
19 is allowed in a single system.
20
21
22 Example:
23 smcc: memory-controller@e000e000
24 compatible = "arm,pl353-smc-r2p1", "arm,primecell";
25 clock-names = "memclk", "apb_pclk";
26 clocks = <&clkc 11>, <&clkc 44>;
27 reg = <0xe000e000 0x1000>;
28 #address-cells = <2>;
29 #size-cells = <1>;
30 ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
31 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
32 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
33 nand_0: flash@e1000000 {
34 compatible = "arm,pl353-nand-r2p1"
35 reg = <0 0 0x1000000>;
36 (...)
37 };
38 nor0: flash@e2000000 {
39 compatible = "cfi-flash";
40 reg = <1 0 0x2000000>;
41 };
42 nor1: flash@e4000000 {
43 compatible = "cfi-flash";
44 reg = <2 0 0x2000000>;
45 };
46 };