Documentation/devicetree/bindings/mtd/mtk-nand.txt

   1 MTK SoCs NAND FLASH controller (NFC) DT binding
   2
   3 This file documents the device tree bindings for MTK SoCs NAND controllers.
   4 The functional split of the controller requires two drivers to operate:
   5 the nand controller interface driver and the ECC engine driver.
   6
   7 The hardware description for both devices must be captured as device
   8 tree nodes.
   9
  10 1) NFC NAND Controller Interface (NFI):
  11 =======================================
  12
  13 The first part of NFC is NAND Controller Interface (NFI) HW.
  14 Required NFI properties:
  15 - compatible:                   Should be "mediatek,mtxxxx-nfc".
  16 - reg:                          Base physical address and size of NFI.
  17 - interrupts:                   Interrupts of NFI.
  18 - clocks:                       NFI required clocks.
  19 - clock-names:                  NFI clocks internal name.
  20 - status:                       Disabled default. Then set "okay" by platform.
  21 - ecc-engine:                   Required ECC Engine node.
  22 - #address-cells:               NAND chip index, should be 1.
  23 - #size-cells:                  Should be 0.
  24
  25 Example:
  26
  27         nandc: nfi@1100d000 {
  28                 compatible = "mediatek,mt2701-nfc";
  29                 reg = <0 0x1100d000 0 0x1000>;
  30                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
  31                 clocks = <&pericfg CLK_PERI_NFI>,
  32                          <&pericfg CLK_PERI_NFI_PAD>;
  33                 clock-names = "nfi_clk", "pad_clk";
  34                 status = "disabled";
  35                 ecc-engine = <&bch>;
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38         };
  39
  40 Platform related properties, should be set in {platform_name}.dts:
  41 - children nodes:       NAND chips.
  42
  43 Children nodes properties:
  44 - reg:                  Chip Select Signal, default 0.
  45                         Set as reg = <0>, <1> when need 2 CS.
  46 Optional:
  47 - nand-on-flash-bbt:    Store BBT on NAND Flash.
  48 - nand-ecc-mode:        the NAND ecc mode (check driver for supported modes)
  49 - nand-ecc-step-size:   Number of data bytes covered by a single ECC step.
  50                         valid values: 512 and 1024.
  51                         1024 is recommended for large page NANDs.
  52 - nand-ecc-strength:    Number of bits to correct per ECC step.
  53                         The valid values that the controller supports are: 4, 6,
  54                         8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
  55                         48, 52, 56, 60.
  56                         The strength should be calculated as follows:
  57                         E = (S - F) * 8 / 14
  58                         S = O / (P / Q)
  59                                 E :     nand-ecc-strength.
  60                                 S :     spare size per sector.
  61                                 F :     FDM size, should be in the range [1,8].
  62                                         It is used to store free oob data.
  63                                 O :     oob size.
  64                                 P :     page size.
  65                                 Q :     nand-ecc-step-size.
  66                         If the result does not match any one of the listed
  67                         choices above, please select the smaller valid value from
  68                         the list.
  69                         (otherwise the driver will do the adjustment at runtime)
  70 - pinctrl-names:        Default NAND pin GPIO setting name.
  71 - pinctrl-0:            GPIO setting node.
  72
  73 Example:
  74         &pio {
  75                 nand_pins_default: nanddefault {
  76                         pins_dat {
  77                                 pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
  78                                          <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
  79                                          <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
  80                                          <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
  81                                          <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
  82                                          <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
  83                                          <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
  84                                          <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
  85                                          <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
  86                                 input-enable;
  87                                 drive-strength = <MTK_DRIVE_8mA>;
  88                                 bias-pull-up;
  89                         };
  90
  91                         pins_we {
  92                                 pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
  93                                 drive-strength = <MTK_DRIVE_8mA>;
  94                                 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
  95                         };
  96
  97                         pins_ale {
  98                                 pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
  99                                 drive-strength = <MTK_DRIVE_8mA>;
 100                                 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 101                         };
 102                 };
 103         };
 104
 105         &nandc {
 106                 status = "okay";
 107                 pinctrl-names = "default";
 108                 pinctrl-0 = <&nand_pins_default>;
 109                 nand@0 {
 110                         reg = <0>;
 111                         nand-on-flash-bbt;
 112                         nand-ecc-mode = "hw";
 113                         nand-ecc-strength = <24>;
 114                         nand-ecc-step-size = <1024>;
 115                 };
 116         };
 117
 118 NAND chip optional subnodes:
 119 - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
 120
 121 Example:
 122         nand@0 {
 123                 partitions {
 124                         compatible = "fixed-partitions";
 125                         #address-cells = <1>;
 126                         #size-cells = <1>;
 127
 128                         preloader@0 {
 129                                 label = "pl";
 130                                 read-only;
 131                                 reg = <0x00000000 0x00400000>;
 132                         };
 133                         android@0x00400000 {
 134                                 label = "android";
 135                                 reg = <0x00400000 0x12c00000>;
 136                         };
 137                 };
 138         };
 139
 140 2) ECC Engine:
 141 ==============
 142
 143 Required BCH properties:
 144 - compatible:   Should be "mediatek,mtxxxx-ecc".
 145 - reg:          Base physical address and size of ECC.
 146 - interrupts:   Interrupts of ECC.
 147 - clocks:       ECC required clocks.
 148 - clock-names:  ECC clocks internal name.
 149 - status:       Disabled default. Then set "okay" by platform.
 150
 151 Example:
 152
 153         bch: ecc@1100e000 {
 154                 compatible = "mediatek,mt2701-ecc";
 155                 reg = <0 0x1100e000 0 0x1000>;
 156                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 157                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 158                 clock-names = "nfiecc_clk";
 159                 status = "disabled";
 160         };