Documentation/devicetree/bindings/net/dsa/dsa.txt

   1 Marvell Distributed Switch Architecture Device Tree Bindings
   2 ------------------------------------------------------------
   3
   4 Required properties:
   5 - compatible            : Should be "marvell,dsa"
   6 - #address-cells        : Must be 2, first cell is the address on the MDIO bus
   7                           and second cell is the address in the switch tree.
   8                           Second cell is used only when cascading/chaining.
   9 - #size-cells           : Must be 0
  10 - dsa,ethernet          : Should be a phandle to a valid Ethernet device node
  11 - dsa,mii-bus           : Should be a phandle to a valid MDIO bus device node
  12
  13 Optionnal properties:
  14 - interrupts            : property with a value describing the switch
  15                           interrupt number (not supported by the driver)
  16
  17 A DSA node can contain multiple switch chips which are therefore child nodes of
  18 the parent DSA node. The maximum number of allowed child nodes is 4
  19 (DSA_MAX_SWITCHES).
  20 Each of these switch child nodes should have the following required properties:
  21
  22 - reg                   : Describes the switch address on the MII bus
  23 - #address-cells        : Must be 1
  24 - #size-cells           : Must be 0
  25
  26 A switch may have multiple "port" children nodes
  27
  28 Each port children node must have the following mandatory properties:
  29 - reg                   : Describes the port address in the switch
  30 - label                 : Describes the label associated with this port, special
  31                           labels are "cpu" to indicate a CPU port and "dsa" to
  32                           indicate an uplink/downlink port.
  33
  34 Note that a port labelled "dsa" will imply checking for the uplink phandle
  35 described below.
  36
  37 Optionnal property:
  38 - link                  : Should be a phandle to another switch's DSA port.
  39                           This property is only used when switches are being
  40                           chained/cascaded together.
  41
  42 - phy-handle            : Phandle to a PHY on an external MDIO bus, not the
  43                           switch internal one. See
  44                           Documentation/devicetree/bindings/net/ethernet.txt
  45                           for details.
  46
  47 - phy-mode              : String representing the connection to the designated
  48                           PHY node specified by the 'phy-handle' property. See
  49                           Documentation/devicetree/bindings/net/ethernet.txt
  50                           for details.
  51
  52 Optional subnodes:
  53 - fixed-link            : Fixed-link subnode describing a link to a non-MDIO
  54                           managed entity. See
  55                           Documentation/devicetree/bindings/net/fixed-link.txt
  56                           for details.
  57
  58 Example:
  59
  60         dsa@0 {
  61                 compatible = "marvell,dsa";
  62                 #address-cells = <2>;
  63                 #size-cells = <0>;
  64
  65                 interrupts = <10>;
  66                 dsa,ethernet = <&ethernet0>;
  67                 dsa,mii-bus = <&mii_bus0>;
  68
  69                 switch@0 {
  70                         #address-cells = <1>;
  71                         #size-cells = <0>;
  72                         reg = <16 0>;   /* MDIO address 16, switch 0 in tree */
  73
  74                         port@0 {
  75                                 reg = <0>;
  76                                 label = "lan1";
  77                                 phy-handle = <&phy0>;
  78                         };
  79
  80                         port@1 {
  81                                 reg = <1>;
  82                                 label = "lan2";
  83                         };
  84
  85                         port@5 {
  86                                 reg = <5>;
  87                                 label = "cpu";
  88                         };
  89
  90                         switch0uplink: port@6 {
  91                                 reg = <6>;
  92                                 label = "dsa";
  93                                 link = <&switch1uplink>;
  94                         };
  95                 };
  96
  97                 switch@1 {
  98                         #address-cells = <1>;
  99                         #size-cells = <0>;
 100                         reg = <17 1>;   /* MDIO address 17, switch 1 in tree */
 101
 102                         switch1uplink: port@0 {
 103                                 reg = <0>;
 104                                 label = "dsa";
 105                                 link = <&switch0uplink>;
 106                         };
 107                 };
 108         };