1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Controller Generic Binding
10 - David S. Miller <davem@davemloft.net>
14 pattern: "^ethernet(@.*)?$"
18 Specifies the MAC address that was assigned to the network device.
19 $ref: /schemas/types.yaml#/definitions/uint8-array
26 Specifies the MAC address that was last used by the boot
27 program; should be used in cases where the MAC address assigned
28 to the device by the boot program is different from the
29 local-mac-address property.
30 $ref: /schemas/types.yaml#/definitions/uint8-array
36 $ref: /schemas/types.yaml#/definitions/uint32
38 Maximum transfer unit (IEEE defined MTU), rather than the
39 maximum frame size (there\'s contradiction in the Devicetree
43 $ref: /schemas/types.yaml#/definitions/uint32
45 Specifies maximum speed in Mbit/s supported by the device.
50 Reference to an nvmem node for the MAC address
57 Specifies interface type between the Ethernet device and a physical
60 # There is not a standard bus between the MAC and the PHY,
61 # something proprietary is being used to embed the PHY in the
72 # RX and TX delays are added by the MAC when required
75 # RGMII with internal RX and TX delays provided by the PHY,
76 # the MAC should not add the RX or TX delays in this case
79 # RGMII with internal RX delay provided by the PHY, the MAC
80 # should not add an RX delay in this case
83 # RGMII with internal TX delay provided by the PHY, the MAC
84 # should not add an TX delay in this case
96 # 10GBASE-KR, XFI, SFI
102 $ref: "#/properties/phy-connection-type"
105 $ref: /schemas/types.yaml#/definitions/phandle
107 Specifies a reference to a node representing a PHY device.
110 $ref: "#/properties/phy-handle"
114 $ref: "#/properties/phy-handle"
118 $ref: /schemas/types.yaml#/definitions/uint32
120 The size of the controller\'s receive fifo in bytes. This is used
121 for components that can have configurable receive fifo sizes,
122 and is useful for determining certain configuration settings
123 such as flow control thresholds.
125 rx-internal-delay-ps:
127 RGMII Receive Clock Delay defined in pico seconds.
128 This is used for controllers that have configurable RX internal delays.
129 If this property is present then the MAC applies the RX delay.
132 $ref: /schemas/types.yaml#/definitions/phandle
134 Specifies a reference to a node representing a SFP cage.
137 $ref: /schemas/types.yaml#/definitions/uint32
139 The size of the controller\'s transmit fifo in bytes. This
140 is used for components that can have configurable fifo sizes.
142 tx-internal-delay-ps:
144 RGMII Transmit Clock Delay defined in pico seconds.
145 This is used for controllers that have configurable TX internal delays.
146 If this property is present then the MAC applies the TX delay.
150 Specifies the PHY management type. If auto is set and fixed-link
151 is not specified, it uses MDIO for management.
152 $ref: /schemas/types.yaml#/definitions/string
171 Emulated PHY ID, choose any but unique to the all
172 specified fixed-links
176 Duplex configuration. 0 for half duplex or 1 for
179 - enum: [10, 100, 1000]
181 Link speed in Mbits/sec.
185 Pause configuration. 0 for no pause, 1 for pause
189 Asymmetric pause configuration. 0 for no asymmetric
190 pause, 1 for asymmetric pause
200 $ref: /schemas/types.yaml#/definitions/uint32
201 enum: [10, 100, 1000]
204 $ref: /schemas/types.yaml#/definitions/flag
206 Indicates that full-duplex is used. When absent, half
210 $ref: /schemas/types.yaml#definitions/flag
212 Indicates that pause should be enabled.
215 $ref: /schemas/types.yaml#/definitions/flag
217 Indicates that asym_pause should be enabled.
222 GPIO to determine if the link is up
227 additionalProperties: true